Changeset 106068 in vbox for trunk/src/VBox
- Timestamp:
- Sep 17, 2024 8:44:27 AM (3 months ago)
- File:
-
- 1 edited
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trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32
r106060 r106068 1408 1408 /*xcpt? */ true, true }, \ 1409 1409 1410 /** 1411 * Table D-9: Packed double-precision floating-point invalid values. 1412 * For instructions: maxpd, minpd. 1413 **/ 1414 #define FP64_TABLE_D9_PD_INVALIDS \ 1415 /*0 */{ { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \ 1416 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, \ 1417 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \ 1418 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1419 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1420 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1421 /*xcpt? */ false, false }, \ 1422 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \ 1423 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2) } }, \ 1424 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \ 1425 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1426 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1427 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1428 /*xcpt? */ false, false }, \ 1429 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } }, \ 1430 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } }, \ 1431 { /* => */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } }, \ 1432 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, \ 1433 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, \ 1434 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, \ 1435 /*xcpt? */ false, false }, \ 1436 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } }, \ 1437 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V3) } }, \ 1438 { /* => */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } }, \ 1439 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1440 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1441 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1442 /*xcpt? */ false, false }, \ 1443 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \ 1444 { /*src1 */ { FP64_1(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, \ 1445 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \ 1446 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS, \ 1447 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS, \ 1448 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS, \ 1449 /*xcpt? */ false, false }, \ 1450 { { /*src2 */ { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V1) } }, \ 1451 { /*src1 */ { FP64_1(0), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } }, \ 1452 { /* => */ { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V1) } }, \ 1453 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1454 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1455 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1456 /*xcpt? */ false, false }, \ 1457 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \ 1458 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, \ 1459 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \ 1460 /*mxcsr:in */ 0, \ 1461 /*128:out */ X86_MXCSR_IE, \ 1462 /*256:out */ X86_MXCSR_IE, \ 1463 /*xcpt? */ true, true }, \ 1464 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \ 1465 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2) } }, \ 1466 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \ 1467 /*mxcsr:in */ 0, \ 1468 /*128:out */ X86_MXCSR_IE, \ 1469 /*256:out */ X86_MXCSR_IE, \ 1470 /*xcpt? */ true, true }, \ 1471 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } }, \ 1472 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } }, \ 1473 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \ 1474 /*mxcsr:in */ 0, \ 1475 /*128:out */ X86_MXCSR_IE, \ 1476 /*256:out */ X86_MXCSR_IE, \ 1477 /*xcpt? */ true, true }, \ 1478 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } }, \ 1479 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V3) } }, \ 1480 { /* => */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } }, \ 1481 /*mxcsr:in */ 0, \ 1482 /*128:out */ X86_MXCSR_IE, \ 1483 /*256:out */ X86_MXCSR_IE, \ 1484 /*xcpt? */ true, true }, \ 1485 1410 1486 1411 1487 /** … … 9252 9328 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 9253 9329 /*xcpt? */ false, false }, 9254 /** @todo Normals; Denormals; Invalids. */ 9330 /* 9331 * Normals. 9332 */ 9333 /*20*/{ { /*src2 */ { FP64_NORM_V0(0), FP64_NORM_V1(1), FP64_NORM_V2(0), FP64_NORM_V1(1) } }, 9334 { /*src1 */ { FP64_NORM_V3(1), FP64_NORM_V1(0), FP64_NORM_V2(1), FP64_NORM_V1(0) } }, 9335 { /* => */ { FP64_NORM_V0(0), FP64_NORM_V1(0), FP64_NORM_V2(0), FP64_NORM_V1(0) } }, 9336 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 9337 /*128:out */ X86_MXCSR_XCPT_MASK, 9338 /*256:out */ X86_MXCSR_XCPT_MASK, 9339 /*xcpt? */ false, false }, 9340 { { /*src2 */ { FP64_NORM_V0(0), FP64_0(1), FP64_NORM_V2(0), FP64_0(1) } }, 9341 { /*src1 */ { FP64_0(0), FP64_NORM_V1(1), FP64_0(0), FP64_NORM_V1(0) } }, 9342 { /* => */ { FP64_NORM_V0(0), FP64_0(1), FP64_NORM_V2(0), FP64_NORM_V1(0) } }, 9343 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 9344 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 9345 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 9346 /*xcpt? */ false, false }, 9347 { { /*src2 */ { FP64_V(0, 0, 0x409)/*1024*/, FP64_V(0, 0xb800000000000, 0x404)/*55*/, FP64_V(0, 0x8000000000000, 0x409)/*1536*/, FP64_V(0, 0xf000000000000, 0x404)/* 62*/ } }, 9348 { /*src1 */ { FP64_V(0, 0, 0x408)/* 512*/, FP64_V(0, 0xc000000000000, 0x401)/* 7*/, FP64_1(1), FP64_V(1, 0xf000000000000, 0x404)/*-62*/ } }, 9349 { /* => */ { FP64_V(0, 0, 0x409)/*1024*/, FP64_V(0, 0xb800000000000, 0x404)/*55*/, FP64_V(0, 0x8000000000000, 0x409)/*1536*/, FP64_V(0, 0xf000000000000, 0x404)/* 62*/ } }, 9350 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, 9351 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, 9352 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, 9353 /*xcpt? */ false, false }, 9354 { { /*src2 */ { FP64_V(0, 0x26580b4800000, 0x41d)/* 1234567890*/, FP64_V(0, 0xd6f3458800000, 0x41c)/*987654321*/, FP64_V(0, 0xd6f3426800000, 0x41c)/*987654221*/, FP64_V(0, 0xcf0033a34f337, 0x432)/*4072598000007579.5*/ } }, 9355 { /*src1 */ { FP64_V(1, 0x26580b4800000, 0x41d)/*-1234567890*/, FP64_V(0, 0x9000000000000, 0x405)/* -100*/, FP64_1(0), FP64_V(0, 0xd6eca42000000, 0x419)/* 123450000.5*/ } }, 9356 { /* => */ { FP64_V(0, 0x26580b4800000, 0x41d)/* 1234567890*/, FP64_V(0, 0xd6f3458800000, 0x41c)/*987654321*/, FP64_V(0, 0xd6f3426800000, 0x41c)/*987654221*/, FP64_V(0, 0xcf0033a34f337, 0x432)/*4072598000007579.5*/ } }, 9357 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ, 9358 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ, 9359 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ, 9360 /*xcpt? */ false, false }, 9361 { { /*src2 */ { FP64_V(0, 0x26580b4800000, 0x41d)/* 1234567890*/, FP64_V(0, 0xd6f3458800000, 0x41c)/*987654321*/, FP64_V(0, 0xd6f3426800000, 0x41c)/*987654221*/, FP64_V(0, 0xcf0033a34f337, 0x432)/*4072598000007579.5*/ } }, 9362 { /*src1 */ { FP64_V(1, 0x26580b4800000, 0x41d)/*-1234567890*/, FP64_V(0, 0x9000000000000, 0x405)/* -100*/, FP64_1(0), FP64_V(0, 0xd6eca42000000, 0x419)/* 123450000.5*/ } }, 9363 { /* => */ { FP64_V(0, 0x26580b4800000, 0x41d)/* 1234567890*/, FP64_V(0, 0xd6f3458800000, 0x41c)/*987654321*/, FP64_V(0, 0xd6f3426800000, 0x41c)/*987654221*/, FP64_V(0, 0xcf0033a34f337, 0x432)/*4072598000007579.5*/ } }, 9364 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 9365 /*128:out */ X86_MXCSR_RC_ZERO, 9366 /*256:out */ X86_MXCSR_RC_ZERO, 9367 /*xcpt? */ false, false }, 9368 { { /*src2 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MIN(0) } }, 9369 { /*src1 */ { FP64_1(0), FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(0), FP64_0(0) } }, 9370 { /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MIN(0) } }, 9371 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 9372 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 9373 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 9374 /*xcpt? */ false, false }, 9375 { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_0(0), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(1) } }, 9376 { /*src1 */ { FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(1), FP64_0(0), FP64_NORM_SAFE_INT_MIN(0) } }, 9377 { /* => */ { FP64_NORM_SAFE_INT_MIN(0), FP64_0(0), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(0) } }, 9378 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 9379 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 9380 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 9381 /*xcpt? */ false, false }, 9382 { { /*src2 */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_V(1, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/ } }, 9383 { /*src1 */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/ } }, 9384 { /* => */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/ } }, 9385 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, 9386 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, 9387 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, 9388 /*xcpt? */ false, false }, 9389 { { /*src2 */ { FP64_V(0, 0xc000000000000, 0x3ff)/*1.75*/, FP64_V(0, 0, 0x3fd)/*0.25*/, FP64_V(0, 0x26580b4c7e6b7, 0x41d)/*1234567891.1234567*/, FP64_V(0, 0xf9b0207d06184, 0x3fb)/*0.1234589833333129*/ } }, 9390 { /*src1 */ { FP64_V(0, 0, 0x3fd)/*0.25*/, FP64_V(0, 0, 0x3fe)/*0.50*/, FP64_V(0, 0x26580b4c7e6bc, 0x41d)/*1234567891.1234580*/, FP64_V(0, 0xf9b0207d0617d, 0x3fb)/*0.1234589833333128*/ } }, 9391 { /* => */ { FP64_V(0, 0xc000000000000, 0x3ff)/*1.75*/, FP64_V(0, 0, 0x3fe)/*0.25*/, FP64_V(0, 0x26580b4c7e6bc, 0x41d)/*1234567891.1234580*/, FP64_V(0, 0xf9b0207d06184, 0x3fb)/*0.1234589833333129*/ } }, 9392 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 9393 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 9394 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 9395 /*xcpt? */ false, false }, 9396 /** @todo Denormals. */ 9397 /* 9398 * Invalids. 9399 */ 9400 /*29*/ FP64_TABLE_D9_PD_INVALIDS 9255 9401 }; 9256 9402
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