Changeset 10607 in vbox for trunk/src/VBox

Timestamp:

Jul 14, 2008 4:17:10 PM (16 years ago)

Author:

vboxsync

Message:

Guest state loading and host state saving *must* be done after TPR handling as that code can jump back to ring 3 (!).

Location:

trunk/src/VBox/VMM/VMMR0

Files:

• HWSVMR0.cpp (modified) (2 diffs)
• HWVMXR0.cpp (modified) (2 diffs)

trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp

@@ -853 +853 @@
     }
 
-    /* Load the guest state */
-    rc = SVMR0LoadGuestState(pVM, pCtx);
-    if (rc != VINF_SUCCESS)
-    {
-        STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
-        goto end;
-    }
-    fGuestStateSynced = true;
-
     /* TPR caching using CR8 is only available in 64 bits mode */
     /* Note the 32 bits exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but that appears missing in Intel CPUs */
-    /* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock). */
+    /* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!!!!! */
     if (pCtx->msrEFER & MSR_K6_EFER_LMA)
     {
@@ -897 +888 @@
      *       (until the actual world switch)
      */
+
+    /* Load the guest state; *must* be here as it sets up the shadow cr0 for lazy fpu syncing! */
+    rc = SVMR0LoadGuestState(pVM, pCtx);
+    if (rc != VINF_SUCCESS)
+    {
+        STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
+        goto end;
+    }
+    fGuestStateSynced = true;
+
     pCpu = HWACCMR0GetCurrentCpu();
     /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */

trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp

@@ -1168 +1168 @@
     /** @todo check timers?? */
 
-    /* Save the host state first. */
-    rc  = VMXR0SaveHostState(pVM);
-    if (rc != VINF_SUCCESS)
-    {
-        STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
-        goto end;
-    }
-    /* Load the guest state */
-    rc = VMXR0LoadGuestState(pVM, pCtx);
-    if (rc != VINF_SUCCESS)
-    {
-        STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
-        goto end;
-    }
-    fGuestStateSynced = true;
-
     /* TPR caching using CR8 is only available in 64 bits mode */
     /* Note the 32 bits exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but that appears missing in Intel CPUs */
-    /* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock). */
+    /* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!! */
     /*
      * @todo reduce overhead
@@ -1204 +1188 @@
         AssertRC(rc);
     }
+
+    /*
+     * NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
+     *       (until the actual world switch)
+     */
+    /* Save the host state first. */
+    rc  = VMXR0SaveHostState(pVM);
+    if (rc != VINF_SUCCESS)
+    {
+        STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
+        goto end;
+    }
+    /* Load the guest state */
+    rc = VMXR0LoadGuestState(pVM, pCtx);
+    if (rc != VINF_SUCCESS)
+    {
+        STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
+        goto end;
+    }
+    fGuestStateSynced = true;
 
     /* Non-register state Guest Context */