Changeset 106091 in vbox for trunk/src/VBox

Timestamp:

Sep 19, 2024 9:25:16 AM (3 months ago)

Author:

vboxsync

Message:

ValidationKit/bootsectors: bugref:10658 SIMD FP testcase: [v]maxss -- denormals.

File:

• trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32 (modified) (3 diffs)

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32

@@ -9969 +9969 @@
      * Infinity.
      */
-    /*9 */{ { /*src2     */ { FP32_INF(0), FP32_RAND_V6(1), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V1(1), FP32_RAND_V0(1) } },
+    /*11*/{ { /*src2     */ { FP32_INF(0), FP32_RAND_V6(1), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V1(1), FP32_RAND_V0(1) } },
             { /*src1     */ { FP32_0(0),   FP32_RAND_V1(0), FP32_RAND_V5(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V3(0), FP32_RAND_V1(0), FP32_RAND_V6(1) } },
             { /* =>      */ { FP32_INF(0), FP32_RAND_V1(0), FP32_RAND_V5(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V3(0), FP32_RAND_V1(0), FP32_RAND_V6(1) } },
@@ -10084 +10084 @@
      * Normals.
      */
-    /*25*/{ { /*src2     */ { FP32_NORM_MAX(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V1(1) } },
+    /*27*/{ { /*src2     */ { FP32_NORM_MAX(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V1(1) } },
             { /*src1     */ { FP32_NORM_MAX(0), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V6(0), FP32_RAND_V7(0), FP32_RAND_V3(1), FP32_RAND_V1(1) } },
             { /* =>      */ { FP32_NORM_MAX(0), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V6(0), FP32_RAND_V7(0), FP32_RAND_V3(1), FP32_RAND_V1(1) } },
@@ -10218 +10218 @@
               /*xcpt?    */ false, false },
     /** @todo More Normals. */
-    /** @todo Normals; Denormals; Invalids; Rounding; FZ etc. */
+    /*
+     * Denormals.
+     */
+    /*46*/{ { /*src2     */ { FP32_DENORM_MAX(0), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V2(0), FP32_RAND_V1(1), FP32_RAND_V7(0), FP32_RAND_V2(1) } },
+            { /*src1     */ { FP32_0(0),          FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V5(0), FP32_RAND_V6(1), FP32_RAND_V7(0), FP32_RAND_V1(1) } },
+            { /* =>      */ { FP32_0(0),          FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V5(0), FP32_RAND_V6(1), FP32_RAND_V7(0), FP32_RAND_V1(1) } },
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_DE,
+              /*256:out  */ X86_MXCSR_DE,
+              /*xcpt?    */ true, true },
+          { { /*src2     */ { FP32_0(0),          FP32_SNAN(0),    FP32_QNAN(1),    FP32_QNAN(0),    FP32_SNAN(0), FP32_SNAN(0),    FP32_SNAN(0),    FP32_QNAN(1)    } },
+            { /*src1     */ { FP32_DENORM_MAX(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_QNAN(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
+            { /* =>      */ { FP32_DENORM_MAX(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_QNAN(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_DENORM_MIN(0), FP32_INF(1), FP32_SNAN(0), FP32_INF(1),  FP32_RAND_V2(1), FP32_RAND_V5(1), FP32_RAND_V2(1), FP32_RAND_V0(1) } },
+            { /*src1     */ { FP32_DENORM_MAX(0), FP32_INF(0), FP32_QNAN(1), FP32_SNAN(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V3(0) } },
+            { /* =>      */ { FP32_0(0),          FP32_INF(0), FP32_QNAN(1), FP32_SNAN(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V3(0) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_DENORM_MAX(0), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V2(0), FP32_RAND_V1(1), FP32_RAND_V7(0), FP32_RAND_V0(0) } },
+            { /*src1     */ { FP32_DENORM_MAX(0), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V6(1), FP32_RAND_V7(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V4(1) } },
+            { /* =>      */ { FP32_DENORM_MAX(0), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V6(1), FP32_RAND_V7(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V4(1) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_DENORM_MAX(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1) } },
+            { /*src1     */ { FP32_DENORM_MAX(1), FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V7(0), FP32_RAND_V5(0), FP32_RAND_V3(1), FP32_RAND_V3(1), FP32_RAND_V2(1) } },
+            { /* =>      */ { FP32_DENORM_MAX(0), FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V7(0), FP32_RAND_V5(0), FP32_RAND_V3(1), FP32_RAND_V3(1), FP32_RAND_V2(1) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_DENORM_MAX(1), FP32_RAND_V3(1), FP32_RAND_V7(0), FP32_RAND_V6(1), FP32_RAND_V2(0), FP32_RAND_V1(0), FP32_RAND_V7(1), FP32_RAND_V2(1) } },
+            { /*src1     */ { FP32_DENORM_MAX(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V5(1), FP32_RAND_V6(1), FP32_RAND_V7(1), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
+            { /* =>      */ { FP32_DENORM_MAX(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V5(1), FP32_RAND_V6(1), FP32_RAND_V7(1), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_DENORM_MIN(1), FP32_RAND_V7(1), FP32_RAND_V6(1), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
+            { /*src1     */ { FP32_DENORM_MIN(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(0), FP32_RAND_V6(1) } },
+            { /* =>      */ { FP32_DENORM_MIN(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(0), FP32_RAND_V6(1) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_DENORM_MIN(1), FP32_INF(0),     FP32_QNAN(1),    FP32_QNAN(0),    FP32_SNAN(1), FP32_SNAN(1),    FP32_SNAN(0),    FP32_QNAN(1)    } },
+            { /*src1     */ { FP32_DENORM_MIN(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_QNAN(0), FP32_RAND_V2(0), FP32_RAND_V4(1), FP32_RAND_V7(0) } },
+            { /* =>      */ { FP32_DENORM_MIN(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_QNAN(0), FP32_RAND_V2(0), FP32_RAND_V4(1), FP32_RAND_V7(0) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_DENORM_MIN(1), FP32_INF(0),     FP32_QNAN(1),    FP32_QNAN(0),    FP32_SNAN(1), FP32_SNAN(1),    FP32_SNAN(0),    FP32_QNAN(1)    } },
+            { /*src1     */ { FP32_DENORM_MIN(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_QNAN(0), FP32_RAND_V2(0), FP32_RAND_V4(1), FP32_RAND_V7(0) } },
+            { /* =>      */ { FP32_0(1),          FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_QNAN(0), FP32_RAND_V2(0), FP32_RAND_V4(1), FP32_RAND_V7(0) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_DENORM_MIN(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(0), FP32_RAND_V6(1) } },
+            { /*src1     */ { FP32_0(0),          FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
+            { /* =>      */ { FP32_DENORM_MIN(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*xcpt?    */ false, false },
+    /** @todo More Denormals. */
+    /** @todo Invalids; Rounding; FZ etc. */
     };