Changeset 106092 in vbox for trunk/src/VBox
- Timestamp:
- Sep 19, 2024 10:38:13 AM (3 months ago)
- File:
-
- 1 edited
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trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32
r106091 r106092 1484 1484 /*xcpt? */ true, true }, \ 1485 1485 1486 /** 1487 * Table D-9: Scalar single-precision floating-point invalid values. 1488 * For instructions: maxss, minss. 1489 **/ 1490 #define FP32_TABLE_D9_SS_INVALIDS \ 1491 /* QNan, QNan (Masked). */ \ 1492 /*0 */{ { /*src2 */ { FP32_QNAN(0), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V2(0), FP32_RAND_V1(1), FP32_RAND_V7(0), FP32_RAND_V2(1) } }, \ 1493 { /*src1 */ { FP32_QNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V5(1), FP32_RAND_V6(1), FP32_RAND_V7(1), FP32_RAND_V1(1) } }, \ 1494 { /* => */ { FP32_QNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V5(1), FP32_RAND_V6(1), FP32_RAND_V7(1), FP32_RAND_V1(1) } }, \ 1495 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1496 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1497 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1498 /*xcpt? */ false, false }, \ 1499 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(0), FP32_RAND_V6(1) } }, \ 1500 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V1(0) } }, \ 1501 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V1(0) } }, \ 1502 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1503 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1504 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1505 /*xcpt? */ false, false }, \ 1506 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_V0), FP32_RAND_V0(1), FP32_RAND_V7(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } }, \ 1507 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_RAND_V1(0), FP32_RAND_V7(0), FP32_RAND_V2(1), FP32_RAND_V6(1), FP32_RAND_V3(1), FP32_RAND_V5(0), FP32_RAND_V4(1) } }, \ 1508 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V0), FP32_RAND_V1(0), FP32_RAND_V7(0), FP32_RAND_V2(1), FP32_RAND_V6(1), FP32_RAND_V3(1), FP32_RAND_V5(0), FP32_RAND_V4(1) } }, \ 1509 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1510 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1511 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1512 /*xcpt? */ false, false }, \ 1513 /* QNan, SNan (Masked). */ \ 1514 { { /*src2 */ { FP32_QNAN(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V2(0), FP32_RAND_V2(1), FP32_RAND_V1(0), FP32_RAND_V0(1) } }, \ 1515 { /*src1 */ { FP32_SNAN(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, \ 1516 { /* => */ { FP32_QNAN(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, \ 1517 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1518 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1519 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1520 /*xcpt? */ false, false }, \ 1521 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V1(1), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, \ 1522 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V3(0) } }, \ 1523 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V3(0) } }, \ 1524 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1525 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1526 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1527 /*xcpt? */ false, false }, \ 1528 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_V0), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V1(1), FP32_RAND_V0(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, \ 1529 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V1(0) } }, \ 1530 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V0), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V1(0) } }, \ 1531 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1532 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1533 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1534 /*xcpt? */ false, false }, \ 1535 /* SNan, QNan (Masked). */ \ 1536 { { /*src2 */ { FP32_SNAN(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V1(1), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, \ 1537 { /*src1 */ { FP32_QNAN(0), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V3(0) } }, \ 1538 { /* => */ { FP32_SNAN(0), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V3(0) } }, \ 1539 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, \ 1540 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, \ 1541 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, \ 1542 /*xcpt? */ false, false }, \ 1543 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V7(1) } }, \ 1544 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_RAND_V2(0), FP32_RAND_V4(0), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V2(0) } }, \ 1545 { /* => */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_RAND_V2(0), FP32_RAND_V4(0), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V2(0) } }, \ 1546 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1547 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1548 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1549 /*xcpt? */ false, false }, \ 1550 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_V1), FP32_RAND_V1(1), FP32_RAND_V7(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } }, \ 1551 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V0(1), FP32_RAND_V2(0), FP32_RAND_V3(1) } }, \ 1552 { /* => */ { FP32_SNAN_V(0, FP32_FRAC_V1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V0(1), FP32_RAND_V2(0), FP32_RAND_V3(1) } }, \ 1553 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1554 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1555 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1556 /*xcpt? */ false, false }, \ 1557 /* SNan, SNan (Masked). */ \ 1558 { { /*src2 */ { FP32_SNAN(0), FP32_RAND_V1(1), FP32_RAND_V7(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } }, \ 1559 { /*src1 */ { FP32_SNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V7(0) } }, \ 1560 { /* => */ { FP32_SNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V7(0) } }, \ 1561 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1562 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1563 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1564 /*xcpt? */ false, false }, \ 1565 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_RAND_V1(0), FP32_RAND_V7(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V1(1), FP32_RAND_V2(1) } }, \ 1566 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_RAND_V7(0), FP32_RAND_V5(0), FP32_RAND_V7(1), FP32_RAND_V6(1), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V2(1) } }, \ 1567 { /* => */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_RAND_V7(0), FP32_RAND_V5(0), FP32_RAND_V7(1), FP32_RAND_V6(1), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V2(1) } }, \ 1568 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1569 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1570 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1571 /*xcpt? */ false, false }, \ 1572 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_V1), FP32_RAND_V1(1), FP32_RAND_V6(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } }, \ 1573 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_V4), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V0(1) } }, \ 1574 { /* => */ { FP32_SNAN_V(0, FP32_FRAC_V1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V0(1) } }, \ 1575 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1576 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1577 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1578 /*xcpt? */ false, false }, \ 1579 /* QNan, Normal (Masked). */ \ 1580 { { /*src2 */ { FP32_QNAN(0), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } }, \ 1581 { /*src1 */ { FP32_1(0), FP32_RAND_V2(1), FP32_RAND_V4(1), FP32_RAND_V6(1), FP32_RAND_V2(1), FP32_RAND_V7(0), FP32_RAND_V3(0), FP32_RAND_V4(1) } }, \ 1582 { /* => */ { FP32_QNAN(0), FP32_RAND_V2(1), FP32_RAND_V4(1), FP32_RAND_V6(1), FP32_RAND_V2(1), FP32_RAND_V7(0), FP32_RAND_V3(0), FP32_RAND_V4(1) } }, \ 1583 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS, \ 1584 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS, \ 1585 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS, \ 1586 /*xcpt? */ false, false }, \ 1587 /* SNan, Normal (Masked). */ \ 1588 { { /*src2 */ { FP32_SNAN(1), FP32_RAND_V0(1), FP32_RAND_V2(1), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } }, \ 1589 { /*src1 */ { FP32_1(0), FP32_RAND_V0(1), FP32_RAND_V1(1), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V6(0), FP32_RAND_V7(0), FP32_RAND_V1(1) } }, \ 1590 { /* => */ { FP32_SNAN(1), FP32_RAND_V0(1), FP32_RAND_V1(1), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V6(0), FP32_RAND_V7(0), FP32_RAND_V1(1) } }, \ 1591 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1592 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1593 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1594 /*xcpt? */ false, false }, \ 1595 /* QNan, QNan (Unmasked). */ \ 1596 /*0 */{ { /*src2 */ { FP32_QNAN(0), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V2(0), FP32_RAND_V1(1), FP32_RAND_V7(0), FP32_RAND_V2(1) } }, \ 1597 { /*src1 */ { FP32_QNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V5(1), FP32_RAND_V6(1), FP32_RAND_V7(1), FP32_RAND_V1(1) } }, \ 1598 { /* => */ { FP32_QNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V5(1), FP32_RAND_V6(1), FP32_RAND_V7(1), FP32_RAND_V1(1) } }, \ 1599 /*mxcsr:in */ 0, \ 1600 /*128:out */ X86_MXCSR_IE, \ 1601 /*256:out */ X86_MXCSR_IE, \ 1602 /*xcpt? */ true, true }, \ 1603 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(0), FP32_RAND_V6(1) } }, \ 1604 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V1(0) } }, \ 1605 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V1(0) } }, \ 1606 /*mxcsr:in */ 0, \ 1607 /*128:out */ X86_MXCSR_IE, \ 1608 /*256:out */ X86_MXCSR_IE, \ 1609 /*xcpt? */ true, true }, \ 1610 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_V0), FP32_RAND_V0(1), FP32_RAND_V7(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } }, \ 1611 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_RAND_V1(0), FP32_RAND_V7(0), FP32_RAND_V2(1), FP32_RAND_V6(1), FP32_RAND_V3(1), FP32_RAND_V5(0), FP32_RAND_V4(1) } }, \ 1612 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V0), FP32_RAND_V1(0), FP32_RAND_V7(0), FP32_RAND_V2(1), FP32_RAND_V6(1), FP32_RAND_V3(1), FP32_RAND_V5(0), FP32_RAND_V4(1) } }, \ 1613 /*mxcsr:in */ 0, \ 1614 /*128:out */ X86_MXCSR_IE, \ 1615 /*256:out */ X86_MXCSR_IE, \ 1616 /*xcpt? */ true, true }, \ 1617 /* QNan, SNan (Unmasked). */ \ 1618 { { /*src2 */ { FP32_QNAN(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V2(0), FP32_RAND_V2(1), FP32_RAND_V1(0), FP32_RAND_V0(1) } }, \ 1619 { /*src1 */ { FP32_SNAN(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, \ 1620 { /* => */ { FP32_QNAN(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, \ 1621 /*mxcsr:in */ 0, \ 1622 /*128:out */ X86_MXCSR_IE, \ 1623 /*256:out */ X86_MXCSR_IE, \ 1624 /*xcpt? */ true, true }, \ 1625 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V1(1), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, \ 1626 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V3(0) } }, \ 1627 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V3(0) } }, \ 1628 /*mxcsr:in */ 0, \ 1629 /*128:out */ X86_MXCSR_IE, \ 1630 /*256:out */ X86_MXCSR_IE, \ 1631 /*xcpt? */ true, true }, \ 1632 { { /*src2 */ { FP32_QNAN_V(0, FP32_FRAC_V0), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V1(1), FP32_RAND_V0(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, \ 1633 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V1(0) } }, \ 1634 { /* => */ { FP32_QNAN_V(0, FP32_FRAC_V0), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V1(0) } }, \ 1635 /*mxcsr:in */ 0, \ 1636 /*128:out */ X86_MXCSR_IE, \ 1637 /*256:out */ X86_MXCSR_IE, \ 1638 /*xcpt? */ true, true }, \ 1639 /* SNan, QNan (Unmasked). */ \ 1640 { { /*src2 */ { FP32_SNAN(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V1(1), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, \ 1641 { /*src1 */ { FP32_QNAN(0), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V3(0) } }, \ 1642 { /* => */ { FP32_SNAN(0), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V3(0) } }, \ 1643 /*mxcsr:in */ X86_MXCSR_FZ, \ 1644 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_IE, \ 1645 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_IE, \ 1646 /*xcpt? */ true, true }, \ 1647 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V7(1) } }, \ 1648 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_RAND_V2(0), FP32_RAND_V4(0), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V2(0) } }, \ 1649 { /* => */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_RAND_V2(0), FP32_RAND_V4(0), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V2(0) } }, \ 1650 /*mxcsr:in */ 0, \ 1651 /*128:out */ X86_MXCSR_IE, \ 1652 /*256:out */ X86_MXCSR_IE, \ 1653 /*xcpt? */ true, true }, \ 1654 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_V1), FP32_RAND_V1(1), FP32_RAND_V7(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } }, \ 1655 { /*src1 */ { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V0(1), FP32_RAND_V2(0), FP32_RAND_V3(1) } }, \ 1656 { /* => */ { FP32_SNAN_V(0, FP32_FRAC_V1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V0(1), FP32_RAND_V2(0), FP32_RAND_V3(1) } }, \ 1657 /*mxcsr:in */ 0, \ 1658 /*128:out */ X86_MXCSR_IE, \ 1659 /*256:out */ X86_MXCSR_IE, \ 1660 /*xcpt? */ true, true }, \ 1661 /* SNan, SNan (Unmasked). */ \ 1662 { { /*src2 */ { FP32_SNAN(0), FP32_RAND_V1(1), FP32_RAND_V7(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } }, \ 1663 { /*src1 */ { FP32_SNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V7(0) } }, \ 1664 { /* => */ { FP32_SNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V7(0) } }, \ 1665 /*mxcsr:in */ 0, \ 1666 /*128:out */ X86_MXCSR_IE, \ 1667 /*256:out */ X86_MXCSR_IE, \ 1668 /*xcpt? */ true, true }, \ 1669 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_RAND_V1(0), FP32_RAND_V7(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V1(1), FP32_RAND_V2(1) } }, \ 1670 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_RAND_V7(0), FP32_RAND_V5(0), FP32_RAND_V7(1), FP32_RAND_V6(1), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V2(1) } }, \ 1671 { /* => */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_RAND_V7(0), FP32_RAND_V5(0), FP32_RAND_V7(1), FP32_RAND_V6(1), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V2(1) } }, \ 1672 /*mxcsr:in */ 0, \ 1673 /*128:out */ X86_MXCSR_IE, \ 1674 /*256:out */ X86_MXCSR_IE, \ 1675 /*xcpt? */ true, true }, \ 1676 { { /*src2 */ { FP32_SNAN_V(0, FP32_FRAC_V1), FP32_RAND_V1(1), FP32_RAND_V6(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } }, \ 1677 { /*src1 */ { FP32_SNAN_V(0, FP32_FRAC_V4), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V0(1) } }, \ 1678 { /* => */ { FP32_SNAN_V(0, FP32_FRAC_V1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V0(1) } }, \ 1679 /*mxcsr:in */ 0, \ 1680 /*128:out */ X86_MXCSR_IE, \ 1681 /*256:out */ X86_MXCSR_IE, \ 1682 /*xcpt? */ true, true }, \ 1683 /* QNan, Normal (Unmasked). */ \ 1684 { { /*src2 */ { FP32_QNAN(0), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } }, \ 1685 { /*src1 */ { FP32_1(0), FP32_RAND_V2(1), FP32_RAND_V4(1), FP32_RAND_V6(1), FP32_RAND_V2(1), FP32_RAND_V7(0), FP32_RAND_V3(0), FP32_RAND_V4(1) } }, \ 1686 { /* => */ { FP32_QNAN(0), FP32_RAND_V2(1), FP32_RAND_V4(1), FP32_RAND_V6(1), FP32_RAND_V2(1), FP32_RAND_V7(0), FP32_RAND_V3(0), FP32_RAND_V4(1) } }, \ 1687 /*mxcsr:in */ 0, \ 1688 /*128:out */ X86_MXCSR_IE, \ 1689 /*256:out */ X86_MXCSR_IE, \ 1690 /*xcpt? */ true, true }, \ 1691 /* SNan, Normal (Masked). */ \ 1692 { { /*src2 */ { FP32_SNAN(1), FP32_RAND_V0(1), FP32_RAND_V2(1), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } }, \ 1693 { /*src1 */ { FP32_1(0), FP32_RAND_V0(1), FP32_RAND_V1(1), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V6(0), FP32_RAND_V7(0), FP32_RAND_V1(1) } }, \ 1694 { /* => */ { FP32_SNAN(1), FP32_RAND_V0(1), FP32_RAND_V1(1), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V6(0), FP32_RAND_V7(0), FP32_RAND_V1(1) } }, \ 1695 /*mxcsr:in */ 0, \ 1696 /*128:out */ X86_MXCSR_IE, \ 1697 /*256:out */ X86_MXCSR_IE, \ 1698 /*xcpt? */ true, true }, \ 1486 1699 1487 1700 /** … … 10292 10505 /*xcpt? */ false, false }, 10293 10506 /** @todo More Denormals. */ 10294 /** @todo Invalids; Rounding; FZ etc. */ 10507 /*56*/ FP32_TABLE_D9_SS_INVALIDS 10508 /** @todo Rounding; FZ etc. */ 10295 10509 }; 10296 10510
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