Changeset 106104 in vbox for trunk/src/VBox/ValidationKit/bootsectors
- Timestamp:
- Sep 20, 2024 7:00:22 AM (5 months ago)
- File:
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- 1 edited
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trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32
r106103 r106104 1261 1261 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1262 1262 /*xcpt? */ false, false }, \ 1263 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2) } },\1264 { /*src1 */ { FP64_SNAN(0), FP64_QNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V3) } },\1265 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_V1) } },\1263 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2) } }, \ 1264 { /*src1 */ { FP64_SNAN(0), FP64_QNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V3) } }, \ 1265 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \ 1266 1266 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1267 1267 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ … … 6430 6430 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK, 6431 6431 /*xcpt? */ false, false }, 6432 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0) 6433 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1) 6432 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0) } }, 6433 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1) } }, 6434 6434 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1) } }, 6435 6435 /*mxcsr:in */ X86_MXCSR_FZ, … … 8154 8154 */ 8155 8155 /*24*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(1) } }, 8156 { /*src1 */ { FP32_0(0), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(1) ,} },8156 { /*src1 */ { FP32_0(0), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(1) } }, 8157 8157 { /* => */ { FP32_0(0), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(1) } }, 8158 8158 /*mxcsr:in */ 0, … … 8161 8161 /*xcpt? */ true, true }, 8162 8162 { { /*src2 */ { FP32_0(0), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(1) } }, 8163 { /*src1 */ { FP32_DENORM_MAX(0), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(1) ,} },8163 { /*src1 */ { FP32_DENORM_MAX(0), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(1) } }, 8164 8164 { /* => */ { FP32_INF(0), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(1) } }, 8165 8165 /*mxcsr:in */ 0, … … 8168 8168 /*xcpt? */ true, true }, 8169 8169 { { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(1) } }, 8170 { /*src1 */ { FP32_0(0), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(1) ,} },8170 { /*src1 */ { FP32_0(0), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(1) } }, 8171 8171 { /* => */ { FP32_0(0), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(1) } }, 8172 8172 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, … … 8175 8175 /*xcpt? */ false, false }, 8176 8176 { { /*src2 */ { FP32_0(0), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(1) } }, 8177 { /*src1 */ { FP32_DENORM_MAX(0), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(1) ,} },8177 { /*src1 */ { FP32_DENORM_MAX(0), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(1) } }, 8178 8178 { /* => */ { FP32_INF(0), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(1) } }, 8179 8179 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, … … 8891 8891 { { /*src2 */ { FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } }, 8892 8892 { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0) } }, 8893 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) ,} },8893 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 8894 8894 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ, 8895 8895 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ, … … 8898 8898 { { /*src2 */ { FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } }, 8899 8899 { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0) } }, 8900 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) ,} },8900 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 8901 8901 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 8902 8902 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, … … 8905 8905 { { /*src2 */ { FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } }, 8906 8906 { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0) } }, 8907 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) ,} },8907 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 8908 8908 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 8909 8909 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, … … 8912 8912 { { /*src2 */ { FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } }, 8913 8913 { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0) } }, 8914 { /* => */ { FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0) ,} },8914 { /* => */ { FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0) } }, 8915 8915 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN, 8916 8916 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN, … … 9066 9066 /*256:out */ X86_MXCSR_IM | X86_MXCSR_IE, 9067 9067 /*xcpt? */ false, false }, 9068 { { /*src2 */ { FP64_INF(0), FP64_QNAN(1), FP64_QNAN(1), FP64_INF(1) } },9069 { /*src1 */ { FP64_INF(0), FP64_QNAN(1), FP64_QNAN(1), FP64_INF(1) } },9068 { { /*src2 */ { FP64_INF(0), FP64_QNAN(1), FP64_QNAN(1), FP64_INF(1) } }, 9069 { /*src1 */ { FP64_INF(0), FP64_QNAN(1), FP64_QNAN(1), FP64_INF(1) } }, 9070 9070 { /* => */ { FP64_QNAN(1), FP64_QNAN(1), FP64_QNAN(1), FP64_INF(1) } }, 9071 9071 /*mxcsr:in */ X86_MXCSR_IM, … … 9136 9136 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, 9137 9137 /*xcpt? */ false, true }, 9138 { { /*src2 */ { FP64_INF(0), FP64_0(0), FP64_0(1), FP64_0(1) ,} },9138 { { /*src2 */ { FP64_INF(0), FP64_0(0), FP64_0(1), FP64_0(1) } }, 9139 9139 { /*src1 */ { FP64_0(0), FP64_INF(0), FP64_INF(0), FP64_INF(0) } }, 9140 9140 { /* => */ { FP64_INF(1), FP64_INF(0), FP64_INF(0), FP64_INF(0) } }, … … 9181 9181 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, 9182 9182 /*xcpt? */ false, false }, 9183 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_V3(0), FP64_NORM_MAX(0) ,} },9184 { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_V3(0), FP64_NORM_MAX(0) ,} },9185 { /* => */ { FP64_0(0), FP64_V(1, 0, FP64_EXP_NORM_MIN + 1), FP64_0(0), FP64_INF(0) ,} },9183 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_V3(0), FP64_NORM_MAX(0) } }, 9184 { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_V3(0), FP64_NORM_MAX(0) } }, 9185 { /* => */ { FP64_0(0), FP64_V(1, 0, FP64_EXP_NORM_MIN + 1), FP64_0(0), FP64_INF(0) } }, 9186 9186 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 9187 9187 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, … … 9242 9242 /*35*/{ { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_V1(0), FP64_NORM_MAX(1) } }, 9243 9243 { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_V1(0), FP64_NORM_MAX(0) } }, 9244 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) ,} },9244 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 9245 9245 /*mxcsr:in */ 0, 9246 9246 /*128:out */ 0, … … 9300 9300 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, 9301 9301 /*xcpt? */ false, false }, 9302 { { /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) ,} },9303 { /*src1 */ { FP64_0(0), FP64_DENORM_MAX(1), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) ,} },9304 { /* => */ { FP64_DENORM_MAX(1), FP64_DENORM_MAX(1), FP64_0(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_NORM_MIN) ,} },9302 { { /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } }, 9303 { /*src1 */ { FP64_0(0), FP64_DENORM_MAX(1), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } }, 9304 { /* => */ { FP64_DENORM_MAX(1), FP64_DENORM_MAX(1), FP64_0(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_NORM_MIN) } }, 9305 9305 /*mxcsr:in */ 0, 9306 9306 /*128:out */ X86_MXCSR_DE, … … 9540 9540 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, 9541 9541 /*xcpt? */ false, false }, 9542 { { /*src2 */ { FP32_INF(0), FP32_0(0), FP32_INF(0), FP32_0(1), FP32_INF(1), FP32_0(0), FP32_INF(1), FP32_0(0) } },9543 { /*src1 */ { FP32_0(0), FP32_INF(0), FP32_0(1), FP32_INF(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_INF(1) } },9544 { /* => */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },9545 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,9546 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,9547 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,9548 /*xcpt? */ false, false },9549 { { /*src2 */ { FP32_INF(0), FP32_0(0), FP32_INF(0), FP32_0(1), FP32_INF(1), FP32_0(0), FP32_INF(1), FP32_0(0) } },9550 { /*src1 */ { FP32_0(0), FP32_INF(0), FP32_0(1), FP32_INF(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_INF(1) } },9551 { /* => */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },9552 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,9553 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,9554 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,9555 /*xcpt? */ false, false },9556 { { /*src2 */ { FP32_INF(0), FP32_0(0), FP32_INF(0), FP32_0(1), FP32_INF(1), FP32_0(0), FP32_INF(1), FP32_0(0) } },9557 { /*src1 */ { FP32_0(0), FP32_INF(0), FP32_0(1), FP32_INF(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_INF(1) } },9558 { /* => */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },9559 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,9560 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,9561 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,9562 /*xcpt? */ false, false },9563 { { /*src2 */ { FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(0) } },9564 { /*src1 */ { FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_INF(0) } },9565 { /* => */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_INF(0), FP32_INF(0) } },9566 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,9567 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,9568 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,9569 /*xcpt? */ false, false },9570 { { /*src2 */ { FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(0) } },9571 { /*src1 */ { FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_INF(0) } },9572 { /* => */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_INF(0), FP32_INF(0) } },9573 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,9574 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,9575 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,9576 /*xcpt? */ false, false },9577 { { /*src2 */ { FP32_INF(0), FP32_NORM_V1(0), FP32_INF(1), FP32_NORM_V3(1), FP32_INF(1), FP32_NORM_V5(0), FP32_INF(1), FP32_NORM_V7(0) } },9578 { /*src1 */ { FP32_NORM_V0(0), FP32_INF(1), FP32_NORM_V2(0), FP32_INF(1), FP32_NORM_V4(1), FP32_INF(1), FP32_NORM_V6(0), FP32_INF(0) } },9579 { /* => */ { FP32_INF(0), FP32_NORM_V1(0), FP32_NORM_V2(0), FP32_NORM_V3(1), FP32_NORM_V4(1), FP32_NORM_V5(0), FP32_NORM_V6(0), FP32_INF(0) } },9580 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,9581 /*128:out */ X86_MXCSR_XCPT_MASK,9582 /*256:out */ X86_MXCSR_XCPT_MASK,9583 /*xcpt? */ false, false },9584 { { /*src2 */ { FP32_INF(0), FP32_NORM_V1(0), FP32_INF(1), FP32_NORM_V3(1), FP32_INF(1), FP32_NORM_V5(0), FP32_INF(1), FP32_NORM_V7(0) } },9585 { /*src1 */ { FP32_NORM_V0(0), FP32_INF(1), FP32_NORM_V2(0), FP32_INF(1), FP32_NORM_V4(1), FP32_INF(1), FP32_NORM_V6(0), FP32_INF(0) } },9586 { /* => */ { FP32_INF(0), FP32_NORM_V1(0), FP32_NORM_V2(0), FP32_NORM_V3(1), FP32_NORM_V4(1), FP32_NORM_V5(0), FP32_NORM_V6(0), FP32_INF(0) } },9587 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,9588 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,9589 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,9590 /*xcpt? */ false, false },9591 { { /*src2 */ { FP32_NORM_V7(0), FP32_INF(1), FP32_NORM_V5(1), FP32_INF(1), FP32_NORM_V3(0), FP32_INF(1), FP32_NORM_V1(0), FP32_INF(0) } },9592 { /*src1 */ { FP32_INF(1), FP32_NORM_V6(0), FP32_INF(1), FP32_NORM_V4(1), FP32_INF(1), FP32_NORM_V2(0), FP32_INF(0), FP32_NORM_V0(0) } },9593 { /* => */ { FP32_NORM_V7(0), FP32_NORM_V6(0), FP32_NORM_V5(1), FP32_NORM_V4(1), FP32_NORM_V3(0), FP32_NORM_V2(0), FP32_INF(0), FP32_INF(0) } },9594 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,9595 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,9596 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,9597 /*xcpt? */ false, false },9598 { { /*src2 */ { FP32_NORM_V7(0), FP32_INF(1), FP32_NORM_V5(1), FP32_INF(1), FP32_NORM_V3(0), FP32_INF(1), FP32_NORM_V1(0), FP32_INF(0) } },9599 { /*src1 */ { FP32_INF(0), FP32_NORM_V6(0), FP32_INF(0), FP32_NORM_V4(1), FP32_INF(0), FP32_NORM_V2(0), FP32_INF(1), FP32_NORM_V0(0) } },9600 { /* => */ { FP32_INF(0), FP32_NORM_V6(0), FP32_INF(0), FP32_NORM_V4(1), FP32_INF(0), FP32_NORM_V2(0), FP32_NORM_V1(0), FP32_INF(0) } },9601 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,9602 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,9603 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,9604 /*xcpt? */ false, false },9542 { { /*src2 */ { FP32_INF(0), FP32_0(0), FP32_INF(0), FP32_0(1), FP32_INF(1), FP32_0(0), FP32_INF(1), FP32_0(0) } }, 9543 { /*src1 */ { FP32_0(0), FP32_INF(0), FP32_0(1), FP32_INF(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_INF(1) } }, 9544 { /* => */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 9545 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 9546 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 9547 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 9548 /*xcpt? */ false, false }, 9549 { { /*src2 */ { FP32_INF(0), FP32_0(0), FP32_INF(0), FP32_0(1), FP32_INF(1), FP32_0(0), FP32_INF(1), FP32_0(0) } }, 9550 { /*src1 */ { FP32_0(0), FP32_INF(0), FP32_0(1), FP32_INF(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_INF(1) } }, 9551 { /* => */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 9552 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 9553 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 9554 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 9555 /*xcpt? */ false, false }, 9556 { { /*src2 */ { FP32_INF(0), FP32_0(0), FP32_INF(0), FP32_0(1), FP32_INF(1), FP32_0(0), FP32_INF(1), FP32_0(0) } }, 9557 { /*src1 */ { FP32_0(0), FP32_INF(0), FP32_0(1), FP32_INF(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_INF(1) } }, 9558 { /* => */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 9559 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 9560 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 9561 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 9562 /*xcpt? */ false, false }, 9563 { { /*src2 */ { FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(0) } }, 9564 { /*src1 */ { FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_INF(0) } }, 9565 { /* => */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_INF(0), FP32_INF(0) } }, 9566 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 9567 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 9568 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 9569 /*xcpt? */ false, false }, 9570 { { /*src2 */ { FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(0) } }, 9571 { /*src1 */ { FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_INF(0) } }, 9572 { /* => */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_INF(0), FP32_INF(0) } }, 9573 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 9574 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 9575 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 9576 /*xcpt? */ false, false }, 9577 { { /*src2 */ { FP32_INF(0), FP32_NORM_V1(0), FP32_INF(1), FP32_NORM_V3(1), FP32_INF(1), FP32_NORM_V5(0), FP32_INF(1), FP32_NORM_V7(0) } }, 9578 { /*src1 */ { FP32_NORM_V0(0), FP32_INF(1), FP32_NORM_V2(0), FP32_INF(1), FP32_NORM_V4(1), FP32_INF(1), FP32_NORM_V6(0), FP32_INF(0) } }, 9579 { /* => */ { FP32_INF(0), FP32_NORM_V1(0), FP32_NORM_V2(0), FP32_NORM_V3(1), FP32_NORM_V4(1), FP32_NORM_V5(0), FP32_NORM_V6(0), FP32_INF(0) } }, 9580 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 9581 /*128:out */ X86_MXCSR_XCPT_MASK, 9582 /*256:out */ X86_MXCSR_XCPT_MASK, 9583 /*xcpt? */ false, false }, 9584 { { /*src2 */ { FP32_INF(0), FP32_NORM_V1(0), FP32_INF(1), FP32_NORM_V3(1), FP32_INF(1), FP32_NORM_V5(0), FP32_INF(1), FP32_NORM_V7(0) } }, 9585 { /*src1 */ { FP32_NORM_V0(0), FP32_INF(1), FP32_NORM_V2(0), FP32_INF(1), FP32_NORM_V4(1), FP32_INF(1), FP32_NORM_V6(0), FP32_INF(0) } }, 9586 { /* => */ { FP32_INF(0), FP32_NORM_V1(0), FP32_NORM_V2(0), FP32_NORM_V3(1), FP32_NORM_V4(1), FP32_NORM_V5(0), FP32_NORM_V6(0), FP32_INF(0) } }, 9587 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 9588 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 9589 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 9590 /*xcpt? */ false, false }, 9591 { { /*src2 */ { FP32_NORM_V7(0), FP32_INF(1), FP32_NORM_V5(1), FP32_INF(1), FP32_NORM_V3(0), FP32_INF(1), FP32_NORM_V1(0), FP32_INF(0) } }, 9592 { /*src1 */ { FP32_INF(1), FP32_NORM_V6(0), FP32_INF(1), FP32_NORM_V4(1), FP32_INF(1), FP32_NORM_V2(0), FP32_INF(0), FP32_NORM_V0(0) } }, 9593 { /* => */ { FP32_NORM_V7(0), FP32_NORM_V6(0), FP32_NORM_V5(1), FP32_NORM_V4(1), FP32_NORM_V3(0), FP32_NORM_V2(0), FP32_INF(0), FP32_INF(0) } }, 9594 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 9595 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 9596 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 9597 /*xcpt? */ false, false }, 9598 { { /*src2 */ { FP32_NORM_V7(0), FP32_INF(1), FP32_NORM_V5(1), FP32_INF(1), FP32_NORM_V3(0), FP32_INF(1), FP32_NORM_V1(0), FP32_INF(0) } }, 9599 { /*src1 */ { FP32_INF(0), FP32_NORM_V6(0), FP32_INF(0), FP32_NORM_V4(1), FP32_INF(0), FP32_NORM_V2(0), FP32_INF(1), FP32_NORM_V0(0) } }, 9600 { /* => */ { FP32_INF(0), FP32_NORM_V6(0), FP32_INF(0), FP32_NORM_V4(1), FP32_INF(0), FP32_NORM_V2(0), FP32_NORM_V1(0), FP32_INF(0) } }, 9601 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 9602 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 9603 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 9604 /*xcpt? */ false, false }, 9605 9605 /* 9606 9606 * Normals. … … 9673 9673 * Denormals. 9674 9674 */ 9675 /*29*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } },9675 /*29*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 9676 9676 { /*src1 */ { FP32_0(0), FP32_DENORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(1) } }, 9677 9677 { /* => */ { FP32_0(0), FP32_DENORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(1) } }, … … 9694 9694 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 9695 9695 /*xcpt? */ false, false }, 9696 { { /*src2 */ { FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },9697 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } },9698 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },9699 /*mxcsr:in */ 0,9700 /*128:out */ X86_MXCSR_DE,9701 /*256:out */ X86_MXCSR_DE,9702 /*xcpt? */ true, true },9696 { { /*src2 */ { FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 9697 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 9698 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 9699 /*mxcsr:in */ 0, 9700 /*128:out */ X86_MXCSR_DE, 9701 /*256:out */ X86_MXCSR_DE, 9702 /*xcpt? */ true, true }, 9703 9703 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(1) } }, 9704 9704 { /*src1 */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, … … 9860 9860 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, 9861 9861 /*xcpt? */ false, false }, 9862 { { /*src2 */ { FP64_INF(0), FP64_0(0), FP64_INF(0), FP64_0(1) } },9863 { /*src1 */ { FP64_0(0), FP64_INF(0), FP64_0(1), FP64_INF(0) } },9864 { /* => */ { FP64_INF(0), FP64_INF(0), FP64_INF(0), FP64_INF(0) } },9865 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,9866 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,9867 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,9868 /*xcpt? */ false, false },9869 { { /*src2 */ { FP64_INF(0), FP64_0(0), FP64_INF(0), FP64_0(1) } },9870 { /*src1 */ { FP64_0(0), FP64_INF(0), FP64_0(1), FP64_INF(0) } },9871 { /* => */ { FP64_INF(0), FP64_INF(0), FP64_INF(0), FP64_INF(0) } },9872 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,9873 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,9874 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,9875 /*xcpt? */ false, false },9876 { { /*src2 */ { FP64_INF(0), FP64_0(0), FP64_INF(0), FP64_0(1) } },9877 { /*src1 */ { FP64_0(0), FP64_INF(0), FP64_0(1), FP64_INF(0) } },9878 { /* => */ { FP64_INF(0), FP64_INF(0), FP64_INF(0), FP64_INF(0) } },9879 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,9880 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,9881 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,9882 /*xcpt? */ false, false },9883 { { /*src2 */ { FP64_INF(0), FP64_INF(0), FP64_INF(1), FP64_INF(1) } },9884 { /*src1 */ { FP64_INF(0), FP64_INF(1), FP64_INF(0), FP64_INF(1) } },9885 { /* => */ { FP64_INF(0), FP64_INF(0), FP64_INF(0), FP64_INF(1) } },9886 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,9887 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,9888 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,9889 /*xcpt? */ false, false },9890 { { /*src2 */ { FP64_INF(0), FP64_INF(0), FP64_INF(1), FP64_INF(1) } },9891 { /*src1 */ { FP64_INF(0), FP64_INF(1), FP64_INF(0), FP64_INF(1) } },9892 { /* => */ { FP64_INF(0), FP64_INF(0), FP64_INF(0), FP64_INF(1) } },9893 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,9894 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,9895 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,9896 /*xcpt? */ false, false },9897 { { /*src2 */ { FP64_INF(0), FP64_NORM_V1(0), FP64_INF(1), FP64_NORM_V3(1) } },9898 { /*src1 */ { FP64_NORM_V0(0), FP64_INF(1), FP64_NORM_V2(0), FP64_INF(1) } },9899 { /* => */ { FP64_INF(0), FP64_NORM_V1(0), FP64_NORM_V2(0), FP64_NORM_V3(1) } },9900 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,9901 /*128:out */ X86_MXCSR_XCPT_MASK,9902 /*256:out */ X86_MXCSR_XCPT_MASK,9903 /*xcpt? */ false, false },9904 { { /*src2 */ { FP64_INF(0), FP64_NORM_V1(0), FP64_INF(1), FP64_NORM_V3(1) } },9905 { /*src1 */ { FP64_NORM_V0(0), FP64_INF(1), FP64_NORM_V2(0), FP64_INF(1) } },9906 { /* => */ { FP64_INF(0), FP64_NORM_V1(0), FP64_NORM_V2(0), FP64_NORM_V3(1) } },9907 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,9908 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,9909 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,9910 /*xcpt? */ false, false },9911 { { /*src2 */ { FP64_NORM_V1(0), FP64_INF(1), FP64_NORM_V2(1), FP64_INF(1) } },9912 { /*src1 */ { FP64_INF(1), FP64_NORM_V3(0), FP64_INF(1), FP64_NORM_V0(1) } },9913 { /* => */ { FP64_NORM_V1(0), FP64_NORM_V3(0), FP64_NORM_V2(1), FP64_NORM_V0(1) } },9914 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,9915 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,9916 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,9917 /*xcpt? */ false, false },9918 { { /*src2 */ { FP64_NORM_V1(0), FP64_INF(1), FP64_NORM_V3(1), FP64_INF(1) } },9919 { /*src1 */ { FP64_INF(0), FP64_NORM_V2(0), FP64_INF(0), FP64_NORM_V0(1) } },9920 { /* => */ { FP64_INF(0), FP64_NORM_V2(0), FP64_INF(0), FP64_NORM_V0(1) } },9921 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,9922 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,9923 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,9924 /*xcpt? */ false, false },9862 { { /*src2 */ { FP64_INF(0), FP64_0(0), FP64_INF(0), FP64_0(1) } }, 9863 { /*src1 */ { FP64_0(0), FP64_INF(0), FP64_0(1), FP64_INF(0) } }, 9864 { /* => */ { FP64_INF(0), FP64_INF(0), FP64_INF(0), FP64_INF(0) } }, 9865 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 9866 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 9867 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 9868 /*xcpt? */ false, false }, 9869 { { /*src2 */ { FP64_INF(0), FP64_0(0), FP64_INF(0), FP64_0(1) } }, 9870 { /*src1 */ { FP64_0(0), FP64_INF(0), FP64_0(1), FP64_INF(0) } }, 9871 { /* => */ { FP64_INF(0), FP64_INF(0), FP64_INF(0), FP64_INF(0) } }, 9872 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 9873 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 9874 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 9875 /*xcpt? */ false, false }, 9876 { { /*src2 */ { FP64_INF(0), FP64_0(0), FP64_INF(0), FP64_0(1) } }, 9877 { /*src1 */ { FP64_0(0), FP64_INF(0), FP64_0(1), FP64_INF(0) } }, 9878 { /* => */ { FP64_INF(0), FP64_INF(0), FP64_INF(0), FP64_INF(0) } }, 9879 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 9880 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 9881 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 9882 /*xcpt? */ false, false }, 9883 { { /*src2 */ { FP64_INF(0), FP64_INF(0), FP64_INF(1), FP64_INF(1) } }, 9884 { /*src1 */ { FP64_INF(0), FP64_INF(1), FP64_INF(0), FP64_INF(1) } }, 9885 { /* => */ { FP64_INF(0), FP64_INF(0), FP64_INF(0), FP64_INF(1) } }, 9886 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 9887 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 9888 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 9889 /*xcpt? */ false, false }, 9890 { { /*src2 */ { FP64_INF(0), FP64_INF(0), FP64_INF(1), FP64_INF(1) } }, 9891 { /*src1 */ { FP64_INF(0), FP64_INF(1), FP64_INF(0), FP64_INF(1) } }, 9892 { /* => */ { FP64_INF(0), FP64_INF(0), FP64_INF(0), FP64_INF(1) } }, 9893 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 9894 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 9895 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 9896 /*xcpt? */ false, false }, 9897 { { /*src2 */ { FP64_INF(0), FP64_NORM_V1(0), FP64_INF(1), FP64_NORM_V3(1) } }, 9898 { /*src1 */ { FP64_NORM_V0(0), FP64_INF(1), FP64_NORM_V2(0), FP64_INF(1) } }, 9899 { /* => */ { FP64_INF(0), FP64_NORM_V1(0), FP64_NORM_V2(0), FP64_NORM_V3(1) } }, 9900 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 9901 /*128:out */ X86_MXCSR_XCPT_MASK, 9902 /*256:out */ X86_MXCSR_XCPT_MASK, 9903 /*xcpt? */ false, false }, 9904 { { /*src2 */ { FP64_INF(0), FP64_NORM_V1(0), FP64_INF(1), FP64_NORM_V3(1) } }, 9905 { /*src1 */ { FP64_NORM_V0(0), FP64_INF(1), FP64_NORM_V2(0), FP64_INF(1) } }, 9906 { /* => */ { FP64_INF(0), FP64_NORM_V1(0), FP64_NORM_V2(0), FP64_NORM_V3(1) } }, 9907 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 9908 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 9909 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 9910 /*xcpt? */ false, false }, 9911 { { /*src2 */ { FP64_NORM_V1(0), FP64_INF(1), FP64_NORM_V2(1), FP64_INF(1) } }, 9912 { /*src1 */ { FP64_INF(1), FP64_NORM_V3(0), FP64_INF(1), FP64_NORM_V0(1) } }, 9913 { /* => */ { FP64_NORM_V1(0), FP64_NORM_V3(0), FP64_NORM_V2(1), FP64_NORM_V0(1) } }, 9914 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 9915 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 9916 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 9917 /*xcpt? */ false, false }, 9918 { { /*src2 */ { FP64_NORM_V1(0), FP64_INF(1), FP64_NORM_V3(1), FP64_INF(1) } }, 9919 { /*src1 */ { FP64_INF(0), FP64_NORM_V2(0), FP64_INF(0), FP64_NORM_V0(1) } }, 9920 { /* => */ { FP64_INF(0), FP64_NORM_V2(0), FP64_INF(0), FP64_NORM_V0(1) } }, 9921 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 9922 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 9923 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 9924 /*xcpt? */ false, false }, 9925 9925 /* 9926 9926 * Normals.
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