Changeset 106108 in vbox for trunk/src/VBox

Timestamp:

Sep 20, 2024 9:05:35 AM (2 months ago)

Author:

vboxsync

Message:

ValidationKit/bootsectors: bugref:10658 SIMD FP testcase: [v]maxsd - denormals.

File:

• trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32 (modified) (1 diff)

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32

@@ -10888 +10888 @@
               /*xcpt?    */ false, false },
     /** @todo More Normals. */
-    /** @todo Normals; Denormals; Invalids. */
+    /*
+     * Denormals.
+     */
+    /*46*/{ { /*src2     */ { FP64_DENORM_MAX(0), FP64_RAND_V2(0), FP64_RAND_V0(1), FP64_RAND_V3(0) } },
+            { /*src1     */ { FP64_0(0),          FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V2(1) } },
+            { /* =>      */ { FP64_0(0),          FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V2(1) } },
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_DE,
+              /*256:out  */ X86_MXCSR_DE,
+              /*xcpt?    */ true, true },
+          { { /*src2     */ { FP64_0(0),          FP64_SNAN(0),    FP64_QNAN(1),    FP64_QNAN(0)    } },
+            { /*src1     */ { FP64_DENORM_MAX(0), FP64_RAND_V2(0), FP64_RAND_V3(1), FP64_RAND_V2(0) } },
+            { /* =>      */ { FP64_DENORM_MAX(0), FP64_RAND_V2(0), FP64_RAND_V3(1), FP64_RAND_V2(0) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_DENORM_MIN(0), FP64_INF(1), FP64_SNAN(0), FP64_INF(1)  } },
+            { /*src1     */ { FP64_DENORM_MAX(0), FP64_INF(0), FP64_QNAN(1), FP64_SNAN(1) } },
+            { /* =>      */ { FP64_0(0),          FP64_INF(0), FP64_QNAN(1), FP64_SNAN(1) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_DENORM_MAX(0), FP64_RAND_V2(1), FP64_RAND_V0(1), FP64_RAND_V3(0) } },
+            { /*src1     */ { FP64_DENORM_MAX(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },
+            { /* =>      */ { FP64_DENORM_MAX(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_DENORM_MAX(0), FP64_RAND_V1(1), FP64_RAND_V2(1), FP64_RAND_V2(0) } },
+            { /*src1     */ { FP64_DENORM_MAX(1), FP64_RAND_V0(0), FP64_RAND_V3(0), FP64_RAND_V0(0) } },
+            { /* =>      */ { FP64_DENORM_MAX(0), FP64_RAND_V0(0), FP64_RAND_V3(0), FP64_RAND_V0(0) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_DENORM_MAX(1), FP64_RAND_V3(1), FP64_RAND_V0(0), FP64_RAND_V3(1) } },
+            { /*src1     */ { FP64_DENORM_MAX(0), FP64_RAND_V2(1), FP64_RAND_V3(1), FP64_RAND_V2(1) } },
+            { /* =>      */ { FP64_DENORM_MAX(0), FP64_RAND_V2(1), FP64_RAND_V3(1), FP64_RAND_V2(1) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_DENORM_MIN(1), FP64_RAND_V0(1), FP64_RAND_V3(1), FP64_RAND_V2(1) } },
+            { /*src1     */ { FP64_DENORM_MIN(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
+            { /* =>      */ { FP64_DENORM_MIN(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_DENORM_MIN(1), FP64_INF(0),     FP64_QNAN(1),    FP64_SNAN_V(1, 1) } },
+            { /*src1     */ { FP64_DENORM_MIN(1), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V0(1)   } },
+            { /* =>      */ { FP64_DENORM_MIN(1), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V0(1)   } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_DENORM_MIN(1), FP64_SNAN(1),    FP64_SNAN(0),    FP64_QNAN(0)    } },
+            { /*src1     */ { FP64_DENORM_MIN(1), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } },
+            { /* =>      */ { FP64_0(1),          FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_DENORM_MIN(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
+            { /*src1     */ { FP64_0(0),          FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(0) } },
+            { /* =>      */ { FP64_DENORM_MIN(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(0) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*xcpt?    */ false, false },
+     /** @todo More Denormals. */
+    /** @todo Invalids. */
     };