Changeset 106110 in vbox for trunk/src/VBox/ValidationKit
- Timestamp:
- Sep 20, 2024 9:45:22 AM (5 months ago)
- svn:sync-xref-src-repo-rev:
- 164886
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32
r106108 r106110 1699 1699 1700 1700 /** 1701 * Table D-9: Scalar double-precision floating-point invalid values. 1702 * For instructions: maxsd, minsd. 1703 **/ 1704 #define FP64_TABLE_D9_SD_INVALIDS \ 1705 /* QNan, QNan (Masked). */ \ 1706 /*0 */{ { /*src2 */ { FP64_QNAN(0), FP64_RAND_V2(0), FP64_RAND_V0(1), FP64_RAND_V1(0) } }, \ 1707 { /*src1 */ { FP64_QNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, \ 1708 { /* => */ { FP64_QNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, \ 1709 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1710 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1711 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1712 /*xcpt? */ false, false }, \ 1713 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(0) } }, \ 1714 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V3(1) } }, \ 1715 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V3(1) } }, \ 1716 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1717 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1718 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1719 /*xcpt? */ false, false }, \ 1720 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_V0), FP64_RAND_V0(1), FP64_RAND_V0(1), FP64_RAND_V2(0) } }, \ 1721 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_RAND_V1(0), FP64_RAND_V0(0), FP64_RAND_V2(1) } }, \ 1722 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V0), FP64_RAND_V1(0), FP64_RAND_V0(0), FP64_RAND_V2(1) } }, \ 1723 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1724 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1725 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1726 /*xcpt? */ false, false }, \ 1727 /* QNan, SNan (Masked). */ \ 1728 { { /*src2 */ { FP64_QNAN(0), FP64_RAND_V1(0), FP64_RAND_V3(1), FP64_RAND_V2(0) } }, \ 1729 { /*src1 */ { FP64_SNAN(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(0) } }, \ 1730 { /* => */ { FP64_QNAN(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(0) } }, \ 1731 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1732 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1733 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1734 /*xcpt? */ false, false }, \ 1735 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_RAND_V2(1), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, \ 1736 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, \ 1737 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, \ 1738 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1739 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1740 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1741 /*xcpt? */ false, false }, \ 1742 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_V0), FP64_RAND_V1(1), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, \ 1743 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_RAND_V3(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } }, \ 1744 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V0), FP64_RAND_V3(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } }, \ 1745 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1746 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1747 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1748 /*xcpt? */ false, false }, \ 1749 /* SNan, QNan (Masked). */ \ 1750 { { /*src2 */ { FP64_SNAN(0), FP64_RAND_V2(1), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, \ 1751 { /*src1 */ { FP64_QNAN(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, \ 1752 { /* => */ { FP64_SNAN(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, \ 1753 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, \ 1754 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, \ 1755 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, \ 1756 /*xcpt? */ false, false }, \ 1757 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_RAND_V1(1), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, \ 1758 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_RAND_V2(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, \ 1759 { /* => */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_RAND_V2(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, \ 1760 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1761 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1762 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1763 /*xcpt? */ false, false }, \ 1764 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_V1), FP64_RAND_V1(1), FP64_RAND_V0(1), FP64_RAND_V2(0) } }, \ 1765 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } }, \ 1766 { /* => */ { FP64_SNAN_V(0, FP64_FRAC_V1), FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } }, \ 1767 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1768 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1769 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1770 /*xcpt? */ false, false }, \ 1771 /* SNan, SNan (Masked). */ \ 1772 { { /*src2 */ { FP64_SNAN(0), FP64_RAND_V1(1), FP64_RAND_V0(1), FP64_RAND_V2(0) } }, \ 1773 { /*src1 */ { FP64_SNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, \ 1774 { /* => */ { FP64_SNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, \ 1775 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1776 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1777 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1778 /*xcpt? */ false, false }, \ 1779 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_RAND_V1(0), FP64_RAND_V0(1), FP64_RAND_V2(1) } }, \ 1780 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_RAND_V0(0), FP64_RAND_V3(0), FP64_RAND_V0(1) } }, \ 1781 { /* => */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_RAND_V0(0), FP64_RAND_V3(0), FP64_RAND_V0(1) } }, \ 1782 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1783 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1784 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1785 /*xcpt? */ false, false }, \ 1786 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_V1), FP64_RAND_V1(1), FP64_RAND_V1(1), FP64_RAND_V2(0) } }, \ 1787 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_V2), FP64_RAND_V2(1), FP64_RAND_V3(1), FP64_RAND_V1(1) } }, \ 1788 { /* => */ { FP64_SNAN_V(0, FP64_FRAC_V1), FP64_RAND_V2(1), FP64_RAND_V3(1), FP64_RAND_V1(1) } }, \ 1789 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1790 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1791 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1792 /*xcpt? */ false, false }, \ 1793 /* QNan, Normal (Masked). */ \ 1794 { { /*src2 */ { FP64_QNAN(0), FP64_RAND_V3(1), FP64_RAND_V2(1), FP64_RAND_V2(0) } }, \ 1795 { /*src1 */ { FP64_1(0), FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V1(1) } }, \ 1796 { /* => */ { FP64_QNAN(0), FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V1(1) } }, \ 1797 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS, \ 1798 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS, \ 1799 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS, \ 1800 /*xcpt? */ false, false }, \ 1801 /* SNan, Normal (Masked). */ \ 1802 { { /*src2 */ { FP64_SNAN(1), FP64_RAND_V0(1), FP64_RAND_V2(1), FP64_RAND_V2(0) } }, \ 1803 { /*src1 */ { FP64_1(0), FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V3(1) } }, \ 1804 { /* => */ { FP64_SNAN(1), FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V3(1) } }, \ 1805 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1806 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1807 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1808 /*xcpt? */ false, false }, \ 1809 /* QNan, QNan (Unmasked). */ \ 1810 /*0 */{ { /*src2 */ { FP64_QNAN(0), FP64_RAND_V2(0), FP64_RAND_V0(1), FP64_RAND_V1(0) } }, \ 1811 { /*src1 */ { FP64_QNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, \ 1812 { /* => */ { FP64_QNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, \ 1813 /*mxcsr:in */ 0, \ 1814 /*128:out */ X86_MXCSR_IE, \ 1815 /*256:out */ X86_MXCSR_IE, \ 1816 /*xcpt? */ true, true }, \ 1817 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(0) } }, \ 1818 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V3(1) } }, \ 1819 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V3(1) } }, \ 1820 /*mxcsr:in */ 0, \ 1821 /*128:out */ X86_MXCSR_IE, \ 1822 /*256:out */ X86_MXCSR_IE, \ 1823 /*xcpt? */ true, true }, \ 1824 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_V0), FP64_RAND_V0(1), FP64_RAND_V0(1), FP64_RAND_V2(0) } }, \ 1825 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_RAND_V1(0), FP64_RAND_V0(0), FP64_RAND_V2(1) } }, \ 1826 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V0), FP64_RAND_V1(0), FP64_RAND_V0(0), FP64_RAND_V2(1) } }, \ 1827 /*mxcsr:in */ 0, \ 1828 /*128:out */ X86_MXCSR_IE, \ 1829 /*256:out */ X86_MXCSR_IE, \ 1830 /*xcpt? */ true, true }, \ 1831 /* QNan, SNan (Unmasked). */ \ 1832 { { /*src2 */ { FP64_QNAN(0), FP64_RAND_V1(0), FP64_RAND_V3(1), FP64_RAND_V2(0) } }, \ 1833 { /*src1 */ { FP64_SNAN(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(0) } }, \ 1834 { /* => */ { FP64_QNAN(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(0) } }, \ 1835 /*mxcsr:in */ 0, \ 1836 /*128:out */ X86_MXCSR_IE, \ 1837 /*256:out */ X86_MXCSR_IE, \ 1838 /*xcpt? */ true, true }, \ 1839 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_RAND_V2(1), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, \ 1840 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, \ 1841 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, \ 1842 /*mxcsr:in */ 0, \ 1843 /*128:out */ X86_MXCSR_IE, \ 1844 /*256:out */ X86_MXCSR_IE, \ 1845 /*xcpt? */ true, true }, \ 1846 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_V0), FP64_RAND_V1(1), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, \ 1847 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_RAND_V3(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } }, \ 1848 { /* => */ { FP64_QNAN_V(0, FP64_FRAC_V0), FP64_RAND_V3(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } }, \ 1849 /*mxcsr:in */ 0, \ 1850 /*128:out */ X86_MXCSR_IE, \ 1851 /*256:out */ X86_MXCSR_IE, \ 1852 /*xcpt? */ true, true }, \ 1853 /* SNan, QNan (Unmasked). */ \ 1854 { { /*src2 */ { FP64_SNAN(0), FP64_RAND_V2(1), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, \ 1855 { /*src1 */ { FP64_QNAN(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, \ 1856 { /* => */ { FP64_SNAN(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, \ 1857 /*mxcsr:in */ X86_MXCSR_FZ, \ 1858 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_IE, \ 1859 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_IE, \ 1860 /*xcpt? */ true, true }, \ 1861 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_RAND_V1(1), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, \ 1862 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_RAND_V2(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, \ 1863 { /* => */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_RAND_V2(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, \ 1864 /*mxcsr:in */ 0, \ 1865 /*128:out */ X86_MXCSR_IE, \ 1866 /*256:out */ X86_MXCSR_IE, \ 1867 /*xcpt? */ true, true }, \ 1868 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_V1), FP64_RAND_V1(1), FP64_RAND_V0(1), FP64_RAND_V2(0) } }, \ 1869 { /*src1 */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } }, \ 1870 { /* => */ { FP64_SNAN_V(0, FP64_FRAC_V1), FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } }, \ 1871 /*mxcsr:in */ 0, \ 1872 /*128:out */ X86_MXCSR_IE, \ 1873 /*256:out */ X86_MXCSR_IE, \ 1874 /*xcpt? */ true, true }, \ 1875 /* SNan, SNan (Unmasked). */ \ 1876 { { /*src2 */ { FP64_SNAN(0), FP64_RAND_V1(1), FP64_RAND_V0(1), FP64_RAND_V2(0) } }, \ 1877 { /*src1 */ { FP64_SNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, \ 1878 { /* => */ { FP64_SNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, \ 1879 /*mxcsr:in */ 0, \ 1880 /*128:out */ X86_MXCSR_IE, \ 1881 /*256:out */ X86_MXCSR_IE, \ 1882 /*xcpt? */ true, true }, \ 1883 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_RAND_V1(0), FP64_RAND_V0(1), FP64_RAND_V2(1) } }, \ 1884 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_RAND_V0(0), FP64_RAND_V3(0), FP64_RAND_V0(1) } }, \ 1885 { /* => */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_RAND_V0(0), FP64_RAND_V3(0), FP64_RAND_V0(1) } }, \ 1886 /*mxcsr:in */ 0, \ 1887 /*128:out */ X86_MXCSR_IE, \ 1888 /*256:out */ X86_MXCSR_IE, \ 1889 /*xcpt? */ true, true }, \ 1890 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_V1), FP64_RAND_V1(1), FP64_RAND_V1(1), FP64_RAND_V2(0) } }, \ 1891 { /*src1 */ { FP64_SNAN_V(0, FP64_FRAC_V2), FP64_RAND_V2(1), FP64_RAND_V3(1), FP64_RAND_V1(1) } }, \ 1892 { /* => */ { FP64_SNAN_V(0, FP64_FRAC_V1), FP64_RAND_V2(1), FP64_RAND_V3(1), FP64_RAND_V1(1) } }, \ 1893 /*mxcsr:in */ 0, \ 1894 /*128:out */ X86_MXCSR_IE, \ 1895 /*256:out */ X86_MXCSR_IE, \ 1896 /*xcpt? */ true, true }, \ 1897 /* QNan, Normal (Unmasked). */ \ 1898 { { /*src2 */ { FP64_QNAN(0), FP64_RAND_V3(1), FP64_RAND_V2(1), FP64_RAND_V2(0) } }, \ 1899 { /*src1 */ { FP64_1(0), FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V1(1) } }, \ 1900 { /* => */ { FP64_QNAN(0), FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V1(1) } }, \ 1901 /*mxcsr:in */ 0, \ 1902 /*128:out */ X86_MXCSR_IE, \ 1903 /*256:out */ X86_MXCSR_IE, \ 1904 /*xcpt? */ true, true }, \ 1905 /* SNan, Normal (Masked). */ \ 1906 { { /*src2 */ { FP64_SNAN(1), FP64_RAND_V0(1), FP64_RAND_V2(1), FP64_RAND_V2(0) } }, \ 1907 { /*src1 */ { FP64_1(0), FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V3(1) } }, \ 1908 { /* => */ { FP64_SNAN(1), FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V3(1) } }, \ 1909 /*mxcsr:in */ 0, \ 1910 /*128:out */ X86_MXCSR_IE, \ 1911 /*256:out */ X86_MXCSR_IE, \ 1912 /*xcpt? */ true, true }, \ 1913 1914 1915 /** 1701 1916 * Returns the name of an X86 exception given the vector. 1702 1917 * … … 10961 11176 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, 10962 11177 /*xcpt? */ false, false }, 10963 /** @todo More Denormals. */ 10964 /** @todo Invalids. */ 11178 /** @todo More Denormals. */ 11179 /* 11180 * Invalids. 11181 */ 11182 /*56*/ FP64_TABLE_D9_SD_INVALIDS 10965 11183 }; 10966 11184
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