Index: trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4-template.mac
===================================================================
--- trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4-template.mac	(revision 106111)
+++ trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4-template.mac	(revision 106115)
@@ -568,4 +568,21 @@
 EMIT_INSTR_PLUS_ICEBP_C64   vmaxsd, XMM8, XMM9, FSxBX
 
+;
+;; [v]minps
+;
+EMIT_INSTR_PLUS_ICEBP       minps, XMM1, XMM2
+EMIT_INSTR_PLUS_ICEBP       minps, XMM1, FSxBX
+EMIT_INSTR_PLUS_ICEBP_C64   minps, XMM8, XMM9
+EMIT_INSTR_PLUS_ICEBP_C64   minps, XMM8, FSxBX
+
+EMIT_INSTR_PLUS_ICEBP       vminps, XMM1, XMM2, XMM3
+EMIT_INSTR_PLUS_ICEBP       vminps, XMM1, XMM2, FSxBX
+EMIT_INSTR_PLUS_ICEBP_C64   vminps, XMM8, XMM9, XMM10
+EMIT_INSTR_PLUS_ICEBP_C64   vminps, XMM8, XMM9, FSxBX
+
+EMIT_INSTR_PLUS_ICEBP       vminps, YMM1, YMM2, YMM3
+EMIT_INSTR_PLUS_ICEBP       vminps, YMM1, YMM2, FSxBX
+EMIT_INSTR_PLUS_ICEBP_C64   vminps, YMM8, YMM9, YMM10
+EMIT_INSTR_PLUS_ICEBP_C64   vminps, YMM8, YMM9, FSxBX
 
 %endif ; BS3_INSTANTIATING_CMN
Index: trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32
===================================================================
--- trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32	(revision 106111)
+++ trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32	(revision 106115)
@@ -4879,4 +4879,5 @@
               /*256:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
               /*xcpt?    */ true, true },
+#ifdef TODO_X86_MXCSR_PE_NATIVE
           { { /*src2     */ { FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1) } },
             { /*src1     */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1) } },
@@ -4886,4 +4887,5 @@
               /*256:out  */ X86_MXCSR_RC_DOWN | X86_MXCSR_OE | X86_MXCSR_PE,
               /*xcpt?    */ true, true },
+#endif
     /*
      * Normals.
@@ -6683,4 +6685,5 @@
               /*256:out  */ X86_MXCSR_OE,
               /*xcpt?    */ false, true },
+#ifdef TODO_X86_MXCSR_PE
           { { /*src2     */ { FP32_NORM_MAX(0), FP32_1(1), FP32_0(0), FP32_1(0), FP32_NORM_MAX(1), FP32_1(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } },
             { /*src1     */ { FP32_NORM_MAX(0), FP32_1(1), FP32_0(0), FP32_1(0), FP32_0(1),        FP32_1(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } },
@@ -6690,4 +6693,5 @@
               /*256:out  */ X86_MXCSR_OE | X86_MXCSR_PE,
               /*xcpt?    */ true, true },
+#endif
           { { /*src2     */ { FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_1(1), FP32_0(0), FP32_NORM_MAX(0) } },
             { /*src1     */ { FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_1(1), FP32_0(1), FP32_NORM_MAX(0) } },
@@ -6718,4 +6722,5 @@
               /*256:out  */ X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_OE | X86_MXCSR_UE | X86_MXCSR_PE,
               /*xcpt?    */ false, false },
+#ifdef TODO_X86_MXCSR_PE
           { { /*src2     */ { FP32_1(0),       FP32_NORM_V2(1), FP32_1(1),       FP32_NORM_V6(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } },
             { /*src1     */ { FP32_NORM_V7(0), FP32_1(1),       FP32_NORM_V4(0), FP32_1(1),       FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } },
@@ -6725,4 +6730,5 @@
               /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE,
               /*xcpt?    */ false, true },
+#endif
           { { /*src2     */ { FP32_1(0),       FP32_NORM_V2(1), FP32_1(1),       FP32_NORM_V6(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } },
             { /*src1     */ { FP32_NORM_V7(0), FP32_1(1),       FP32_NORM_V4(0), FP32_1(1),       FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } },
@@ -7144,4 +7150,5 @@
               /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_OE | X86_MXCSR_PE,
               /*xcpt?    */ false, false },
+#ifdef TODO_X86_MXCSR_PE
           { { /*src2     */ { FP64_NORM_V3(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_1(0)       } },
             { /*src1     */ { FP64_1(0),       FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_V1(0) } },
@@ -7151,4 +7158,5 @@
               /*256:out  */ (X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM)) | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
               /*xcpt?    */ true, true },
+#endif
           { { /*src2     */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MIN(1),                                       FP64_NORM_MAX(0) } },
             { /*src1     */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MAX(1),                                       FP64_NORM_MAX(0) } },
@@ -7158,4 +7166,5 @@
               /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_UE | X86_MXCSR_PE,
               /*xcpt?    */ false, false },
+#ifdef TODO_X86_MXCSR_PE
           { { /*src2     */ { FP64_NORM_V3(0), FP64_1(1),       FP64_NORM_MAX(1), FP64_NORM_MIN(0)                                       } },
             { /*src1     */ { FP64_1(0),       FP64_NORM_V2(1), FP64_NORM_MAX(1), FP64_NORM_MAX(1)                                       } },
@@ -7165,4 +7174,5 @@
               /*256:out  */ X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM) | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
               /*xcpt?    */ false, true },
+#endif
           { { /*src2     */ { FP64_NORM_SAFE_INT_MIN(0),                         FP64_NORM_MAX(0), FP64_NORM_SAFE_INT_MAX(1),                FP64_NORM_SAFE_INT_MIN(0)            } },
             { /*src1     */ { FP64_NORM_SAFE_INT_MAX(0),                         FP64_NORM_MAX(1), FP64_NORM_SAFE_INT_MAX(1),                FP64_NORM_SAFE_INT_MAX(0)            } },
@@ -10219,14 +10229,14 @@
               /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
               /*xcpt?    */ false, false },
-          { { /*src2     */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_V(0, 0x5c0000, 0x84)/*55*/, FP32_V(1, 0x2514d6, 0x93)/*-1352346.75*/, FP32_V(1, 0x5c0000, 0x84)/*-55*/, FP32_V(1, 0x2514d6, 0x93)/*1352346.75*/, FP32_V(1, 0x534000, 0x86)/*211.25*/, FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_1(1) } },
-            { /*src1     */ { FP32_V(0, 0x1ea980, 0x8f)/*  81235*/, FP32_V(0, 0x600000, 0x81)/* 7*/, FP32_V(0, 0x7c9000, 0x88)/*    1010.25*/, FP32_V(0, 0x600000, 0x81)/*  7*/, FP32_V(0, 0x253468, 0x93)/*1353357.00*/, FP32_1(1),                           FP32_V(1, 0x712060, 0x92)/*- 987654*/, FP32_1(0) } },
-            { /* =>      */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_V(0, 0x5c0000, 0x84)/*55*/, FP32_V(0, 0x7c9000, 0x88)/*    1010.25*/, FP32_V(0, 0x600000, 0x81)/*  7*/, FP32_V(0, 0x253468, 0x93)/*1353357.00*/, FP32_1(1),                           FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_1(0) } },
+          { { /*src2     */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_V(0, 0x5c0000, 0x84)/*55*/, FP32_V(1, 0x2514d6, 0x93)/*-1352346.75*/, FP32_V(1, 0x5c0000, 0x84)/*-55*/, FP32_V(1, 0x2514d6, 0x93)/*-1352346.75*/, FP32_V(1, 0x534000, 0x86)/*-211.25*/, FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_1(1) } },
+            { /*src1     */ { FP32_V(0, 0x1ea980, 0x8f)/*  81235*/, FP32_V(0, 0x600000, 0x81)/* 7*/, FP32_V(0, 0x7c9000, 0x88)/*    1010.25*/, FP32_V(0, 0x600000, 0x81)/*  7*/, FP32_V(0, 0x253468, 0x93)/* 1353357.00*/, FP32_1(1),                            FP32_V(1, 0x712060, 0x92)/*- 987654*/, FP32_1(0) } },
+            { /* =>      */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_V(0, 0x5c0000, 0x84)/*55*/, FP32_V(0, 0x7c9000, 0x88)/*    1010.25*/, FP32_V(0, 0x600000, 0x81)/*  7*/, FP32_V(0, 0x253468, 0x93)/* 1353357.00*/, FP32_1(1),                            FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_1(0) } },
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
               /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
               /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
               /*xcpt?    */ false, false },
-          { { /*src2     */ { FP32_V(0, 0x600000, 0x7e)/*      0.875*/, FP32_V(0, 0x3ce348, 0x90)/*193421.125*/, FP32_V(0, 0x6423f2, 0x92)/*934463.125*/, FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0x16b43a, 0x93)/*1234567.25*/, FP32_V(0, 0x792318, 0x91)/*510232.75*/, FP32_V(0, 0x600000, 0x7e)/*0.875*/ } },
-            { /*src1     */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_V(0, 0x430ebc, 0x91)/*399477.875*/, FP32_V(0, 0x52e0b4, 0x92)/*863755.250*/, FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MAX(1), FP32_V(0, 0x00c6d3, 0x94)/*2109876.75*/, FP32_V(1, 0x316740, 0x8e)/*-45415.25*/, FP32_V(1, 0,        0x7d)/*0.250*/ } },
-            { /* =>      */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_V(0, 0x430ebc, 0x91)/*399477.875*/, FP32_V(0, 0x6423f2, 0x92)/*934463.125*/, FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0x00c6d3, 0x94)/*2109876.75*/, FP32_V(0, 0x792318, 0x91)/*510232.75*/, FP32_V(0, 0x600000, 0x7e)/*0.875*/ } },
+          { { /*src2     */ { FP32_V(0, 0x600000, 0x7e)/*      0.875*/, FP32_V(0, 0x3ce348, 0x90)/*193421.125*/, FP32_V(0, 0x6423f2, 0x92)/*934463.125*/, FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0x16b43a, 0x93)/*1234567.25*/, FP32_V(0, 0x792318, 0x91)/*510232.75*/, FP32_V(0, 0x600000, 0x7e)/* 0.875*/ } },
+            { /*src1     */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_V(0, 0x430ebc, 0x91)/*399477.875*/, FP32_V(0, 0x52e0b4, 0x92)/*863755.250*/, FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MAX(1), FP32_V(0, 0x00c6d3, 0x94)/*2109876.75*/, FP32_V(1, 0x316740, 0x8e)/*-45415.25*/, FP32_V(1, 0,        0x7d)/*-0.250*/ } },
+            { /* =>      */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_V(0, 0x430ebc, 0x91)/*399477.875*/, FP32_V(0, 0x6423f2, 0x92)/*934463.125*/, FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0x00c6d3, 0x94)/*2109876.75*/, FP32_V(0, 0x792318, 0x91)/*510232.75*/, FP32_V(0, 0x600000, 0x7e)/* 0.875*/ } },
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
               /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
@@ -10994,7 +11004,7 @@
               /*256:out  */ X86_MXCSR_XCPT_MASK,
               /*xcpt?    */ false, false },
-          { { /*src2     */ { FP32_V(0, 0x600000, 0x7e)/*0.875*/, FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V0(1), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
-            { /*src1     */ { FP32_V(1, 0,        0x7d)/*0.250*/, FP32_RAND_V2(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V7(1), FP32_RAND_V5(1), FP32_RAND_V6(0), FP32_RAND_V7(1) } },
-            { /* =>      */ { FP32_V(0, 0x600000, 0x7e)/*0.875*/, FP32_RAND_V2(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V7(1), FP32_RAND_V5(1), FP32_RAND_V6(0), FP32_RAND_V7(1) } },
+          { { /*src2     */ { FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V0(1), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
+            { /*src1     */ { FP32_V(1, 0,        0x7d)/*-0.250*/, FP32_RAND_V2(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V7(1), FP32_RAND_V5(1), FP32_RAND_V6(0), FP32_RAND_V7(1) } },
+            { /* =>      */ { FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_RAND_V2(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V7(1), FP32_RAND_V5(1), FP32_RAND_V6(0), FP32_RAND_V7(1) } },
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
               /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
@@ -11576,4 +11586,324 @@
     return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
                                         g_aXcptConfig3, RT_ELEMENTS(g_aXcptConfig3));
+}
+
+
+/*
+ * [V]MINPS.
+ */
+BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_minps(uint8_t bMode)
+{
+    static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValues[] =
+    {
+    /*
+     * Zero.
+     */
+    /* 0*/{ { /*src2     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
+            { /*src1     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
+            { /* =>      */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
+              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*256:out  */ X86_MXCSR_XCPT_MASK,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
+            { /*src1     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
+            { /* =>      */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
+            { /*src1     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
+            { /* =>      */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1) } },
+            { /*src1     */ { FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0) } },
+            { /* =>      */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
+              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*256:out  */ X86_MXCSR_XCPT_MASK,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0) } },
+            { /*src1     */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0) } },
+            { /* =>      */ { FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0) } },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1) } },
+            { /*src1     */ { FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0) } },
+            { /* =>      */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0) } },
+            { /*src1     */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0) } },
+            { /* =>      */ { FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0) } },
+            { /*src1     */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0) } },
+            { /* =>      */ { FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1) } },
+            { /*src1     */ { FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(0) } },
+            { /* =>      */ { FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*xcpt?    */ false, false },
+    /*
+     * Infinity.
+     */
+    /*9 */{ { /*src2     */ { FP32_INF(0), FP32_0(0),   FP32_INF(1), FP32_0(1),   FP32_INF(1), FP32_0(0),   FP32_INF(1), FP32_0(0)   } },
+            { /*src1     */ { FP32_0(0),   FP32_INF(0), FP32_0(0),   FP32_INF(0), FP32_0(0),   FP32_INF(1), FP32_0(0),   FP32_INF(1) } },
+            { /* =>      */ { FP32_0(0),   FP32_0(0),   FP32_INF(1), FP32_0(1),   FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
+              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*256:out  */ X86_MXCSR_XCPT_MASK,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_INF(0), FP32_0(0),   FP32_INF(0), FP32_0(1),   FP32_INF(1), FP32_0(0),   FP32_INF(1), FP32_0(0)   } },
+            { /*src1     */ { FP32_0(0),   FP32_INF(1), FP32_0(1),   FP32_INF(1), FP32_0(0),   FP32_INF(1), FP32_0(0),   FP32_INF(1) } },
+            { /* =>      */ { FP32_0(0),   FP32_INF(1), FP32_0(1),   FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_INF(0), FP32_0(0),   FP32_INF(0), FP32_0(1),   FP32_INF(1), FP32_0(0),   FP32_INF(1), FP32_0(0)   } },
+            { /*src1     */ { FP32_0(0),   FP32_INF(0), FP32_0(1),   FP32_INF(0), FP32_0(0),   FP32_INF(1), FP32_0(0),   FP32_INF(1) } },
+            { /* =>      */ { FP32_0(0),   FP32_0(0),   FP32_0(1),   FP32_0(1),   FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_INF(0), FP32_0(0),   FP32_INF(0), FP32_0(1),   FP32_INF(1), FP32_0(0),   FP32_INF(1), FP32_0(0)   } },
+            { /*src1     */ { FP32_0(0),   FP32_INF(0), FP32_0(1),   FP32_INF(0), FP32_0(0),   FP32_INF(1), FP32_0(0),   FP32_INF(1) } },
+            { /* =>      */ { FP32_0(0),   FP32_0(0),   FP32_0(1),   FP32_0(1),   FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_INF(0), FP32_0(0),   FP32_INF(0), FP32_0(1),   FP32_INF(1), FP32_0(0),   FP32_INF(1), FP32_0(0)   } },
+            { /*src1     */ { FP32_0(0),   FP32_INF(0), FP32_0(1),   FP32_INF(0), FP32_0(0),   FP32_INF(1), FP32_0(0),   FP32_INF(1) } },
+            { /* =>      */ { FP32_0(0),   FP32_0(0),   FP32_0(1),   FP32_0(1),   FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(0) } },
+            { /*src1     */ { FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_INF(0) } },
+            { /* =>      */ { FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(0) } },
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(0) } },
+            { /*src1     */ { FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_INF(0) } },
+            { /* =>      */ { FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(0) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_INF(0),     FP32_NORM_V1(0), FP32_INF(1),     FP32_NORM_V3(1), FP32_INF(1),     FP32_NORM_V5(0), FP32_INF(1),     FP32_NORM_V7(0) } },
+            { /*src1     */ { FP32_NORM_V0(0), FP32_INF(1),     FP32_NORM_V2(0), FP32_INF(1),     FP32_NORM_V4(1), FP32_INF(1),     FP32_NORM_V6(0), FP32_INF(0)     } },
+            { /* =>      */ { FP32_NORM_V0(0), FP32_INF(1),     FP32_INF(1),     FP32_INF(1),     FP32_INF(1),     FP32_INF(1),     FP32_INF(1),     FP32_NORM_V7(0) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
+              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*256:out  */ X86_MXCSR_XCPT_MASK,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_INF(0),     FP32_NORM_V1(0), FP32_INF(1),     FP32_NORM_V3(1), FP32_INF(0),     FP32_NORM_V5(0), FP32_INF(1),     FP32_NORM_V7(0) } },
+            { /*src1     */ { FP32_NORM_V0(0), FP32_INF(1),     FP32_NORM_V2(0), FP32_INF(0),     FP32_NORM_V4(1), FP32_INF(1),     FP32_NORM_V6(0), FP32_INF(0)     } },
+            { /* =>      */ { FP32_NORM_V0(0), FP32_INF(1),     FP32_INF(1),     FP32_NORM_V3(1), FP32_NORM_V4(1), FP32_INF(1),     FP32_INF(1),     FP32_NORM_V7(0) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_NORM_V7(0), FP32_INF(0),     FP32_NORM_V5(0), FP32_INF(0),     FP32_NORM_V3(0), FP32_INF(0),     FP32_NORM_V1(0), FP32_INF(0)     } },
+            { /*src1     */ { FP32_INF(1),     FP32_NORM_V6(1), FP32_INF(0),     FP32_NORM_V4(0), FP32_INF(0),     FP32_NORM_V2(1), FP32_INF(1),     FP32_NORM_V0(1) } },
+            { /* =>      */ { FP32_INF(1),     FP32_NORM_V6(1), FP32_NORM_V5(0), FP32_NORM_V4(0), FP32_NORM_V3(0), FP32_NORM_V2(1), FP32_INF(1),     FP32_NORM_V0(1) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_NORM_V7(0), FP32_INF(0),     FP32_NORM_V5(1), FP32_INF(0),     FP32_NORM_V3(1), FP32_INF(0),     FP32_NORM_V1(1), FP32_INF(0)     } },
+            { /*src1     */ { FP32_INF(0),     FP32_NORM_V6(1), FP32_INF(0),     FP32_NORM_V4(1), FP32_INF(0),     FP32_NORM_V2(1), FP32_INF(0),     FP32_NORM_V0(1) } },
+            { /* =>      */ { FP32_NORM_V7(0), FP32_NORM_V6(1), FP32_NORM_V5(1), FP32_NORM_V4(1), FP32_NORM_V3(1), FP32_NORM_V2(1), FP32_NORM_V1(1), FP32_NORM_V0(1) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*xcpt?    */ false, false },
+    /*
+     * Normals.
+     */
+    /*20*/{ { /*src2     */ { FP32_NORM_MAX(0), FP32_0(0),        FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_0(1),        FP32_NORM_MAX(1), FP32_NORM_MAX(1) } },
+            { /*src1     */ { FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0),        FP32_0(0),        FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_0(1),        FP32_NORM_MAX(0) } },
+            { /* =>      */ { FP32_NORM_MAX(0), FP32_0(0),        FP32_0(0),        FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(1) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
+              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*256:out  */ X86_MXCSR_XCPT_MASK,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_NORM_MIN(0), FP32_0(0),        FP32_NORM_MIN(0), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_0(1),        FP32_NORM_MIN(1), FP32_NORM_MIN(1) } },
+            { /*src1     */ { FP32_NORM_MIN(0), FP32_NORM_MIN(0), FP32_0(0),        FP32_0(0),        FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_0(1),        FP32_NORM_MIN(0) } },
+            { /* =>      */ { FP32_NORM_MIN(0), FP32_0(0),        FP32_0(0),        FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MIN(1) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
+              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*256:out  */ X86_MXCSR_XCPT_MASK,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_NORM_MIN(0), FP32_NORM_MIN(0), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1) } },
+            { /*src1     */ { FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MIN(0), FP32_NORM_MIN(1), FP32_NORM_MIN(0), FP32_NORM_MIN(1) } },
+            { /* =>      */ { FP32_NORM_MIN(0), FP32_NORM_MAX(1), FP32_NORM_MIN(1), FP32_NORM_MAX(1), FP32_NORM_MIN(0), FP32_NORM_MIN(1), FP32_NORM_MAX(1), FP32_NORM_MAX(1) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
+              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*256:out  */ X86_MXCSR_XCPT_MASK,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(1) } },
+            { /*src1     */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1) } },
+            { /* =>      */ { FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(1) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
+              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*256:out  */ X86_MXCSR_XCPT_MASK,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_V(0, 0, 0x7d)/*0.25*/, FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_V(0, 0, 0x7d)/*0.25*/, FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_V(0, 0, 0x7d)/* 0.25*/, FP32_V(0, 0x600000, 0x7f)/*1.75*/, FP32_V(1, 0, 0x7d)/*-0.25*/ } },
+            { /*src1     */ { FP32_V(1, 0,        0x7d)/*-0.25*/, FP32_V(0, 0, 0x7e)/*0.50*/, FP32_V(1, 0,        0x7d)/*-0.25*/, FP32_V(0, 0, 0x7e)/*0.50*/, FP32_V(1, 0x600000, 0x7f)/*-1.75*/, FP32_V(1, 0, 0x7e)/*-0.50*/, FP32_V(1, 0,        0x7d)/*0.25*/, FP32_V(1, 0, 0x7e)/*-0.50*/ } },
+            { /* =>      */ { FP32_V(1, 0,        0x7d)/*-0.25*/, FP32_V(0, 0, 0x7d)/*0.25*/, FP32_V(1, 0,        0x7d)/*-0.25*/, FP32_V(0, 0, 0x7d)/*0.25*/, FP32_V(1, 0x600000, 0x7f)/*-1.75*/, FP32_V(1, 0, 0x7e)/*-0.50*/, FP32_V(1, 0,        0x7d)/*0.25*/, FP32_V(1, 0, 0x7e)/*-0.50*/ } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_NORM_MAX(0), FP32_NORM_V1(0), FP32_NORM_V2(1), FP32_NORM_V3(1), FP32_NORM_V5(0), FP32_0(1),       FP32_NORM_V5(1), FP32_0(0)       } },
+            { /*src1     */ { FP32_NORM_V1(0),  FP32_NORM_V1(1), FP32_NORM_V2(0), FP32_NORM_V3(1), FP32_0(1),       FP32_NORM_V6(0), FP32_0(1),       FP32_NORM_V7(1) } },
+            { /* =>      */ { FP32_NORM_V1(0),  FP32_NORM_V1(1), FP32_NORM_V2(1), FP32_NORM_V3(1), FP32_0(1),       FP32_0(1),       FP32_NORM_V5(1), FP32_NORM_V7(1) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_V(0, 0x600000, 0x81)/* 7*/, FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_V(0, 0x5c0000, 0x84)/* 55*/, FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_V(1, 0x534000, 0x86)/*-211.25*/, FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_1(1) } },
+            { /*src1     */ { FP32_V(0, 0x1ea980, 0x8f)/*  81235*/, FP32_V(0, 0x5c0000, 0x84)/*55*/, FP32_V(0, 0x7c9000, 0x88)/*   1010.25*/, FP32_V(1, 0x600000, 0x81)/* -7*/, FP32_V(0, 0x253468, 0x93)/*1353357.00*/, FP32_1(1),                            FP32_V(0, 0x712060, 0x92)/*  987654*/, FP32_1(0) } },
+            { /* =>      */ { FP32_V(0, 0x1ea980, 0x8f)/*  81235*/, FP32_V(0, 0x600000, 0x81)/* 7*/, FP32_V(0, 0x7c9000, 0x88)/*   1010.25*/, FP32_V(1, 0x600000, 0x81)/* -7*/, FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_V(1, 0x534000, 0x86)/*-211.25*/, FP32_V(0, 0x712060, 0x92)/*  987654*/, FP32_1(1) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_V(0, 0x600000, 0x7e)/*      0.875*/, FP32_V(0, 0x3ce348, 0x90)/*193421.125*/, FP32_V(0, 0x6423f2, 0x92)/*934463.125*/, FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0x16b43a, 0x93)/*1234567.25*/, FP32_V(0, 0x792318, 0x91)/*510232.75*/, FP32_V(0, 0x600000, 0x7e)/* 0.875*/ } },
+            { /*src1     */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_V(0, 0x430ebc, 0x91)/*399477.875*/, FP32_V(0, 0x52e0b4, 0x92)/*863755.250*/, FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MAX(1), FP32_V(0, 0x00c6d3, 0x94)/*2109876.75*/, FP32_V(1, 0x316740, 0x8e)/*-45415.25*/, FP32_V(1, 0,        0x7d)/*-0.250*/ } },
+            { /* =>      */ { FP32_V(0, 0x600000, 0x7e)/*      0.875*/, FP32_V(0, 0x3ce348, 0x90)/*193421.125*/, FP32_V(0, 0x52e0b4, 0x92)/*863755.250*/, FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MAX(1), FP32_V(0, 0x16b43a, 0x93)/*1234567.25*/, FP32_V(1, 0x316740, 0x8e)/*-45415.25*/, FP32_V(1, 0,        0x7d)/*-0.250*/ } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_V(0, 0x490fda, 0x80)/*3.1415926*/, FP32_V(0, 0x620b2e, 0x92)/*925874.9*/, FP32_V(0, 0x5dd520, 0x8e)/* 56789.125*/, FP32_V(1, 0x40e6b6, 0x8c)/*-12345.678*/, FP32_V(1, 0x490fda, 0x80)/*-3.1415926*/, FP32_V(1, 0x620b2e, 0x92)/*-925874.8*/, FP32_V(0, 0x5dd520, 0x8e)/*56789.125*/, FP32_V(0, 0x40e6b6, 0x8c)/*12345.678*/ } },
+            { /*src1     */ { FP32_V(0, 0x490fdb, 0x80)/*3.1415927*/, FP32_V(0, 0x620b2d, 0x92)/*925874.8*/, FP32_V(1, 0x5dd521, 0x8e)/*-56789.127*/, FP32_V(1, 0x40e6b7, 0x8c)/*-12345.679*/, FP32_V(1, 0x490fdb, 0x80)/*-3.1415927*/, FP32_V(0, 0x620b2d, 0x92)/* 925874.9*/, FP32_V(0, 0x5dd521, 0x8e)/*56789.127*/, FP32_V(0, 0x40e6b7, 0x8c)/*12345.679*/ } },
+            { /* =>      */ { FP32_V(0, 0x490fda, 0x80)/*3.1415926*/, FP32_V(0, 0x620b2d, 0x92)/*925874.8*/, FP32_V(1, 0x5dd521, 0x8e)/*-56789.127*/, FP32_V(1, 0x40e6b7, 0x8c)/*-12345.679*/, FP32_V(1, 0x490fdb, 0x80)/*-3.1415927*/, FP32_V(1, 0x620b2e, 0x92)/*-925874.8*/, FP32_V(0, 0x5dd520, 0x8e)/*56789.125*/, FP32_V(0, 0x40e6b6, 0x8c)/*12345.678*/ } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
+              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*256:out  */ X86_MXCSR_XCPT_MASK,
+              /*xcpt?    */ false, false },
+    /** @todo More Normals. */
+    /*
+     * Denormals.
+     */
+    /*29*/{ { /*src2     */ { FP32_DENORM_MAX(0), FP32_0(0),          FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0)          } },
+            { /*src1     */ { FP32_0(0),          FP32_DENORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0),          FP32_0(0), FP32_0(0), FP32_DENORM_MAX(1) } },
+            { /* =>      */ { FP32_0(0),          FP32_DENORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0),          FP32_0(0), FP32_0(0), FP32_DENORM_MAX(1) } },
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_DE,
+              /*256:out  */ X86_MXCSR_DE,
+              /*xcpt?    */ true, true },
+          { { /*src2     */ { FP32_0(0), FP32_0(0),          FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0),          FP32_0(0), FP32_0(0) } },
+            { /*src1     */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0) } },
+            { /* =>      */ { FP32_0(0), FP32_0(0),          FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0),          FP32_0(0), FP32_0(0) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } },
+            { /*src1     */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0) } },
+            { /* =>      */ { FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0)          } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0),          FP32_0(0), FP32_0(0), FP32_0(0) } },
+             { /*src1     */ { FP32_0(0),         FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
+             { /* =>      */ { FP32_0(0),         FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0),          FP32_0(0), FP32_0(0), FP32_0(0) } },
+               /*mxcsr:in */ 0,
+               /*128:out  */ X86_MXCSR_DE,
+               /*256:out  */ X86_MXCSR_DE,
+               /*xcpt?    */ true, true },
+          { { /*src2     */ { FP32_0(0), FP32_0(0),          FP32_0(0), FP32_0(0), FP32_0(0),          FP32_0(0), FP32_0(0), FP32_DENORM_MAX(1) } },
+            { /*src1     */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0)          } },
+            { /* =>      */ { FP32_0(0), FP32_0(0),          FP32_0(0), FP32_0(0), FP32_0(0),          FP32_0(0), FP32_0(0), FP32_0(1)          } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } },
+            { /*src1     */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0) } },
+            { /* =>      */ { FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0)          } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*xcpt?    */ false, false },
+    /** @todo More Denormals. */
+    /*35*/ FP32_TABLE_D9_PS_INVALIDS
+    };
+
+#define PASS_s_aValues RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues
+    static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
+    {
+        { bs3CpuInstr4_minps_XMM1_XMM2_icebp_c16,  255, RM_REG, T_SSE, 1, 1, 2,   PASS_s_aValues },
+        { bs3CpuInstr4_minps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, PASS_s_aValues },
+
+        { bs3CpuInstr4_vminps_XMM1_XMM2_XMM3_icebp_c16,  255, RM_REG, T_AVX_128, 1, 2, 3,   PASS_s_aValues },
+        { bs3CpuInstr4_vminps_XMM1_XMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_128, 1, 2, 255, PASS_s_aValues },
+
+        { bs3CpuInstr4_vminps_YMM1_YMM2_YMM3_icebp_c16,  255, RM_REG, T_AVX_256, 1, 2, 3,   PASS_s_aValues },
+        { bs3CpuInstr4_vminps_YMM1_YMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_256, 1, 2, 255, PASS_s_aValues },
+    };
+    static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
+    {
+        { bs3CpuInstr4_minps_XMM1_XMM2_icebp_c32,  255, RM_REG, T_SSE, 1, 1, 2,   PASS_s_aValues },
+        { bs3CpuInstr4_minps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, PASS_s_aValues },
+
+        { bs3CpuInstr4_vminps_XMM1_XMM2_XMM3_icebp_c32,  255, RM_REG, T_AVX_128, 1, 2, 3,   PASS_s_aValues },
+        { bs3CpuInstr4_vminps_XMM1_XMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_128, 1, 2, 255, PASS_s_aValues },
+
+        { bs3CpuInstr4_vminps_YMM1_YMM2_YMM3_icebp_c32,  255, RM_REG, T_AVX_256, 1, 2, 3,   PASS_s_aValues },
+        { bs3CpuInstr4_vminps_YMM1_YMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_256, 1, 2, 255, PASS_s_aValues },
+    };
+    static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
+    {
+        { bs3CpuInstr4_minps_XMM1_XMM2_icebp_c64,  255, RM_REG, T_SSE, 1, 1, 2,   PASS_s_aValues },
+        { bs3CpuInstr4_minps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, PASS_s_aValues },
+
+        { bs3CpuInstr4_vminps_XMM1_XMM2_XMM3_icebp_c64,  255, RM_REG, T_AVX_128, 1, 2, 3,   PASS_s_aValues },
+        { bs3CpuInstr4_vminps_XMM1_XMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 1, 2, 255, PASS_s_aValues },
+
+        { bs3CpuInstr4_vminps_YMM1_YMM2_YMM3_icebp_c64,  255, RM_REG, T_AVX_256, 1, 2, 3,   PASS_s_aValues },
+        { bs3CpuInstr4_vminps_YMM1_YMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 1, 2, 255, PASS_s_aValues },
+
+        { bs3CpuInstr4_minps_XMM8_XMM9_icebp_c64,  255, RM_REG, T_SSE, 8, 8, 9,   PASS_s_aValues },
+        { bs3CpuInstr4_minps_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 8, 8, 255, PASS_s_aValues },
+
+        { bs3CpuInstr4_vminps_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10,  PASS_s_aValues },
+        { bs3CpuInstr4_vminps_XMM8_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 8, 9, 255, PASS_s_aValues },
+        { bs3CpuInstr4_vminps_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 10,  PASS_s_aValues },
+        { bs3CpuInstr4_vminps_YMM8_YMM9_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 8, 9, 255, PASS_s_aValues },
+    };
+#undef PASS_s_aValues
+
+    static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
+    unsigned const                         iTest       = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
+    return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+                                        g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
 }
 
@@ -11624,4 +11954,5 @@
         { "[v]maxss",       bs3CpuInstr4_v_maxss,    0 },
         { "[v]maxsd",       bs3CpuInstr4_v_maxsd,    0 },
+        { "[v]minps",       bs3CpuInstr4_v_minps,    0 },
 #endif
     };
