Index: trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4-template.mac
===================================================================
--- trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4-template.mac	(revision 106115)
+++ trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4-template.mac	(revision 106132)
@@ -586,4 +586,23 @@
 EMIT_INSTR_PLUS_ICEBP_C64   vminps, YMM8, YMM9, FSxBX
 
+;
+;; [v]sqrtps
+;
+EMIT_INSTR_PLUS_ICEBP       sqrtps, XMM1, XMM2
+EMIT_INSTR_PLUS_ICEBP       sqrtps, XMM1, FSxBX
+EMIT_INSTR_PLUS_ICEBP_C64   sqrtps, XMM8, XMM9
+EMIT_INSTR_PLUS_ICEBP_C64   sqrtps, XMM8, FSxBX
+
+EMIT_INSTR_PLUS_ICEBP       vsqrtps, XMM1, XMM2
+EMIT_INSTR_PLUS_ICEBP       vsqrtps, XMM1, FSxBX
+EMIT_INSTR_PLUS_ICEBP_C64   vsqrtps, XMM8, XMM9
+EMIT_INSTR_PLUS_ICEBP_C64   vsqrtps, XMM8, FSxBX
+
+EMIT_INSTR_PLUS_ICEBP       vsqrtps, YMM1, YMM2
+EMIT_INSTR_PLUS_ICEBP       vsqrtps, YMM1, FSxBX
+EMIT_INSTR_PLUS_ICEBP_C64   vsqrtps, YMM8, YMM9
+EMIT_INSTR_PLUS_ICEBP_C64   vsqrtps, YMM8, FSxBX
+
+
 %endif ; BS3_INSTANTIATING_CMN
 
Index: trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32
===================================================================
--- trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32	(revision 106115)
+++ trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32	(revision 106132)
@@ -8365,5 +8365,5 @@
              /*xcpt?    */ false, false },
 #ifdef TODO_X86_MXCSR_UE /** @todo THIS FAILS ON IEM: X86_MXCSR_UE not set in 256:out */
- /*--/22*/{ { /*src2     */ { FP64_1(0), FP64_1(1), FP64_1(0),          FP64_1(0)          } },
+ /*--|22*/{ { /*src2     */ { FP64_1(0), FP64_1(1), FP64_1(0),          FP64_1(0)          } },
             { /*src1     */ { FP64_0(0), FP64_0(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0) } },
             { /* =>      */ { FP64_0(0), FP64_0(1), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0) } },
@@ -8373,5 +8373,5 @@
              /*xcpt?    */ false, true },
 #endif /* TODO_X86_MXCSR_UE */
- /*22/23*/{ { /*src2     */ { FP64_1(0),          FP64_1(0),          FP64_DENORM_MIN(0), FP64_DENORM_MAX(0) } },
+ /*22|23*/{ { /*src2     */ { FP64_1(0),          FP64_1(0),          FP64_DENORM_MIN(0), FP64_DENORM_MAX(0) } },
             { /*src1     */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_0(0),          FP64_1(1)          } },
             { /* =>      */ { FP64_0(0),          FP64_0(0),          FP64_QNAN(1),       FP64_INF(1)        } },
@@ -11909,4 +11909,387 @@
 
 
+/*
+ * [V]SQRTPS.
+ */
+BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_sqrtps(uint8_t bMode)
+{
+#define FP32_x8_UNUSED FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0)
+    static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValues[] =
+    {
+    /*
+     * Zero.
+     */
+    /* 0*/{ { /*src1     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1) } },
+            { /*unused   */ { FP32_x8_UNUSED } },
+            { /* =>      */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
+              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*256:out  */ X86_MXCSR_XCPT_MASK,
+              /*xcpt?    */ false, false },
+          { { /*src1     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1) } },
+            { /*unused   */ { FP32_x8_UNUSED } },
+            { /* =>      */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1) } },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0,
+              /*xcpt?    */ false, false },
+          { { /*src1     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1) } },
+            { /*unused   */ { FP32_x8_UNUSED } },
+            { /* =>      */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1) } },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*xcpt?    */ false, false },
+          { { /*src1     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1) } },
+            { /*unused   */ { FP32_x8_UNUSED } },
+            { /* =>      */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1) } },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_RC_ZERO,
+              /*xcpt?    */ false, false },
+          { { /*src1     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1) } },
+            { /*unused   */ { FP32_x8_UNUSED } },
+            { /* =>      */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*xcpt?    */ false, false },
+    /*
+     * Infinity.
+     */
+    /* 5*/{ { /*src1     */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1),  FP32_0(0), FP32_0(0), FP32_0(0) } },
+            { /*unused   */ { FP32_x8_UNUSED } },
+            { /* =>      */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN(1), FP32_0(0), FP32_0(0), FP32_0(0) } },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ X86_MXCSR_IE,
+              /*xcpt?    */ false, true },
+          { { /*src1     */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1),  FP32_0(0), FP32_0(0), FP32_0(0) } },
+            { /*unused   */ { FP32_x8_UNUSED } },
+            { /* =>      */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN(1), FP32_0(0), FP32_0(0), FP32_0(0) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
+              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
+              /*xcpt?    */ false, false },
+    /*
+     * Precision (Overflow, Underflow not possible).
+     */
+    /* 7*/{ { /*src1     */ { FP32_0(0), FP32_1(0), FP32_1(0), FP32_0(1), FP32_1(0), FP32_0(0), FP32_1(0), FP32_2(0)                            } },
+            { /*unused   */ { FP32_x8_UNUSED } },
+            { /* =>      */ { FP32_0(0), FP32_1(0), FP32_1(0), FP32_0(1), FP32_1(0), FP32_0(0), FP32_1(0), FP32_V(0, 0x3504f3, 0x7f)/*sqrt(2)*/ } },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ X86_MXCSR_PE,
+              /*xcpt?    */ false, true },
+          { { /*src1     */ { FP32_0(0), FP32_1(0), FP32_1(0), FP32_0(1), FP32_1(0), FP32_0(0), FP32_1(0), FP32_2(0)                            } },
+            { /*unused   */ { FP32_x8_UNUSED } },
+            { /* =>      */ { FP32_0(0), FP32_1(0), FP32_1(0), FP32_0(1), FP32_1(0), FP32_0(0), FP32_1(0), FP32_V(0, 0x3504f3, 0x7f)/*sqrt(2)*/ } },
+              /*mxcsr:in */ X86_MXCSR_PM,
+              /*128:out  */ X86_MXCSR_PM,
+              /*256:out  */ X86_MXCSR_PM | X86_MXCSR_PE,
+              /*xcpt?    */ false, false },
+          { { /*src1     */ { FP32_0(0), FP32_1(0), FP32_1(0), FP32_0(1), FP32_1(0), FP32_0(0), FP32_1(0), FP32_2(0)                            } },
+            { /*unused   */ { FP32_x8_UNUSED } },
+            { /* =>      */ { FP32_0(0), FP32_1(0), FP32_1(0), FP32_0(1), FP32_1(0), FP32_0(0), FP32_1(0), FP32_V(0, 0x3504f3, 0x7f)/*sqrt(2)*/ } },
+              /*mxcsr:in */ X86_MXCSR_PM | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_PM | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_PM | X86_MXCSR_RC_DOWN | X86_MXCSR_PE,
+              /*xcpt?    */ false, false },
+          { { /*src1     */ { FP32_0(0), FP32_1(0), FP32_1(0), FP32_0(1), FP32_1(0), FP32_0(0), FP32_1(0), FP32_2(0)                             } },
+            { /*unused   */ { FP32_x8_UNUSED } },
+            { /* =>      */ { FP32_0(0), FP32_1(0), FP32_1(0), FP32_0(1), FP32_1(0), FP32_0(0), FP32_1(0), FP32_V(0, 0x3504f4, 0x7f)/*sqrt^(2)*/ } },
+              /*mxcsr:in */ X86_MXCSR_PM | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_PM | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_PE,
+              /*xcpt?    */ false, false },
+          { { /*src1     */ { FP32_0(0), FP32_1(0), FP32_1(0), FP32_0(1), FP32_1(0), FP32_0(0), FP32_1(0), FP32_2(0)                            } },
+            { /*unused   */ { FP32_x8_UNUSED } },
+            { /* =>      */ { FP32_0(0), FP32_1(0), FP32_1(0), FP32_0(1), FP32_1(0), FP32_0(0), FP32_1(0), FP32_V(0, 0x3504f3, 0x7f)/*sqrt(2)*/ } },
+              /*mxcsr:in */ X86_MXCSR_PM | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_PM | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
+              /*xcpt?    */ false, false },
+          { { /*src1     */ { FP32_0(0), FP32_1(0), FP32_1(0), FP32_0(1), FP32_1(0), FP32_0(0), FP32_1(0), FP32_2(0)                            } },
+            { /*unused   */ { FP32_x8_UNUSED } },
+            { /* =>      */ { FP32_0(0), FP32_1(0), FP32_1(0), FP32_0(1), FP32_1(0), FP32_0(0), FP32_1(0), FP32_V(0, 0x3504f3, 0x7f)/*sqrt(2)*/ } },
+              /*mxcsr:in */ X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_DAZ,
+              /*128:out  */ X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_DAZ,
+              /*256:out  */ X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_DAZ | X86_MXCSR_PE,
+              /*xcpt?    */ false, false },
+    /*
+     * Normals.
+     */
+    /*13*/{ { /*src1     */ { FP32_NORM_V0(0), FP32_NORM_V1(0), FP32_NORM_V2(0), FP32_NORM_V3(0), FP32_NORM_V4(0), FP32_NORM_V5(0), FP32_NORM_V6(0), FP32_NORM_V7(0) } },
+            { /*unused   */ { FP32_x8_UNUSED } },
+            { /* =>      */ { FP32_V(0,0x1ccf5c,0x40)/*sqrt(FP32_NORM_V0)*/,
+                              FP32_V(0,0x293fdb,0x97)/*sqrt(FP32_NORM_V1)*/,
+                              FP32_V(0,0x3455c7,0x7e)/*sqrt(FP32_NORM_V2)*/,
+                              FP32_V(0,0x27905f,0xbe)/*sqrt(FP32_NORM_V3)*/,
+                              FP32_V(0,0x49278b,0x9d)/*sqrt(FP32_NORM_V4)*/,
+                              FP32_V(0,0x009150,0xa8)/*sqrt(FP32_NORM_V5)*/,
+                              FP32_V(0,0x561776,0x5d)/*sqrt(FP32_NORM_V6)*/,
+                              FP32_V(0,0x3504f3,0x68)/*sqrt(FP32_NORM_V7)*/ } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_PE,
+              /*xcpt?    */ false, false },
+          { { /*src1     */ { FP32_V(0,0x44000,0x88)/*529.0*/,
+                              FP32_V(0,0x0,0x87)/*256.0*/,
+                              FP32_V(0,0x440000,0x7c)/*(7/16)^2*/,
+                              FP32_V(0,0x6f4840,0x8c)/*123.75^2*/,
+                              FP32_V(0,0x40000,0x88)/*528.0*/,
+                              FP32_V(0,0x8000,0x87)/*257.0*/,
+                              FP32_V(0,0x43ffff,0x7c)/*(7/16)^2-epsilon*/,
+                              FP32_V(0,0x6f4841,0x8c)/*123.75^2+epsilon*/ } },
+            { /*unused   */ { FP32_x8_UNUSED } },
+            { /* =>      */ { FP32_V(0,0x380000,0x83)/*23.0*/,
+                              FP32_V(0,0x0,0x83)/*16.0*/,
+                              FP32_V(0,0x600000,0x7d)/*7/16*/,
+                              FP32_V(0,0x778000,0x85)/*123.75*/,
+                              FP32_V(0,0x37d375,0x83)/*sqrt(528)*/,
+                              FP32_V(0,0x3ff0,0x83)/*sqrt(257)*/,
+                              FP32_V(0,0x5fffff,0x7d)/*7/16-*/,
+                              FP32_V(0,0x778001,0x85)/*123.75+*/ } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
+              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_PE,
+              /*xcpt?    */ false, false },
+          { { /*src1     */ { FP32_V(0,0x44000,0x88)/*529.0*/,
+                              FP32_V(0,0x0,0x87)/*256.0*/,
+                              FP32_V(0,0x440000,0x7c)/*(7/16)^2*/,
+                              FP32_V(0,0x6f4840,0x8c)/*123.75^2*/,
+                              FP32_V(0,0x40000,0x88)/*528.0*/,
+                              FP32_V(0,0x8000,0x87)/*257.0*/,
+                              FP32_V(0,0x43ffff,0x7c)/*(7/16)^2-epsilon*/,
+                              FP32_V(0,0x6f4841,0x8c)/*123.75^2+epsilon*/ } },
+            { /*unused   */ { FP32_x8_UNUSED } },
+            { /* =>      */ { FP32_V(0,0x380000,0x83)/*23.0*/,
+                              FP32_V(0,0x0,0x83)/*16.0*/,
+                              FP32_V(0,0x600000,0x7d)/*7/16*/,
+                              FP32_V(0,0x778000,0x85)/*123.75*/,
+                              FP32_V(0,0x37d375,0x83)/*sqrt(528)*/,
+                              FP32_V(0,0x3ff0,0x83)/*sqrt(257)*/,
+                              FP32_V(0,0x5fffff,0x7d)/*7/16-*/,
+                              FP32_V(0,0x778000,0x85)/*123.75[DOWN]*/ } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_PE | X86_MXCSR_RC_DOWN,
+              /*xcpt?    */ false, false },
+          { { /*src1     */ { FP32_V(0,0x44000,0x88)/*529.0*/,
+                              FP32_V(0,0x0,0x87)/*256.0*/,
+                              FP32_V(0,0x440000,0x7c)/*(7/16)^2*/,
+                              FP32_V(0,0x6f4840,0x8c)/*123.75^2*/,
+                              FP32_V(0,0x40000,0x88)/*528.0*/,
+                              FP32_V(0,0x8000,0x87)/*257.0*/,
+                              FP32_V(0,0x43ffff,0x7c)/*(7/16)^2-epsilon*/,
+                              FP32_V(0,0x6f4841,0x8c)/*123.75^2+epsilon*/ } },
+            { /*unused   */ { FP32_x8_UNUSED } },
+            { /* =>      */ { FP32_V(0,0x380000,0x83)/*23.0*/,
+                              FP32_V(0,0x0,0x83)/*16.0*/,
+                              FP32_V(0,0x600000,0x7d)/*7/16*/,
+                              FP32_V(0,0x778000,0x85)/*123.75*/,
+                              FP32_V(0,0x37d376,0x83)/*sqrt(528)[UP]*/,
+                              FP32_V(0,0x3ff1,0x83)/*sqrt(257)[UP]*/,
+                              FP32_V(0,0x600000,0x7d)/*7/16[UP]*/,
+                              FP32_V(0,0x778001,0x85)/*123.75+*/ } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_PE | X86_MXCSR_RC_UP,
+              /*xcpt?    */ false, false },
+          { { /*src1     */ { FP32_V(0,0x44000,0x88)/*529.0*/,
+                              FP32_V(0,0x0,0x87)/*256.0*/,
+                              FP32_V(0,0x440000,0x7c)/*(7/16)^2*/,
+                              FP32_V(0,0x6f4840,0x8c)/*123.75^2*/,
+                              FP32_V(0,0x40000,0x88)/*528.0*/,
+                              FP32_V(0,0x8000,0x87)/*257.0*/,
+                              FP32_V(0,0x43ffff,0x7c)/*(7/16)^2-epsilon*/,
+                              FP32_V(0,0x6f4841,0x8c)/*123.75^2+epsilon*/ } },
+            { /*unused   */ { FP32_x8_UNUSED } },
+            { /* =>      */ { FP32_V(0,0x380000,0x83)/*23.0*/,
+                              FP32_V(0,0x0,0x83)/*16.0*/,
+                              FP32_V(0,0x600000,0x7d)/*7/16*/,
+                              FP32_V(0,0x778000,0x85)/*123.75*/,
+                              FP32_V(0,0x37d375,0x83)/*sqrt(528)*/,
+                              FP32_V(0,0x3ff0,0x83)/*sqrt(257)*/,
+                              FP32_V(0,0x5fffff,0x7d)/*7/16-*/,
+                              FP32_V(0,0x778000,0x85)/*123.75[ZERO=DOWN]*/ } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_PE | X86_MXCSR_RC_ZERO,
+              /*xcpt?    */ false, false },
+          { { /*src1     */ { FP32_NORM_MAX(0),
+                              FP32_NORM_MIN(0),
+                              FP32_NORM_SAFE_INT_MAX(0),
+                              FP32_NORM_SAFE_INT_MIN(0),
+                              FP32_NORM_MAX(1),
+                              FP32_NORM_MIN(1),
+                              FP32_NORM_SAFE_INT_MAX(1),
+                              FP32_NORM_SAFE_INT_MIN(1) } },
+            { /*unused   */ { FP32_x8_UNUSED } },
+            { /* =>      */ { FP32_V(0,0x7fffff,0xbe)/*sqrt(FP32_NORM_MAX)*/,
+                              FP32_V(0,0x0,0x40)/*sqrt(FP32_NORM_MIN)*/,
+                              FP32_V(0,0x7fffff,0x8a)/*sqrt(FP32_NORM_SAFE_INT_MAX)*/,
+                              FP32_V(0,0x0,0x40)/*sqrt(FP32_NORM_SAFE_INT_MIN)*/,
+                              FP32_QNAN(1),
+                              FP32_QNAN(1),
+                              FP32_QNAN(1),
+                              FP32_QNAN(1) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_PE | X86_MXCSR_IE,
+              /*xcpt?    */ false, false },
+    /** @todo More Normals. */
+   /*
+    * Denormals.
+    */
+    /*19*/{ { /*src1     */ { FP32_DENORM_MAX(0),      FP32_DENORM_MAX(0),      FP32_0(0), FP32_0(1), FP32_DENORM_MAX(1), FP32_DENORM_MAX(1), FP32_0(1), FP32_0(0) } },
+            { /*unused   */ { FP32_x8_UNUSED } },
+            { /* =>      */ { FP32_V(0,0x7fffff,0x3f), FP32_V(0,0x7fffff,0x3f), FP32_0(0), FP32_0(1), FP32_QNAN(1),       FP32_QNAN(1),       FP32_0(1), FP32_0(0) } },
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_DE,
+              /*256:out  */ X86_MXCSR_DE | X86_MXCSR_IE,
+              /*xcpt?    */ true, true },
+#ifdef TODO_X86_MXCSR_PE /** @todo THIS FAILS ON IEM: X86_MXCSR_PE not set in 256:out */
+ /*--|20*/{ { /*src1     */ { FP32_DENORM_MAX(0),      FP32_DENORM_MAX(0),      FP32_0(0), FP32_0(1), FP32_DENORM_MAX(1), FP32_DENORM_MAX(1), FP32_0(1), FP32_0(0) } },
+            { /*unused   */ { FP32_x8_UNUSED } },
+            { /* =>      */ { FP32_V(0,0x7fffff,0x3f), FP32_V(0,0x7fffff,0x3f), FP32_0(0), FP32_0(1), FP32_QNAN(1),       FP32_QNAN(1),       FP32_0(1), FP32_0(0) } },
+              /*mxcsr:in */ X86_MXCSR_DM,
+              /*128:out  */ X86_MXCSR_DM | X86_MXCSR_DE | X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_DM | X86_MXCSR_DE | X86_MXCSR_IE,
+              /*xcpt?    */ true, true },
+#endif /* TODO_X86_MXCSR_PE */
+ /*20|21*/{ { /*src1     */ { FP32_DENORM_MAX(0),      FP32_DENORM_MAX(0),      FP32_0(0), FP32_0(1), FP32_DENORM_MAX(1), FP32_DENORM_MAX(1), FP32_0(1), FP32_0(0) } },
+            { /*unused   */ { FP32_x8_UNUSED } },
+            { /* =>      */ { FP32_V(0,0x7fffff,0x3f), FP32_V(0,0x7fffff,0x3f), FP32_0(0), FP32_0(1), FP32_QNAN(1),       FP32_QNAN(1),       FP32_0(1), FP32_0(0) } },
+              /*mxcsr:in */ X86_MXCSR_PM,
+              /*128:out  */ X86_MXCSR_PM | X86_MXCSR_DE,
+              /*256:out  */ X86_MXCSR_PM | X86_MXCSR_DE | X86_MXCSR_IE,
+              /*xcpt?    */ true, true },
+#ifdef TODO_X86_MXCSR_PE /** @todo THIS FAILS ON IEM: X86_MXCSR_PE unexpectedly set in 256:out */
+ /*--|22*/{ { /*src1     */ { FP32_DENORM_MAX(0),      FP32_DENORM_MAX(0),      FP32_0(0), FP32_0(1), FP32_DENORM_MAX(1), FP32_DENORM_MAX(1), FP32_0(1), FP32_0(0) } },
+            { /*unused   */ { FP32_x8_UNUSED } },
+            { /* =>      */ { FP32_V(0,0x7fffff,0x3f), FP32_V(0,0x7fffff,0x3f), FP32_0(0), FP32_0(1), FP32_QNAN(1),       FP32_QNAN(1),       FP32_0(1), FP32_0(0) } },
+              /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_PM,
+              /*128:out  */ X86_MXCSR_DM | X86_MXCSR_PM | X86_MXCSR_DE | X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_DM | X86_MXCSR_PM | X86_MXCSR_DE | X86_MXCSR_IE,
+              /*xcpt?    */ false, true },
+#endif /* TODO_X86_MXCSR_PE */
+ /*21|23*/{ { /*src1     */ { FP32_DENORM_MAX(0),      FP32_DENORM_MAX(0),      FP32_0(0), FP32_0(1), FP32_DENORM_MAX(1), FP32_DENORM_MAX(1), FP32_0(1), FP32_0(0) } },
+            { /*unused   */ { FP32_x8_UNUSED } },
+            { /* =>      */ { FP32_V(0,0x7fffff,0x3f), FP32_V(0,0x7fffff,0x3f), FP32_0(0), FP32_0(1), FP32_QNAN(1),       FP32_QNAN(1),       FP32_0(1), FP32_0(0) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_IE | X86_MXCSR_PE,
+              /*xcpt?    */ false, false },
+          { { /*src1     */ { FP32_DENORM_MIN(0),      FP32_DENORM_MIN(0),      FP32_0(0), FP32_0(1), FP32_DENORM_MIN(1), FP32_DENORM_MIN(1), FP32_0(1), FP32_0(0) } },
+            { /*unused   */ { FP32_x8_UNUSED } },
+            { /* =>      */ { FP32_V(0,0x3504f3,0x34), FP32_V(0,0x3504f3,0x34), FP32_0(0), FP32_0(1), FP32_QNAN(1),       FP32_QNAN(1),       FP32_0(1), FP32_0(0) } },
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_DE,
+              /*256:out  */ X86_MXCSR_DE | X86_MXCSR_IE,
+              /*xcpt?    */ true, true },
+          { { /*src1     */ { FP32_DENORM_MIN(0),      FP32_DENORM_MIN(0),      FP32_0(0), FP32_0(1), FP32_DENORM_MIN(1), FP32_DENORM_MIN(1), FP32_0(1), FP32_0(0) } },
+            { /*unused   */ { FP32_x8_UNUSED } },
+            { /* =>      */ { FP32_V(0,0x3504f3,0x34), FP32_V(0,0x3504f3,0x34), FP32_0(0), FP32_0(1), FP32_QNAN(1),       FP32_QNAN(1),       FP32_0(1), FP32_0(0) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_IE | X86_MXCSR_PE,
+              /*xcpt?    */ false, false },
+          { { /*src1     */ { FP32_DENORM_MIN(0),      FP32_DENORM_MAX(0),      FP32_0(0), FP32_0(1), FP32_DENORM_MIN(1), FP32_DENORM_MAX(1), FP32_0(1), FP32_0(0) } },
+            { /*unused   */ { FP32_x8_UNUSED } },
+            { /* =>      */ { FP32_V(0,0x3504f3+1,0x34), FP32_V(0,0x7fffff,0x3f), FP32_0(0), FP32_0(1), FP32_QNAN(1),     FP32_QNAN(1),       FP32_0(1), FP32_0(0) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_IE | X86_MXCSR_PE | X86_MXCSR_RC_UP,
+              /*xcpt?    */ false, false },
+          { { /*src1     */ { FP32_DENORM_MIN(0),      FP32_DENORM_MAX(0),      FP32_0(0), FP32_0(1), FP32_DENORM_MIN(1), FP32_DENORM_MAX(1), FP32_0(1), FP32_0(0) } },
+            { /*unused   */ { FP32_x8_UNUSED } },
+            { /* =>      */ { FP32_V(0,0x3504f3,0x34), FP32_V(0,0x7fffff-1,0x3f), FP32_0(0), FP32_0(1), FP32_QNAN(1),     FP32_QNAN(1),       FP32_0(1), FP32_0(0) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_IE | X86_MXCSR_PE | X86_MXCSR_RC_DOWN,
+              /*xcpt?    */ false, false },
+          { { /*src1     */ { FP32_DENORM_MIN(0),      FP32_DENORM_MAX(0),      FP32_0(0), FP32_0(1), FP32_DENORM_MIN(1), FP32_DENORM_MAX(1), FP32_0(1), FP32_0(0) } },
+            { /*unused   */ { FP32_x8_UNUSED } },
+            { /* =>      */ { FP32_V(0,0x3504f3,0x34), FP32_V(0,0x7fffff-1,0x3f), FP32_0(0), FP32_0(1), FP32_QNAN(1),     FP32_QNAN(1),       FP32_0(1), FP32_0(0) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_IE | X86_MXCSR_PE | X86_MXCSR_RC_ZERO,
+              /*xcpt?    */ false, false },
+          { { /*src1     */ { FP32_DENORM_MIN(0),      FP32_DENORM_MAX(0),      FP32_0(0), FP32_0(1), FP32_DENORM_MIN(1), FP32_DENORM_MAX(1), FP32_0(1), FP32_0(0) } },
+            { /*unused   */ { FP32_x8_UNUSED } },
+            { /* =>      */ { FP32_V(0,0x3504f3,0x34), FP32_V(0,0x7fffff,0x3f), FP32_0(0), FP32_0(1), FP32_QNAN(1),       FP32_QNAN(1),       FP32_0(1), FP32_0(0) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_FZ,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_IE | X86_MXCSR_PE | X86_MXCSR_FZ,
+              /*xcpt?    */ false, false },
+          { { /*src1     */ { FP32_DENORM_MIN(0),      FP32_DENORM_MAX(0),      FP32_0(0), FP32_0(1), FP32_DENORM_MIN(1), FP32_DENORM_MAX(1), FP32_0(1), FP32_0(0) } },
+            { /*unused   */ { FP32_x8_UNUSED } },
+            { /* =>      */ { FP32_0(0),               FP32_0(0),               FP32_0(0), FP32_0(1), FP32_0(1),          FP32_0(1),          FP32_0(1), FP32_0(0) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
+              /*xcpt?    */ false, false },
+    /** @todo More Denormals. */
+    /*
+     * Invalids.
+     */
+    /** @todo Invalids. */
+ /*29|31*/ /* FP32_TABLE_D10_PS_INVALIDS */
+    /** @todo Underflow, Precision; Rounding; FZ etc. */
+    };
+#undef FP32_x8_UNUSED
+
+#define PASS_s_aValues RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues
+    static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
+    {
+        { bs3CpuInstr4_sqrtps_XMM1_XMM2_icebp_c16,   255, RM_REG, T_SSE,     1, 1, 2,   PASS_s_aValues },
+        { bs3CpuInstr4_sqrtps_XMM1_FSxBX_icebp_c16,  255, RM_MEM, T_SSE,     1, 1, 255, PASS_s_aValues },
+
+        { bs3CpuInstr4_vsqrtps_XMM1_XMM2_icebp_c16,  255, RM_REG, T_AVX_128, 1, 1, 2,   PASS_s_aValues },
+        { bs3CpuInstr4_vsqrtps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_128, 1, 1, 255, PASS_s_aValues },
+
+        { bs3CpuInstr4_vsqrtps_YMM1_YMM2_icebp_c16,  255, RM_REG, T_AVX_256, 1, 1, 2,   PASS_s_aValues },
+        { bs3CpuInstr4_vsqrtps_YMM1_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_256, 1, 1, 255, PASS_s_aValues },
+    };
+    static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
+    {
+        { bs3CpuInstr4_sqrtps_XMM1_XMM2_icebp_c32,   255, RM_REG, T_SSE,     1, 1, 2,   PASS_s_aValues },
+        { bs3CpuInstr4_sqrtps_XMM1_FSxBX_icebp_c32,  255, RM_MEM, T_SSE,     1, 1, 255, PASS_s_aValues },
+
+        { bs3CpuInstr4_vsqrtps_XMM1_XMM2_icebp_c32,  255, RM_REG, T_AVX_128, 1, 1, 2,   PASS_s_aValues },
+        { bs3CpuInstr4_vsqrtps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_128, 1, 1, 255, PASS_s_aValues },
+
+        { bs3CpuInstr4_vsqrtps_YMM1_YMM2_icebp_c32,  255, RM_REG, T_AVX_256, 1, 1, 2,   PASS_s_aValues },
+        { bs3CpuInstr4_vsqrtps_YMM1_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_256, 1, 1, 255, PASS_s_aValues },
+    };
+    static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
+    {
+        { bs3CpuInstr4_sqrtps_XMM1_XMM2_icebp_c64,   255, RM_REG, T_SSE,     1, 1, 2,   PASS_s_aValues },
+        { bs3CpuInstr4_sqrtps_XMM1_FSxBX_icebp_c64,  255, RM_MEM, T_SSE,     1, 1, 255, PASS_s_aValues },
+
+        { bs3CpuInstr4_vsqrtps_XMM1_XMM2_icebp_c64,  255, RM_REG, T_AVX_128, 1, 1, 2,   PASS_s_aValues },
+        { bs3CpuInstr4_vsqrtps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 1, 1, 255, PASS_s_aValues },
+
+        { bs3CpuInstr4_vsqrtps_YMM1_YMM2_icebp_c64,  255, RM_REG, T_AVX_256, 1, 1, 2,   PASS_s_aValues },
+        { bs3CpuInstr4_vsqrtps_YMM1_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 1, 1, 255, PASS_s_aValues },
+
+        { bs3CpuInstr4_sqrtps_XMM8_XMM9_icebp_c64,   255, RM_REG, T_SSE,     8, 8, 9,   PASS_s_aValues },
+        { bs3CpuInstr4_sqrtps_XMM8_FSxBX_icebp_c64,  255, RM_MEM, T_SSE,     8, 8, 255, PASS_s_aValues },
+
+        { bs3CpuInstr4_vsqrtps_XMM8_XMM9_icebp_c64,  255, RM_REG, T_AVX_128, 8, 8, 9,   PASS_s_aValues },
+        { bs3CpuInstr4_vsqrtps_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 8, 8, 255, PASS_s_aValues },
+        { bs3CpuInstr4_vsqrtps_YMM8_YMM9_icebp_c64,  255, RM_REG, T_AVX_256, 8, 8, 9,   PASS_s_aValues },
+        { bs3CpuInstr4_vsqrtps_YMM8_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 8, 8, 255, PASS_s_aValues },
+    };
+#undef PASS_s_aValues
+
+    static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
+    unsigned const                         iTest       = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
+    return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+                                        g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
+}
+
+
 /**
  * The 32-bit protected mode main function.
@@ -11955,4 +12338,5 @@
         { "[v]maxsd",       bs3CpuInstr4_v_maxsd,    0 },
         { "[v]minps",       bs3CpuInstr4_v_minps,    0 },
+        { "[v]sqrtps",      bs3CpuInstr4_v_sqrtps,   0 },
 #endif
     };
