VirtualBox

Changeset 106200 in vbox for trunk/src/VBox/VMM


Ignore:
Timestamp:
Oct 1, 2024 11:37:05 PM (4 months ago)
Author:
vboxsync
Message:

VMM/IEM: Refactored the xxxxx_r_r_efl functions to take the constant argument (cOpBits) as template argument. bugref:10720

Location:
trunk/src/VBox/VMM/VMMAll
Files:
3 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/VMM/VMMAll/IEMAllInstCommonBodyMacros.h

    r106061 r106200  
    5656                    IEM_MC_FETCH_GREG_U16(u16Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
    5757                    IEM_MC_LOCAL_EFLAGS(uEFlags); \
    58                     IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl), u16Dst, u16Src, uEFlags, 16); \
     58                    IEM_MC_NATIVE_EMIT_3(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl)<16>, u16Dst, u16Src, uEFlags); \
    5959                    IEM_MC_STORE_GREG_U16(IEM_GET_MODRM_REG(pVCpu, bRm), u16Dst); \
    6060                    IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
    … …  
    7979                    IEM_MC_FETCH_GREG_U32(u32Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
    8080                    IEM_MC_LOCAL_EFLAGS(uEFlags); \
    81                     IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl), u32Dst, u32Src, uEFlags, 32); \
     81                    IEM_MC_NATIVE_EMIT_3(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl)<32>, u32Dst, u32Src, uEFlags); \
    8282                    IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u32Dst); \
    8383                    IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
    … …  
    103103                    IEM_MC_FETCH_GREG_U64(u64Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
    104104                    IEM_MC_LOCAL_EFLAGS(uEFlags); \
    105                     IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl), u64Dst, u64Src, uEFlags, 64); \
     105                    IEM_MC_NATIVE_EMIT_3(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl)<64>, u64Dst, u64Src, uEFlags); \
    106106                    IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), u64Dst); \
    107107                    IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
    … …  
    138138                    IEM_MC_FETCH_GREG_U16(u16Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
    139139                    IEM_MC_LOCAL_EFLAGS(uEFlags); \
    140                     IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl), u16Dst, u16Src, uEFlags, 16); \
     140                    IEM_MC_NATIVE_EMIT_3(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl)<16>, u16Dst, u16Src, uEFlags); \
    141141                    IEM_MC_STORE_GREG_U16(IEM_GET_MODRM_REG(pVCpu, bRm), u16Dst); \
    142142                    IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
    … …  
    163163                    IEM_MC_FETCH_GREG_U32(u32Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
    164164                    IEM_MC_LOCAL_EFLAGS(uEFlags); \
    165                     IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl), u32Dst, u32Src, uEFlags, 32); \
     165                    IEM_MC_NATIVE_EMIT_3(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl)<32>, u32Dst, u32Src, uEFlags); \
    166166                    IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u32Dst); \
    167167                    IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
    … …  
    189189                    IEM_MC_FETCH_GREG_U64(u64Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
    190190                    IEM_MC_LOCAL_EFLAGS(uEFlags); \
    191                     IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl), u64Dst, u64Src, uEFlags, 64); \
     191                    IEM_MC_NATIVE_EMIT_3(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl)<64>, u64Dst, u64Src, uEFlags); \
    192192                    IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), u64Dst); \
    193193                    IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
    … …  
    232232                    IEM_MC_FETCH_GREG_U16(u16Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
    233233                    IEM_MC_LOCAL_EFLAGS(uEFlags); \
    234                     IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl), u16Dst, u16Src, uEFlags, 16); \
     234                    IEM_MC_NATIVE_EMIT_3(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl)<16>, u16Dst, u16Src, uEFlags); \
    235235                    IEM_MC_STORE_GREG_U16(IEM_GET_MODRM_REG(pVCpu, bRm), u16Dst); \
    236236                    IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
    … …  
    255255                    IEM_MC_FETCH_GREG_U32(u32Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
    256256                    IEM_MC_LOCAL_EFLAGS(uEFlags); \
    257                     IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl), u32Dst, u32Src, uEFlags, 32); \
     257                    IEM_MC_NATIVE_EMIT_3(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl)<32>, u32Dst, u32Src, uEFlags); \
    258258                    IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u32Dst); \
    259259                    IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
    … …  
    279279                    IEM_MC_FETCH_GREG_U64(u64Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
    280280                    IEM_MC_LOCAL_EFLAGS(uEFlags); \
    281                     IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl), u64Dst, u64Src, uEFlags, 64); \
     281                    IEM_MC_NATIVE_EMIT_3(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl)<64>, u64Dst, u64Src, uEFlags); \
    282282                    IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), u64Dst); \
    283283                    IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
    … …  
    314314                    IEM_MC_FETCH_GREG_U16(u16Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
    315315                    IEM_MC_LOCAL_EFLAGS(uEFlags); \
    316                     IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl), u16Dst, u16Src, uEFlags, 16); \
     316                    IEM_MC_NATIVE_EMIT_3(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl)<16>, u16Dst, u16Src, uEFlags); \
    317317                    IEM_MC_STORE_GREG_U16(IEM_GET_MODRM_REG(pVCpu, bRm), u16Dst); \
    318318                    IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
    … …  
    339339                    IEM_MC_FETCH_GREG_U32(u32Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
    340340                    IEM_MC_LOCAL_EFLAGS(uEFlags); \
    341                     IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl), u32Dst, u32Src, uEFlags, 32); \
     341                    IEM_MC_NATIVE_EMIT_3(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl)<32>, u32Dst, u32Src, uEFlags); \
    342342                    IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u32Dst); \
    343343                    IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
    … …  
    365365                    IEM_MC_FETCH_GREG_U64(u64Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
    366366                    IEM_MC_LOCAL_EFLAGS(uEFlags); \
    367                     IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl), u64Dst, u64Src, uEFlags, 64); \
     367                    IEM_MC_NATIVE_EMIT_3(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl)<64>, u64Dst, u64Src, uEFlags); \
    368368                    IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), u64Dst); \
    369369                    IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \

  • trunk/src/VBox/VMM/VMMAll/IEMAllInstOneByte.cpp.h

    r106199 r106200  
    9797            IEM_MC_FETCH_GREG_U8(u8Dst, IEM_GET_MODRM_RM(pVCpu, a_bRm)); \
    9898            IEM_MC_LOCAL_EFLAGS(uEFlags); \
    99             IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl), u8Dst, u8Src, uEFlags, 8); \
     99            IEM_MC_NATIVE_EMIT_3(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl)<8>, u8Dst, u8Src, uEFlags); \
    100100            IEM_MC_STORE_GREG_U8(IEM_GET_MODRM_RM(pVCpu, a_bRm), u8Dst); \
    101101            IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
    … …  
    176176            IEM_MC_FETCH_GREG_U8(u8Dst, IEM_GET_MODRM_RM(pVCpu, a_bRm)); \
    177177            IEM_MC_LOCAL_EFLAGS(uEFlags); \
    178             IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl), u8Dst, u8Src, uEFlags, 8); \
     178            IEM_MC_NATIVE_EMIT_3(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl)<8>, u8Dst, u8Src, uEFlags); \
    179179            IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
    180180        } IEM_MC_NATIVE_ELSE() { \
    … …  
    205205                IEM_MC_FETCH_GREG_U8(u8SrcEmit, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
    206206                IEM_MC_LOCAL_EFLAGS(uEFlags); \
    207                 IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl), u8Dst, u8SrcEmit, uEFlags, 8); \
     207                IEM_MC_NATIVE_EMIT_3(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl)<8>, u8Dst, u8SrcEmit, uEFlags); \
    208208                IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
    209209            } IEM_MC_NATIVE_ELSE() { \
    … …  
    248248            IEM_MC_FETCH_GREG_U8(u8Dst, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
    249249            IEM_MC_LOCAL_EFLAGS(uEFlags); \
    250             IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl), u8Dst, u8Src, uEFlags, 8); \
     250            IEM_MC_NATIVE_EMIT_3(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl)<8>, u8Dst, u8Src, uEFlags); \
    251251            IEM_MC_STORE_GREG_U8(IEM_GET_MODRM_REG(pVCpu, a_bRm), u8Dst); \
    252252            IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
    … …  
    276276            IEM_MC_FETCH_GREG_U8(u8Dst, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
    277277            IEM_MC_LOCAL_EFLAGS(uEFlags); \
    278             IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl), u8Dst, u8Src, uEFlags, 8); \
     278            IEM_MC_NATIVE_EMIT_3(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl)<8>, u8Dst, u8Src, uEFlags); \
    279279            IEM_MC_STORE_GREG_U8(IEM_GET_MODRM_REG(pVCpu, a_bRm), u8Dst); \
    280280            IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
    … …  
    308308            IEM_MC_FETCH_GREG_U8(u8Dst, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
    309309            IEM_MC_LOCAL_EFLAGS(uEFlags); \
    310             IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl), u8Dst, u8Src, uEFlags, 8); \
     310            IEM_MC_NATIVE_EMIT_3(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl)<8>, u8Dst, u8Src, uEFlags); \
    311311            IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
    312312        } IEM_MC_NATIVE_ELSE() { \
    … …  
    335335            IEM_MC_FETCH_GREG_U8(u8Dst, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
    336336            IEM_MC_LOCAL_EFLAGS(uEFlags); \
    337             IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl), u8Dst, u8Src, uEFlags, 8); \
     337            IEM_MC_NATIVE_EMIT_3(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl)<8>, u8Dst, u8Src, uEFlags); \
    338338            IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
    339339        } IEM_MC_NATIVE_ELSE() { \
    … …  
    371371                    IEM_MC_FETCH_GREG_U16(u16Dst, IEM_GET_MODRM_RM(pVCpu, a_bRm)); \
    372372                    IEM_MC_LOCAL_EFLAGS(uEFlags); \
    373                     IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl), u16Dst, u16Src, uEFlags, 16); \
     373                    IEM_MC_NATIVE_EMIT_3(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl)<16>, u16Dst, u16Src, uEFlags); \
    374374                    IEM_MC_STORE_GREG_U16(IEM_GET_MODRM_RM(pVCpu, a_bRm), u16Dst); \
    375375                    IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
    … …  
    394394                    IEM_MC_FETCH_GREG_U32(u32Dst, IEM_GET_MODRM_RM(pVCpu, a_bRm)); \
    395395                    IEM_MC_LOCAL_EFLAGS(uEFlags); \
    396                     IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl), u32Dst, u32Src, uEFlags, 32); \
     396                    IEM_MC_NATIVE_EMIT_3(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl)<32>, u32Dst, u32Src, uEFlags); \
    397397                    IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, a_bRm), u32Dst); \
    398398                    IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
    … …  
    418418                    IEM_MC_FETCH_GREG_U64(u64Dst, IEM_GET_MODRM_RM(pVCpu, a_bRm)); \
    419419                    IEM_MC_LOCAL_EFLAGS(uEFlags); \
    420                     IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl), u64Dst, u64Src, uEFlags, 64); \
     420                    IEM_MC_NATIVE_EMIT_3(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl)<64>, u64Dst, u64Src, uEFlags); \
    421421                    IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_RM(pVCpu, a_bRm), u64Dst); \
    422422                    IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
    … …  
    601601                    IEM_MC_FETCH_GREG_U16(u16Dst, IEM_GET_MODRM_RM(pVCpu, a_bRm)); \
    602602                    IEM_MC_LOCAL_EFLAGS(uEFlags); \
    603                     IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl), u16Dst, u16Src, uEFlags, 16); \
     603                    IEM_MC_NATIVE_EMIT_3(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl)<16>, u16Dst, u16Src, uEFlags); \
    604604                    IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
    605605                } IEM_MC_NATIVE_ELSE() { \
    … …  
    623623                    IEM_MC_FETCH_GREG_U32(u32Dst, IEM_GET_MODRM_RM(pVCpu, a_bRm)); \
    624624                    IEM_MC_LOCAL_EFLAGS(uEFlags); \
    625                     IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl), u32Dst, u32Src, uEFlags, 32); \
     625                    IEM_MC_NATIVE_EMIT_3(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl)<32>, u32Dst, u32Src, uEFlags); \
    626626                    IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
    627627                } IEM_MC_NATIVE_ELSE() { \
    … …  
    645645                    IEM_MC_FETCH_GREG_U64(u64Dst, IEM_GET_MODRM_RM(pVCpu, a_bRm)); \
    646646                    IEM_MC_LOCAL_EFLAGS(uEFlags); \
    647                     IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl), u64Dst, u64Src, uEFlags, 64); \
     647                    IEM_MC_NATIVE_EMIT_3(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl)<64>, u64Dst, u64Src, uEFlags); \
    648648                    IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
    649649                } IEM_MC_NATIVE_ELSE() { \
    … …  
    681681                        IEM_MC_FETCH_GREG_U16(u16SrcEmit, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
    682682                        IEM_MC_LOCAL_EFLAGS(uEFlags); \
    683                         IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl), u16Dst, u16SrcEmit, uEFlags, 16); \
     683                        IEM_MC_NATIVE_EMIT_3(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl)<16>, u16Dst, u16SrcEmit, uEFlags); \
    684684                        IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
    685685                    } IEM_MC_NATIVE_ELSE() { \
    … …  
    709709                        IEM_MC_FETCH_GREG_U32(u32SrcEmit, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
    710710                        IEM_MC_LOCAL_EFLAGS(uEFlags); \
    711                         IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl), u32Dst, u32SrcEmit, uEFlags, 32); \
     711                        IEM_MC_NATIVE_EMIT_3(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl)<32>, u32Dst, u32SrcEmit, uEFlags); \
    712712                        IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
    713713                    } IEM_MC_NATIVE_ELSE() { \
    … …  
    737737                        IEM_MC_FETCH_GREG_U64(u64SrcEmit, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
    738738                        IEM_MC_LOCAL_EFLAGS(uEFlags); \
    739                         IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl), u64Dst, u64SrcEmit, uEFlags, 64); \
     739                        IEM_MC_NATIVE_EMIT_3(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl)<64>, u64Dst, u64SrcEmit, uEFlags); \
    740740                        IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
    741741                    } IEM_MC_NATIVE_ELSE() { \
    … …  
    19561956                    IEM_MC_FETCH_GREG_U16(u16Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
    19571957                    IEM_MC_LOCAL_EFLAGS(uEFlags); \
    1958                     IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl), u16Dst, u16Src, uEFlags, 16); \
     1958                    IEM_MC_NATIVE_EMIT_3(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl)<16>, u16Dst, u16Src, uEFlags); \
    19591959                    IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
    19601960                } IEM_MC_NATIVE_ELSE() { \
    … …  
    19781978                    IEM_MC_FETCH_GREG_U32(u32Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
    19791979                    IEM_MC_LOCAL_EFLAGS(uEFlags); \
    1980                     IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl), u32Dst, u32Src, uEFlags, 32); \
     1980                    IEM_MC_NATIVE_EMIT_3(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl)<32>, u32Dst, u32Src, uEFlags); \
    19811981                    IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
    19821982                } IEM_MC_NATIVE_ELSE() { \
    … …  
    20002000                    IEM_MC_FETCH_GREG_U64(u64Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
    20012001                    IEM_MC_LOCAL_EFLAGS(uEFlags); \
    2002                     IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl), u64Dst, u64Src, uEFlags, 64); \
     2002                    IEM_MC_NATIVE_EMIT_3(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl)<64>, u64Dst, u64Src, uEFlags); \
    20032003                    IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
    20042004                } IEM_MC_NATIVE_ELSE() { \
    … …  
    20342034                    IEM_MC_FETCH_GREG_U16(u16Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
    20352035                    IEM_MC_LOCAL_EFLAGS(uEFlags); \
    2036                     IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl), u16Dst, u16Src, uEFlags, 16); \
     2036                    IEM_MC_NATIVE_EMIT_3(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl)<16>, u16Dst, u16Src, uEFlags); \
    20372037                    IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
    20382038                } IEM_MC_NATIVE_ELSE() { \
    … …  
    20582058                    IEM_MC_FETCH_GREG_U32(u32Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
    20592059                    IEM_MC_LOCAL_EFLAGS(uEFlags); \
    2060                     IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl), u32Dst, u32Src, uEFlags, 32); \
     2060                    IEM_MC_NATIVE_EMIT_3(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl)<32>, u32Dst, u32Src, uEFlags); \
    20612061                    IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
    20622062                } IEM_MC_NATIVE_ELSE() { \
    … …  
    20822082                    IEM_MC_FETCH_GREG_U64(u64Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
    20832083                    IEM_MC_LOCAL_EFLAGS(uEFlags); \
    2084                     IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl), u64Dst, u64Src, uEFlags, 64); \
     2084                    IEM_MC_NATIVE_EMIT_3(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl)<64>, u64Dst, u64Src, uEFlags); \
    20852085                    IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
    20862086                } IEM_MC_NATIVE_ELSE() { \
    … …  
    57805780        IEM_MC_NATIVE_IF(RT_ARCH_VAL_AMD64 | RT_ARCH_VAL_ARM64) {
    57815781            IEM_MC_LOCAL_EFLAGS(uEFlags);
    5782             IEM_MC_NATIVE_EMIT_4(iemNativeEmit_test_r_r_efl, u8Src, u8Src, uEFlags, 8);
     5782            IEM_MC_NATIVE_EMIT_3(iemNativeEmit_test_r_r_efl<8>, u8Src, u8Src, uEFlags);
    57835783            IEM_MC_COMMIT_EFLAGS_OPT(uEFlags);
    57845784        } IEM_MC_NATIVE_ELSE() {
    … …  
    58245824                IEM_MC_NATIVE_IF(RT_ARCH_VAL_AMD64 | RT_ARCH_VAL_ARM64) {
    58255825                    IEM_MC_LOCAL_EFLAGS(uEFlags);
    5826                     IEM_MC_NATIVE_EMIT_4(iemNativeEmit_test_r_r_efl, u16Src, u16Src, uEFlags, 16);
     5826                    IEM_MC_NATIVE_EMIT_3(iemNativeEmit_test_r_r_efl<16>, u16Src, u16Src, uEFlags);
    58275827                    IEM_MC_COMMIT_EFLAGS_OPT(uEFlags);
    58285828                } IEM_MC_NATIVE_ELSE() {
    … …  
    58445844                IEM_MC_NATIVE_IF(RT_ARCH_VAL_AMD64 | RT_ARCH_VAL_ARM64) {
    58455845                    IEM_MC_LOCAL_EFLAGS(uEFlags);
    5846                     IEM_MC_NATIVE_EMIT_4(iemNativeEmit_test_r_r_efl, u32Src, u32Src, uEFlags, 32);
     5846                    IEM_MC_NATIVE_EMIT_3(iemNativeEmit_test_r_r_efl<32>, u32Src, u32Src, uEFlags);
    58475847                    IEM_MC_COMMIT_EFLAGS_OPT(uEFlags);
    58485848                } IEM_MC_NATIVE_ELSE() {
    … …  
    58645864                IEM_MC_NATIVE_IF(RT_ARCH_VAL_AMD64 | RT_ARCH_VAL_ARM64) {
    58655865                    IEM_MC_LOCAL_EFLAGS(uEFlags);
    5866                     IEM_MC_NATIVE_EMIT_4(iemNativeEmit_test_r_r_efl, u64Src, u64Src, uEFlags, 64);
     5866                    IEM_MC_NATIVE_EMIT_3(iemNativeEmit_test_r_r_efl<64>, u64Src, u64Src, uEFlags);
    58675867                    IEM_MC_COMMIT_EFLAGS_OPT(uEFlags);
    58685868                } IEM_MC_NATIVE_ELSE() {

  • trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllN8veEmit-x86.h

    r106199 r106200  
    851851 * set the other flags according to the result.
    852852 */
    853 DECL_INLINE_THROW(uint32_t)
    854 iemNativeEmit_and_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off,
    855                           uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl, uint8_t cOpBits)
     853template<uint8_t const a_cOpBits>
     854DECL_INLINE_THROW(uint32_t)
     855iemNativeEmit_and_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl)
    856856{
    857857    uint8_t const idxRegDst = iemNativeVarRegisterAcquire(pReNative, idxVarDst, &off, true /*fInitialized*/);
    … …  
    860860    /* On AMD64 we just use the correctly sized AND instruction harvest the EFLAGS. */
    861861    off = iemNativeEmitAmd64OneByteModRmInstrRREx(iemNativeInstrBufEnsure(pReNative, off, 4), off,
    862                                                   0x22, 0x23, cOpBits, idxRegDst, idxRegSrc);
     862                                                  0x22, 0x23, a_cOpBits, idxRegDst, idxRegSrc);
    863863    IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
    864864    iemNativeVarRegisterRelease(pReNative, idxVarSrc);
    865865
    866     off = iemNativeEmitEFlagsForLogical<false>(pReNative, off, idxVarEfl, cOpBits, idxRegDst);
     866    off = iemNativeEmitEFlagsForLogical<false>(pReNative, off, idxVarEfl, a_cOpBits, idxRegDst);
    867867
    868868#elif defined(RT_ARCH_ARM64)
    869869    /* On ARM64 we use 32-bit AND for the 8-bit and 16-bit bit ones. */
    870870    PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 1);
    871     pCodeBuf[off++] = Armv8A64MkInstrAnds(idxRegDst, idxRegDst, idxRegSrc, cOpBits > 32 /*f64Bit*/);
     871    pCodeBuf[off++] = Armv8A64MkInstrAnds(idxRegDst, idxRegDst, idxRegSrc, a_cOpBits > 32 /*f64Bit*/);
    872872    IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
    873873    iemNativeVarRegisterRelease(pReNative, idxVarSrc);
    874874
    875     off = iemNativeEmitEFlagsForLogical<false>(pReNative, off, idxVarEfl, cOpBits, idxRegDst);
     875    off = iemNativeEmitEFlagsForLogical<false>(pReNative, off, idxVarEfl, a_cOpBits, idxRegDst);
    876876#else
    877877# error "Port me"
    … …  
    938938 * set the other flags according to the result.
    939939 */
    940 DECL_INLINE_THROW(uint32_t)
    941 iemNativeEmit_test_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off,
    942                            uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl, uint8_t cOpBits)
     940template<uint8_t const a_cOpBits>
     941DECL_INLINE_THROW(uint32_t)
     942iemNativeEmit_test_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl)
    943943{
    944944    uint8_t const         idxRegDst    = iemNativeVarRegisterAcquire(pReNative, idxVarDst, &off, true /*fInitialized*/);
    … …  
    948948    /* On AMD64 we just use the correctly sized TEST instruction harvest the EFLAGS. */
    949949    off = iemNativeEmitAmd64OneByteModRmInstrRREx(iemNativeInstrBufEnsure(pReNative, off, 4), off,
    950                                                   0x84, 0x85, cOpBits, idxRegSrc, idxRegDst);
     950                                                  0x84, 0x85, a_cOpBits, idxRegSrc, idxRegDst);
    951951    IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
    952952
    … …  
    956956    uint8_t const         idxRegResult = iemNativeRegAllocTmp(pReNative, &off);
    957957    PIEMNATIVEINSTR const pCodeBuf     = iemNativeInstrBufEnsure(pReNative, off, 1);
    958     if (cOpBits >= 32)
    959         pCodeBuf[off++] = Armv8A64MkInstrAnds(idxRegResult, idxRegDst, idxRegSrc, cOpBits > 32 /*f64Bit*/);
     958    if RT_CONSTEXPR_IF(a_cOpBits >= 32)
     959        pCodeBuf[off++] = Armv8A64MkInstrAnds(idxRegResult, idxRegDst, idxRegSrc, a_cOpBits > 32 /*f64Bit*/);
    960960    else
    961         pCodeBuf[off++] = Armv8A64MkInstrAnd(idxRegResult, idxRegDst, idxRegSrc, cOpBits > 32 /*f64Bit*/);
     961        pCodeBuf[off++] = Armv8A64MkInstrAnd(idxRegResult, idxRegDst, idxRegSrc, a_cOpBits > 32 /*f64Bit*/);
    962962    IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
    963963
    … …  
    970970
    971971#ifdef RT_ARCH_AMD64
    972     off = iemNativeEmitEFlagsForLogical<false>(pReNative, off, idxVarEfl, cOpBits, UINT8_MAX);
    973 #else
    974     if (cOpBits >= 32)
    975         off = iemNativeEmitEFlagsForLogical<false>(pReNative, off, idxVarEfl, cOpBits, idxRegResult);
     972    off = iemNativeEmitEFlagsForLogical<false>(pReNative, off, idxVarEfl, a_cOpBits, UINT8_MAX);
     973#else
     974    if RT_CONSTEXPR_IF(a_cOpBits >= 32)
     975        off = iemNativeEmitEFlagsForLogical<false>(pReNative, off, idxVarEfl, a_cOpBits, idxRegResult);
    976976    else
    977         off = iemNativeEmitEFlagsForLogical<true>(pReNative, off, idxVarEfl, cOpBits, idxRegResult);
     977        off = iemNativeEmitEFlagsForLogical<true>(pReNative, off, idxVarEfl, a_cOpBits, idxRegResult);
    978978    iemNativeRegFreeTmp(pReNative, idxRegResult);
    979979#endif
    … …  
    10431043 * set the other flags according to the result.
    10441044 */
    1045 DECL_INLINE_THROW(uint32_t)
    1046 iemNativeEmit_or_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off,
    1047                          uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl, uint8_t cOpBits)
     1045template<uint8_t const a_cOpBits>
     1046DECL_INLINE_THROW(uint32_t)
     1047iemNativeEmit_or_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl)
    10481048{
    10491049    uint8_t const idxRegDst = iemNativeVarRegisterAcquire(pReNative, idxVarDst, &off, true /*fInitialized*/);
    … …  
    10521052    /* On AMD64 we just use the correctly sized OR instruction harvest the EFLAGS. */
    10531053    off = iemNativeEmitAmd64OneByteModRmInstrRREx(iemNativeInstrBufEnsure(pReNative, off, 4), off,
    1054                                                   0x0a, 0x0b, cOpBits, idxRegDst, idxRegSrc);
     1054                                                  0x0a, 0x0b, a_cOpBits, idxRegDst, idxRegSrc);
    10551055    IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
    10561056    iemNativeVarRegisterRelease(pReNative, idxVarSrc);
    10571057
    1058     off = iemNativeEmitEFlagsForLogical<false>(pReNative, off, idxVarEfl, cOpBits, idxRegDst);
     1058    off = iemNativeEmitEFlagsForLogical<false>(pReNative, off, idxVarEfl, a_cOpBits, idxRegDst);
    10591059
    10601060#elif defined(RT_ARCH_ARM64)
    10611061    /* On ARM64 we use 32-bit OR for the 8-bit and 16-bit bit ones. */
    10621062    PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 1);
    1063     pCodeBuf[off++] = Armv8A64MkInstrOrr(idxRegDst, idxRegDst, idxRegSrc, cOpBits > 32 /*f64Bit*/);
     1063    pCodeBuf[off++] = Armv8A64MkInstrOrr(idxRegDst, idxRegDst, idxRegSrc, a_cOpBits > 32 /*f64Bit*/);
    10641064    IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
    10651065    iemNativeVarRegisterRelease(pReNative, idxVarSrc);
    10661066
    1067     off = iemNativeEmitEFlagsForLogical<true>(pReNative, off, idxVarEfl, cOpBits, idxRegDst);
     1067    off = iemNativeEmitEFlagsForLogical<true>(pReNative, off, idxVarEfl, a_cOpBits, idxRegDst);
    10681068
    10691069#else
    … …  
    11251125 * set the other flags according to the result.
    11261126 */
    1127 DECL_INLINE_THROW(uint32_t)
    1128 iemNativeEmit_xor_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off,
    1129                           uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl, uint8_t cOpBits)
     1127template<uint8_t const a_cOpBits>
     1128DECL_INLINE_THROW(uint32_t)
     1129iemNativeEmit_xor_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl)
    11301130{
    11311131    uint8_t const idxRegDst = iemNativeVarRegisterAcquire(pReNative, idxVarDst, &off, true /*fInitialized*/);
    … …  
    11341134    /* On AMD64 we just use the correctly sized OR instruction harvest the EFLAGS. */
    11351135    off = iemNativeEmitAmd64OneByteModRmInstrRREx(iemNativeInstrBufEnsure(pReNative, off, 4), off,
    1136                                                   0x32, 0x33, cOpBits, idxRegDst, idxRegSrc);
     1136                                                  0x32, 0x33, a_cOpBits, idxRegDst, idxRegSrc);
    11371137    IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
    11381138    iemNativeVarRegisterRelease(pReNative, idxVarSrc);
    11391139
    1140     off = iemNativeEmitEFlagsForLogical<false>(pReNative, off, idxVarEfl, cOpBits, idxRegDst);
     1140    off = iemNativeEmitEFlagsForLogical<false>(pReNative, off, idxVarEfl, a_cOpBits, idxRegDst);
    11411141
    11421142#elif defined(RT_ARCH_ARM64)
    11431143    /* On ARM64 we use 32-bit OR for the 8-bit and 16-bit bit ones. */
    11441144    PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 1);
    1145     pCodeBuf[off++] = Armv8A64MkInstrEor(idxRegDst, idxRegDst, idxRegSrc, cOpBits > 32 /*f64Bit*/);
     1145    pCodeBuf[off++] = Armv8A64MkInstrEor(idxRegDst, idxRegDst, idxRegSrc, a_cOpBits > 32 /*f64Bit*/);
    11461146    IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
    11471147    iemNativeVarRegisterRelease(pReNative, idxVarSrc);
    11481148
    1149     off = iemNativeEmitEFlagsForLogical<true>(pReNative, off, idxVarEfl, cOpBits, idxRegDst);
     1149    off = iemNativeEmitEFlagsForLogical<true>(pReNative, off, idxVarEfl, a_cOpBits, idxRegDst);
    11501150
    11511151#else
    … …  
    12111211 * The ADD instruction will set all status flags.
    12121212 */
    1213 DECL_INLINE_THROW(uint32_t)
    1214 iemNativeEmit_add_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off,
    1215                           uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl, uint8_t cOpBits)
     1213template<uint8_t const a_cOpBits>
     1214DECL_INLINE_THROW(uint32_t)
     1215iemNativeEmit_add_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl)
    12161216{
    12171217    uint8_t const idxRegDst = iemNativeVarRegisterAcquire(pReNative, idxVarDst, &off, true /*fInitialized*/);
    … …  
    12211221    /* On AMD64 we just use the correctly sized ADD instruction to get the right EFLAGS.SF value. */
    12221222    off = iemNativeEmitAmd64OneByteModRmInstrRREx(iemNativeInstrBufEnsure(pReNative, off, 4), off,
    1223                                                   0x02, 0x03, cOpBits, idxRegDst, idxRegSrc);
     1223                                                  0x02, 0x03, a_cOpBits, idxRegDst, idxRegSrc);
    12241224    IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
    12251225
    … …  
    12351235    uint8_t const         idxRegDstIn = iemNativeRegAllocTmp(pReNative, &off);
    12361236    PIEMNATIVEINSTR const pCodeBuf    = iemNativeInstrBufEnsure(pReNative, off, 4);
    1237     if (cOpBits >= 32)
     1237    if RT_CONSTEXPR_IF(a_cOpBits >= 32)
    12381238    {
    12391239        off = iemNativeEmitLoadGprFromGprEx(pCodeBuf, off, idxRegDstIn, idxRegDst);
    1240         pCodeBuf[off++] = Armv8A64MkInstrAddReg(idxRegDst, idxRegDst, idxRegSrc, cOpBits > 32 /*f64Bit*/, true /*fSetFlags*/);
     1240        pCodeBuf[off++] = Armv8A64MkInstrAddReg(idxRegDst, idxRegDst, idxRegSrc, a_cOpBits > 32 /*f64Bit*/, true /*fSetFlags*/);
    12411241    }
    12421242    else
    12431243    {
    12441244        /* Shift the operands up so we can perform a 32-bit operation and get all four flags. */
    1245         uint32_t const cShift = 32 - cOpBits;
     1245        uint32_t const cShift = 32 - a_cOpBits;
    12461246        pCodeBuf[off++] = Armv8A64MkInstrOrr(idxRegDstIn, ARMV8_A64_REG_XZR, idxRegDst, false /*f64Bit*/, cShift);
    12471247        pCodeBuf[off++] = Armv8A64MkInstrAddReg(idxRegDst, idxRegDstIn, idxRegSrc, false /*f64Bit*/,
    … …  
    12491249        pCodeBuf[off++] = Armv8A64MkInstrLsrImm(idxRegDstIn, idxRegDstIn, cShift, false /*f64Bit*/);
    12501250        pCodeBuf[off++] = Armv8A64MkInstrLsrImm(idxRegDst, idxRegDst, cShift, false /*f64Bit*/);
    1251         cOpBits = 32;
    1252     }
    1253     IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
    1254 
    1255     off = iemNativeEmitEFlagsForArithmetic(pReNative, off, idxVarEfl, UINT8_MAX, cOpBits, idxRegDst,
     1251    }
     1252    IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
     1253
     1254    off = iemNativeEmitEFlagsForArithmetic(pReNative, off, idxVarEfl, UINT8_MAX, a_cOpBits > 32 ? a_cOpBits : 32, idxRegDst,
    12561255                                           idxRegDstIn, idxRegSrc, false /*fInvertCarry*/, 0);
    12571256
    … …  
    13381337 * The ADC instruction takes CF as input and will set all status flags.
    13391338 */
    1340 DECL_INLINE_THROW(uint32_t)
    1341 iemNativeEmit_adc_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off,
    1342                           uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl, uint8_t cOpBits)
     1339template<uint8_t const a_cOpBits>
     1340DECL_INLINE_THROW(uint32_t)
     1341iemNativeEmit_adc_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl)
    13431342{
    13441343    uint8_t const idxRegDst = iemNativeVarRegisterAcquire(pReNative, idxVarDst, &off, true /*fInitialized*/);
    … …  
    13551354    pCodeBuf[off++] = X86_EFL_CF_BIT;
    13561355
    1357     off = iemNativeEmitAmd64OneByteModRmInstrRREx(pCodeBuf, off, 0x12, 0x13, cOpBits, idxRegDst, idxRegSrc);
     1356    off = iemNativeEmitAmd64OneByteModRmInstrRREx(pCodeBuf, off, 0x12, 0x13, a_cOpBits, idxRegDst, idxRegSrc);
    13581357    IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
    13591358
    … …  
    13721371    pCodeBuf[off++] = Armv8A64MkInstrRmif(idxRegEfl, (X86_EFL_CF_BIT - 1) & 63, RT_BIT_32(1) /*fMask=C*/);
    13731372    off = iemNativeEmitLoadGprFromGprEx(pCodeBuf, off, idxRegDstIn, idxRegDst);
    1374     if (cOpBits >= 32)
    1375         pCodeBuf[off++] = Armv8A64MkInstrAdcs(idxRegDst, idxRegDst, idxRegSrc, cOpBits > 32 /*f64Bit*/);
     1373    if RT_CONSTEXPR_IF(a_cOpBits >= 32)
     1374        pCodeBuf[off++] = Armv8A64MkInstrAdcs(idxRegDst, idxRegDst, idxRegSrc, a_cOpBits > 32 /*f64Bit*/);
    13761375    else
    13771376    {
    … …  
    13791378           doesn't work. So, we have to calculate carry & overflow manually. */
    13801379        pCodeBuf[off++] = Armv8A64MkInstrAdc(idxRegDst, idxRegDst, idxRegSrc, false /*f64Bit*/);
    1381         pCodeBuf[off++] = Armv8A64MkInstrSetF8SetF16(idxRegDst, cOpBits > 8); /* NZ are okay, CV aren't.*/
    1382     }
    1383     IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
    1384 
    1385     off = iemNativeEmitEFlagsForArithmetic(pReNative, off, UINT8_MAX, idxRegEfl, cOpBits, idxRegDst,
     1380        pCodeBuf[off++] = Armv8A64MkInstrSetF8SetF16(idxRegDst, a_cOpBits > 8); /* NZ are okay, CV aren't.*/
     1381    }
     1382    IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
     1383
     1384    off = iemNativeEmitEFlagsForArithmetic(pReNative, off, UINT8_MAX, idxRegEfl, a_cOpBits, idxRegDst,
    13861385                                           idxRegDstIn, idxRegSrc, false /*fInvertCarry*/, 0);
    13871386
    13881387    iemNativeRegFreeTmp(pReNative, idxRegDstIn);
    13891388    iemNativeVarRegisterRelease(pReNative, idxVarSrc);
    1390     if (cOpBits < 32)
    1391         off = iemNativeEmitAndGpr32ByImm(pReNative, off, idxRegDst, RT_BIT_32(cOpBits) - 1U);
     1389    if RT_CONSTEXPR_IF(a_cOpBits < 32)
     1390        off = iemNativeEmitAndGpr32ByImm(pReNative, off, idxRegDst, RT_BIT_32(a_cOpBits) - 1U);
    13921391    iemNativeVarRegisterRelease(pReNative, idxVarDst);
    13931392
    … …  
    14671466 * The SUB instruction will set all status flags.
    14681467 */
    1469 DECL_INLINE_THROW(uint32_t)
    1470 iemNativeEmit_sub_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off,
    1471                           uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl, uint8_t cOpBits)
     1468template<uint8_t const a_cOpBits>
     1469DECL_INLINE_THROW(uint32_t)
     1470iemNativeEmit_sub_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl)
    14721471{
    14731472    uint8_t const idxRegDst = iemNativeVarRegisterAcquire(pReNative, idxVarDst, &off, true /*fInitialized*/);
    … …  
    14771476    /* On AMD64 we just use the correctly sized SUB instruction to get the right EFLAGS.SF value. */
    14781477    off = iemNativeEmitAmd64OneByteModRmInstrRREx(iemNativeInstrBufEnsure(pReNative, off, 4), off,
    1479                                                   0x2a, 0x2b, cOpBits, idxRegDst, idxRegSrc);
     1478                                                  0x2a, 0x2b, a_cOpBits, idxRegDst, idxRegSrc);
    14801479    IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
    14811480
    … …  
    14911490    uint8_t const         idxRegDstIn = iemNativeRegAllocTmp(pReNative, &off);
    14921491    PIEMNATIVEINSTR const pCodeBuf    = iemNativeInstrBufEnsure(pReNative, off, 4);
    1493     if (cOpBits >= 32)
     1492    if RT_CONSTEXPR_IF(a_cOpBits >= 32)
    14941493    {
    14951494        off = iemNativeEmitLoadGprFromGprEx(pCodeBuf, off, idxRegDstIn, idxRegDst);
    1496         pCodeBuf[off++] = Armv8A64MkInstrSubReg(idxRegDst, idxRegDst, idxRegSrc, cOpBits > 32 /*f64Bit*/, true /*fSetFlags*/);
     1495        pCodeBuf[off++] = Armv8A64MkInstrSubReg(idxRegDst, idxRegDst, idxRegSrc, a_cOpBits > 32 /*f64Bit*/, true /*fSetFlags*/);
    14971496    }
    14981497    else
    14991498    {
    15001499        /* Shift the operands up so we can perform a 32-bit operation and get all four flags. */
    1501         uint32_t const cShift = 32 - cOpBits;
     1500        uint32_t const cShift = 32 - a_cOpBits;
    15021501        pCodeBuf[off++] = Armv8A64MkInstrOrr(idxRegDstIn, ARMV8_A64_REG_XZR, idxRegDst, false /*f64Bit*/, cShift);
    15031502        pCodeBuf[off++] = Armv8A64MkInstrSubReg(idxRegDst, idxRegDstIn, idxRegSrc, false /*f64Bit*/,
    … …  
    15051504        pCodeBuf[off++] = Armv8A64MkInstrLsrImm(idxRegDstIn, idxRegDstIn, cShift, false /*f64Bit*/);
    15061505        pCodeBuf[off++] = Armv8A64MkInstrLsrImm(idxRegDst, idxRegDst, cShift, false /*f64Bit*/);
    1507         cOpBits = 32;
    1508     }
    1509     IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
    1510 
    1511     off = iemNativeEmitEFlagsForArithmetic(pReNative, off, idxVarEfl, UINT8_MAX, cOpBits, idxRegDst,
     1506    }
     1507    IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
     1508
     1509    off = iemNativeEmitEFlagsForArithmetic(pReNative, off, idxVarEfl, UINT8_MAX, a_cOpBits > 32 ? a_cOpBits : 32, idxRegDst,
    15121510                                           idxRegDstIn, idxRegSrc, true /*fInvertCarry*/, 0);
    15131511
    … …  
    15961594 * The CMP instruction will set all status flags, but modifies no registers.
    15971595 */
    1598 DECL_INLINE_THROW(uint32_t)
    1599 iemNativeEmit_cmp_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off,
    1600                           uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl, uint8_t cOpBits)
     1596template<uint8_t const a_cOpBits>
     1597DECL_INLINE_THROW(uint32_t)
     1598iemNativeEmit_cmp_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl)
    16011599{
    16021600    uint8_t const idxRegDst = iemNativeVarRegisterAcquire(pReNative, idxVarDst, &off, true /*fInitialized*/);
    … …  
    16061604    /* On AMD64 we just use the correctly sized CMP instruction to get the right EFLAGS.SF value. */
    16071605    off = iemNativeEmitAmd64OneByteModRmInstrRREx(iemNativeInstrBufEnsure(pReNative, off, 4), off,
    1608                                                   0x3a, 0x3b, cOpBits, idxRegDst, idxRegSrc);
     1606                                                  0x3a, 0x3b, a_cOpBits, idxRegDst, idxRegSrc);
    16091607    IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
    16101608
    … …  
    16201618    uint8_t const         idxRegResult = iemNativeRegAllocTmp(pReNative, &off);
    16211619    PIEMNATIVEINSTR const pCodeBuf     = iemNativeInstrBufEnsure(pReNative, off, 3);
    1622     if (cOpBits >= 32)
    1623         pCodeBuf[off++] = Armv8A64MkInstrSubReg(idxRegResult, idxRegDst, idxRegSrc, cOpBits > 32 /*f64Bit*/, true /*fSetFlags*/);
     1620    if RT_CONSTEXPR_IF(a_cOpBits >= 32)
     1621        pCodeBuf[off++] = Armv8A64MkInstrSubReg(idxRegResult, idxRegDst, idxRegSrc, a_cOpBits > 32 /*f64Bit*/, true /*fSetFlags*/);
    16241622    else
    16251623    {
    16261624        /* Shift the operands up so we can perform a 32-bit operation and get all four flags. */
    1627         uint32_t const cShift = 32 - cOpBits;
     1625        uint32_t const cShift = 32 - a_cOpBits;
    16281626        pCodeBuf[off++] = Armv8A64MkInstrOrr(idxRegResult, ARMV8_A64_REG_XZR, idxRegDst, false /*f64Bit*/, cShift);
    16291627        pCodeBuf[off++] = Armv8A64MkInstrSubReg(idxRegResult, idxRegResult, idxRegSrc, false /*f64Bit*/,
    16301628                                                true /*fSetFlags*/, cShift);
    16311629        pCodeBuf[off++] = Armv8A64MkInstrLsrImm(idxRegResult, idxRegResult, cShift, false /*f64Bit*/);
    1632         cOpBits = 32;
    1633     }
    1634     IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
    1635 
    1636     off = iemNativeEmitEFlagsForArithmetic(pReNative, off, idxVarEfl, UINT8_MAX, cOpBits, idxRegResult,
     1630    }
     1631    IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
     1632
     1633    off = iemNativeEmitEFlagsForArithmetic(pReNative, off, idxVarEfl, UINT8_MAX, a_cOpBits > 32 ? a_cOpBits : 32, idxRegResult,
    16371634                                           idxRegDst, idxRegSrc, true /*fInvertCarry*/, 0);
    16381635
    … …  
    17191716 * The SBB instruction takes CF as input and will set all status flags.
    17201717 */
    1721 DECL_INLINE_THROW(uint32_t)
    1722 iemNativeEmit_sbb_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off,
    1723                           uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl, uint8_t cOpBits)
     1718template<uint8_t const a_cOpBits>
     1719DECL_INLINE_THROW(uint32_t)
     1720iemNativeEmit_sbb_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl)
    17241721{
    17251722    uint8_t const idxRegDst = iemNativeVarRegisterAcquire(pReNative, idxVarDst, &off, true /*fInitialized*/);
    … …  
    17351732    pCodeBuf[off++] = X86_EFL_CF_BIT;
    17361733
    1737     off = iemNativeEmitAmd64OneByteModRmInstrRREx(pCodeBuf, off, 0x1a, 0x1b, cOpBits, idxRegDst, idxRegSrc);
     1734    off = iemNativeEmitAmd64OneByteModRmInstrRREx(pCodeBuf, off, 0x1a, 0x1b, a_cOpBits, idxRegDst, idxRegSrc);
    17381735    IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
    17391736
    … …  
    17541751    pCodeBuf[off++] = ARMV8_A64_INSTR_CFINV;
    17551752    off = iemNativeEmitLoadGprFromGprEx(pCodeBuf, off, idxRegDstIn, idxRegDst);
    1756     if (cOpBits >= 32)
    1757         pCodeBuf[off++] = Armv8A64MkInstrSbcs(idxRegDst, idxRegDst, idxRegSrc, cOpBits > 32 /*f64Bit*/);
     1753    if RT_CONSTEXPR_IF(a_cOpBits >= 32)
     1754        pCodeBuf[off++] = Armv8A64MkInstrSbcs(idxRegDst, idxRegDst, idxRegSrc, a_cOpBits > 32 /*f64Bit*/);
    17581755    else
    17591756    {
    … …  
    17611758           doesn't work. So, we have to calculate carry & overflow manually. */
    17621759        pCodeBuf[off++] = Armv8A64MkInstrSbc(idxRegDst, idxRegDst, idxRegSrc, false /*f64Bit*/);
    1763         pCodeBuf[off++] = Armv8A64MkInstrSetF8SetF16(idxRegDst, cOpBits > 8); /* NZ are okay, CV aren't.*/
    1764     }
    1765     IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
    1766 
    1767     off = iemNativeEmitEFlagsForArithmetic(pReNative, off, UINT8_MAX, idxRegEfl, cOpBits, idxRegDst,
     1760        pCodeBuf[off++] = Armv8A64MkInstrSetF8SetF16(idxRegDst, a_cOpBits > 8); /* NZ are okay, CV aren't.*/
     1761    }
     1762    IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
     1763
     1764    off = iemNativeEmitEFlagsForArithmetic(pReNative, off, UINT8_MAX, idxRegEfl, a_cOpBits, idxRegDst,
    17681765                                           idxRegDstIn, idxRegSrc, true /*fInvertCarry*/, 0);
    17691766
    17701767    iemNativeRegFreeTmp(pReNative, idxRegDstIn);
    17711768    iemNativeVarRegisterRelease(pReNative, idxVarSrc);
    1772     if (cOpBits < 32)
    1773         off = iemNativeEmitAndGpr32ByImm(pReNative, off, idxRegDst, RT_BIT_32(cOpBits) - 1U);
     1769    if RT_CONSTEXPR_IF(a_cOpBits < 32)
     1770        off = iemNativeEmitAndGpr32ByImm(pReNative, off, idxRegDst, RT_BIT_32(a_cOpBits) - 1U);
    17741771    iemNativeVarRegisterRelease(pReNative, idxVarDst);
    17751772
    … …  
    18481845
    18491846
    1850 DECL_INLINE_THROW(uint32_t)
    1851 iemNativeEmit_imul_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off,
    1852                            uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl, uint8_t cOpBits)
    1853 {
    1854     RT_NOREF(idxVarDst, idxVarSrc, idxVarEfl, cOpBits);
     1847template<uint8_t const a_cOpBits>
     1848DECL_INLINE_THROW(uint32_t)
     1849iemNativeEmit_imul_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl)
     1850{
     1851    RT_NOREF(idxVarDst, idxVarSrc, idxVarEfl);
    18551852    AssertFailed();
    18561853    return iemNativeEmitBrk(pReNative, off, 0x666);
    … …  
    18581855
    18591856
    1860 DECL_INLINE_THROW(uint32_t)
    1861 iemNativeEmit_popcnt_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off,
    1862                              uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl, uint8_t cOpBits)
    1863 {
    1864     RT_NOREF(idxVarDst, idxVarSrc, idxVarEfl, cOpBits);
     1857template<uint8_t const a_cOpBits>
     1858DECL_INLINE_THROW(uint32_t)
     1859iemNativeEmit_popcnt_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl)
     1860{
     1861    RT_NOREF(idxVarDst, idxVarSrc, idxVarEfl);
    18651862    AssertFailed();
    18661863    return iemNativeEmitBrk(pReNative, off, 0x666);
    … …  
    18681865
    18691866
    1870 DECL_INLINE_THROW(uint32_t)
    1871 iemNativeEmit_tzcnt_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off,
    1872                             uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl, uint8_t cOpBits)
    1873 {
    1874     RT_NOREF(idxVarDst, idxVarSrc, idxVarEfl, cOpBits);
     1867template<uint8_t const a_cOpBits>
     1868DECL_INLINE_THROW(uint32_t)
     1869iemNativeEmit_tzcnt_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl)
     1870{
     1871    RT_NOREF(idxVarDst, idxVarSrc, idxVarEfl);
    18751872    AssertFailed();
    18761873    return iemNativeEmitBrk(pReNative, off, 0x666);
    … …  
    18781875
    18791876
    1880 DECL_INLINE_THROW(uint32_t)
    1881 iemNativeEmit_lzcnt_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off,
    1882                             uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl, uint8_t cOpBits)
    1883 {
    1884     RT_NOREF(idxVarDst, idxVarSrc, idxVarEfl, cOpBits);
     1877template<uint8_t const a_cOpBits>
     1878DECL_INLINE_THROW(uint32_t)
     1879iemNativeEmit_lzcnt_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl)
     1880{
     1881    RT_NOREF(idxVarDst, idxVarSrc, idxVarEfl);
    18851882    AssertFailed();
    18861883    return iemNativeEmitBrk(pReNative, off, 0x666);
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