- Timestamp:
- Oct 3, 2024 8:25:02 AM (7 months ago)
- svn:sync-xref-src-repo-rev:
- 164997
- File:
-
- 1 edited
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trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32
r106205 r106213 105 105 #define FP32_QNAN(a_Sign) RTFLOAT32U_INIT_QNAN(a_Sign) 106 106 #define FP32_QNAN_V(a_Sign, a_Val) RTFLOAT32U_INIT_QNAN_EX(a_Sign, a_Val) 107 #define FP32_QNAN_MAX(a_Sign) RTFLOAT32U_INIT_QNAN_EX(a_Sign, FP32_FRAC_QNAN_MAX) 107 108 #define FP32_SNAN(a_Sign) RTFLOAT32U_INIT_SNAN(a_Sign) 108 109 #define FP32_SNAN_V(a_Sign, a_Val) RTFLOAT32U_INIT_SNAN_EX(a_Sign, a_Val) 110 #define FP32_SNAN_MAX(a_Sign) RTFLOAT32U_INIT_SNAN_EX(a_Sign, FP32_FRAC_SNAN_MAX) 109 111 /** @todo Move this to iprt/types.h after renaming it to RTFLOAT32U_MAKE? */ 110 112 #ifdef RT_BIG_ENDIAN … … 194 196 /* 195 197 * Single-precision floating-point invalids. 196 * (1 to 0x3fffff fractional part for SNANs and 0x400000 to 0x7fffff for QNAN). 198 * 1 to 0x3fffff fractional part for SNANs and 0x400000 to 0x7fffff for QNAN. 199 * The QNAN initialization macro ensures the range for QNAN is correct by OR'ing 0x400000. 197 200 */ 198 201 #define FP32_FRAC_INV_V0 0x3fffff … … 625 628 **/ 626 629 #define FP32_TABLE_D1_PS_INVALIDS \ 627 /*0 */{ { /*src2 */ { FP32_QNAN(0), FP32_QNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },\628 { /*src1 */ { FP32_QNAN(0), FP32_QNAN _V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },\629 { /* => */ { FP32_QNAN(0), FP32_QNAN _V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },\630 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 631 /*128:out */ X86_MXCSR_XCPT_MASK, 632 /*256:out */ X86_MXCSR_XCPT_MASK, 633 /*xcpt? */ false, false }, 634 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, \635 { /*src1 */ { FP32_SNAN(0), FP32_SNAN _V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, \636 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, \637 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 638 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 639 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 640 /*xcpt? */ false, false }, 641 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN _V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },\642 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },\643 { /* => */ { FP32_QNAN(0), FP32_QNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },\644 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, 645 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, 646 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, 647 /*xcpt? */ false, false }, 648 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN _V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },\649 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },\650 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2) } },\651 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 652 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 653 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 654 /*xcpt? */ false, false }, 655 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_ V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } },\656 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },\657 { /* => */ { FP32_QNAN(0), FP32_QNAN_ V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } },\658 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS, 659 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS, 660 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS, 661 /*xcpt? */ false, false }, 662 { { /*src2 */ { FP32_SNAN(1), FP32_SNAN_ V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } },\663 { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },\664 { /* => */ { FP32_QNAN_V(1, 1), FP32_QNAN_ V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } },\665 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 666 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 667 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 668 /*xcpt? */ false, false }, 669 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },\670 { /*src1 */ { FP32_QNAN(0), FP32_QNAN _V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },\671 { /* => */ { FP32_QNAN(0), FP32_QNAN _V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },\672 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 673 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 674 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 675 /*xcpt? */ false, false }, 676 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, \677 { /*src1 */ { FP32_SNAN(0), FP32_SNAN _V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, \678 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, \679 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 680 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 681 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 682 /*xcpt? */ true, true }, 683 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN _V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },\684 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },\685 { /* => */ { FP32_QNAN(0), FP32_QNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },\686 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 687 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, 688 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, 689 /*xcpt? */ true, true }, 690 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN _V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },\691 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },\692 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2) } },\693 /*mxcsr:in */ X86_MXCSR_RC_UP, 694 /*128:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, 695 /*256:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, 696 /*xcpt? */ true, true }, 697 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_ V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } },\698 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },\699 { /* => */ { FP32_QNAN(0), FP32_QNAN_ V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } },\700 /*mxcsr:in */ 0, 701 /*128:out */ 0, 702 /*256:out */ 0, 703 /*xcpt? */ false, false }, 704 /*11*/{ { /*src2 */ { FP32_SNAN(1), FP32_SNAN_ V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } },\705 { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },\706 { /* => */ { FP32_QNAN_V(1, 1), FP32_QNAN_ V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } },\707 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 708 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 709 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 710 /*xcpt? */ true, true }, 630 /*0 */{ { /*src2 */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \ 631 { /*src1 */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } }, \ 632 { /* => */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } }, \ 633 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 634 /*128:out */ X86_MXCSR_XCPT_MASK, \ 635 /*256:out */ X86_MXCSR_XCPT_MASK, \ 636 /*xcpt? */ false, false }, \ 637 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \ 638 { /*src1 */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_MAX(0), FP32_SNAN_V2(0), FP32_SNAN_V6(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V4(0) } }, \ 639 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } }, \ 640 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 641 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 642 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 643 /*xcpt? */ false, false }, \ 644 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_V1(0), FP32_SNAN_V1(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V5(0), FP32_SNAN_V6(0) } }, \ 645 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } }, \ 646 { /* => */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } }, \ 647 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, \ 648 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, \ 649 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, \ 650 /*xcpt? */ false, false }, \ 651 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V7(0), FP32_SNAN_V1(0), FP32_SNAN_V6(0), FP32_SNAN_V1(0) } }, \ 652 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_MAX(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } }, \ 653 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_MAX(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V5(0), FP32_QNAN_V3(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0) } }, \ 654 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 655 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 656 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 657 /*xcpt? */ false, false }, \ 658 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_MAX(1), FP32_NORM_V0(1), FP32_QNAN_V1(0), FP32_NORM_V3(0), FP32_QNAN_V3(1), FP32_NORM_V5(0), FP32_QNAN_V5(1) } }, \ 659 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V0(1), FP32_NORM_V2(1), FP32_QNAN_V2(0), FP32_NORM_V4(0), FP32_QNAN_V4(1), FP32_NORM_V6(1) } }, \ 660 { /* => */ { FP32_QNAN(0), FP32_QNAN_MAX(1), FP32_QNAN_V0(1), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(1), FP32_QNAN_V4(1), FP32_QNAN_V5(1) } }, \ 661 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS, \ 662 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS, \ 663 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS, \ 664 /*xcpt? */ false, false }, \ 665 { { /*src2 */ { FP32_SNAN(1), FP32_SNAN_MAX(1), FP32_NORM_V0(1), FP32_SNAN_V1(0), FP32_NORM_V3(0), FP32_SNAN_V3(1), FP32_NORM_V5(0), FP32_SNAN_V5(1) } }, \ 666 { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V0(1), FP32_NORM_V2(1), FP32_SNAN_V2(1), FP32_NORM_V4(0), FP32_SNAN_V4(1), FP32_NORM_V6(1) } }, \ 667 { /* => */ { FP32_QNAN_V(1, 1), FP32_QNAN_MAX(1), FP32_QNAN_V0(1), FP32_QNAN_V1(0), FP32_QNAN_V2(1), FP32_QNAN_V3(1), FP32_QNAN_V4(1), FP32_QNAN_V5(1) } }, \ 668 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 669 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 670 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 671 /*xcpt? */ false, false }, \ 672 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \ 673 { /*src1 */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } }, \ 674 { /* => */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } }, \ 675 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, \ 676 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, \ 677 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, \ 678 /*xcpt? */ false, false }, \ 679 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \ 680 { /*src1 */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_MAX(0), FP32_SNAN_V2(0), FP32_SNAN_V6(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V4(0) } }, \ 681 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } }, \ 682 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, \ 683 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, \ 684 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, \ 685 /*xcpt? */ true, true }, \ 686 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_V1(0), FP32_SNAN_V1(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V5(0), FP32_SNAN_V6(0) } }, \ 687 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } }, \ 688 { /* => */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } }, \ 689 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, \ 690 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, \ 691 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, \ 692 /*xcpt? */ true, true }, \ 693 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V7(0), FP32_SNAN_V1(0), FP32_SNAN_V6(0), FP32_SNAN_V1(0) } }, \ 694 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_MAX(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } }, \ 695 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_MAX(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V5(0), FP32_QNAN_V3(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0) } }, \ 696 /*mxcsr:in */ X86_MXCSR_RC_UP, \ 697 /*128:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, \ 698 /*256:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, \ 699 /*xcpt? */ true, true }, \ 700 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_MAX(1), FP32_NORM_V0(1), FP32_QNAN_V1(0), FP32_NORM_V3(0), FP32_QNAN_V3(1), FP32_NORM_V5(0), FP32_QNAN_V5(1) } }, \ 701 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V0(1), FP32_NORM_V2(1), FP32_QNAN_V2(0), FP32_NORM_V4(0), FP32_QNAN_V4(1), FP32_NORM_V6(1) } }, \ 702 { /* => */ { FP32_QNAN(0), FP32_QNAN_MAX(1), FP32_QNAN_V0(1), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(1), FP32_QNAN_V4(1), FP32_QNAN_V5(1) } }, \ 703 /*mxcsr:in */ 0, \ 704 /*128:out */ 0, \ 705 /*256:out */ 0, \ 706 /*xcpt? */ false, false }, \ 707 /*11*/{ { /*src2 */ { FP32_SNAN(1), FP32_SNAN_MAX(1), FP32_NORM_V0(1), FP32_SNAN_V1(0), FP32_NORM_V3(0), FP32_SNAN_V3(1), FP32_NORM_V5(0), FP32_SNAN_V5(1) } }, \ 708 { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V0(1), FP32_NORM_V2(1), FP32_SNAN_V2(1), FP32_NORM_V4(0), FP32_SNAN_V4(1), FP32_NORM_V6(1) } }, \ 709 { /* => */ { FP32_QNAN_V(1, 1), FP32_QNAN_MAX(1), FP32_QNAN_V0(1), FP32_QNAN_V1(0), FP32_QNAN_V2(1), FP32_QNAN_V3(1), FP32_QNAN_V4(1), FP32_QNAN_V5(1) } }, \ 710 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, \ 711 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, \ 712 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, \ 713 /*xcpt? */ true, true }, \ 711 714 712 715 /** … … 806 809 #define FP32_TABLE_D1_SS_INVALIDS \ 807 810 /* QNan, QNan (Masked). */ \ 808 /*0 */{ { /*src2 */ { FP32_QNAN(0), FP32_QNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },\809 { /*src1 */ { FP32_QNAN(0), FP32_QNAN _V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },\810 { /* => */ { FP32_QNAN(0), FP32_QNAN _V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },\811 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 812 /*128:out */ X86_MXCSR_XCPT_MASK, 813 /*256:out */ X86_MXCSR_XCPT_MASK, 814 /*xcpt? */ false, false }, 815 { { /*src2 */ { FP32_QNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } },\816 { /*src1 */ { FP32_QNAN _V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },\817 { /* => */ { FP32_QNAN _V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },\818 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 819 /*128:out */ X86_MXCSR_XCPT_MASK, 820 /*256:out */ X86_MXCSR_XCPT_MASK, 821 /*xcpt? */ false, false }, 822 { { /*src2 */ { FP32_QNAN_V (0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } },\823 { /*src1 */ { FP32_QNAN_V (0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },\824 { /* => */ { FP32_QNAN_V (0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },\825 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 826 /*128:out */ X86_MXCSR_XCPT_MASK, 827 /*256:out */ X86_MXCSR_XCPT_MASK, 828 /*xcpt? */ false, false }, 829 /* QNan, SNan (Masked). */ 830 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V (0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } },\831 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V (0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V1) } },\832 { /* => */ { FP32_QNAN_V(0, 1), FP32_ QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },\833 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 834 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 835 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 836 /*xcpt? */ false, false }, 837 { { /*src2 */ { FP32_QNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, \838 { /*src1 */ { FP32_SNAN _V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, \839 { /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, \840 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 841 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 842 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 843 /*xcpt? */ false, false }, 844 { { /*src2 */ { FP32_QNAN_V (0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },\845 { /*src1 */ { FP32_SNAN_V (0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },\846 { /* => */ { FP32_ SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },\847 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 848 /*128:out */ X86_MXCSR_XCPT_MASK ,\849 /*256:out */ X86_MXCSR_XCPT_MASK ,\850 /*xcpt? */ false, false }, 851 /* SNan, QNan (Masked). */ 852 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN _V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },\853 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },\854 { /* => */ { FP32_QNAN(0), FP32_QNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },\855 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 856 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 857 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 858 /*xcpt? */ false, false }, 859 { { /*src2 */ { FP32_SNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },\860 { /*src1 */ { FP32_QNAN _V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },\861 { /* => */ { FP32_QNAN _V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },\862 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 863 /*128:out */ X86_MXCSR_XCPT_MASK ,\864 /*256:out */ X86_MXCSR_XCPT_MASK ,\865 /*xcpt? */ false, false }, 866 { { /*src2 */ { FP32_SNAN_V (0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },\867 { /*src1 */ { FP32_QNAN_V (0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },\868 { /* => */ { FP32_QNAN_V (0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },\869 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 870 /*128:out */ X86_MXCSR_XCPT_MASK ,\871 /*256:out */ X86_MXCSR_XCPT_MASK ,\872 /*xcpt? */ false, false }, 873 /* SNan, SNan (Masked). */ 874 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN _V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },\875 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },\876 { /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },\877 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 878 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 879 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 880 /*xcpt? */ false, false }, 881 { { /*src2 */ { FP32_SNAN _V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },\882 { /*src1 */ { FP32_SNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },\883 { /* => */ { FP32_ SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },\884 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 885 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 886 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 887 /*xcpt? */ false, false }, 888 { { /*src2 */ { FP32_SNAN_V (0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },\889 { /*src1 */ { FP32_SNAN_V (0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } },\890 { /* => */ { FP32_QNAN_V (0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } },\891 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 892 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 893 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 894 /*xcpt? */ false, false }, 895 /* QNan, Norm FP (Masked). */ 896 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_ V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } },\897 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },\898 { /* => */ { FP32_QNAN(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },\899 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 900 /*128:out */ X86_MXCSR_XCPT_MASK, 901 /*256:out */ X86_MXCSR_XCPT_MASK, 902 /*xcpt? */ false, false }, 903 /* SNan, Norm FP (Masked). */ 904 { { /*src2 */ { FP32_SNAN(1), FP32_SNAN_ V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } },\905 { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },\906 { /* => */ { FP32_QNAN_V(1, 1), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },\907 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 908 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 909 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 910 /*xcpt? */ false, false }, 911 /* QNan, QNan (Unmasked). */ 912 /*14*/{ { /*src2 */ { FP32_QNAN(0), FP32_QNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },\913 { /*src1 */ { FP32_QNAN(0), FP32_QNAN _V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },\914 { /* => */ { FP32_QNAN(0), FP32_QNAN _V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },\915 /*mxcsr:in */ 0, 916 /*128:out */ 0, 917 /*256:out */ 0, 918 /*xcpt? */ false, false }, 919 { { /*src2 */ { FP32_QNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } },\920 { /*src1 */ { FP32_QNAN _V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },\921 { /* => */ { FP32_QNAN _V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },\922 /*mxcsr:in */ 0, 923 /*128:out */ 0, 924 /*256:out */ 0, 925 /*xcpt? */ false, false }, 926 { { /*src2 */ { FP32_QNAN_V (0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } },\927 { /*src1 */ { FP32_QNAN_V (0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },\928 { /* => */ { FP32_QNAN_V (0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },\929 /*mxcsr:in */ 0, 930 /*128:out */ 0, 931 /*256:out */ 0, 932 /*xcpt? */ false, false }, 933 934 /* QNan, SNan (Unmasked). */ 935 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V (0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } },\936 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V (0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V1) } },\937 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V (0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },\938 /*mxcsr:in */ 0, 939 /*128:out */ X86_MXCSR_IE, 940 /*256:out */ X86_MXCSR_IE, 941 /*xcpt? */ true, true }, 942 { { /*src2 */ { FP32_QNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, \943 { /*src1 */ { FP32_SNAN _V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, \944 { /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, \945 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 946 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, 947 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, 948 /*xcpt? */ true, true }, 949 { { /*src2 */ { FP32_QNAN_V (0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },\950 { /*src1 */ { FP32_SNAN_V (0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },\951 { /* => */ { FP32_SNAN_V (0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },\952 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 953 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO ,\954 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO ,\955 /*xcpt? */ false, false },\956 /* SNan, QNan (Unmasked). */ 957 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN _V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },\958 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },\959 { /* => */ { FP32_QNAN(0), FP32_QNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },\960 /*mxcsr:in */ X86_MXCSR_DAZ, 961 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_IE, 962 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_IE, 963 /*xcpt? */ true, true }, 964 { { /*src2 */ { FP32_SNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },\965 { /*src1 */ { FP32_QNAN _V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },\966 { /* => */ { FP32_QNAN _V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },\967 /*mxcsr:in */ X86_MXCSR_RC_UP, 968 /*128:out */ X86_MXCSR_RC_UP ,\969 /*256:out */ X86_MXCSR_RC_UP ,\970 /*xcpt? */ false, false },\971 { { /*src2 */ { FP32_SNAN_V (0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },\972 { /*src1 */ { FP32_QNAN_V (0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },\973 { /* => */ { FP32_QNAN_V (0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },\974 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 975 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN ,\976 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN ,\977 /*xcpt? */ false, false },\978 /* SNan, SNan (Unmasked). */ 979 /*24*/{ { /*src2 */ { FP32_SNAN(0), FP32_SNAN _V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },\980 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },\981 { /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },\982 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 983 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE, 984 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE, 985 /*xcpt? */ true, true }, 986 { { /*src2 */ { FP32_SNAN _V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },\987 { /*src1 */ { FP32_SNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },\988 { /* => */ { FP32_SNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },\989 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 990 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 991 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 992 /*xcpt? */ true, true }, 993 { { /*src2 */ { FP32_SNAN_V (0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },\994 { /*src1 */ { FP32_SNAN_V (0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } },\995 { /* => */ { FP32_QNAN_V (0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } },\996 /*mxcsr:in */ 0, 997 /*128:out */ X86_MXCSR_IE, 998 /*256:out */ X86_MXCSR_IE, 999 /*xcpt? */ true, true }, 1000 /* QNan, Norm FP (Unmasked). */ 1001 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_ V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } },\1002 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },\1003 { /* => */ { FP32_QNAN(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },\1004 /*mxcsr:in */ X86_MXCSR_FZ, 1005 /*128:out */ X86_MXCSR_FZ, 1006 /*256:out */ X86_MXCSR_FZ, 1007 /*xcpt? */ false, false }, 1008 /* SNan, Norm FP (Unmasked). */ 1009 /*28*/{ { /*src2 */ { FP32_SNAN(1), FP32_SNAN_ V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } },\1010 { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },\1011 { /* => */ { FP32_QNAN_V(1, 1), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },\1012 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 1013 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 1014 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 1015 /*xcpt? */ true, true }, 811 /*0 */{ { /*src2 */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \ 812 { /*src1 */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } }, \ 813 { /* => */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } }, \ 814 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 815 /*128:out */ X86_MXCSR_XCPT_MASK, \ 816 /*256:out */ X86_MXCSR_XCPT_MASK, \ 817 /*xcpt? */ false, false }, \ 818 { { /*src2 */ { FP32_QNAN_MAX(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0) } }, \ 819 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0), FP32_QNAN_V1(0) } }, \ 820 { /* => */ { FP32_QNAN(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0), FP32_QNAN_V1(0) } }, \ 821 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 822 /*128:out */ X86_MXCSR_XCPT_MASK, \ 823 /*256:out */ X86_MXCSR_XCPT_MASK, \ 824 /*xcpt? */ false, false }, \ 825 { { /*src2 */ { FP32_QNAN_V1(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0) } }, \ 826 { /*src1 */ { FP32_QNAN_V2(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0), FP32_QNAN_V1(0) } }, \ 827 { /* => */ { FP32_QNAN_V2(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0), FP32_QNAN_V1(0) } }, \ 828 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 829 /*128:out */ X86_MXCSR_XCPT_MASK, \ 830 /*256:out */ X86_MXCSR_XCPT_MASK, \ 831 /*xcpt? */ false, false }, \ 832 /* QNan, SNan (Masked). */ \ 833 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0) } }, \ 834 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V2(0), FP32_SNAN_V6(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V4(0), FP32_SNAN_V1(0) } }, \ 835 { /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_V2(0), FP32_SNAN_V6(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V4(0), FP32_QNAN_V1(0) } }, \ 836 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 837 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 838 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 839 /*xcpt? */ false, false }, \ 840 { { /*src2 */ { FP32_QNAN_MAX(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \ 841 { /*src1 */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_MAX(0), FP32_SNAN_V2(0), FP32_SNAN_V6(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V4(0) } }, \ 842 { /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN(0), FP32_SNAN_MAX(0), FP32_SNAN_V2(0), FP32_SNAN_V6(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V4(0) } }, \ 843 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 844 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 845 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 846 /*xcpt? */ false, false }, \ 847 { { /*src2 */ { FP32_QNAN_V1(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \ 848 { /*src1 */ { FP32_SNAN_V2(0), FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } }, \ 849 { /* => */ { FP32_QNAN_V2(0), FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } }, \ 850 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 851 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 852 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 853 /*xcpt? */ false, false }, \ 854 /* SNan, QNan (Masked). */ \ 855 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_V1(0), FP32_SNAN_V1(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V5(0), FP32_SNAN_V6(0) } }, \ 856 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } }, \ 857 { /* => */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } }, \ 858 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 859 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 860 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 861 /*xcpt? */ false, false }, \ 862 { { /*src2 */ { FP32_SNAN_MAX(0), FP32_SNAN_MAX(0), FP32_SNAN_V1(0), FP32_SNAN_V1(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V5(0), FP32_SNAN_V6(0) } }, \ 863 { /*src1 */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } }, \ 864 { /* => */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } }, \ 865 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 866 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 867 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 868 /*xcpt? */ false, false }, \ 869 { { /*src2 */ { FP32_SNAN_V0(0), FP32_SNAN_MAX(0), FP32_SNAN_V1(0), FP32_SNAN_V1(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V5(0), FP32_SNAN_V6(0) } }, \ 870 { /*src1 */ { FP32_QNAN_V6(0), FP32_QNAN(0), FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } }, \ 871 { /* => */ { FP32_QNAN_V6(0), FP32_QNAN(0), FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } }, \ 872 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 873 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 874 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 875 /*xcpt? */ false, false }, \ 876 /* SNan, SNan (Masked). */ \ 877 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V7(0), FP32_SNAN_V1(0), FP32_SNAN_V6(0), FP32_SNAN_V1(0) } }, \ 878 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_MAX(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } }, \ 879 { /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_MAX(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } }, \ 880 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 881 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 882 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 883 /*xcpt? */ false, false }, \ 884 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V7(0), FP32_SNAN_V1(0), FP32_SNAN_V6(0), FP32_SNAN_V1(0) } }, \ 885 { /*src1 */ { FP32_SNAN_MAX(0), FP32_SNAN_V0(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } }, \ 886 { /* => */ { FP32_QNAN_MAX(0), FP32_SNAN_V0(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } }, \ 887 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 888 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 889 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 890 /*xcpt? */ false, false }, \ 891 { { /*src2 */ { FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V7(0), FP32_SNAN_V1(0), FP32_SNAN_V6(0), FP32_SNAN_V1(0) } }, \ 892 { /*src1 */ { FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V0(0) } }, \ 893 { /* => */ { FP32_QNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V0(0) } }, \ 894 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 895 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 896 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 897 /*xcpt? */ false, false }, \ 898 /* QNan, Norm FP (Masked). */ \ 899 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_MAX(1), FP32_NORM_V0(1), FP32_QNAN_V1(0), FP32_NORM_V3(0), FP32_QNAN_V3(1), FP32_NORM_V5(0), FP32_QNAN_V5(1) } }, \ 900 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V0(1), FP32_NORM_V2(1), FP32_QNAN_V2(0), FP32_NORM_V4(0), FP32_QNAN_V4(1), FP32_NORM_V6(1) } }, \ 901 { /* => */ { FP32_QNAN(0), FP32_1(1), FP32_QNAN_V0(1), FP32_NORM_V2(1), FP32_QNAN_V2(0), FP32_NORM_V4(0), FP32_QNAN_V4(1), FP32_NORM_V6(1) } }, \ 902 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 903 /*128:out */ X86_MXCSR_XCPT_MASK, \ 904 /*256:out */ X86_MXCSR_XCPT_MASK, \ 905 /*xcpt? */ false, false }, \ 906 /* SNan, Norm FP (Masked). */ \ 907 { { /*src2 */ { FP32_SNAN(1), FP32_SNAN_MAX(1), FP32_NORM_V0(1), FP32_SNAN_V1(0), FP32_NORM_V3(0), FP32_SNAN_V3(1), FP32_NORM_V5(0), FP32_SNAN_V5(1) } }, \ 908 { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V0(1), FP32_NORM_V2(1), FP32_SNAN_V2(1), FP32_NORM_V4(0), FP32_SNAN_V4(1), FP32_NORM_V6(1) } }, \ 909 { /* => */ { FP32_QNAN_V(1, 1), FP32_1(0), FP32_SNAN_V0(1), FP32_NORM_V2(1), FP32_SNAN_V2(1), FP32_NORM_V4(0), FP32_SNAN_V4(1), FP32_NORM_V6(1) } }, \ 910 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 911 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 912 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 913 /*xcpt? */ false, false }, \ 914 /* QNan, QNan (Unmasked). */ \ 915 /*14*/{ { /*src2 */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \ 916 { /*src1 */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } }, \ 917 { /* => */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } }, \ 918 /*mxcsr:in */ 0, \ 919 /*128:out */ 0, \ 920 /*256:out */ 0, \ 921 /*xcpt? */ false, false }, \ 922 { { /*src2 */ { FP32_QNAN_MAX(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0) } }, \ 923 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0), FP32_QNAN_V1(0) } }, \ 924 { /* => */ { FP32_QNAN(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0), FP32_QNAN_V1(0) } }, \ 925 /*mxcsr:in */ 0, \ 926 /*128:out */ 0, \ 927 /*256:out */ 0, \ 928 /*xcpt? */ false, false }, \ 929 { { /*src2 */ { FP32_QNAN_V1(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0) } }, \ 930 { /*src1 */ { FP32_QNAN_V2(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0), FP32_QNAN_V1(0) } }, \ 931 { /* => */ { FP32_QNAN_V2(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0), FP32_QNAN_V1(0) } }, \ 932 /*mxcsr:in */ 0, \ 933 /*128:out */ 0, \ 934 /*256:out */ 0, \ 935 /*xcpt? */ false, false }, \ 936 \ 937 /* QNan, SNan (Unmasked). */ \ 938 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0) } }, \ 939 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V2(0), FP32_SNAN_V6(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V4(0), FP32_SNAN_V1(0) } }, \ 940 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V2(0), FP32_SNAN_V6(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V4(0), FP32_QNAN_V1(0) } }, \ 941 /*mxcsr:in */ 0, \ 942 /*128:out */ X86_MXCSR_IE, \ 943 /*256:out */ X86_MXCSR_IE, \ 944 /*xcpt? */ true, true }, \ 945 { { /*src2 */ { FP32_QNAN_MAX(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \ 946 { /*src1 */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_MAX(0), FP32_SNAN_V2(0), FP32_SNAN_V6(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V4(0) } }, \ 947 { /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN(0), FP32_SNAN_MAX(0), FP32_SNAN_V2(0), FP32_SNAN_V6(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V4(0) } }, \ 948 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, \ 949 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, \ 950 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, \ 951 /*xcpt? */ true, true }, \ 952 { { /*src2 */ { FP32_QNAN_V1(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \ 953 { /*src1 */ { FP32_SNAN_V2(0), FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } }, \ 954 { /* => */ { FP32_SNAN_V2(0), FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } }, \ 955 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, \ 956 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, \ 957 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, \ 958 /*xcpt? */ true, true }, \ 959 /* SNan, QNan (Unmasked). */ \ 960 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_V1(0), FP32_SNAN_V1(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V5(0), FP32_SNAN_V6(0) } }, \ 961 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } }, \ 962 { /* => */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } }, \ 963 /*mxcsr:in */ X86_MXCSR_DAZ, \ 964 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_IE, \ 965 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_IE, \ 966 /*xcpt? */ true, true }, \ 967 { { /*src2 */ { FP32_SNAN_MAX(0), FP32_SNAN_MAX(0), FP32_SNAN_V1(0), FP32_SNAN_V1(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V5(0), FP32_SNAN_V6(0) } }, \ 968 { /*src1 */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } }, \ 969 { /* => */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } }, \ 970 /*mxcsr:in */ X86_MXCSR_RC_UP, \ 971 /*128:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, \ 972 /*256:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, \ 973 /*xcpt? */ true, true }, \ 974 { { /*src2 */ { FP32_SNAN_V0(0), FP32_SNAN_MAX(0), FP32_SNAN_V1(0), FP32_SNAN_V1(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V5(0), FP32_SNAN_V6(0) } }, \ 975 { /*src1 */ { FP32_QNAN_V6(0), FP32_QNAN(0), FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } }, \ 976 { /* => */ { FP32_QNAN_V6(0), FP32_QNAN(0), FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } }, \ 977 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, \ 978 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, \ 979 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, \ 980 /*xcpt? */ true, true }, \ 981 /* SNan, SNan (Unmasked). */ \ 982 /*24*/{ { /*src2 */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V7(0), FP32_SNAN_V1(0), FP32_SNAN_V6(0), FP32_SNAN_V1(0) } }, \ 983 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_MAX(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } }, \ 984 { /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_MAX(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } }, \ 985 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, \ 986 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE, \ 987 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE, \ 988 /*xcpt? */ true, true }, \ 989 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V7(0), FP32_SNAN_V1(0), FP32_SNAN_V6(0), FP32_SNAN_V1(0) } }, \ 990 { /*src1 */ { FP32_SNAN_MAX(0), FP32_SNAN_V0(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } }, \ 991 { /* => */ { FP32_SNAN_MAX(0), FP32_SNAN_V0(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } }, \ 992 /*mxcsr:in */ X86_MXCSR_RC_ZERO, \ 993 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE, \ 994 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE, \ 995 /*xcpt? */ true, true }, \ 996 { { /*src2 */ { FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V7(0), FP32_SNAN_V1(0), FP32_SNAN_V6(0), FP32_SNAN_V1(0) } }, \ 997 { /*src1 */ { FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V0(0) } }, \ 998 { /* => */ { FP32_QNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V0(0) } }, \ 999 /*mxcsr:in */ 0, \ 1000 /*128:out */ X86_MXCSR_IE, \ 1001 /*256:out */ X86_MXCSR_IE, \ 1002 /*xcpt? */ true, true }, \ 1003 /* QNan, Norm FP (Unmasked). */ \ 1004 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_MAX(1), FP32_NORM_V0(1), FP32_QNAN_V1(0), FP32_NORM_V3(0), FP32_QNAN_V3(1), FP32_NORM_V5(0), FP32_QNAN_V5(1) } }, \ 1005 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V0(1), FP32_NORM_V2(1), FP32_QNAN_V2(0), FP32_NORM_V4(0), FP32_QNAN_V4(1), FP32_NORM_V6(1) } }, \ 1006 { /* => */ { FP32_QNAN(0), FP32_1(1), FP32_QNAN_V0(1), FP32_NORM_V2(1), FP32_QNAN_V2(0), FP32_NORM_V4(0), FP32_QNAN_V4(1), FP32_NORM_V6(1) } }, \ 1007 /*mxcsr:in */ X86_MXCSR_FZ, \ 1008 /*128:out */ X86_MXCSR_FZ, \ 1009 /*256:out */ X86_MXCSR_FZ, \ 1010 /*xcpt? */ false, false }, \ 1011 /* SNan, Norm FP (Unmasked). */ \ 1012 /*28*/{ { /*src2 */ { FP32_SNAN(1), FP32_SNAN_MAX(1), FP32_NORM_V0(1), FP32_SNAN_V1(0), FP32_NORM_V3(0), FP32_SNAN_V3(1), FP32_NORM_V5(0), FP32_SNAN_V5(1) } }, \ 1013 { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V0(1), FP32_NORM_V2(1), FP32_SNAN_V2(1), FP32_NORM_V4(0), FP32_SNAN_V4(1), FP32_NORM_V6(1) } }, \ 1014 { /* => */ { FP32_QNAN_V(1, 1), FP32_1(0), FP32_SNAN_V0(1), FP32_NORM_V2(1), FP32_SNAN_V2(1), FP32_NORM_V4(0), FP32_SNAN_V4(1), FP32_NORM_V6(1) } }, \ 1015 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, \ 1016 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, \ 1017 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, \ 1018 /*xcpt? */ true, true }, \ 1016 1019 1017 1020 /** … … 1235 1238 **/ 1236 1239 #define FP32_TABLE_D1_H_PS_INVALIDS \ 1237 /*0 */{ { /*src2 */ { FP32_QNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5) } },\1238 { /*src1 */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },\1239 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3) } },\1240 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1241 /*128:out */ X86_MXCSR_XCPT_MASK, 1242 /*256:out */ X86_MXCSR_XCPT_MASK, 1243 /*xcpt? */ false, false }, 1244 { { /*src2 */ { FP32_QNAN(0), FP32_SNAN _V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5) } },\1245 { /*src1 */ { FP32_QNAN(0), FP32_SNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },\1246 { /* => */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V4) } },\1247 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1248 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1249 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1250 /*xcpt? */ false, false }, 1251 { { /*src2 */ { FP32_SNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V6) } },\1252 { /*src1 */ { FP32_SNAN(0), FP32_QNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },\1253 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5) } },\1254 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1255 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1256 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1257 /*xcpt? */ false, false }, 1258 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },\1259 { /*src1 */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },\1260 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V7), FP32_QNAN_V(0, FP32_FRAC_V6) } },\1261 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1262 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1263 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1264 /*xcpt? */ false, false }, 1265 { { /*src2 */ { FP32_QNAN(0), FP32_NORM_V1(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(1), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_NORM_V5(1) } },\1266 { /*src1 */ { FP32_QNAN(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },\1267 { /* => */ { FP32_QNAN(0), FP32_QNAN_ V(1, FP32_FRAC_NORM_MAX), FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V5) } },\1268 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1269 /*128:out */ X86_MXCSR_XCPT_MASK, 1270 /*256:out */ X86_MXCSR_XCPT_MASK, 1271 /*xcpt? */ false, false }, 1272 { { /*src2 */ { FP32_SNAN_ V(1, FP32_FRAC_NORM_MAX), FP32_1(0), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_NORM_V3(1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_NORM_V7(1) } },\1273 { /*src1 */ { FP32_SNAN(0), FP32_1(1), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },\1274 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V6) } },\1275 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1276 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1277 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1278 /*xcpt? */ false, false }, 1279 { { /*src2 */ { FP32_QNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5) } },\1280 { /*src1 */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },\1281 { /* => */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3) } },\1282 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 1283 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 1284 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 1285 /*xcpt? */ false, false }, 1286 { { /*src2 */ { FP32_QNAN(0), FP32_SNAN _V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5) } },\1287 { /*src1 */ { FP32_QNAN(0), FP32_SNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },\1288 { /* => */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V4) } },\1289 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 1290 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, 1291 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, 1292 /*xcpt? */ true, true }, 1293 { { /*src2 */ { FP32_SNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V6) } },\1294 { /*src1 */ { FP32_SNAN(0), FP32_QNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },\1295 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5) } },\1296 /*mxcsr:in */ 0, 1297 /*128:out */ X86_MXCSR_IE, 1298 /*256:out */ X86_MXCSR_IE, 1299 /*xcpt? */ true, true }, 1300 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },\1301 { /*src1 */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },\1302 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V7), FP32_QNAN_V(0, FP32_FRAC_V6) } },\1303 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 1304 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, 1305 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, 1306 /*xcpt? */ true, true }, 1307 { { /*src2 */ { FP32_QNAN(0), FP32_NORM_V1(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(1), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_NORM_V5(1) } },\1308 { /*src1 */ { FP32_QNAN(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },\1309 { /* => */ { FP32_QNAN(0), FP32_QNAN_ V(1, FP32_FRAC_NORM_MAX), FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V5) } },\1310 /*mxcsr:in */ 0, 1311 /*128:out */ 0, 1312 /*256:out */ 0, 1313 /*xcpt? */ false, false }, 1314 { { /*src2 */ { FP32_SNAN_ V(1, FP32_FRAC_NORM_MAX), FP32_1(0), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_NORM_V3(1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_NORM_V7(1) } },\1315 { /*src1 */ { FP32_SNAN(0), FP32_1(1), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },\1316 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V6) } },\1317 /*mxcsr:in */ X86_MXCSR_RC_UP, 1318 /*128:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, 1319 /*256:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, 1320 /*xcpt? */ true, true }, 1240 /*0 */{ { /*src2 */ { FP32_QNAN_MAX(0), FP32_QNAN(0), FP32_QNAN_V0(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V3(0), FP32_QNAN_V5(0) } }, \ 1241 { /*src1 */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } }, \ 1242 { /* => */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0), FP32_QNAN_V6(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0) } }, \ 1243 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1244 /*128:out */ X86_MXCSR_XCPT_MASK, \ 1245 /*256:out */ X86_MXCSR_XCPT_MASK, \ 1246 /*xcpt? */ false, false }, \ 1247 { { /*src2 */ { FP32_QNAN(0), FP32_SNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_SNAN_V3(0), FP32_QNAN_V4(0), FP32_SNAN_V5(0) } }, \ 1248 { /*src1 */ { FP32_QNAN(0), FP32_SNAN(0), FP32_QNAN(0), FP32_SNAN_V2(0), FP32_QNAN_V6(0), FP32_SNAN_V2(0), FP32_QNAN_V1(0), FP32_SNAN_V4(0) } }, \ 1249 { /* => */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V6(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V4(0) } }, \ 1250 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1251 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1252 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1253 /*xcpt? */ false, false }, \ 1254 { { /*src2 */ { FP32_SNAN_MAX(0), FP32_QNAN_V2(0), FP32_SNAN_V1(0), FP32_QNAN_V2(0), FP32_SNAN_V3(0), FP32_QNAN_V4(0), FP32_SNAN_V5(0), FP32_QNAN_V6(0) } }, \ 1255 { /*src1 */ { FP32_SNAN(0), FP32_QNAN(0), FP32_SNAN(0), FP32_QNAN_V5(0), FP32_SNAN_V4(0), FP32_QNAN_V3(0), FP32_SNAN_V2(0), FP32_QNAN_V1(0) } }, \ 1256 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_MAX(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V5(0) } }, \ 1257 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1258 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1259 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1260 /*xcpt? */ false, false }, \ 1261 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_MAX(0), FP32_SNAN_MAX(0), FP32_SNAN(0), FP32_SNAN_V7(0), FP32_SNAN_V1(0), FP32_SNAN_V6(0), FP32_SNAN_V1(0) } }, \ 1262 { /*src1 */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_MAX(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } }, \ 1263 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_MAX(0), FP32_QNAN_V5(0), FP32_QNAN_V1(0), FP32_QNAN_V7(0), FP32_QNAN_V6(0) } }, \ 1264 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1265 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1266 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1267 /*xcpt? */ false, false }, \ 1268 { { /*src2 */ { FP32_QNAN(0), FP32_NORM_V1(0), FP32_QNAN_MAX(0), FP32_QNAN_V1(0), FP32_QNAN_V1(0), FP32_NORM_V3(1), FP32_QNAN_V5(0), FP32_NORM_V5(1) } }, \ 1269 { /*src1 */ { FP32_QNAN(0), FP32_1(1), FP32_QNAN_MAX(1), FP32_NORM_V2(1), FP32_QNAN_V2(0), FP32_NORM_V4(0), FP32_QNAN_V4(1), FP32_NORM_V6(1) } }, \ 1270 { /* => */ { FP32_QNAN(0), FP32_QNAN_MAX(1), FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V4(1), FP32_QNAN_V1(0), FP32_QNAN_V5(0) } }, \ 1271 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1272 /*128:out */ X86_MXCSR_XCPT_MASK, \ 1273 /*256:out */ X86_MXCSR_XCPT_MASK, \ 1274 /*xcpt? */ false, false }, \ 1275 { { /*src2 */ { FP32_SNAN_MAX(1), FP32_1(0), FP32_SNAN_V1(0), FP32_NORM_V3(0), FP32_SNAN_V0(0), FP32_NORM_V3(1), FP32_SNAN_V6(0), FP32_NORM_V7(1) } }, \ 1276 { /*src1 */ { FP32_SNAN(0), FP32_1(1), FP32_SNAN_MAX(0), FP32_NORM_V2(1), FP32_SNAN_V2(1), FP32_NORM_V4(0), FP32_SNAN_V4(1), FP32_NORM_V6(1) } }, \ 1277 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_MAX(0), FP32_QNAN_MAX(1), FP32_QNAN_V1(0), FP32_QNAN_V2(1), FP32_QNAN_V4(1), FP32_QNAN_V0(0), FP32_QNAN_V6(0) } }, \ 1278 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1279 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1280 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1281 /*xcpt? */ false, false }, \ 1282 { { /*src2 */ { FP32_QNAN_MAX(0), FP32_QNAN(0), FP32_QNAN_V0(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V3(0), FP32_QNAN_V5(0) } }, \ 1283 { /*src1 */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } }, \ 1284 { /* => */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0), FP32_QNAN_V6(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0) } }, \ 1285 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, \ 1286 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, \ 1287 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, \ 1288 /*xcpt? */ false, false }, \ 1289 { { /*src2 */ { FP32_QNAN(0), FP32_SNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_SNAN_V3(0), FP32_QNAN_V4(0), FP32_SNAN_V5(0) } }, \ 1290 { /*src1 */ { FP32_QNAN(0), FP32_SNAN(0), FP32_QNAN(0), FP32_SNAN_V2(0), FP32_QNAN_V6(0), FP32_SNAN_V2(0), FP32_QNAN_V1(0), FP32_SNAN_V4(0) } }, \ 1291 { /* => */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V6(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V4(0) } }, \ 1292 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, \ 1293 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, \ 1294 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, \ 1295 /*xcpt? */ true, true }, \ 1296 { { /*src2 */ { FP32_SNAN_MAX(0), FP32_QNAN_V2(0), FP32_SNAN_V1(0), FP32_QNAN_V2(0), FP32_SNAN_V3(0), FP32_QNAN_V4(0), FP32_SNAN_V5(0), FP32_QNAN_V6(0) } }, \ 1297 { /*src1 */ { FP32_SNAN(0), FP32_QNAN(0), FP32_SNAN(0), FP32_QNAN_V5(0), FP32_SNAN_V4(0), FP32_QNAN_V3(0), FP32_SNAN_V2(0), FP32_QNAN_V1(0) } }, \ 1298 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_MAX(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V5(0) } }, \ 1299 /*mxcsr:in */ 0, \ 1300 /*128:out */ X86_MXCSR_IE, \ 1301 /*256:out */ X86_MXCSR_IE, \ 1302 /*xcpt? */ true, true }, \ 1303 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_MAX(0), FP32_SNAN_MAX(0), FP32_SNAN(0), FP32_SNAN_V7(0), FP32_SNAN_V1(0), FP32_SNAN_V6(0), FP32_SNAN_V1(0) } }, \ 1304 { /*src1 */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_MAX(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } }, \ 1305 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_MAX(0), FP32_QNAN_V5(0), FP32_QNAN_V1(0), FP32_QNAN_V7(0), FP32_QNAN_V6(0) } }, \ 1306 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, \ 1307 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, \ 1308 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, \ 1309 /*xcpt? */ true, true }, \ 1310 { { /*src2 */ { FP32_QNAN(0), FP32_NORM_V1(0), FP32_QNAN_MAX(0), FP32_QNAN_V1(0), FP32_QNAN_V1(0), FP32_NORM_V3(1), FP32_QNAN_V5(0), FP32_NORM_V5(1) } }, \ 1311 { /*src1 */ { FP32_QNAN(0), FP32_1(1), FP32_QNAN_MAX(1), FP32_NORM_V2(1), FP32_QNAN_V2(0), FP32_NORM_V4(0), FP32_QNAN_V4(1), FP32_NORM_V6(1) } }, \ 1312 { /* => */ { FP32_QNAN(0), FP32_QNAN_MAX(1), FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V4(1), FP32_QNAN_V1(0), FP32_QNAN_V5(0) } }, \ 1313 /*mxcsr:in */ 0, \ 1314 /*128:out */ 0, \ 1315 /*256:out */ 0, \ 1316 /*xcpt? */ false, false }, \ 1317 { { /*src2 */ { FP32_SNAN_MAX(1), FP32_1(0), FP32_SNAN_V1(0), FP32_NORM_V3(0), FP32_SNAN_V0(0), FP32_NORM_V3(1), FP32_SNAN_V6(0), FP32_NORM_V7(1) } }, \ 1318 { /*src1 */ { FP32_SNAN(0), FP32_1(1), FP32_SNAN_MAX(0), FP32_NORM_V2(1), FP32_SNAN_V2(1), FP32_NORM_V4(0), FP32_SNAN_V4(1), FP32_NORM_V6(1) } }, \ 1319 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_MAX(0), FP32_QNAN_MAX(1), FP32_QNAN_V1(0), FP32_QNAN_V2(1), FP32_QNAN_V4(1), FP32_QNAN_V0(0), FP32_QNAN_V6(0) } }, \ 1320 /*mxcsr:in */ X86_MXCSR_RC_UP, \ 1321 /*128:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, \ 1322 /*256:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, \ 1323 /*xcpt? */ true, true }, \ 1321 1324 1322 1325 /** … … 1415 1418 **/ 1416 1419 #define FP32_TABLE_D9_PS_INVALIDS \ 1417 /*0 */{ { /*src2 */ { FP32_QNAN(0), FP32_QNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, \1418 { /*src1 */ { FP32_QNAN(0), FP32_QNAN _V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, \1419 { /* => */ { FP32_QNAN(0), FP32_QNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, \1420 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1421 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1422 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1423 /*xcpt? */ false, false }, 1424 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, \1425 { /*src1 */ { FP32_SNAN(0), FP32_SNAN _V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, \1426 { /* => */ { FP32_QNAN(0), FP32_QNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, \1427 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1428 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1429 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1430 /*xcpt? */ false, false }, 1431 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN _V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },\1432 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },\1433 { /* => */ { FP32_SNAN(0), FP32_SNAN _V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },\1434 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, 1435 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, 1436 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, 1437 /*xcpt? */ false, false }, 1438 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN _V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },\1439 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },\1440 { /* => */ { FP32_SNAN(0), FP32_SNAN _V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },\1441 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1442 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1443 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1444 /*xcpt? */ false, false }, 1445 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_ V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } },\1446 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },\1447 { /* => */ { FP32_QNAN(0), FP32_QNAN_ V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_QNAN_V(1, FP32_FRAC_V5) } },\1448 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1449 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1450 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1451 /*xcpt? */ false, false }, 1452 { { /*src2 */ { FP32_SNAN(1), FP32_SNAN_ V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } },\1453 { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1), FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0), FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1) } },\1454 { /* => */ { FP32_SNAN(1), FP32_SNAN_ V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0), FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0), FP32_SNAN_V(1, FP32_FRAC_V5) } },\1455 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1456 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1457 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1458 /*xcpt? */ false, false }, 1459 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, \1460 { /*src1 */ { FP32_QNAN(0), FP32_QNAN _V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, \1461 { /* => */ { FP32_QNAN(0), FP32_QNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, \1462 /*mxcsr:in */ 0, 1463 /*128:out */ X86_MXCSR_IE, 1464 /*256:out */ X86_MXCSR_IE, 1465 /*xcpt? */ true, true }, 1466 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, \1467 { /*src1 */ { FP32_SNAN(0), FP32_SNAN _V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, \1468 { /* => */ { FP32_QNAN(0), FP32_QNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, \1469 /*mxcsr:in */ 0, 1470 /*128:out */ X86_MXCSR_IE, 1471 /*256:out */ X86_MXCSR_IE, 1472 /*xcpt? */ true, true }, 1473 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN _V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },\1474 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },\1475 { /* => */ { FP32_SNAN(0), FP32_SNAN _V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },\1476 /*mxcsr:in */ 0, 1477 /*128:out */ X86_MXCSR_IE, 1478 /*256:out */ X86_MXCSR_IE, 1479 /*xcpt? */ true, true }, 1480 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN _V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },\1481 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },\1482 { /* => */ { FP32_SNAN(0), FP32_SNAN _V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },\1483 /*mxcsr:in */ 0, 1484 /*128:out */ X86_MXCSR_IE, 1485 /*256:out */ X86_MXCSR_IE, 1486 /*xcpt? */ true, true }, 1420 /*0 */{ { /*src2 */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \ 1421 { /*src1 */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } }, \ 1422 { /* => */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \ 1423 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1424 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1425 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1426 /*xcpt? */ false, false }, \ 1427 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \ 1428 { /*src1 */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_MAX(0), FP32_SNAN_V2(0), FP32_SNAN_V6(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V4(0) } }, \ 1429 { /* => */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \ 1430 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1431 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1432 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1433 /*xcpt? */ false, false }, \ 1434 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_V1(0), FP32_SNAN_V1(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V5(0), FP32_SNAN_V6(0) } }, \ 1435 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } }, \ 1436 { /* => */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_V1(0), FP32_SNAN_V1(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V5(0), FP32_SNAN_V6(0) } }, \ 1437 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, \ 1438 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, \ 1439 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, \ 1440 /*xcpt? */ false, false }, \ 1441 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V7(0), FP32_SNAN_V1(0), FP32_SNAN_V6(0), FP32_SNAN_V1(0) } }, \ 1442 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_MAX(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } }, \ 1443 { /* => */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V7(0), FP32_SNAN_V1(0), FP32_SNAN_V6(0), FP32_SNAN_V1(0) } }, \ 1444 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1445 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1446 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1447 /*xcpt? */ false, false }, \ 1448 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_MAX(1), FP32_NORM_V0(1), FP32_QNAN_V1(0), FP32_NORM_V3(0), FP32_QNAN_V3(1), FP32_NORM_V5(0), FP32_QNAN_V5(1) } }, \ 1449 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V0(1), FP32_NORM_V2(1), FP32_QNAN_V2(0), FP32_NORM_V4(0), FP32_QNAN_V4(1), FP32_NORM_V6(1) } }, \ 1450 { /* => */ { FP32_QNAN(0), FP32_QNAN_MAX(1), FP32_NORM_V0(1), FP32_QNAN_V1(0), FP32_NORM_V3(0), FP32_QNAN_V3(1), FP32_NORM_V5(0), FP32_QNAN_V5(1) } }, \ 1451 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1452 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1453 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1454 /*xcpt? */ false, false }, \ 1455 { { /*src2 */ { FP32_SNAN(1), FP32_SNAN_MAX(1), FP32_NORM_V0(1), FP32_SNAN_V1(0), FP32_NORM_V3(0), FP32_SNAN_V3(1), FP32_NORM_V5(0), FP32_SNAN_V5(1) } }, \ 1456 { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V0(1), FP32_NORM_V2(1), FP32_SNAN_V2(1), FP32_NORM_V4(0), FP32_SNAN_V4(1), FP32_NORM_V6(1) } }, \ 1457 { /* => */ { FP32_SNAN(1), FP32_SNAN_MAX(1), FP32_NORM_V0(1), FP32_SNAN_V1(0), FP32_NORM_V3(0), FP32_SNAN_V3(1), FP32_NORM_V5(0), FP32_SNAN_V5(1) } }, \ 1458 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1459 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1460 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1461 /*xcpt? */ false, false }, \ 1462 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \ 1463 { /*src1 */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } }, \ 1464 { /* => */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \ 1465 /*mxcsr:in */ 0, \ 1466 /*128:out */ X86_MXCSR_IE, \ 1467 /*256:out */ X86_MXCSR_IE, \ 1468 /*xcpt? */ true, true }, \ 1469 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \ 1470 { /*src1 */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_MAX(0), FP32_SNAN_V2(0), FP32_SNAN_V6(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V4(0) } }, \ 1471 { /* => */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \ 1472 /*mxcsr:in */ 0, \ 1473 /*128:out */ X86_MXCSR_IE, \ 1474 /*256:out */ X86_MXCSR_IE, \ 1475 /*xcpt? */ true, true }, \ 1476 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_V1(0), FP32_SNAN_V1(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V5(0), FP32_SNAN_V6(0) } }, \ 1477 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } }, \ 1478 { /* => */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_V1(0), FP32_SNAN_V1(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V5(0), FP32_SNAN_V6(0) } }, \ 1479 /*mxcsr:in */ 0, \ 1480 /*128:out */ X86_MXCSR_IE, \ 1481 /*256:out */ X86_MXCSR_IE, \ 1482 /*xcpt? */ true, true }, \ 1483 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V7(0), FP32_SNAN_V1(0), FP32_SNAN_V6(0), FP32_SNAN_V1(0) } }, \ 1484 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_MAX(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } }, \ 1485 { /* => */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V7(0), FP32_SNAN_V1(0), FP32_SNAN_V6(0), FP32_SNAN_V1(0) } }, \ 1486 /*mxcsr:in */ 0, \ 1487 /*128:out */ X86_MXCSR_IE, \ 1488 /*256:out */ X86_MXCSR_IE, \ 1489 /*xcpt? */ true, true }, \ 1487 1490 1488 1491 /** … … 1567 1570 **/ 1568 1571 #define FP32_TABLE_D9_SS_INVALIDS \ 1569 /* QNan, QNan (Masked). */ 1570 /*0 */{ { /*src2 */ { FP32_QNAN(0), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V2(0), FP32_RAND_V1(1), FP32_RAND_V7(0), FP32_RAND_V2(1) } }, 1571 { /*src1 */ { FP32_QNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V5(1), FP32_RAND_V6(1), FP32_RAND_V7(1), FP32_RAND_V1(1) } }, 1572 { /* => */ { FP32_QNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V5(1), FP32_RAND_V6(1), FP32_RAND_V7(1), FP32_RAND_V1(1) } }, 1573 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1574 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1575 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1576 /*xcpt? */ false, false }, 1577 { { /*src2 */ { FP32_QNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(0), FP32_RAND_V6(1) } },\1578 { /*src1 */ { FP32_QNAN _V(0, FP32_FRAC_NORM_MIN), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V1(0) } },\1579 { /* => */ { FP32_QNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V1(0) } },\1580 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1581 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1582 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1583 /*xcpt? */ false, false }, 1584 { { /*src2 */ { FP32_QNAN_V (0, FP32_FRAC_V0), FP32_RAND_V0(1), FP32_RAND_V7(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } },\1585 { /*src1 */ { FP32_QNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_RAND_V1(0), FP32_RAND_V7(0), FP32_RAND_V2(1), FP32_RAND_V6(1), FP32_RAND_V3(1), FP32_RAND_V5(0), FP32_RAND_V4(1) } },\1586 { /* => */ { FP32_QNAN_V (0, FP32_FRAC_V0), FP32_RAND_V1(0), FP32_RAND_V7(0), FP32_RAND_V2(1), FP32_RAND_V6(1), FP32_RAND_V3(1), FP32_RAND_V5(0), FP32_RAND_V4(1) } },\1587 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1588 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1589 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1590 /*xcpt? */ false, false }, 1591 /* QNan, SNan (Masked). */ 1592 { { /*src2 */ { FP32_QNAN(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V2(0), FP32_RAND_V2(1), FP32_RAND_V1(0), FP32_RAND_V0(1) } }, 1593 { /*src1 */ { FP32_SNAN(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, 1594 { /* => */ { FP32_QNAN(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, 1595 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1596 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1597 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1598 /*xcpt? */ false, false }, 1599 { { /*src2 */ { FP32_QNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V1(1), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(1) } },\1600 { /*src1 */ { FP32_SNAN _V(0, FP32_FRAC_NORM_MIN), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V3(0) } },\1601 { /* => */ { FP32_QNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V3(0) } },\1602 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1603 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1604 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1605 /*xcpt? */ false, false }, 1606 { { /*src2 */ { FP32_QNAN_V (0, FP32_FRAC_V0), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V1(1), FP32_RAND_V0(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(1) } },\1607 { /*src1 */ { FP32_SNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V1(0) } },\1608 { /* => */ { FP32_QNAN_V (0, FP32_FRAC_V0), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V1(0) } },\1609 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1610 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1611 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1612 /*xcpt? */ false, false }, 1613 /* SNan, QNan (Masked). */ 1614 { { /*src2 */ { FP32_SNAN(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V1(1), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, 1615 { /*src1 */ { FP32_QNAN(0), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V3(0) } }, 1616 { /* => */ { FP32_SNAN(0), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V3(0) } }, 1617 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, 1618 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, 1619 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, 1620 /*xcpt? */ false, false }, 1621 { { /*src2 */ { FP32_SNAN _V(0, FP32_FRAC_NORM_MIN), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V7(1) } },\1622 { /*src1 */ { FP32_QNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_RAND_V2(0), FP32_RAND_V4(0), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V2(0) } },\1623 { /* => */ { FP32_SNAN _V(0, FP32_FRAC_NORM_MIN), FP32_RAND_V2(0), FP32_RAND_V4(0), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V2(0) } },\1624 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1625 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1626 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1627 /*xcpt? */ false, false }, 1628 { { /*src2 */ { FP32_SNAN_V (0, FP32_FRAC_V1), FP32_RAND_V1(1), FP32_RAND_V7(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } },\1629 { /*src1 */ { FP32_QNAN_V (0, FP32_FRAC_V6), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V0(1), FP32_RAND_V2(0), FP32_RAND_V3(1) } },\1630 { /* => */ { FP32_SNAN_V (0, FP32_FRAC_V1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V0(1), FP32_RAND_V2(0), FP32_RAND_V3(1) } },\1631 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1632 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1633 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1634 /*xcpt? */ false, false }, 1635 /* SNan, SNan (Masked). */ 1636 { { /*src2 */ { FP32_SNAN(0), FP32_RAND_V1(1), FP32_RAND_V7(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } }, 1637 { /*src1 */ { FP32_SNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V7(0) } }, 1638 { /* => */ { FP32_SNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V7(0) } }, 1639 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1640 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1641 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1642 /*xcpt? */ false, false }, 1643 { { /*src2 */ { FP32_SNAN _V(0, FP32_FRAC_NORM_MIN), FP32_RAND_V1(0), FP32_RAND_V7(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V1(1), FP32_RAND_V2(1) } },\1644 { /*src1 */ { FP32_SNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_RAND_V7(0), FP32_RAND_V5(0), FP32_RAND_V7(1), FP32_RAND_V6(1), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V2(1) } },\1645 { /* => */ { FP32_SNAN _V(0, FP32_FRAC_NORM_MIN), FP32_RAND_V7(0), FP32_RAND_V5(0), FP32_RAND_V7(1), FP32_RAND_V6(1), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V2(1) } },\1646 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1647 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1648 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1649 /*xcpt? */ false, false }, 1650 { { /*src2 */ { FP32_SNAN_V (0, FP32_FRAC_V1), FP32_RAND_V1(1), FP32_RAND_V6(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } },\1651 { /*src1 */ { FP32_SNAN_V (0, FP32_FRAC_V4), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V0(1) } },\1652 { /* => */ { FP32_SNAN_V (0, FP32_FRAC_V1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V0(1) } },\1653 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1654 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1655 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1656 /*xcpt? */ false, false }, 1657 /* QNan, Normal (Unmasked). */ 1658 { { /*src2 */ { FP32_QNAN(0), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } }, 1659 { /*src1 */ { FP32_1(0), FP32_RAND_V2(1), FP32_RAND_V4(1), FP32_RAND_V6(1), FP32_RAND_V2(1), FP32_RAND_V7(0), FP32_RAND_V3(0), FP32_RAND_V4(1) } }, 1660 { /* => */ { FP32_QNAN(0), FP32_RAND_V2(1), FP32_RAND_V4(1), FP32_RAND_V6(1), FP32_RAND_V2(1), FP32_RAND_V7(0), FP32_RAND_V3(0), FP32_RAND_V4(1) } }, 1661 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1662 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1663 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1664 /*xcpt? */ false, false }, 1665 /* SNan, Normal (Masked). */ 1666 { { /*src2 */ { FP32_SNAN(1), FP32_RAND_V0(1), FP32_RAND_V2(1), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } }, 1667 { /*src1 */ { FP32_1(0), FP32_RAND_V0(1), FP32_RAND_V1(1), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V6(0), FP32_RAND_V7(0), FP32_RAND_V1(1) } }, 1668 { /* => */ { FP32_SNAN(1), FP32_RAND_V0(1), FP32_RAND_V1(1), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V6(0), FP32_RAND_V7(0), FP32_RAND_V1(1) } }, 1669 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1670 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1671 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1672 /*xcpt? */ false, false }, 1673 /* QNan, QNan (Unmasked). */ 1674 /*0 */{ { /*src2 */ { FP32_QNAN(0), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V2(0), FP32_RAND_V1(1), FP32_RAND_V7(0), FP32_RAND_V2(1) } }, 1675 { /*src1 */ { FP32_QNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V5(1), FP32_RAND_V6(1), FP32_RAND_V7(1), FP32_RAND_V1(1) } }, 1676 { /* => */ { FP32_QNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V5(1), FP32_RAND_V6(1), FP32_RAND_V7(1), FP32_RAND_V1(1) } }, 1677 /*mxcsr:in */ 0, 1678 /*128:out */ X86_MXCSR_IE, 1679 /*256:out */ X86_MXCSR_IE, 1680 /*xcpt? */ true, true }, 1681 { { /*src2 */ { FP32_QNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(0), FP32_RAND_V6(1) } },\1682 { /*src1 */ { FP32_QNAN _V(0, FP32_FRAC_NORM_MIN), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V1(0) } },\1683 { /* => */ { FP32_QNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V1(0) } },\1684 /*mxcsr:in */ 0, 1685 /*128:out */ X86_MXCSR_IE, 1686 /*256:out */ X86_MXCSR_IE, 1687 /*xcpt? */ true, true }, 1688 { { /*src2 */ { FP32_QNAN_V (0, FP32_FRAC_V0), FP32_RAND_V0(1), FP32_RAND_V7(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } },\1689 { /*src1 */ { FP32_QNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_RAND_V1(0), FP32_RAND_V7(0), FP32_RAND_V2(1), FP32_RAND_V6(1), FP32_RAND_V3(1), FP32_RAND_V5(0), FP32_RAND_V4(1) } },\1690 { /* => */ { FP32_QNAN_V (0, FP32_FRAC_V0), FP32_RAND_V1(0), FP32_RAND_V7(0), FP32_RAND_V2(1), FP32_RAND_V6(1), FP32_RAND_V3(1), FP32_RAND_V5(0), FP32_RAND_V4(1) } },\1691 /*mxcsr:in */ 0, 1692 /*128:out */ X86_MXCSR_IE, 1693 /*256:out */ X86_MXCSR_IE, 1694 /*xcpt? */ true, true }, 1695 /* QNan, SNan (Unmasked). */ 1696 { { /*src2 */ { FP32_QNAN(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V2(0), FP32_RAND_V2(1), FP32_RAND_V1(0), FP32_RAND_V0(1) } }, 1697 { /*src1 */ { FP32_SNAN(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, 1698 { /* => */ { FP32_QNAN(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, 1699 /*mxcsr:in */ 0, 1700 /*128:out */ X86_MXCSR_IE, 1701 /*256:out */ X86_MXCSR_IE, 1702 /*xcpt? */ true, true }, 1703 { { /*src2 */ { FP32_QNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V1(1), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(1) } },\1704 { /*src1 */ { FP32_SNAN _V(0, FP32_FRAC_NORM_MIN), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V3(0) } },\1705 { /* => */ { FP32_QNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V3(0) } },\1706 /*mxcsr:in */ 0, 1707 /*128:out */ X86_MXCSR_IE, 1708 /*256:out */ X86_MXCSR_IE, 1709 /*xcpt? */ true, true }, 1710 { { /*src2 */ { FP32_QNAN_V (0, FP32_FRAC_V0), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V1(1), FP32_RAND_V0(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(1) } },\1711 { /*src1 */ { FP32_SNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V1(0) } },\1712 { /* => */ { FP32_QNAN_V (0, FP32_FRAC_V0), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V1(0) } },\1713 /*mxcsr:in */ 0, 1714 /*128:out */ X86_MXCSR_IE, 1715 /*256:out */ X86_MXCSR_IE, 1716 /*xcpt? */ true, true }, 1717 /* SNan, QNan (Unmasked). */ 1718 { { /*src2 */ { FP32_SNAN(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V1(1), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, 1719 { /*src1 */ { FP32_QNAN(0), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V3(0) } }, 1720 { /* => */ { FP32_SNAN(0), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V3(0) } }, 1721 /*mxcsr:in */ X86_MXCSR_FZ, 1722 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_IE, 1723 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_IE, 1724 /*xcpt? */ true, true }, 1725 { { /*src2 */ { FP32_SNAN _V(0, FP32_FRAC_NORM_MIN), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V7(1) } },\1726 { /*src1 */ { FP32_QNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_RAND_V2(0), FP32_RAND_V4(0), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V2(0) } },\1727 { /* => */ { FP32_SNAN _V(0, FP32_FRAC_NORM_MIN), FP32_RAND_V2(0), FP32_RAND_V4(0), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V2(0) } },\1728 /*mxcsr:in */ 0, 1729 /*128:out */ X86_MXCSR_IE, 1730 /*256:out */ X86_MXCSR_IE, 1731 /*xcpt? */ true, true }, 1732 { { /*src2 */ { FP32_SNAN_V (0, FP32_FRAC_V1), FP32_RAND_V1(1), FP32_RAND_V7(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } },\1733 { /*src1 */ { FP32_QNAN_V (0, FP32_FRAC_V6), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V0(1), FP32_RAND_V2(0), FP32_RAND_V3(1) } },\1734 { /* => */ { FP32_SNAN_V (0, FP32_FRAC_V1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V0(1), FP32_RAND_V2(0), FP32_RAND_V3(1) } },\1735 /*mxcsr:in */ 0, 1736 /*128:out */ X86_MXCSR_IE, 1737 /*256:out */ X86_MXCSR_IE, 1738 /*xcpt? */ true, true }, 1739 /* SNan, SNan (Unmasked). */ 1740 { { /*src2 */ { FP32_SNAN(0), FP32_RAND_V1(1), FP32_RAND_V7(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } }, 1741 { /*src1 */ { FP32_SNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V7(0) } }, 1742 { /* => */ { FP32_SNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V7(0) } }, 1743 /*mxcsr:in */ 0, 1744 /*128:out */ X86_MXCSR_IE, 1745 /*256:out */ X86_MXCSR_IE, 1746 /*xcpt? */ true, true }, 1747 { { /*src2 */ { FP32_SNAN _V(0, FP32_FRAC_NORM_MIN), FP32_RAND_V1(0), FP32_RAND_V7(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V1(1), FP32_RAND_V2(1) } },\1748 { /*src1 */ { FP32_SNAN_ V(0, FP32_FRAC_NORM_MAX), FP32_RAND_V7(0), FP32_RAND_V5(0), FP32_RAND_V7(1), FP32_RAND_V6(1), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V2(1) } },\1749 { /* => */ { FP32_SNAN _V(0, FP32_FRAC_NORM_MIN), FP32_RAND_V7(0), FP32_RAND_V5(0), FP32_RAND_V7(1), FP32_RAND_V6(1), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V2(1) } },\1750 /*mxcsr:in */ 0, 1751 /*128:out */ X86_MXCSR_IE, 1752 /*256:out */ X86_MXCSR_IE, 1753 /*xcpt? */ true, true }, 1754 { { /*src2 */ { FP32_SNAN_V (0, FP32_FRAC_V1), FP32_RAND_V1(1), FP32_RAND_V6(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } },\1755 { /*src1 */ { FP32_SNAN_V (0, FP32_FRAC_V4), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V0(1) } },\1756 { /* => */ { FP32_SNAN_V (0, FP32_FRAC_V1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V0(1) } },\1757 /*mxcsr:in */ 0, 1758 /*128:out */ X86_MXCSR_IE, 1759 /*256:out */ X86_MXCSR_IE, 1760 /*xcpt? */ true, true }, 1761 /* QNan, Normal (Unmasked). */ 1762 { { /*src2 */ { FP32_QNAN(0), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } }, 1763 { /*src1 */ { FP32_1(0), FP32_RAND_V2(1), FP32_RAND_V4(1), FP32_RAND_V6(1), FP32_RAND_V2(1), FP32_RAND_V7(0), FP32_RAND_V3(0), FP32_RAND_V4(1) } }, 1764 { /* => */ { FP32_QNAN(0), FP32_RAND_V2(1), FP32_RAND_V4(1), FP32_RAND_V6(1), FP32_RAND_V2(1), FP32_RAND_V7(0), FP32_RAND_V3(0), FP32_RAND_V4(1) } }, 1765 /*mxcsr:in */ 0, 1766 /*128:out */ X86_MXCSR_IE, 1767 /*256:out */ X86_MXCSR_IE, 1768 /*xcpt? */ true, true }, 1769 /* SNan, Normal (Masked). */ 1770 { { /*src2 */ { FP32_SNAN(1), FP32_RAND_V0(1), FP32_RAND_V2(1), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } }, 1771 { /*src1 */ { FP32_1(0), FP32_RAND_V0(1), FP32_RAND_V1(1), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V6(0), FP32_RAND_V7(0), FP32_RAND_V1(1) } }, 1772 { /* => */ { FP32_SNAN(1), FP32_RAND_V0(1), FP32_RAND_V1(1), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V6(0), FP32_RAND_V7(0), FP32_RAND_V1(1) } }, 1773 /*mxcsr:in */ 0, 1774 /*128:out */ X86_MXCSR_IE, 1775 /*256:out */ X86_MXCSR_IE, 1776 /*xcpt? */ true, true }, 1572 /* QNan, QNan (Masked). */ \ 1573 /*0 */{ { /*src2 */ { FP32_QNAN(0), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V2(0), FP32_RAND_V1(1), FP32_RAND_V7(0), FP32_RAND_V2(1) } }, \ 1574 { /*src1 */ { FP32_QNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V5(1), FP32_RAND_V6(1), FP32_RAND_V7(1), FP32_RAND_V1(1) } }, \ 1575 { /* => */ { FP32_QNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V5(1), FP32_RAND_V6(1), FP32_RAND_V7(1), FP32_RAND_V1(1) } }, \ 1576 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1577 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1578 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1579 /*xcpt? */ false, false }, \ 1580 { { /*src2 */ { FP32_QNAN_MAX(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(0), FP32_RAND_V6(1) } }, \ 1581 { /*src1 */ { FP32_QNAN(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V1(0) } }, \ 1582 { /* => */ { FP32_QNAN_MAX(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V1(0) } }, \ 1583 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1584 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1585 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1586 /*xcpt? */ false, false }, \ 1587 { { /*src2 */ { FP32_QNAN_V0(0), FP32_RAND_V0(1), FP32_RAND_V7(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } }, \ 1588 { /*src1 */ { FP32_QNAN_MAX(0), FP32_RAND_V1(0), FP32_RAND_V7(0), FP32_RAND_V2(1), FP32_RAND_V6(1), FP32_RAND_V3(1), FP32_RAND_V5(0), FP32_RAND_V4(1) } }, \ 1589 { /* => */ { FP32_QNAN_V0(0), FP32_RAND_V1(0), FP32_RAND_V7(0), FP32_RAND_V2(1), FP32_RAND_V6(1), FP32_RAND_V3(1), FP32_RAND_V5(0), FP32_RAND_V4(1) } }, \ 1590 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1591 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1592 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1593 /*xcpt? */ false, false }, \ 1594 /* QNan, SNan (Masked). */ \ 1595 { { /*src2 */ { FP32_QNAN(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V2(0), FP32_RAND_V2(1), FP32_RAND_V1(0), FP32_RAND_V0(1) } }, \ 1596 { /*src1 */ { FP32_SNAN(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, \ 1597 { /* => */ { FP32_QNAN(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, \ 1598 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1599 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1600 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1601 /*xcpt? */ false, false }, \ 1602 { { /*src2 */ { FP32_QNAN_MAX(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V1(1), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, \ 1603 { /*src1 */ { FP32_SNAN(0), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V3(0) } }, \ 1604 { /* => */ { FP32_QNAN_MAX(0), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V3(0) } }, \ 1605 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1606 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1607 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1608 /*xcpt? */ false, false }, \ 1609 { { /*src2 */ { FP32_QNAN_V0(0), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V1(1), FP32_RAND_V0(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, \ 1610 { /*src1 */ { FP32_SNAN_MAX(0), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V1(0) } }, \ 1611 { /* => */ { FP32_QNAN_V0(0), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V1(0) } }, \ 1612 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1613 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1614 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1615 /*xcpt? */ false, false }, \ 1616 /* SNan, QNan (Masked). */ \ 1617 { { /*src2 */ { FP32_SNAN(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V1(1), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, \ 1618 { /*src1 */ { FP32_QNAN(0), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V3(0) } }, \ 1619 { /* => */ { FP32_SNAN(0), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V3(0) } }, \ 1620 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, \ 1621 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, \ 1622 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, \ 1623 /*xcpt? */ false, false }, \ 1624 { { /*src2 */ { FP32_SNAN(0), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V7(1) } }, \ 1625 { /*src1 */ { FP32_QNAN_MAX(0), FP32_RAND_V2(0), FP32_RAND_V4(0), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V2(0) } }, \ 1626 { /* => */ { FP32_SNAN(0), FP32_RAND_V2(0), FP32_RAND_V4(0), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V2(0) } }, \ 1627 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1628 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1629 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1630 /*xcpt? */ false, false }, \ 1631 { { /*src2 */ { FP32_SNAN_V1(0), FP32_RAND_V1(1), FP32_RAND_V7(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } }, \ 1632 { /*src1 */ { FP32_QNAN_V6(0), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V0(1), FP32_RAND_V2(0), FP32_RAND_V3(1) } }, \ 1633 { /* => */ { FP32_SNAN_V1(0), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V0(1), FP32_RAND_V2(0), FP32_RAND_V3(1) } }, \ 1634 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1635 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1636 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1637 /*xcpt? */ false, false }, \ 1638 /* SNan, SNan (Masked). */ \ 1639 { { /*src2 */ { FP32_SNAN(0), FP32_RAND_V1(1), FP32_RAND_V7(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } }, \ 1640 { /*src1 */ { FP32_SNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V7(0) } }, \ 1641 { /* => */ { FP32_SNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V7(0) } }, \ 1642 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1643 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1644 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1645 /*xcpt? */ false, false }, \ 1646 { { /*src2 */ { FP32_SNAN(0), FP32_RAND_V1(0), FP32_RAND_V7(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V1(1), FP32_RAND_V2(1) } }, \ 1647 { /*src1 */ { FP32_SNAN_MAX(0), FP32_RAND_V7(0), FP32_RAND_V5(0), FP32_RAND_V7(1), FP32_RAND_V6(1), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V2(1) } }, \ 1648 { /* => */ { FP32_SNAN(0), FP32_RAND_V7(0), FP32_RAND_V5(0), FP32_RAND_V7(1), FP32_RAND_V6(1), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V2(1) } }, \ 1649 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1650 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1651 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1652 /*xcpt? */ false, false }, \ 1653 { { /*src2 */ { FP32_SNAN_V1(0), FP32_RAND_V1(1), FP32_RAND_V6(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } }, \ 1654 { /*src1 */ { FP32_SNAN_V4(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V0(1) } }, \ 1655 { /* => */ { FP32_SNAN_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V0(1) } }, \ 1656 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1657 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1658 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1659 /*xcpt? */ false, false }, \ 1660 /* QNan, Normal (Unmasked). */ \ 1661 { { /*src2 */ { FP32_QNAN(0), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } }, \ 1662 { /*src1 */ { FP32_1(0), FP32_RAND_V2(1), FP32_RAND_V4(1), FP32_RAND_V6(1), FP32_RAND_V2(1), FP32_RAND_V7(0), FP32_RAND_V3(0), FP32_RAND_V4(1) } }, \ 1663 { /* => */ { FP32_QNAN(0), FP32_RAND_V2(1), FP32_RAND_V4(1), FP32_RAND_V6(1), FP32_RAND_V2(1), FP32_RAND_V7(0), FP32_RAND_V3(0), FP32_RAND_V4(1) } }, \ 1664 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1665 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1666 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1667 /*xcpt? */ false, false }, \ 1668 /* SNan, Normal (Masked). */ \ 1669 { { /*src2 */ { FP32_SNAN(1), FP32_RAND_V0(1), FP32_RAND_V2(1), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } }, \ 1670 { /*src1 */ { FP32_1(0), FP32_RAND_V0(1), FP32_RAND_V1(1), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V6(0), FP32_RAND_V7(0), FP32_RAND_V1(1) } }, \ 1671 { /* => */ { FP32_SNAN(1), FP32_RAND_V0(1), FP32_RAND_V1(1), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V6(0), FP32_RAND_V7(0), FP32_RAND_V1(1) } }, \ 1672 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1673 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1674 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1675 /*xcpt? */ false, false }, \ 1676 /* QNan, QNan (Unmasked). */ \ 1677 /*0 */{ { /*src2 */ { FP32_QNAN(0), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V2(0), FP32_RAND_V1(1), FP32_RAND_V7(0), FP32_RAND_V2(1) } }, \ 1678 { /*src1 */ { FP32_QNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V5(1), FP32_RAND_V6(1), FP32_RAND_V7(1), FP32_RAND_V1(1) } }, \ 1679 { /* => */ { FP32_QNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V5(1), FP32_RAND_V6(1), FP32_RAND_V7(1), FP32_RAND_V1(1) } }, \ 1680 /*mxcsr:in */ 0, \ 1681 /*128:out */ X86_MXCSR_IE, \ 1682 /*256:out */ X86_MXCSR_IE, \ 1683 /*xcpt? */ true, true }, \ 1684 { { /*src2 */ { FP32_QNAN_MAX(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(0), FP32_RAND_V6(1) } }, \ 1685 { /*src1 */ { FP32_QNAN(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V1(0) } }, \ 1686 { /* => */ { FP32_QNAN_MAX(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V1(0) } }, \ 1687 /*mxcsr:in */ 0, \ 1688 /*128:out */ X86_MXCSR_IE, \ 1689 /*256:out */ X86_MXCSR_IE, \ 1690 /*xcpt? */ true, true }, \ 1691 { { /*src2 */ { FP32_QNAN_V0(0), FP32_RAND_V0(1), FP32_RAND_V7(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } }, \ 1692 { /*src1 */ { FP32_QNAN_MAX(0), FP32_RAND_V1(0), FP32_RAND_V7(0), FP32_RAND_V2(1), FP32_RAND_V6(1), FP32_RAND_V3(1), FP32_RAND_V5(0), FP32_RAND_V4(1) } }, \ 1693 { /* => */ { FP32_QNAN_V0(0), FP32_RAND_V1(0), FP32_RAND_V7(0), FP32_RAND_V2(1), FP32_RAND_V6(1), FP32_RAND_V3(1), FP32_RAND_V5(0), FP32_RAND_V4(1) } }, \ 1694 /*mxcsr:in */ 0, \ 1695 /*128:out */ X86_MXCSR_IE, \ 1696 /*256:out */ X86_MXCSR_IE, \ 1697 /*xcpt? */ true, true }, \ 1698 /* QNan, SNan (Unmasked). */ \ 1699 { { /*src2 */ { FP32_QNAN(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V2(0), FP32_RAND_V2(1), FP32_RAND_V1(0), FP32_RAND_V0(1) } }, \ 1700 { /*src1 */ { FP32_SNAN(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, \ 1701 { /* => */ { FP32_QNAN(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, \ 1702 /*mxcsr:in */ 0, \ 1703 /*128:out */ X86_MXCSR_IE, \ 1704 /*256:out */ X86_MXCSR_IE, \ 1705 /*xcpt? */ true, true }, \ 1706 { { /*src2 */ { FP32_QNAN_MAX(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V1(1), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, \ 1707 { /*src1 */ { FP32_SNAN(0), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V3(0) } }, \ 1708 { /* => */ { FP32_QNAN_MAX(0), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V3(0) } }, \ 1709 /*mxcsr:in */ 0, \ 1710 /*128:out */ X86_MXCSR_IE, \ 1711 /*256:out */ X86_MXCSR_IE, \ 1712 /*xcpt? */ true, true }, \ 1713 { { /*src2 */ { FP32_QNAN_V0(0), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V1(1), FP32_RAND_V0(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, \ 1714 { /*src1 */ { FP32_SNAN_MAX(0), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V1(0) } }, \ 1715 { /* => */ { FP32_QNAN_V0(0), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V1(0) } }, \ 1716 /*mxcsr:in */ 0, \ 1717 /*128:out */ X86_MXCSR_IE, \ 1718 /*256:out */ X86_MXCSR_IE, \ 1719 /*xcpt? */ true, true }, \ 1720 /* SNan, QNan (Unmasked). */ \ 1721 { { /*src2 */ { FP32_SNAN(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V1(1), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, \ 1722 { /*src1 */ { FP32_QNAN(0), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V3(0) } }, \ 1723 { /* => */ { FP32_SNAN(0), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V3(0) } }, \ 1724 /*mxcsr:in */ X86_MXCSR_FZ, \ 1725 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_IE, \ 1726 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_IE, \ 1727 /*xcpt? */ true, true }, \ 1728 { { /*src2 */ { FP32_SNAN(0), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V7(1) } }, \ 1729 { /*src1 */ { FP32_QNAN_MAX(0), FP32_RAND_V2(0), FP32_RAND_V4(0), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V2(0) } }, \ 1730 { /* => */ { FP32_SNAN(0), FP32_RAND_V2(0), FP32_RAND_V4(0), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V2(0) } }, \ 1731 /*mxcsr:in */ 0, \ 1732 /*128:out */ X86_MXCSR_IE, \ 1733 /*256:out */ X86_MXCSR_IE, \ 1734 /*xcpt? */ true, true }, \ 1735 { { /*src2 */ { FP32_SNAN_V1(0), FP32_RAND_V1(1), FP32_RAND_V7(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } }, \ 1736 { /*src1 */ { FP32_QNAN_V6(0), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V0(1), FP32_RAND_V2(0), FP32_RAND_V3(1) } }, \ 1737 { /* => */ { FP32_SNAN_V1(0), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V0(1), FP32_RAND_V2(0), FP32_RAND_V3(1) } }, \ 1738 /*mxcsr:in */ 0, \ 1739 /*128:out */ X86_MXCSR_IE, \ 1740 /*256:out */ X86_MXCSR_IE, \ 1741 /*xcpt? */ true, true }, \ 1742 /* SNan, SNan (Unmasked). */ \ 1743 { { /*src2 */ { FP32_SNAN(0), FP32_RAND_V1(1), FP32_RAND_V7(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } }, \ 1744 { /*src1 */ { FP32_SNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V7(0) } }, \ 1745 { /* => */ { FP32_SNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V7(0) } }, \ 1746 /*mxcsr:in */ 0, \ 1747 /*128:out */ X86_MXCSR_IE, \ 1748 /*256:out */ X86_MXCSR_IE, \ 1749 /*xcpt? */ true, true }, \ 1750 { { /*src2 */ { FP32_SNAN(0), FP32_RAND_V1(0), FP32_RAND_V7(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V1(1), FP32_RAND_V2(1) } }, \ 1751 { /*src1 */ { FP32_SNAN_MAX(0), FP32_RAND_V7(0), FP32_RAND_V5(0), FP32_RAND_V7(1), FP32_RAND_V6(1), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V2(1) } }, \ 1752 { /* => */ { FP32_SNAN(0), FP32_RAND_V7(0), FP32_RAND_V5(0), FP32_RAND_V7(1), FP32_RAND_V6(1), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V2(1) } }, \ 1753 /*mxcsr:in */ 0, \ 1754 /*128:out */ X86_MXCSR_IE, \ 1755 /*256:out */ X86_MXCSR_IE, \ 1756 /*xcpt? */ true, true }, \ 1757 { { /*src2 */ { FP32_SNAN_V1(0), FP32_RAND_V1(1), FP32_RAND_V6(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } }, \ 1758 { /*src1 */ { FP32_SNAN_V4(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V0(1) } }, \ 1759 { /* => */ { FP32_SNAN_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V0(1) } }, \ 1760 /*mxcsr:in */ 0, \ 1761 /*128:out */ X86_MXCSR_IE, \ 1762 /*256:out */ X86_MXCSR_IE, \ 1763 /*xcpt? */ true, true }, \ 1764 /* QNan, Normal (Unmasked). */ \ 1765 { { /*src2 */ { FP32_QNAN(0), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } }, \ 1766 { /*src1 */ { FP32_1(0), FP32_RAND_V2(1), FP32_RAND_V4(1), FP32_RAND_V6(1), FP32_RAND_V2(1), FP32_RAND_V7(0), FP32_RAND_V3(0), FP32_RAND_V4(1) } }, \ 1767 { /* => */ { FP32_QNAN(0), FP32_RAND_V2(1), FP32_RAND_V4(1), FP32_RAND_V6(1), FP32_RAND_V2(1), FP32_RAND_V7(0), FP32_RAND_V3(0), FP32_RAND_V4(1) } }, \ 1768 /*mxcsr:in */ 0, \ 1769 /*128:out */ X86_MXCSR_IE, \ 1770 /*256:out */ X86_MXCSR_IE, \ 1771 /*xcpt? */ true, true }, \ 1772 /* SNan, Normal (Masked). */ \ 1773 { { /*src2 */ { FP32_SNAN(1), FP32_RAND_V0(1), FP32_RAND_V2(1), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } }, \ 1774 { /*src1 */ { FP32_1(0), FP32_RAND_V0(1), FP32_RAND_V1(1), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V6(0), FP32_RAND_V7(0), FP32_RAND_V1(1) } }, \ 1775 { /* => */ { FP32_SNAN(1), FP32_RAND_V0(1), FP32_RAND_V1(1), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V6(0), FP32_RAND_V7(0), FP32_RAND_V1(1) } }, \ 1776 /*mxcsr:in */ 0, \ 1777 /*128:out */ X86_MXCSR_IE, \ 1778 /*256:out */ X86_MXCSR_IE, \ 1779 /*xcpt? */ true, true }, \ 1777 1780 1778 1781 /** … … 11455 11458 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 11456 11459 /*xcpt? */ false, false }, 11457 { { /*src2 */ { FP32_0(0), FP32_INF(0), FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN(1), FP32_QNAN(1), FP32_INF(1), FP32_RAND_V7(0)} },11458 { /*src1 */ { FP32_0(0), FP32_INF(1), FP32_QNAN(0), FP32_SNAN(1), FP32_QNAN_V(0, 1), FP32_QNAN_V(1, 1), FP32_SNAN _V(1, 1), FP32_SNAN_V(0, 1) } },11459 { /* => */ { FP32_0(0), FP32_INF(1), FP32_QNAN(0), FP32_SNAN(1), FP32_QNAN_V(0, 1), FP32_QNAN_V(1, 1), FP32_SNAN _V(1, 1), FP32_SNAN_V(0, 1) } },11460 { { /*src2 */ { FP32_0(0), FP32_INF(0), FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN(1), FP32_QNAN(1), FP32_INF(1), FP32_RAND_V7(0) } }, 11461 { /*src1 */ { FP32_0(0), FP32_INF(1), FP32_QNAN(0), FP32_SNAN(1), FP32_QNAN_V(0, 1), FP32_QNAN_V(1, 1), FP32_SNAN(1), FP32_SNAN(0) } }, 11462 { /* => */ { FP32_0(0), FP32_INF(1), FP32_QNAN(0), FP32_SNAN(1), FP32_QNAN_V(0, 1), FP32_QNAN_V(1, 1), FP32_SNAN(1), FP32_SNAN(0) } }, 11460 11463 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 11461 11464 /*128:out */ X86_MXCSR_XCPT_MASK, … … 11550 11553 /*xcpt? */ false, false }, 11551 11554 { { /*src2 */ { FP32_INF(0), FP32_RAND_V3(1), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(1) } }, 11552 { /*src1 */ { FP32_INF(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V5(1), FP32_RAND_V6(0), FP32_SNAN _V(0, 1), FP32_SNAN_V(1,1), FP32_RAND_V2(1) } },11553 { /* => */ { FP32_INF(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V5(1), FP32_RAND_V6(0), FP32_SNAN _V(0, 1), FP32_SNAN_V(1,1), FP32_RAND_V2(1) } },11555 { /*src1 */ { FP32_INF(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V5(1), FP32_RAND_V6(0), FP32_SNAN(0), FP32_SNAN(1), FP32_RAND_V2(1) } }, 11556 { /* => */ { FP32_INF(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V5(1), FP32_RAND_V6(0), FP32_SNAN(0), FP32_SNAN(1), FP32_RAND_V2(1) } }, 11554 11557 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 11555 11558 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, … … 11557 11560 /*xcpt? */ false, false }, 11558 11561 { { /*src2 */ { FP32_INF(0), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(1) } }, 11559 { /*src1 */ { FP32_INF(0), FP32_RAND_V0(1), FP32_RAND_V0(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_SNAN _V(1,1), FP32_QNAN_V(1, 1), FP32_RAND_V3(1) } },11560 { /* => */ { FP32_INF(0), FP32_RAND_V0(1), FP32_RAND_V0(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_SNAN _V(1,1), FP32_QNAN_V(1, 1), FP32_RAND_V3(1) } },11562 { /*src1 */ { FP32_INF(0), FP32_RAND_V0(1), FP32_RAND_V0(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_SNAN(1), FP32_QNAN_V(1, 1), FP32_RAND_V3(1) } }, 11563 { /* => */ { FP32_INF(0), FP32_RAND_V0(1), FP32_RAND_V0(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_SNAN(1), FP32_QNAN_V(1, 1), FP32_RAND_V3(1) } }, 11561 11564 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 11562 11565 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, … … 11693 11696 /*xcpt? */ false, false }, 11694 11697 { { /*src2 */ { FP32_V(0, 0, 0x7d)/*0.25*/, FP32_RAND_V2(1), FP32_RAND_V5(0), FP32_RAND_V6(1), FP32_RAND_V4(0), FP32_RAND_V3(1), FP32_RAND_V7(0), FP32_RAND_V1(1) } }, 11695 { /*src1 */ { FP32_V(0, 0, 0x7e)/*0.50*/, FP32_RAND_V0(0), FP32_RAND_V5(0), FP32_RAND_V7(0), FP32_RAND_V2(1), FP32_SNAN _V(1, 1), FP32_SNAN_V(0, 1), FP32_RAND_V3(0) } },11696 { /* => */ { FP32_V(0, 0, 0x7e)/*0.50*/, FP32_RAND_V0(0), FP32_RAND_V5(0), FP32_RAND_V7(0), FP32_RAND_V2(1), FP32_SNAN _V(1, 1), FP32_SNAN_V(0, 1), FP32_RAND_V3(0) } },11698 { /*src1 */ { FP32_V(0, 0, 0x7e)/*0.50*/, FP32_RAND_V0(0), FP32_RAND_V5(0), FP32_RAND_V7(0), FP32_RAND_V2(1), FP32_SNAN(1), FP32_SNAN(0), FP32_RAND_V3(0) } }, 11699 { /* => */ { FP32_V(0, 0, 0x7e)/*0.50*/, FP32_RAND_V0(0), FP32_RAND_V5(0), FP32_RAND_V7(0), FP32_RAND_V2(1), FP32_SNAN(1), FP32_SNAN(0), FP32_RAND_V3(0) } }, 11697 11700 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 11698 11701 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, … … 13014 13017 /*xcpt? */ false, false }, 13015 13018 { { /*src2 */ { FP32_0(0), FP32_INF(0), FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN(1), FP32_QNAN(1), FP32_INF(1), FP32_RAND_V7(0) } }, 13016 { /*src1 */ { FP32_0(0), FP32_INF(1), FP32_QNAN(0), FP32_SNAN(1), FP32_QNAN_V(0, 1), FP32_QNAN_V(1, 1), FP32_SNAN _V(1, 1), FP32_SNAN_V(0, 1) } },13017 { /* => */ { FP32_0(0), FP32_INF(1), FP32_QNAN(0), FP32_SNAN(1), FP32_QNAN_V(0, 1), FP32_QNAN_V(1, 1), FP32_SNAN _V(1, 1), FP32_SNAN_V(0, 1) } },13019 { /*src1 */ { FP32_0(0), FP32_INF(1), FP32_QNAN(0), FP32_SNAN(1), FP32_QNAN_V(0, 1), FP32_QNAN_V(1, 1), FP32_SNAN(1), FP32_SNAN(0) } }, 13020 { /* => */ { FP32_0(0), FP32_INF(1), FP32_QNAN(0), FP32_SNAN(1), FP32_QNAN_V(0, 1), FP32_QNAN_V(1, 1), FP32_SNAN(1), FP32_SNAN(0) } }, 13018 13021 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 13019 13022 /*128:out */ X86_MXCSR_XCPT_MASK, … … 13108 13111 /*xcpt? */ false, false }, 13109 13112 { { /*src2 */ { FP32_INF(0), FP32_RAND_V3(1), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(1) } }, 13110 { /*src1 */ { FP32_INF(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V5(1), FP32_RAND_V6(0), FP32_SNAN _V(0, 1), FP32_SNAN_V(1,1), FP32_RAND_V2(1) } },13111 { /* => */ { FP32_INF(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V5(1), FP32_RAND_V6(0), FP32_SNAN _V(0, 1), FP32_SNAN_V(1,1), FP32_RAND_V2(1) } },13113 { /*src1 */ { FP32_INF(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V5(1), FP32_RAND_V6(0), FP32_SNAN(0), FP32_SNAN(1), FP32_RAND_V2(1) } }, 13114 { /* => */ { FP32_INF(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V5(1), FP32_RAND_V6(0), FP32_SNAN(0), FP32_SNAN(1), FP32_RAND_V2(1) } }, 13112 13115 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 13113 13116 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, … … 13115 13118 /*xcpt? */ false, false }, 13116 13119 { { /*src2 */ { FP32_INF(0), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(1) } }, 13117 { /*src1 */ { FP32_INF(0), FP32_RAND_V0(1), FP32_RAND_V0(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_SNAN _V(1,1), FP32_QNAN_V(1, 1), FP32_RAND_V3(1) } },13118 { /* => */ { FP32_INF(0), FP32_RAND_V0(1), FP32_RAND_V0(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_SNAN _V(1,1), FP32_QNAN_V(1, 1), FP32_RAND_V3(1) } },13120 { /*src1 */ { FP32_INF(0), FP32_RAND_V0(1), FP32_RAND_V0(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_SNAN(1), FP32_QNAN_V(1, 1), FP32_RAND_V3(1) } }, 13121 { /* => */ { FP32_INF(0), FP32_RAND_V0(1), FP32_RAND_V0(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_SNAN(1), FP32_QNAN_V(1, 1), FP32_RAND_V3(1) } }, 13119 13122 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 13120 13123 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, … … 13251 13254 /*xcpt? */ false, false }, 13252 13255 { { /*src2 */ { FP32_V(0, 0, 0x7d)/*0.25*/, FP32_RAND_V2(1), FP32_RAND_V5(0), FP32_RAND_V6(1), FP32_RAND_V4(0), FP32_RAND_V3(1), FP32_RAND_V7(0), FP32_RAND_V1(1) } }, 13253 { /*src1 */ { FP32_V(0, 0, 0x7e)/*0.50*/, FP32_RAND_V0(0), FP32_RAND_V5(0), FP32_RAND_V7(0), FP32_RAND_V2(1), FP32_SNAN _V(1, 1), FP32_SNAN_V(0, 1), FP32_RAND_V3(0) } },13254 { /* => */ { FP32_V(0, 0, 0x7d)/*0.25*/, FP32_RAND_V0(0), FP32_RAND_V5(0), FP32_RAND_V7(0), FP32_RAND_V2(1), FP32_SNAN _V(1, 1), FP32_SNAN_V(0, 1), FP32_RAND_V3(0) } },13256 { /*src1 */ { FP32_V(0, 0, 0x7e)/*0.50*/, FP32_RAND_V0(0), FP32_RAND_V5(0), FP32_RAND_V7(0), FP32_RAND_V2(1), FP32_SNAN(1), FP32_SNAN(0), FP32_RAND_V3(0) } }, 13257 { /* => */ { FP32_V(0, 0, 0x7d)/*0.25*/, FP32_RAND_V0(0), FP32_RAND_V5(0), FP32_RAND_V7(0), FP32_RAND_V2(1), FP32_SNAN(1), FP32_SNAN(0), FP32_RAND_V3(0) } }, 13255 13258 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 13256 13259 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
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