Index: trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32
===================================================================
--- trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32	(revision 106212)
+++ trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32	(revision 106213)
@@ -105,6 +105,8 @@
 #define FP32_QNAN(a_Sign)                   RTFLOAT32U_INIT_QNAN(a_Sign)
 #define FP32_QNAN_V(a_Sign, a_Val)          RTFLOAT32U_INIT_QNAN_EX(a_Sign, a_Val)
+#define FP32_QNAN_MAX(a_Sign)               RTFLOAT32U_INIT_QNAN_EX(a_Sign, FP32_FRAC_QNAN_MAX)
 #define FP32_SNAN(a_Sign)                   RTFLOAT32U_INIT_SNAN(a_Sign)
 #define FP32_SNAN_V(a_Sign, a_Val)          RTFLOAT32U_INIT_SNAN_EX(a_Sign, a_Val)
+#define FP32_SNAN_MAX(a_Sign)               RTFLOAT32U_INIT_SNAN_EX(a_Sign, FP32_FRAC_SNAN_MAX)
 /** @todo Move this to iprt/types.h after renaming it to RTFLOAT32U_MAKE? */
 #ifdef RT_BIG_ENDIAN
@@ -194,5 +196,6 @@
 /*
  * Single-precision floating-point invalids.
- * (1 to 0x3fffff fractional part for SNANs and 0x400000 to 0x7fffff for QNAN).
+ * 1 to 0x3fffff fractional part for SNANs and 0x400000 to 0x7fffff for QNAN.
+ * The QNAN initialization macro ensures the range for QNAN is correct by OR'ing 0x400000.
  */
 #define FP32_FRAC_INV_V0                    0x3fffff
@@ -625,88 +628,88 @@
  **/
 #define FP32_TABLE_D1_PS_INVALIDS \
-    /*0 */{ { /*src2     */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0),       FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },      \
-            { /*src1     */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },      \
-            { /* =>      */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },      \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                                                                                                                   \
-              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                                                                                                                                   \
-              /*256:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                                                                                                                                   \
-              /*xcpt?    */ false, false },                                                                                                                                                                                                                                        \
-          { { /*src2     */ { FP32_QNAN(0),      FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0),       FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, \
-            { /*src1     */ { FP32_SNAN(0),      FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, \
-            { /* =>      */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1),                  FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                                                                                                                   \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                                                                                                    \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                                                                                                    \
-              /*xcpt?    */ false, false },                                                                                                                                                                                                                                        \
-          { { /*src2     */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },            \
-            { /*src1     */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },            \
-            { /* =>      */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },            \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,                                                                                                                                                                                                                    \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,                                                                                                                                                                                                     \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,                                                                                                                                                                                                     \
-              /*xcpt?    */ false, false },                                                                                                                                                                                                                                        \
-          { { /*src2     */ { FP32_SNAN(0),      FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },       \
-            { /*src1     */ { FP32_SNAN(0),      FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },       \
-            { /* =>      */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2) } },       \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                                                                                                                   \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                                                                                                    \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                                                                                                    \
-              /*xcpt?    */ false, false },                                                                                                                                                                                                                                        \
-          { { /*src2     */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1),              FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0),              FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0),              FP32_QNAN_V(1, FP32_FRAC_V5) } },            \
-            { /*src1     */ { FP32_1(0),    FP32_1(1),                          FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1),              FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0),              FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1)              } },            \
-            { /* =>      */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } },            \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS,                                                                                                                                                                                                            \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS,                                                                                                                                                                                                            \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS,                                                                                                                                                                                                            \
-              /*xcpt?    */ false, false },                                                                                                                                                                                                                                        \
-          { { /*src2     */ { FP32_SNAN(1),      FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1),              FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0),              FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0),              FP32_SNAN_V(1, FP32_FRAC_V5) } },       \
-            { /*src1     */ { FP32_1(0),         FP32_1(0),                          FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1),              FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0),              FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1)              } },       \
-            { /* =>      */ { FP32_QNAN_V(1, 1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } },       \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                                                                                                                   \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                                                                                                    \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                                                                                                    \
-              /*xcpt?    */ false, false },                                                                                                                                                                                                                                        \
-          { { /*src2     */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0),       FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },      \
-            { /*src1     */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },      \
-            { /* =>      */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },      \
-              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,                                                                                                                                                                                                                      \
-              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,                                                                                                                                                                                                                      \
-              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,                                                                                                                                                                                                                      \
-              /*xcpt?    */ false, false },                                                                                                                                                                                                                                        \
-          { { /*src2     */ { FP32_QNAN(0),      FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0),       FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, \
-            { /*src1     */ { FP32_SNAN(0),      FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, \
-            { /* =>      */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1),                  FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, \
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,                                                                                                                                                                                                      \
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,                                                                                                                                                                                       \
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,                                                                                                                                                                                       \
-              /*xcpt?    */ true, true },                                                                                                                                                                                                                                          \
-          { { /*src2     */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },            \
-            { /*src1     */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },            \
-            { /* =>      */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },            \
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,                                                                                                                                                                                                        \
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,                                                                                                                                                                                         \
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,                                                                                                                                                                                         \
-              /*xcpt?    */ true, true },                                                                                                                                                                                                                                          \
-          { { /*src2     */ { FP32_SNAN(0),      FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },       \
-            { /*src1     */ { FP32_SNAN(0),      FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },       \
-            { /* =>      */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2) } },       \
-              /*mxcsr:in */ X86_MXCSR_RC_UP,                                                                                                                                                                                                                                       \
-              /*128:out  */ X86_MXCSR_RC_UP | X86_MXCSR_IE,                                                                                                                                                                                                                        \
-              /*256:out  */ X86_MXCSR_RC_UP | X86_MXCSR_IE,                                                                                                                                                                                                                        \
-              /*xcpt?    */ true, true },                                                                                                                                                                                                                                          \
-          { { /*src2     */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1),              FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0),              FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0),              FP32_QNAN_V(1, FP32_FRAC_V5) } },            \
-            { /*src1     */ { FP32_1(0),    FP32_1(1),                          FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1),              FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0),              FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1)              } },            \
-            { /* =>      */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } },            \
-              /*mxcsr:in */ 0,                                                                                                                                                                                                                                                     \
-              /*128:out  */ 0,                                                                                                                                                                                                                                                     \
-              /*256:out  */ 0,                                                                                                                                                                                                                                                     \
-              /*xcpt?    */ false, false },                                                                                                                                                                                                                                        \
-    /*11*/{ { /*src2     */ { FP32_SNAN(1),      FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1),              FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0),              FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0),              FP32_SNAN_V(1, FP32_FRAC_V5) } },       \
-            { /*src1     */ { FP32_1(0),         FP32_1(0),                          FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1),              FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0),              FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1)              } },       \
-            { /* =>      */ { FP32_QNAN_V(1, 1), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V3), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(1, FP32_FRAC_V5) } },       \
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,                                                                                                                                                                                                                     \
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,                                                                                                                                                                                                      \
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,                                                                                                                                                                                                      \
-              /*xcpt?    */ true, true },                                                                                                                                                                                                                                          \
+    /*0 */{ { /*src2     */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0),  FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } },       \
+            { /*src1     */ { FP32_QNAN(0), FP32_QNAN(0),     FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } },       \
+            { /* =>      */ { FP32_QNAN(0), FP32_QNAN(0),     FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } },       \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                               \
+              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                               \
+              /*256:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                               \
+              /*xcpt?    */ false, false },                                                                                                                                    \
+          { { /*src2     */ { FP32_QNAN(0),      FP32_QNAN_MAX(0),  FP32_QNAN_V0(0),  FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \
+            { /*src1     */ { FP32_SNAN(0),      FP32_SNAN(0),      FP32_SNAN_MAX(0), FP32_SNAN_V2(0), FP32_SNAN_V6(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V4(0) } }, \
+            { /* =>      */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } }, \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                               \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                \
+              /*xcpt?    */ false, false },                                                                                                                                    \
+          { { /*src2     */ { FP32_SNAN(0), FP32_SNAN(0),     FP32_SNAN_V1(0), FP32_SNAN_V1(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V5(0), FP32_SNAN_V6(0) } },        \
+            { /*src1     */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } },        \
+            { /* =>      */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } },        \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,                                                                                                                \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,                                                                                                 \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,                                                                                                 \
+              /*xcpt?    */ false, false },                                                                                                                                    \
+          { { /*src2     */ { FP32_SNAN(0),      FP32_SNAN(0),     FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V7(0), FP32_SNAN_V1(0), FP32_SNAN_V6(0), FP32_SNAN_V1(0) } },   \
+            { /*src1     */ { FP32_SNAN(0),      FP32_SNAN_MAX(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } },   \
+            { /* =>      */ { FP32_QNAN_V(0, 1), FP32_QNAN_MAX(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V5(0), FP32_QNAN_V3(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0) } },   \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                               \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                \
+              /*xcpt?    */ false, false },                                                                                                                                    \
+          { { /*src2     */ { FP32_QNAN(0), FP32_QNAN_MAX(1), FP32_NORM_V0(1), FP32_QNAN_V1(0), FP32_NORM_V3(0), FP32_QNAN_V3(1), FP32_NORM_V5(0), FP32_QNAN_V5(1) } },        \
+            { /*src1     */ { FP32_1(0),    FP32_1(1),        FP32_QNAN_V0(1), FP32_NORM_V2(1), FP32_QNAN_V2(0), FP32_NORM_V4(0), FP32_QNAN_V4(1), FP32_NORM_V6(1) } },        \
+            { /* =>      */ { FP32_QNAN(0), FP32_QNAN_MAX(1), FP32_QNAN_V0(1), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(1), FP32_QNAN_V4(1), FP32_QNAN_V5(1) } },        \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS,                                                                                                        \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS,                                                                                                        \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS,                                                                                                        \
+              /*xcpt?    */ false, false },                                                                                                                                    \
+          { { /*src2     */ { FP32_SNAN(1),      FP32_SNAN_MAX(1), FP32_NORM_V0(1), FP32_SNAN_V1(0), FP32_NORM_V3(0), FP32_SNAN_V3(1), FP32_NORM_V5(0), FP32_SNAN_V5(1) } },   \
+            { /*src1     */ { FP32_1(0),         FP32_1(0),        FP32_SNAN_V0(1), FP32_NORM_V2(1), FP32_SNAN_V2(1), FP32_NORM_V4(0), FP32_SNAN_V4(1), FP32_NORM_V6(1) } },   \
+            { /* =>      */ { FP32_QNAN_V(1, 1), FP32_QNAN_MAX(1), FP32_QNAN_V0(1), FP32_QNAN_V1(0), FP32_QNAN_V2(1), FP32_QNAN_V3(1), FP32_QNAN_V4(1), FP32_QNAN_V5(1) } },   \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                               \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                \
+              /*xcpt?    */ false, false },                                                                                                                                    \
+          { { /*src2     */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0),  FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } },       \
+            { /*src1     */ { FP32_QNAN(0), FP32_QNAN(0),     FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } },       \
+            { /* =>      */ { FP32_QNAN(0), FP32_QNAN(0),     FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } },       \
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,                                                                                                                  \
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,                                                                                                                  \
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,                                                                                                                  \
+              /*xcpt?    */ false, false },                                                                                                                                    \
+          { { /*src2     */ { FP32_QNAN(0),      FP32_QNAN_MAX(0),  FP32_QNAN_V0(0),  FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \
+            { /*src1     */ { FP32_SNAN(0),      FP32_SNAN(0),      FP32_SNAN_MAX(0), FP32_SNAN_V2(0), FP32_SNAN_V6(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V4(0) } }, \
+            { /* =>      */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } }, \
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,                                                                                                  \
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,                                                                                   \
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,                                                                                   \
+              /*xcpt?    */ true, true },                                                                                                                                      \
+          { { /*src2     */ { FP32_SNAN(0), FP32_SNAN(0),     FP32_SNAN_V1(0), FP32_SNAN_V1(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V5(0), FP32_SNAN_V6(0) } },        \
+            { /*src1     */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } },        \
+            { /* =>      */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } },        \
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,                                                                                                    \
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,                                                                                     \
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,                                                                                     \
+              /*xcpt?    */ true, true },                                                                                                                                      \
+          { { /*src2     */ { FP32_SNAN(0),      FP32_SNAN(0),     FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V7(0), FP32_SNAN_V1(0), FP32_SNAN_V6(0), FP32_SNAN_V1(0) } },   \
+            { /*src1     */ { FP32_SNAN(0),      FP32_SNAN_MAX(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } },   \
+            { /* =>      */ { FP32_QNAN_V(0, 1), FP32_QNAN_MAX(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V5(0), FP32_QNAN_V3(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0) } },   \
+              /*mxcsr:in */ X86_MXCSR_RC_UP,                                                                                                                                   \
+              /*128:out  */ X86_MXCSR_RC_UP | X86_MXCSR_IE,                                                                                                                    \
+              /*256:out  */ X86_MXCSR_RC_UP | X86_MXCSR_IE,                                                                                                                    \
+              /*xcpt?    */ true, true },                                                                                                                                      \
+          { { /*src2     */ { FP32_QNAN(0), FP32_QNAN_MAX(1), FP32_NORM_V0(1), FP32_QNAN_V1(0), FP32_NORM_V3(0), FP32_QNAN_V3(1), FP32_NORM_V5(0), FP32_QNAN_V5(1) } },        \
+            { /*src1     */ { FP32_1(0),    FP32_1(1),        FP32_QNAN_V0(1), FP32_NORM_V2(1), FP32_QNAN_V2(0), FP32_NORM_V4(0), FP32_QNAN_V4(1), FP32_NORM_V6(1) } },        \
+            { /* =>      */ { FP32_QNAN(0), FP32_QNAN_MAX(1), FP32_QNAN_V0(1), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(1), FP32_QNAN_V4(1), FP32_QNAN_V5(1) } },        \
+              /*mxcsr:in */ 0,                                                                                                                                                 \
+              /*128:out  */ 0,                                                                                                                                                 \
+              /*256:out  */ 0,                                                                                                                                                 \
+              /*xcpt?    */ false, false },                                                                                                                                    \
+    /*11*/{ { /*src2     */ { FP32_SNAN(1),      FP32_SNAN_MAX(1), FP32_NORM_V0(1), FP32_SNAN_V1(0), FP32_NORM_V3(0), FP32_SNAN_V3(1), FP32_NORM_V5(0), FP32_SNAN_V5(1) } },   \
+            { /*src1     */ { FP32_1(0),         FP32_1(0),        FP32_SNAN_V0(1), FP32_NORM_V2(1), FP32_SNAN_V2(1), FP32_NORM_V4(0), FP32_SNAN_V4(1), FP32_NORM_V6(1) } },   \
+            { /* =>      */ { FP32_QNAN_V(1, 1), FP32_QNAN_MAX(1), FP32_QNAN_V0(1), FP32_QNAN_V1(0), FP32_QNAN_V2(1), FP32_QNAN_V3(1), FP32_QNAN_V4(1), FP32_QNAN_V5(1) } },   \
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,                                                                                                                 \
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,                                                                                                  \
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,                                                                                                  \
+              /*xcpt?    */ true, true },                                                                                                                                      \
 
 /**
@@ -806,212 +809,212 @@
 #define FP32_TABLE_D1_SS_INVALIDS \
     /* QNan, QNan (Masked). */                                                                                                                                                                                                                                                                      \
-    /*0 */{ { /*src2     */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0),       FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },                       \
-            { /*src1     */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },                       \
-            { /* =>      */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },                       \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                                                                                                                                    \
-              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                                                                                                                                                    \
-              /*256:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                                                                                                                                                    \
-              /*xcpt?    */ false, false },                                                                                                                                                                                                                                                         \
-          { { /*src2     */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } },                                           \
-            { /*src1     */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },                                           \
-            { /* =>      */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },                                           \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                                                                                                                                    \
-              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                                                                                                                                                    \
-              /*256:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                                                                                                                                                    \
-              /*xcpt?    */ false, false },                                                                                                                                                                                                                                                         \
-          { { /*src2     */ { FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } },                                                 \
-            { /*src1     */ { FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },                                                 \
-            { /* =>      */ { FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },                                                 \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                                                                                                                                    \
-              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                                                                                                                                                    \
-              /*256:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                                                                                                                                                    \
-              /*xcpt?    */ false, false },                                                                                                                                                                                                                                                         \
-    /* QNan, SNan (Masked). */                                                                                                                                                                                                                                                                      \
-          { { /*src2     */ { FP32_QNAN(0),      FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } },                                                            \
-            { /*src1     */ { FP32_SNAN(0),      FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V1) } },                                                            \
-            { /* =>      */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },                                                            \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                                                                                                                                    \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                                                                                                                     \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                                                                                                                     \
-              /*xcpt?    */ false, false },                                                                                                                                                                                                                                                         \
-          { { /*src2     */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0),       FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, \
-            { /*src1     */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, \
-            { /* =>      */ { FP32_QNAN_V(0, 1),                  FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                                                                                                                                    \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                                                                                                                     \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                                                                                                                     \
-              /*xcpt?    */ false, false },                                                                                                                                                                                                                                                         \
-          { { /*src2     */ { FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0),       FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },       \
-            { /*src1     */ { FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },       \
-            { /* =>      */ { FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },       \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                                                                                                                                    \
-              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                                                                                                                                                    \
-              /*256:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                                                                                                                                                    \
-              /*xcpt?    */ false, false },                                                                                                                                                                                                                                                         \
-    /* SNan, QNan (Masked). */                                                                                                                                                                                                                                                                      \
-          { { /*src2     */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },                             \
-            { /*src1     */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },                             \
-            { /* =>      */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },                             \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                                                                                                                                    \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                                                                                                                     \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                                                                                                                     \
-              /*xcpt?    */ false, false },                                                                                                                                                                                                                                                         \
-          { { /*src2     */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },       \
-            { /*src1     */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },       \
-            { /* =>      */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },       \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                                                                                                                                    \
-              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                                                                                                                                                    \
-              /*256:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                                                                                                                                                    \
-              /*xcpt?    */ false, false },                                                                                                                                                                                                                                                         \
-          { { /*src2     */ { FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },             \
-            { /*src1     */ { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },             \
-            { /* =>      */ { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },             \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                                                                                                                                    \
-              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                                                                                                                                                    \
-              /*256:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                                                                                                                                                    \
-              /*xcpt?    */ false, false },                                                                                                                                                                                                                                                         \
-    /* SNan, SNan (Masked). */                                                                                                                                                                                                                                                                      \
-          { { /*src2     */ { FP32_SNAN(0),      FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },                        \
-            { /*src1     */ { FP32_SNAN(0),      FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },                        \
-            { /* =>      */ { FP32_QNAN_V(0, 1), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },                        \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                                                                                                                                    \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                                                                                                                     \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                                                                                                                     \
-              /*xcpt?    */ false, false },                                                                                                                                                                                                                                                         \
-          { { /*src2     */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },             \
-            { /*src1     */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },             \
-            { /* =>      */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },             \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                                                                                                                                    \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                                                                                                                     \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                                                                                                                     \
-              /*xcpt?    */ false, false },                                                                                                                                                                                                                                                         \
-          { { /*src2     */ { FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },                   \
-            { /*src1     */ { FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } },                   \
-            { /* =>      */ { FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } },                   \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                                                                                                                                    \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                                                                                                                     \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                                                                                                                     \
-              /*xcpt?    */ false, false },                                                                                                                                                                                                                                                         \
-    /* QNan, Norm FP (Masked). */                                                                                                                                                                                                                                                                   \
-          { { /*src2     */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1),              FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0),              FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0),              FP32_QNAN_V(1, FP32_FRAC_V5) } },                             \
-            { /*src1     */ { FP32_1(0),    FP32_1(1),                          FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1),              FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0),              FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1)              } },                             \
-            { /* =>      */ { FP32_QNAN(0), FP32_1(1),                          FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1),              FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0),              FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1)              } },                             \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                                                                                                                                    \
-              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                                                                                                                                                    \
-              /*256:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                                                                                                                                                    \
-              /*xcpt?    */ false, false },                                                                                                                                                                                                                                                         \
-    /* SNan, Norm FP (Masked). */                                                                                                                                                                                                                                                                   \
-          { { /*src2     */ { FP32_SNAN(1),      FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1),              FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0),              FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0),              FP32_SNAN_V(1, FP32_FRAC_V5) } },                        \
-            { /*src1     */ { FP32_1(0),         FP32_1(0),                          FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1),              FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0),              FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1)              } },                        \
-            { /* =>      */ { FP32_QNAN_V(1, 1), FP32_1(0),                          FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1),              FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0),              FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1)              } },                        \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                                                                                                                                    \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                                                                                                                     \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                                                                                                                     \
-              /*xcpt?    */ false, false },                                                                                                                                                                                                                                                         \
-    /* QNan, QNan (Unmasked). */                                                                                                                                                                                                                                                                    \
-    /*14*/{ { /*src2     */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0),       FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },                       \
-            { /*src1     */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },                       \
-            { /* =>      */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },                       \
-              /*mxcsr:in */ 0,                                                                                                                                                                                                                                                                      \
-              /*128:out  */ 0,                                                                                                                                                                                                                                                                      \
-              /*256:out  */ 0,                                                                                                                                                                                                                                                                      \
-              /*xcpt?    */ false, false },                                                                                                                                                                                                                                                         \
-          { { /*src2     */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } },                                           \
-            { /*src1     */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },                                           \
-            { /* =>      */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },                                           \
-              /*mxcsr:in */ 0,                                                                                                                                                                                                                                                                      \
-              /*128:out  */ 0,                                                                                                                                                                                                                                                                      \
-              /*256:out  */ 0,                                                                                                                                                                                                                                                                      \
-              /*xcpt?    */ false, false },                                                                                                                                                                                                                                                         \
-          { { /*src2     */ { FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } },                                                 \
-            { /*src1     */ { FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },                                                 \
-            { /* =>      */ { FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },                                                 \
-              /*mxcsr:in */ 0,                                                                                                                                                                                                                                                                      \
-              /*128:out  */ 0,                                                                                                                                                                                                                                                                      \
-              /*256:out  */ 0,                                                                                                                                                                                                                                                                      \
-              /*xcpt?    */ false, false },                                                                                                                                                                                                                                                         \
-                                                                                                                                                                                                                                                                                                    \
-    /* QNan, SNan (Unmasked). */                                                                                                                                                                                                                                                                    \
-          { { /*src2     */ { FP32_QNAN(0),      FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4) } },                                                            \
-            { /*src1     */ { FP32_SNAN(0),      FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V1) } },                                                            \
-            { /* =>      */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1) } },                                                            \
-              /*mxcsr:in */ 0,                                                                                                                                                                                                                                                                      \
-              /*128:out  */ X86_MXCSR_IE,                                                                                                                                                                                                                                                           \
-              /*256:out  */ X86_MXCSR_IE,                                                                                                                                                                                                                                                           \
-              /*xcpt?    */ true, true },                                                                                                                                                                                                                                                           \
-          { { /*src2     */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0),       FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, \
-            { /*src1     */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, \
-            { /* =>      */ { FP32_QNAN_V(0, 1),                  FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, \
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,                                                                                                                                                                                                                       \
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,                                                                                                                                                                                                        \
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,                                                                                                                                                                                                        \
-              /*xcpt?    */ true, true },                                                                                                                                                                                                                                                           \
-          { { /*src2     */ { FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0),       FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } },       \
-            { /*src1     */ { FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },       \
-            { /* =>      */ { FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } },       \
-              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,                                                                                                                                                                                                                                       \
-              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,                                                                                                                                                                                                                                       \
-              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,                                                                                                                                                                                                                                       \
-              /*xcpt?    */ false, false },                                                                                                                                                                                                                                                         \
-    /* SNan, QNan (Unmasked). */                                                                                                                                                                                                                                                                    \
-          { { /*src2     */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },                             \
-            { /*src1     */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },                             \
-            { /* =>      */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },                             \
-              /*mxcsr:in */ X86_MXCSR_DAZ,                                                                                                                                                                                                                                                          \
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_IE,                                                                                                                                                                                                                                           \
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_IE,                                                                                                                                                                                                                                           \
-              /*xcpt?    */ true, true },                                                                                                                                                                                                                                                           \
-          { { /*src2     */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },       \
-            { /*src1     */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },       \
-            { /* =>      */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },       \
-              /*mxcsr:in */ X86_MXCSR_RC_UP,                                                                                                                                                                                                                                                        \
-              /*128:out  */ X86_MXCSR_RC_UP,                                                                                                                                                                                                                                                        \
-              /*256:out  */ X86_MXCSR_RC_UP,                                                                                                                                                                                                                                                        \
-              /*xcpt?    */ false, false },                                                                                                                                                                                                                                                         \
-          { { /*src2     */ { FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },             \
-            { /*src1     */ { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },             \
-            { /* =>      */ { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },             \
-              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,                                                                                                                                                                                                                                       \
-              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,                                                                                                                                                                                                                                       \
-              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,                                                                                                                                                                                                                                       \
-              /*xcpt?    */ false, false },                                                                                                                                                                                                                                                         \
-    /* SNan, SNan (Unmasked). */                                                                                                                                                                                                                                                                    \
-    /*24*/{ { /*src2     */ { FP32_SNAN(0),      FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },                        \
-            { /*src1     */ { FP32_SNAN(0),      FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },                        \
-            { /* =>      */ { FP32_QNAN_V(0, 1), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },                        \
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ,                                                                                                                                                                                                                                           \
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE,                                                                                                                                                                                                                            \
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE,                                                                                                                                                                                                                            \
-              /*xcpt?    */ true, true },                                                                                                                                                                                                                                                           \
-          { { /*src2     */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },             \
-            { /*src1     */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },             \
-            { /* =>      */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V0), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },             \
-              /*mxcsr:in */ X86_MXCSR_RC_ZERO,                                                                                                                                                                                                                                                      \
-              /*128:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE,                                                                                                                                                                                                                                       \
-              /*256:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE,                                                                                                                                                                                                                                       \
-              /*xcpt?    */ true, true },                                                                                                                                                                                                                                                           \
-          { { /*src2     */ { FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },                   \
-            { /*src1     */ { FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } },                   \
-            { /* =>      */ { FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V0) } },                   \
-              /*mxcsr:in */ 0,                                                                                                                                                                                                                                                                      \
-              /*128:out  */ X86_MXCSR_IE,                                                                                                                                                                                                                                                           \
-              /*256:out  */ X86_MXCSR_IE,                                                                                                                                                                                                                                                           \
-              /*xcpt?    */ true, true },                                                                                                                                                                                                                                                           \
-    /* QNan, Norm FP (Unmasked). */                                                                                                                                                                                                                                                                 \
-          { { /*src2     */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1),              FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0),              FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0),              FP32_QNAN_V(1, FP32_FRAC_V5) } },                             \
-            { /*src1     */ { FP32_1(0),    FP32_1(1),                          FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1),              FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0),              FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1)              } },                             \
-            { /* =>      */ { FP32_QNAN(0), FP32_1(1),                          FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1),              FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0),              FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1)              } },                             \
-              /*mxcsr:in */ X86_MXCSR_FZ,                                                                                                                                                                                                                                                           \
-              /*128:out  */ X86_MXCSR_FZ,                                                                                                                                                                                                                                                           \
-              /*256:out  */ X86_MXCSR_FZ,                                                                                                                                                                                                                                                           \
-              /*xcpt?    */ false, false },                                                                                                                                                                                                                                                         \
-    /* SNan, Norm FP (Unmasked). */                                                                                                                                                                                                                                                                 \
-    /*28*/{ { /*src2     */ { FP32_SNAN(1),      FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1),              FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0),              FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0),              FP32_SNAN_V(1, FP32_FRAC_V5) } },                        \
-            { /*src1     */ { FP32_1(0),         FP32_1(0),                          FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1),              FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0),              FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1)              } },                        \
-            { /* =>      */ { FP32_QNAN_V(1, 1), FP32_1(0),                          FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1),              FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0),              FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1)              } },                        \
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,                                                                                                                                                                                                                       \
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,                                                                                                                                                                                                        \
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,                                                                                                                                                                                                        \
-              /*xcpt?    */ true, true },                                                                                                                                                                                                                                                           \
+    /*0 */{ { /*src2     */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0),  FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } },      \
+            { /*src1     */ { FP32_QNAN(0), FP32_QNAN(0),     FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } },      \
+            { /* =>      */ { FP32_QNAN(0), FP32_QNAN(0),     FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } },      \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                              \
+              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                              \
+              /*256:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                              \
+              /*xcpt?    */ false, false },                                                                                                                                   \
+          { { /*src2     */ { FP32_QNAN_MAX(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0) } },                     \
+            { /*src1     */ { FP32_QNAN(0),     FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0), FP32_QNAN_V1(0) } },                     \
+            { /* =>      */ { FP32_QNAN(0),     FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0), FP32_QNAN_V1(0) } },                     \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                              \
+              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                              \
+              /*256:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                              \
+              /*xcpt?    */ false, false },                                                                                                                                   \
+          { { /*src2     */ { FP32_QNAN_V1(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0) } },                      \
+            { /*src1     */ { FP32_QNAN_V2(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0), FP32_QNAN_V1(0) } },                      \
+            { /* =>      */ { FP32_QNAN_V2(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0), FP32_QNAN_V1(0) } },                      \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                              \
+              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                              \
+              /*256:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                              \
+              /*xcpt?    */ false, false },                                                                                                                                   \
+    /* QNan, SNan (Masked). */                                                                                                                                                \
+          { { /*src2     */ { FP32_QNAN(0),      FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0) } },                    \
+            { /*src1     */ { FP32_SNAN(0),      FP32_SNAN_V2(0), FP32_SNAN_V6(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V4(0), FP32_SNAN_V1(0) } },                    \
+            { /* =>      */ { FP32_QNAN_V(0, 1), FP32_SNAN_V2(0), FP32_SNAN_V6(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V4(0), FP32_QNAN_V1(0) } },                    \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                              \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                               \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                               \
+              /*xcpt?    */ false, false },                                                                                                                                   \
+          { { /*src2     */ { FP32_QNAN_MAX(0),  FP32_QNAN_MAX(0), FP32_QNAN_V0(0),  FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \
+            { /*src1     */ { FP32_SNAN(0),      FP32_SNAN(0),     FP32_SNAN_MAX(0), FP32_SNAN_V2(0), FP32_SNAN_V6(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V4(0) } }, \
+            { /* =>      */ { FP32_QNAN_V(0, 1), FP32_SNAN(0),     FP32_SNAN_MAX(0), FP32_SNAN_V2(0), FP32_SNAN_V6(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V4(0) } }, \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                              \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                               \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                               \
+              /*xcpt?    */ false, false },                                                                                                                                   \
+          { { /*src2     */ { FP32_QNAN_V1(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0),  FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } },   \
+            { /*src1     */ { FP32_SNAN_V2(0), FP32_QNAN(0),     FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } },   \
+            { /* =>      */ { FP32_QNAN_V2(0), FP32_QNAN(0),     FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } },   \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                              \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                               \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                               \
+              /*xcpt?    */ false, false },                                                                                                                                   \
+    /* SNan, QNan (Masked). */                                                                                                                                                \
+          { { /*src2     */ { FP32_SNAN(0), FP32_SNAN(0),     FP32_SNAN_V1(0), FP32_SNAN_V1(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V5(0), FP32_SNAN_V6(0) } },       \
+            { /*src1     */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } },       \
+            { /* =>      */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } },       \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                              \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                               \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                               \
+              /*xcpt?    */ false, false },                                                                                                                                   \
+          { { /*src2     */ { FP32_SNAN_MAX(0), FP32_SNAN_MAX(0), FP32_SNAN_V1(0), FP32_SNAN_V1(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V5(0), FP32_SNAN_V6(0) } },   \
+            { /*src1     */ { FP32_QNAN(0),     FP32_QNAN(0),     FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } },   \
+            { /* =>      */ { FP32_QNAN(0),     FP32_QNAN(0),     FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } },   \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                              \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                               \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                               \
+              /*xcpt?    */ false, false },                                                                                                                                   \
+          { { /*src2     */ { FP32_SNAN_V0(0), FP32_SNAN_MAX(0), FP32_SNAN_V1(0), FP32_SNAN_V1(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V5(0), FP32_SNAN_V6(0) } },    \
+            { /*src1     */ { FP32_QNAN_V6(0), FP32_QNAN(0),     FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } },    \
+            { /* =>      */ { FP32_QNAN_V6(0), FP32_QNAN(0),     FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } },    \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                              \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                               \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                               \
+              /*xcpt?    */ false, false },                                                                                                                                   \
+    /* SNan, SNan (Masked). */                                                                                                                                                \
+          { { /*src2     */ { FP32_SNAN(0),      FP32_SNAN(0),     FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V7(0), FP32_SNAN_V1(0), FP32_SNAN_V6(0), FP32_SNAN_V1(0) } },  \
+            { /*src1     */ { FP32_SNAN(0),      FP32_SNAN_MAX(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } },  \
+            { /* =>      */ { FP32_QNAN_V(0, 1), FP32_SNAN_MAX(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } },  \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                              \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                               \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                               \
+              /*xcpt?    */ false, false },                                                                                                                                   \
+          { { /*src2     */ { FP32_SNAN(0),     FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V7(0), FP32_SNAN_V1(0), FP32_SNAN_V6(0), FP32_SNAN_V1(0) } },    \
+            { /*src1     */ { FP32_SNAN_MAX(0), FP32_SNAN_V0(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } },    \
+            { /* =>      */ { FP32_QNAN_MAX(0), FP32_SNAN_V0(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } },    \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                              \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                               \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                               \
+              /*xcpt?    */ false, false },                                                                                                                                   \
+          { { /*src2     */ { FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V7(0), FP32_SNAN_V1(0), FP32_SNAN_V6(0), FP32_SNAN_V1(0) } },     \
+            { /*src1     */ { FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V0(0) } },     \
+            { /* =>      */ { FP32_QNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V0(0) } },     \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                              \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                               \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                               \
+              /*xcpt?    */ false, false },                                                                                                                                   \
+    /* QNan, Norm FP (Masked). */                                                                                                                                             \
+          { { /*src2     */ { FP32_QNAN(0), FP32_QNAN_MAX(1), FP32_NORM_V0(1), FP32_QNAN_V1(0), FP32_NORM_V3(0), FP32_QNAN_V3(1), FP32_NORM_V5(0), FP32_QNAN_V5(1) } },       \
+            { /*src1     */ { FP32_1(0),    FP32_1(1),        FP32_QNAN_V0(1), FP32_NORM_V2(1), FP32_QNAN_V2(0), FP32_NORM_V4(0), FP32_QNAN_V4(1), FP32_NORM_V6(1) } },       \
+            { /* =>      */ { FP32_QNAN(0), FP32_1(1),        FP32_QNAN_V0(1), FP32_NORM_V2(1), FP32_QNAN_V2(0), FP32_NORM_V4(0), FP32_QNAN_V4(1), FP32_NORM_V6(1) } },       \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                              \
+              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                              \
+              /*256:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                              \
+              /*xcpt?    */ false, false },                                                                                                                                   \
+    /* SNan, Norm FP (Masked). */                                                                                                                                             \
+          { { /*src2     */ { FP32_SNAN(1),      FP32_SNAN_MAX(1), FP32_NORM_V0(1), FP32_SNAN_V1(0), FP32_NORM_V3(0), FP32_SNAN_V3(1), FP32_NORM_V5(0), FP32_SNAN_V5(1) } },  \
+            { /*src1     */ { FP32_1(0),         FP32_1(0),        FP32_SNAN_V0(1), FP32_NORM_V2(1), FP32_SNAN_V2(1), FP32_NORM_V4(0), FP32_SNAN_V4(1), FP32_NORM_V6(1) } },  \
+            { /* =>      */ { FP32_QNAN_V(1, 1), FP32_1(0),        FP32_SNAN_V0(1), FP32_NORM_V2(1), FP32_SNAN_V2(1), FP32_NORM_V4(0), FP32_SNAN_V4(1), FP32_NORM_V6(1) } },  \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                              \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                               \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                               \
+              /*xcpt?    */ false, false },                                                                                                                                   \
+    /* QNan, QNan (Unmasked). */                                                                                                                                              \
+    /*14*/{ { /*src2     */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0),  FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } },      \
+            { /*src1     */ { FP32_QNAN(0), FP32_QNAN(0),     FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } },      \
+            { /* =>      */ { FP32_QNAN(0), FP32_QNAN(0),     FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } },      \
+              /*mxcsr:in */ 0,                                                                                                                                                \
+              /*128:out  */ 0,                                                                                                                                                \
+              /*256:out  */ 0,                                                                                                                                                \
+              /*xcpt?    */ false, false },                                                                                                                                   \
+          { { /*src2     */ { FP32_QNAN_MAX(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0) } },                     \
+            { /*src1     */ { FP32_QNAN(0),     FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0), FP32_QNAN_V1(0) } },                     \
+            { /* =>      */ { FP32_QNAN(0),     FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0), FP32_QNAN_V1(0) } },                     \
+              /*mxcsr:in */ 0,                                                                                                                                                \
+              /*128:out  */ 0,                                                                                                                                                \
+              /*256:out  */ 0,                                                                                                                                                \
+              /*xcpt?    */ false, false },                                                                                                                                   \
+          { { /*src2     */ { FP32_QNAN_V1(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0) } },                      \
+            { /*src1     */ { FP32_QNAN_V2(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0), FP32_QNAN_V1(0) } },                      \
+            { /* =>      */ { FP32_QNAN_V2(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0), FP32_QNAN_V1(0) } },                      \
+              /*mxcsr:in */ 0,                                                                                                                                                \
+              /*128:out  */ 0,                                                                                                                                                \
+              /*256:out  */ 0,                                                                                                                                                \
+              /*xcpt?    */ false, false },                                                                                                                                   \
+                                                                                                                                                                              \
+    /* QNan, SNan (Unmasked). */                                                                                                                                              \
+          { { /*src2     */ { FP32_QNAN(0),      FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0) } },                    \
+            { /*src1     */ { FP32_SNAN(0),      FP32_SNAN_V2(0), FP32_SNAN_V6(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V4(0), FP32_SNAN_V1(0) } },                    \
+            { /* =>      */ { FP32_QNAN_V(0, 1), FP32_QNAN_V2(0), FP32_SNAN_V6(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V4(0), FP32_QNAN_V1(0) } },                    \
+              /*mxcsr:in */ 0,                                                                                                                                                \
+              /*128:out  */ X86_MXCSR_IE,                                                                                                                                     \
+              /*256:out  */ X86_MXCSR_IE,                                                                                                                                     \
+              /*xcpt?    */ true, true },                                                                                                                                     \
+          { { /*src2     */ { FP32_QNAN_MAX(0),  FP32_QNAN_MAX(0), FP32_QNAN_V0(0),  FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \
+            { /*src1     */ { FP32_SNAN(0),      FP32_SNAN(0),     FP32_SNAN_MAX(0), FP32_SNAN_V2(0), FP32_SNAN_V6(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V4(0) } }, \
+            { /* =>      */ { FP32_QNAN_V(0, 1), FP32_SNAN(0),     FP32_SNAN_MAX(0), FP32_SNAN_V2(0), FP32_SNAN_V6(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V4(0) } }, \
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,                                                                                                 \
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,                                                                                  \
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,                                                                                  \
+              /*xcpt?    */ true, true },                                                                                                                                     \
+          { { /*src2     */ { FP32_QNAN_V1(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0),  FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } },   \
+            { /*src1     */ { FP32_SNAN_V2(0), FP32_QNAN(0),     FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } },   \
+            { /* =>      */ { FP32_SNAN_V2(0), FP32_QNAN(0),     FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } },   \
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,                                                                                                                 \
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,                                                                                                  \
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,                                                                                                  \
+              /*xcpt?    */ true, true },                                                                                                                                     \
+    /* SNan, QNan (Unmasked). */                                                                                                                                              \
+          { { /*src2     */ { FP32_SNAN(0), FP32_SNAN(0),     FP32_SNAN_V1(0), FP32_SNAN_V1(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V5(0), FP32_SNAN_V6(0) } },       \
+            { /*src1     */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } },       \
+            { /* =>      */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } },       \
+              /*mxcsr:in */ X86_MXCSR_DAZ,                                                                                                                                    \
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_IE,                                                                                                                     \
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_IE,                                                                                                                     \
+              /*xcpt?    */ true, true },                                                                                                                                     \
+          { { /*src2     */ { FP32_SNAN_MAX(0), FP32_SNAN_MAX(0), FP32_SNAN_V1(0), FP32_SNAN_V1(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V5(0), FP32_SNAN_V6(0) } },   \
+            { /*src1     */ { FP32_QNAN(0),     FP32_QNAN(0),     FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } },   \
+            { /* =>      */ { FP32_QNAN(0),     FP32_QNAN(0),     FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } },   \
+              /*mxcsr:in */ X86_MXCSR_RC_UP,                                                                                                                                  \
+              /*128:out  */ X86_MXCSR_RC_UP | X86_MXCSR_IE,                                                                                                                   \
+              /*256:out  */ X86_MXCSR_RC_UP | X86_MXCSR_IE,                                                                                                                   \
+              /*xcpt?    */ true, true },                                                                                                                                     \
+          { { /*src2     */ { FP32_SNAN_V0(0), FP32_SNAN_MAX(0), FP32_SNAN_V1(0), FP32_SNAN_V1(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V5(0), FP32_SNAN_V6(0) } },    \
+            { /*src1     */ { FP32_QNAN_V6(0), FP32_QNAN(0),     FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } },    \
+            { /* =>      */ { FP32_QNAN_V6(0), FP32_QNAN(0),     FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } },    \
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,                                                                                                                 \
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,                                                                                                  \
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,                                                                                                  \
+              /*xcpt?    */ true, true },                                                                                                                                     \
+    /* SNan, SNan (Unmasked). */                                                                                                                                              \
+    /*24*/{ { /*src2     */ { FP32_SNAN(0),      FP32_SNAN(0),     FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V7(0), FP32_SNAN_V1(0), FP32_SNAN_V6(0), FP32_SNAN_V1(0) } },  \
+            { /*src1     */ { FP32_SNAN(0),      FP32_SNAN_MAX(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } },  \
+            { /* =>      */ { FP32_QNAN_V(0, 1), FP32_SNAN_MAX(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } },  \
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ,                                                                                                                     \
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE,                                                                                                      \
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE,                                                                                                      \
+              /*xcpt?    */ true, true },                                                                                                                                     \
+          { { /*src2     */ { FP32_SNAN(0),     FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V7(0), FP32_SNAN_V1(0), FP32_SNAN_V6(0), FP32_SNAN_V1(0) } },    \
+            { /*src1     */ { FP32_SNAN_MAX(0), FP32_SNAN_V0(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } },    \
+            { /* =>      */ { FP32_SNAN_MAX(0), FP32_SNAN_V0(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } },    \
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,                                                                                                                                \
+              /*128:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE,                                                                                                                 \
+              /*256:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE,                                                                                                                 \
+              /*xcpt?    */ true, true },                                                                                                                                     \
+          { { /*src2     */ { FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V7(0), FP32_SNAN_V1(0), FP32_SNAN_V6(0), FP32_SNAN_V1(0) } },     \
+            { /*src1     */ { FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V0(0) } },     \
+            { /* =>      */ { FP32_QNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V0(0) } },     \
+              /*mxcsr:in */ 0,                                                                                                                                                \
+              /*128:out  */ X86_MXCSR_IE,                                                                                                                                     \
+              /*256:out  */ X86_MXCSR_IE,                                                                                                                                     \
+              /*xcpt?    */ true, true },                                                                                                                                     \
+    /* QNan, Norm FP (Unmasked). */                                                                                                                                           \
+          { { /*src2     */ { FP32_QNAN(0), FP32_QNAN_MAX(1), FP32_NORM_V0(1), FP32_QNAN_V1(0), FP32_NORM_V3(0), FP32_QNAN_V3(1), FP32_NORM_V5(0), FP32_QNAN_V5(1) } },       \
+            { /*src1     */ { FP32_1(0),    FP32_1(1),        FP32_QNAN_V0(1), FP32_NORM_V2(1), FP32_QNAN_V2(0), FP32_NORM_V4(0), FP32_QNAN_V4(1), FP32_NORM_V6(1) } },       \
+            { /* =>      */ { FP32_QNAN(0), FP32_1(1),        FP32_QNAN_V0(1), FP32_NORM_V2(1), FP32_QNAN_V2(0), FP32_NORM_V4(0), FP32_QNAN_V4(1), FP32_NORM_V6(1) } },       \
+              /*mxcsr:in */ X86_MXCSR_FZ,                                                                                                                                     \
+              /*128:out  */ X86_MXCSR_FZ,                                                                                                                                     \
+              /*256:out  */ X86_MXCSR_FZ,                                                                                                                                     \
+              /*xcpt?    */ false, false },                                                                                                                                   \
+    /* SNan, Norm FP (Unmasked). */                                                                                                                                           \
+    /*28*/{ { /*src2     */ { FP32_SNAN(1),      FP32_SNAN_MAX(1), FP32_NORM_V0(1), FP32_SNAN_V1(0), FP32_NORM_V3(0), FP32_SNAN_V3(1), FP32_NORM_V5(0), FP32_SNAN_V5(1) } },  \
+            { /*src1     */ { FP32_1(0),         FP32_1(0),        FP32_SNAN_V0(1), FP32_NORM_V2(1), FP32_SNAN_V2(1), FP32_NORM_V4(0), FP32_SNAN_V4(1), FP32_NORM_V6(1) } },  \
+            { /* =>      */ { FP32_QNAN_V(1, 1), FP32_1(0),        FP32_SNAN_V0(1), FP32_NORM_V2(1), FP32_SNAN_V2(1), FP32_NORM_V4(0), FP32_SNAN_V4(1), FP32_NORM_V6(1) } },  \
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,                                                                                                 \
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,                                                                                  \
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,                                                                                  \
+              /*xcpt?    */ true, true },                                                                                                                                     \
 
 /**
@@ -1235,88 +1238,88 @@
  **/
 #define FP32_TABLE_D1_H_PS_INVALIDS \
-    /*0 */{ { /*src2     */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V0),       FP32_QNAN_V(0, FP32_FRAC_V1),       FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5) } }, \
-            { /*src1     */ { FP32_QNAN(0),                       FP32_QNAN(0),                       FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, \
-            { /* =>      */ { FP32_QNAN(0),                       FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0),       FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3) } }, \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                                                                                                                                          \
-              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                                                                                                                                                          \
-              /*256:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                                                                                                                                                          \
-              /*xcpt?    */ false, false },                                                                                                                                                                                                                                                               \
-          { { /*src2     */ { FP32_QNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1),       FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5) } },                       \
-            { /*src1     */ { FP32_QNAN(0), FP32_SNAN(0),                       FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V2),       FP32_QNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },                       \
-            { /* =>      */ { FP32_QNAN(0), FP32_QNAN(0),                       FP32_QNAN(0),                       FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V4) } },                       \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                                                                                                                                          \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                                                                                                                           \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                                                                                                                           \
-              /*xcpt?    */ false, false },                                                                                                                                                                                                                                                               \
-          { { /*src2     */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1),       FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V6) } },             \
-            { /*src1     */ { FP32_SNAN(0),                       FP32_QNAN(0),                 FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },             \
-            { /* =>      */ { FP32_QNAN_V(0, 1),                  FP32_QNAN_V(0, 1),            FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5) } },             \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                                                                                                                                          \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                                                                                                                           \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                                                                                                                           \
-              /*xcpt?    */ false, false },                                                                                                                                                                                                                                                               \
-          { { /*src2     */ { FP32_SNAN(0),      FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },                  \
-            { /*src1     */ { FP32_SNAN(0),      FP32_SNAN(0),                       FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },                  \
-            { /* =>      */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1),                  FP32_QNAN_V(0, 1),                  FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V7), FP32_QNAN_V(0, FP32_FRAC_V6) } },                  \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                                                                                                                                          \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                                                                                                                           \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                                                                                                                           \
-              /*xcpt?    */ false, false },                                                                                                                                                                                                                                                               \
-          { { /*src2     */ { FP32_QNAN(0), FP32_NORM_V1(0),                    FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1),       FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(1),              FP32_QNAN_V(0, FP32_FRAC_V5), FP32_NORM_V5(1)              } },                       \
-            { /*src1     */ { FP32_QNAN(0), FP32_1(1),                          FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V2(1),                    FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0),              FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1)              } },                       \
-            { /* =>      */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN(0),                       FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V5) } },                       \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                                                                                                                                          \
-              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                                                                                                                                                          \
-              /*256:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                                                                                                                                                          \
-              /*xcpt?    */ false, false },                                                                                                                                                                                                                                                               \
-          { { /*src2     */ { FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_1(0),                          FP32_SNAN_V(0, FP32_FRAC_V1),       FP32_NORM_V3(0),              FP32_SNAN_V(0, FP32_FRAC_V0), FP32_NORM_V3(1),              FP32_SNAN_V(0, FP32_FRAC_V6), FP32_NORM_V7(1)              } },       \
-            { /*src1     */ { FP32_SNAN(0),                       FP32_1(1),                          FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_NORM_V2(1),              FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0),              FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1)              } },       \
-            { /* =>      */ { FP32_QNAN_V(0, 1),                  FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V6) } },       \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                                                                                                                                          \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                                                                                                                           \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                                                                                                                           \
-              /*xcpt?    */ false, false },                                                                                                                                                                                                                                                               \
-          { { /*src2     */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V0),       FP32_QNAN_V(0, FP32_FRAC_V1),       FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5) } }, \
-            { /*src1     */ { FP32_QNAN(0),                       FP32_QNAN(0),                       FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, \
-            { /* =>      */ { FP32_QNAN(0),                       FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0),       FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3) } }, \
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,                                                                                                                                                                                                                             \
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,                                                                                                                                                                                                                             \
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,                                                                                                                                                                                                                             \
-              /*xcpt?    */ false, false },                                                                                                                                                                                                                                                               \
-          { { /*src2     */ { FP32_QNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1),       FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5) } },                       \
-            { /*src1     */ { FP32_QNAN(0), FP32_SNAN(0),                       FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V2),       FP32_QNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } },                       \
-            { /* =>      */ { FP32_QNAN(0), FP32_QNAN(0),                       FP32_QNAN(0),                       FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V4) } },                       \
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,                                                                                                                                                                                                                                              \
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,                                                                                                                                                                                                                               \
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,                                                                                                                                                                                                                               \
-              /*xcpt?    */ true, true },                                                                                                                                                                                                                                                                 \
-          { { /*src2     */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1),       FP32_QNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V6) } },             \
-            { /*src1     */ { FP32_SNAN(0),                       FP32_QNAN(0),                 FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },             \
-            { /* =>      */ { FP32_QNAN_V(0, 1),                  FP32_QNAN_V(0, 1),            FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V5) } },             \
-              /*mxcsr:in */ 0,                                                                                                                                                                                                                                                                            \
-              /*128:out  */ X86_MXCSR_IE,                                                                                                                                                                                                                                                                 \
-              /*256:out  */ X86_MXCSR_IE,                                                                                                                                                                                                                                                                 \
-              /*xcpt?    */ true, true },                                                                                                                                                                                                                                                                 \
-          { { /*src2     */ { FP32_SNAN(0),      FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },                  \
-            { /*src1     */ { FP32_SNAN(0),      FP32_SNAN(0),                       FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },                  \
-            { /* =>      */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1),                  FP32_QNAN_V(0, 1),                  FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V7), FP32_QNAN_V(0, FP32_FRAC_V6) } },                  \
-              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,                                                                                                                                                                                                                                               \
-              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,                                                                                                                                                                                                                                \
-              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,                                                                                                                                                                                                                                \
-              /*xcpt?    */ true, true },                                                                                                                                                                                                                                                                 \
-          { { /*src2     */ { FP32_QNAN(0), FP32_NORM_V1(0),                    FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1),       FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(1),              FP32_QNAN_V(0, FP32_FRAC_V5), FP32_NORM_V5(1)              } },                       \
-            { /*src1     */ { FP32_QNAN(0), FP32_1(1),                          FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V2(1),                    FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0),              FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1)              } },                       \
-            { /* =>      */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN(0),                       FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V5) } },                       \
-              /*mxcsr:in */ 0,                                                                                                                                                                                                                                                                            \
-              /*128:out  */ 0,                                                                                                                                                                                                                                                                            \
-              /*256:out  */ 0,                                                                                                                                                                                                                                                                            \
-              /*xcpt?    */ false, false },                                                                                                                                                                                                                                                               \
-          { { /*src2     */ { FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_1(0),                          FP32_SNAN_V(0, FP32_FRAC_V1),       FP32_NORM_V3(0),              FP32_SNAN_V(0, FP32_FRAC_V0), FP32_NORM_V3(1),              FP32_SNAN_V(0, FP32_FRAC_V6), FP32_NORM_V7(1)              } },       \
-            { /*src1     */ { FP32_SNAN(0),                       FP32_1(1),                          FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_NORM_V2(1),              FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0),              FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1)              } },       \
-            { /* =>      */ { FP32_QNAN_V(0, 1),                  FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(1, FP32_FRAC_V2), FP32_QNAN_V(1, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V0), FP32_QNAN_V(0, FP32_FRAC_V6) } },       \
-              /*mxcsr:in */ X86_MXCSR_RC_UP,                                                                                                                                                                                                                                                              \
-              /*128:out  */ X86_MXCSR_RC_UP | X86_MXCSR_IE,                                                                                                                                                                                                                                               \
-              /*256:out  */ X86_MXCSR_RC_UP | X86_MXCSR_IE,                                                                                                                                                                                                                                               \
-              /*xcpt?    */ true, true },                                                                                                                                                                                                                                                                 \
+    /*0 */{ { /*src2     */ { FP32_QNAN_MAX(0), FP32_QNAN(0), FP32_QNAN_V0(0),  FP32_QNAN_V1(0),  FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V3(0), FP32_QNAN_V5(0) } },        \
+            { /*src1     */ { FP32_QNAN(0),     FP32_QNAN(0), FP32_QNAN(0),     FP32_QNAN_MAX(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } },        \
+            { /* =>      */ { FP32_QNAN(0),     FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0),  FP32_QNAN_V6(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0) } },        \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                 \
+              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                                 \
+              /*256:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                                 \
+              /*xcpt?    */ false, false },                                                                                                                                      \
+          { { /*src2     */ { FP32_QNAN(0), FP32_SNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V1(0),  FP32_QNAN_V2(0), FP32_SNAN_V3(0), FP32_QNAN_V4(0), FP32_SNAN_V5(0) } },            \
+            { /*src1     */ { FP32_QNAN(0), FP32_SNAN(0), FP32_QNAN(0),     FP32_SNAN_V2(0),  FP32_QNAN_V6(0), FP32_SNAN_V2(0), FP32_QNAN_V1(0), FP32_SNAN_V4(0) } },            \
+            { /* =>      */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN(0),     FP32_QNAN_MAX(0), FP32_QNAN_V6(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V4(0) } },            \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                 \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                  \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                  \
+              /*xcpt?    */ false, false },                                                                                                                                      \
+          { { /*src2     */ { FP32_SNAN_MAX(0),  FP32_QNAN_V2(0),   FP32_SNAN_V1(0),  FP32_QNAN_V2(0), FP32_SNAN_V3(0), FP32_QNAN_V4(0), FP32_SNAN_V5(0), FP32_QNAN_V6(0) } },   \
+            { /*src1     */ { FP32_SNAN(0),      FP32_QNAN(0),      FP32_SNAN(0),     FP32_QNAN_V5(0), FP32_SNAN_V4(0), FP32_QNAN_V3(0), FP32_SNAN_V2(0), FP32_QNAN_V1(0) } },   \
+            { /* =>      */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_MAX(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V5(0) } },   \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                 \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                  \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                  \
+              /*xcpt?    */ false, false },                                                                                                                                      \
+          { { /*src2     */ { FP32_SNAN(0),      FP32_SNAN_MAX(0),  FP32_SNAN_MAX(0),  FP32_SNAN(0),     FP32_SNAN_V7(0), FP32_SNAN_V1(0), FP32_SNAN_V6(0), FP32_SNAN_V1(0) } }, \
+            { /*src1     */ { FP32_SNAN(0),      FP32_SNAN(0),      FP32_SNAN(0),      FP32_SNAN_MAX(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } }, \
+            { /* =>      */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_MAX(0), FP32_QNAN_V5(0), FP32_QNAN_V1(0), FP32_QNAN_V7(0), FP32_QNAN_V6(0) } }, \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                 \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                  \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                  \
+              /*xcpt?    */ false, false },                                                                                                                                      \
+          { { /*src2     */ { FP32_QNAN(0), FP32_NORM_V1(0),  FP32_QNAN_MAX(0), FP32_QNAN_V1(0),  FP32_QNAN_V1(0), FP32_NORM_V3(1), FP32_QNAN_V5(0), FP32_NORM_V5(1) } },        \
+            { /*src1     */ { FP32_QNAN(0), FP32_1(1),        FP32_QNAN_MAX(1), FP32_NORM_V2(1),  FP32_QNAN_V2(0), FP32_NORM_V4(0), FP32_QNAN_V4(1), FP32_NORM_V6(1) } },        \
+            { /* =>      */ { FP32_QNAN(0), FP32_QNAN_MAX(1), FP32_QNAN(0),     FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V4(1), FP32_QNAN_V1(0), FP32_QNAN_V5(0) } },        \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                 \
+              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                                 \
+              /*256:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                                 \
+              /*xcpt?    */ false, false },                                                                                                                                      \
+          { { /*src2     */ { FP32_SNAN_MAX(1),  FP32_1(0),        FP32_SNAN_V1(0),  FP32_NORM_V3(0), FP32_SNAN_V0(0), FP32_NORM_V3(1), FP32_SNAN_V6(0), FP32_NORM_V7(1) } },    \
+            { /*src1     */ { FP32_SNAN(0),      FP32_1(1),        FP32_SNAN_MAX(0), FP32_NORM_V2(1), FP32_SNAN_V2(1), FP32_NORM_V4(0), FP32_SNAN_V4(1), FP32_NORM_V6(1) } },    \
+            { /* =>      */ { FP32_QNAN_V(0, 1), FP32_QNAN_MAX(0), FP32_QNAN_MAX(1), FP32_QNAN_V1(0), FP32_QNAN_V2(1), FP32_QNAN_V4(1), FP32_QNAN_V0(0), FP32_QNAN_V6(0) } },    \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                 \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                  \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                  \
+              /*xcpt?    */ false, false },                                                                                                                                      \
+          { { /*src2     */ { FP32_QNAN_MAX(0), FP32_QNAN(0), FP32_QNAN_V0(0),  FP32_QNAN_V1(0),  FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V3(0), FP32_QNAN_V5(0) } },        \
+            { /*src1     */ { FP32_QNAN(0),     FP32_QNAN(0), FP32_QNAN(0),     FP32_QNAN_MAX(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } },        \
+            { /* =>      */ { FP32_QNAN(0),     FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0),  FP32_QNAN_V6(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0) } },        \
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,                                                                                                    \
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,                                                                                                    \
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,                                                                                                    \
+              /*xcpt?    */ false, false },                                                                                                                                      \
+          { { /*src2     */ { FP32_QNAN(0), FP32_SNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V1(0),  FP32_QNAN_V2(0), FP32_SNAN_V3(0), FP32_QNAN_V4(0), FP32_SNAN_V5(0) } },            \
+            { /*src1     */ { FP32_QNAN(0), FP32_SNAN(0), FP32_QNAN(0),     FP32_SNAN_V2(0),  FP32_QNAN_V6(0), FP32_SNAN_V2(0), FP32_QNAN_V1(0), FP32_SNAN_V4(0) } },            \
+            { /* =>      */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN(0),     FP32_QNAN_MAX(0), FP32_QNAN_V6(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V4(0) } },            \
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,                                                                                                                     \
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,                                                                                                      \
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,                                                                                                      \
+              /*xcpt?    */ true, true },                                                                                                                                        \
+          { { /*src2     */ { FP32_SNAN_MAX(0),  FP32_QNAN_V2(0),   FP32_SNAN_V1(0),  FP32_QNAN_V2(0), FP32_SNAN_V3(0), FP32_QNAN_V4(0), FP32_SNAN_V5(0), FP32_QNAN_V6(0) } },   \
+            { /*src1     */ { FP32_SNAN(0),      FP32_QNAN(0),      FP32_SNAN(0),     FP32_QNAN_V5(0), FP32_SNAN_V4(0), FP32_QNAN_V3(0), FP32_SNAN_V2(0), FP32_QNAN_V1(0) } },   \
+            { /* =>      */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_MAX(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V5(0) } },   \
+              /*mxcsr:in */ 0,                                                                                                                                                   \
+              /*128:out  */ X86_MXCSR_IE,                                                                                                                                        \
+              /*256:out  */ X86_MXCSR_IE,                                                                                                                                        \
+              /*xcpt?    */ true, true },                                                                                                                                        \
+          { { /*src2     */ { FP32_SNAN(0),      FP32_SNAN_MAX(0),  FP32_SNAN_MAX(0),  FP32_SNAN(0),     FP32_SNAN_V7(0), FP32_SNAN_V1(0), FP32_SNAN_V6(0), FP32_SNAN_V1(0) } }, \
+            { /*src1     */ { FP32_SNAN(0),      FP32_SNAN(0),      FP32_SNAN(0),      FP32_SNAN_MAX(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } }, \
+            { /* =>      */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_MAX(0), FP32_QNAN_V5(0), FP32_QNAN_V1(0), FP32_QNAN_V7(0), FP32_QNAN_V6(0) } }, \
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,                                                                                                                      \
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,                                                                                                       \
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,                                                                                                       \
+              /*xcpt?    */ true, true },                                                                                                                                        \
+          { { /*src2     */ { FP32_QNAN(0), FP32_NORM_V1(0),  FP32_QNAN_MAX(0), FP32_QNAN_V1(0),  FP32_QNAN_V1(0), FP32_NORM_V3(1), FP32_QNAN_V5(0), FP32_NORM_V5(1) } },        \
+            { /*src1     */ { FP32_QNAN(0), FP32_1(1),        FP32_QNAN_MAX(1), FP32_NORM_V2(1),  FP32_QNAN_V2(0), FP32_NORM_V4(0), FP32_QNAN_V4(1), FP32_NORM_V6(1) } },        \
+            { /* =>      */ { FP32_QNAN(0), FP32_QNAN_MAX(1), FP32_QNAN(0),     FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V4(1), FP32_QNAN_V1(0), FP32_QNAN_V5(0) } },        \
+              /*mxcsr:in */ 0,                                                                                                                                                   \
+              /*128:out  */ 0,                                                                                                                                                   \
+              /*256:out  */ 0,                                                                                                                                                   \
+              /*xcpt?    */ false, false },                                                                                                                                      \
+          { { /*src2     */ { FP32_SNAN_MAX(1),  FP32_1(0),        FP32_SNAN_V1(0),  FP32_NORM_V3(0), FP32_SNAN_V0(0), FP32_NORM_V3(1), FP32_SNAN_V6(0), FP32_NORM_V7(1) } },    \
+            { /*src1     */ { FP32_SNAN(0),      FP32_1(1),        FP32_SNAN_MAX(0), FP32_NORM_V2(1), FP32_SNAN_V2(1), FP32_NORM_V4(0), FP32_SNAN_V4(1), FP32_NORM_V6(1) } },    \
+            { /* =>      */ { FP32_QNAN_V(0, 1), FP32_QNAN_MAX(0), FP32_QNAN_MAX(1), FP32_QNAN_V1(0), FP32_QNAN_V2(1), FP32_QNAN_V4(1), FP32_QNAN_V0(0), FP32_QNAN_V6(0) } },    \
+              /*mxcsr:in */ X86_MXCSR_RC_UP,                                                                                                                                     \
+              /*128:out  */ X86_MXCSR_RC_UP | X86_MXCSR_IE,                                                                                                                      \
+              /*256:out  */ X86_MXCSR_RC_UP | X86_MXCSR_IE,                                                                                                                      \
+              /*xcpt?    */ true, true },                                                                                                                                        \
 
 /**
@@ -1415,74 +1418,74 @@
  **/
 #define FP32_TABLE_D9_PS_INVALIDS \
-    /*0 */{ { /*src2     */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0),       FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, \
-            { /*src1     */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, \
-            { /* =>      */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0),       FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                                                                                                              \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                                                                                               \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                                                                                               \
-              /*xcpt?    */ false, false },                                                                                                                                                                                                                                   \
-          { { /*src2     */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0),       FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, \
-            { /*src1     */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, \
-            { /* =>      */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0),       FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                                                                                                              \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                                                                                               \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                                                                                               \
-              /*xcpt?    */ false, false },                                                                                                                                                                                                                                   \
-          { { /*src2     */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },       \
-            { /*src1     */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },       \
-            { /* =>      */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },       \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,                                                                                                                                                                                                               \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,                                                                                                                                                                                                \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,                                                                                                                                                                                                \
-              /*xcpt?    */ false, false },                                                                                                                                                                                                                                   \
-          { { /*src2     */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },       \
-            { /*src1     */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },       \
-            { /* =>      */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },       \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                                                                                                              \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                                                                                               \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                                                                                               \
-              /*xcpt?    */ false, false },                                                                                                                                                                                                                                   \
-          { { /*src2     */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1),              FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0),              FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0),              FP32_QNAN_V(1, FP32_FRAC_V5) } },       \
-            { /*src1     */ { FP32_1(0),    FP32_1(1),                          FP32_QNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1),              FP32_QNAN_V(0, FP32_FRAC_V2), FP32_NORM_V4(0),              FP32_QNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1)              } },       \
-            { /* =>      */ { FP32_QNAN(0), FP32_QNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1),              FP32_QNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0),              FP32_QNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0),              FP32_QNAN_V(1, FP32_FRAC_V5) } },       \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                                                                                                              \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                                                                                               \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                                                                                               \
-              /*xcpt?    */ false, false },                                                                                                                                                                                                                                   \
-          { { /*src2     */ { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1),              FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0),              FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0),              FP32_SNAN_V(1, FP32_FRAC_V5) } },       \
-            { /*src1     */ { FP32_1(0),    FP32_1(0),                          FP32_SNAN_V(1, FP32_FRAC_V0), FP32_NORM_V2(1),              FP32_SNAN_V(1, FP32_FRAC_V2), FP32_NORM_V4(0),              FP32_SNAN_V(1, FP32_FRAC_V4), FP32_NORM_V6(1)              } },       \
-            { /* =>      */ { FP32_SNAN(1), FP32_SNAN_V(1, FP32_FRAC_NORM_MAX), FP32_NORM_V0(1),              FP32_SNAN_V(0, FP32_FRAC_V1), FP32_NORM_V3(0),              FP32_SNAN_V(1, FP32_FRAC_V3), FP32_NORM_V5(0),              FP32_SNAN_V(1, FP32_FRAC_V5) } },       \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                                                                                                              \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                                                                                               \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                                                                                               \
-              /*xcpt?    */ false, false },                                                                                                                                                                                                                                   \
-          { { /*src2     */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0),       FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, \
-            { /*src1     */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V4) } }, \
-            { /* =>      */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0),       FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, \
-              /*mxcsr:in */ 0,                                                                                                                                                                                                                                                \
-              /*128:out  */ X86_MXCSR_IE,                                                                                                                                                                                                                                     \
-              /*256:out  */ X86_MXCSR_IE,                                                                                                                                                                                                                                     \
-              /*xcpt?    */ true, true },                                                                                                                                                                                                                                     \
-          { { /*src2     */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0),       FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, \
-            { /*src1     */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V4) } }, \
-            { /* =>      */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V0),       FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V5) } }, \
-              /*mxcsr:in */ 0,                                                                                                                                                                                                                                                \
-              /*128:out  */ X86_MXCSR_IE,                                                                                                                                                                                                                                     \
-              /*256:out  */ X86_MXCSR_IE,                                                                                                                                                                                                                                     \
-              /*xcpt?    */ true, true },                                                                                                                                                                                                                                     \
-          { { /*src2     */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },       \
-            { /*src1     */ { FP32_QNAN(0), FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_QNAN_V(0, FP32_FRAC_V6), FP32_QNAN_V(0, FP32_FRAC_V5), FP32_QNAN_V(0, FP32_FRAC_V4), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_QNAN_V(0, FP32_FRAC_V2), FP32_QNAN_V(0, FP32_FRAC_V1) } },       \
-            { /* =>      */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V1), FP32_QNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V6) } },       \
-              /*mxcsr:in */ 0,                                                                                                                                                                                                                                                \
-              /*128:out  */ X86_MXCSR_IE,                                                                                                                                                                                                                                     \
-              /*256:out  */ X86_MXCSR_IE,                                                                                                                                                                                                                                     \
-              /*xcpt?    */ true, true },                                                                                                                                                                                                                                     \
-          { { /*src2     */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },       \
-            { /*src1     */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_SNAN_V(0, FP32_FRAC_V4), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V5), FP32_SNAN_V(0, FP32_FRAC_V3), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2) } },       \
-            { /* =>      */ { FP32_SNAN(0), FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V2), FP32_SNAN_V(0, FP32_FRAC_V7), FP32_SNAN_V(0, FP32_FRAC_V1), FP32_SNAN_V(0, FP32_FRAC_V6), FP32_SNAN_V(0, FP32_FRAC_V1) } },       \
-              /*mxcsr:in */ 0,                                                                                                                                                                                                                                                \
-              /*128:out  */ X86_MXCSR_IE,                                                                                                                                                                                                                                     \
-              /*256:out  */ X86_MXCSR_IE,                                                                                                                                                                                                                                     \
-              /*xcpt?    */ true, true },                                                                                                                                                                                                                                     \
+    /*0 */{ { /*src2     */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0),  FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \
+            { /*src1     */ { FP32_QNAN(0), FP32_QNAN(0),     FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } }, \
+            { /* =>      */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0),  FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                         \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                          \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                          \
+              /*xcpt?    */ false, false },                                                                                                                              \
+          { { /*src2     */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0),  FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \
+            { /*src1     */ { FP32_SNAN(0), FP32_SNAN(0),     FP32_SNAN_MAX(0), FP32_SNAN_V2(0), FP32_SNAN_V6(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V4(0) } }, \
+            { /* =>      */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0),  FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                         \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                          \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                          \
+              /*xcpt?    */ false, false },                                                                                                                              \
+          { { /*src2     */ { FP32_SNAN(0), FP32_SNAN(0),     FP32_SNAN_V1(0), FP32_SNAN_V1(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V5(0), FP32_SNAN_V6(0) } },  \
+            { /*src1     */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } },  \
+            { /* =>      */ { FP32_SNAN(0), FP32_SNAN(0),     FP32_SNAN_V1(0), FP32_SNAN_V1(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V5(0), FP32_SNAN_V6(0) } },  \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,                                                                                                          \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,                                                                                           \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,                                                                                           \
+              /*xcpt?    */ false, false },                                                                                                                              \
+          { { /*src2     */ { FP32_SNAN(0), FP32_SNAN(0),     FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V7(0), FP32_SNAN_V1(0), FP32_SNAN_V6(0), FP32_SNAN_V1(0) } },  \
+            { /*src1     */ { FP32_SNAN(0), FP32_SNAN_MAX(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } },  \
+            { /* =>      */ { FP32_SNAN(0), FP32_SNAN(0),     FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V7(0), FP32_SNAN_V1(0), FP32_SNAN_V6(0), FP32_SNAN_V1(0) } },  \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                         \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                          \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                          \
+              /*xcpt?    */ false, false },                                                                                                                              \
+          { { /*src2     */ { FP32_QNAN(0), FP32_QNAN_MAX(1), FP32_NORM_V0(1), FP32_QNAN_V1(0), FP32_NORM_V3(0), FP32_QNAN_V3(1), FP32_NORM_V5(0), FP32_QNAN_V5(1) } },  \
+            { /*src1     */ { FP32_1(0),    FP32_1(1),        FP32_QNAN_V0(1), FP32_NORM_V2(1), FP32_QNAN_V2(0), FP32_NORM_V4(0), FP32_QNAN_V4(1), FP32_NORM_V6(1) } },  \
+            { /* =>      */ { FP32_QNAN(0), FP32_QNAN_MAX(1), FP32_NORM_V0(1), FP32_QNAN_V1(0), FP32_NORM_V3(0), FP32_QNAN_V3(1), FP32_NORM_V5(0), FP32_QNAN_V5(1) } },  \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                         \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                          \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                          \
+              /*xcpt?    */ false, false },                                                                                                                              \
+          { { /*src2     */ { FP32_SNAN(1), FP32_SNAN_MAX(1), FP32_NORM_V0(1), FP32_SNAN_V1(0), FP32_NORM_V3(0), FP32_SNAN_V3(1), FP32_NORM_V5(0), FP32_SNAN_V5(1) } },  \
+            { /*src1     */ { FP32_1(0),    FP32_1(0),        FP32_SNAN_V0(1), FP32_NORM_V2(1), FP32_SNAN_V2(1), FP32_NORM_V4(0), FP32_SNAN_V4(1), FP32_NORM_V6(1) } },  \
+            { /* =>      */ { FP32_SNAN(1), FP32_SNAN_MAX(1), FP32_NORM_V0(1), FP32_SNAN_V1(0), FP32_NORM_V3(0), FP32_SNAN_V3(1), FP32_NORM_V5(0), FP32_SNAN_V5(1) } },  \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                         \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                          \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                          \
+              /*xcpt?    */ false, false },                                                                                                                              \
+          { { /*src2     */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0),  FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \
+            { /*src1     */ { FP32_QNAN(0), FP32_QNAN(0),     FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } }, \
+            { /* =>      */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0),  FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \
+              /*mxcsr:in */ 0,                                                                                                                                           \
+              /*128:out  */ X86_MXCSR_IE,                                                                                                                                \
+              /*256:out  */ X86_MXCSR_IE,                                                                                                                                \
+              /*xcpt?    */ true, true },                                                                                                                                \
+          { { /*src2     */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0),  FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \
+            { /*src1     */ { FP32_SNAN(0), FP32_SNAN(0),     FP32_SNAN_MAX(0), FP32_SNAN_V2(0), FP32_SNAN_V6(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V4(0) } }, \
+            { /* =>      */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0),  FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \
+              /*mxcsr:in */ 0,                                                                                                                                           \
+              /*128:out  */ X86_MXCSR_IE,                                                                                                                                \
+              /*256:out  */ X86_MXCSR_IE,                                                                                                                                \
+              /*xcpt?    */ true, true },                                                                                                                                \
+          { { /*src2     */ { FP32_SNAN(0), FP32_SNAN(0),     FP32_SNAN_V1(0), FP32_SNAN_V1(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V5(0), FP32_SNAN_V6(0) } },  \
+            { /*src1     */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } },  \
+            { /* =>      */ { FP32_SNAN(0), FP32_SNAN(0),     FP32_SNAN_V1(0), FP32_SNAN_V1(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V5(0), FP32_SNAN_V6(0) } },  \
+              /*mxcsr:in */ 0,                                                                                                                                           \
+              /*128:out  */ X86_MXCSR_IE,                                                                                                                                \
+              /*256:out  */ X86_MXCSR_IE,                                                                                                                                \
+              /*xcpt?    */ true, true },                                                                                                                                \
+          { { /*src2     */ { FP32_SNAN(0), FP32_SNAN(0),     FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V7(0), FP32_SNAN_V1(0), FP32_SNAN_V6(0), FP32_SNAN_V1(0) } },  \
+            { /*src1     */ { FP32_SNAN(0), FP32_SNAN_MAX(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } },  \
+            { /* =>      */ { FP32_SNAN(0), FP32_SNAN(0),     FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V7(0), FP32_SNAN_V1(0), FP32_SNAN_V6(0), FP32_SNAN_V1(0) } },  \
+              /*mxcsr:in */ 0,                                                                                                                                           \
+              /*128:out  */ X86_MXCSR_IE,                                                                                                                                \
+              /*256:out  */ X86_MXCSR_IE,                                                                                                                                \
+              /*xcpt?    */ true, true },                                                                                                                                \
 
 /**
@@ -1567,212 +1570,212 @@
  **/
 #define FP32_TABLE_D9_SS_INVALIDS \
-    /* QNan, QNan (Masked). */                                                                                                                                                                                \
-    /*0 */{ { /*src2     */ { FP32_QNAN(0), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V2(0), FP32_RAND_V1(1), FP32_RAND_V7(0), FP32_RAND_V2(1) } },                                        \
-            { /*src1     */ { FP32_QNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V5(1), FP32_RAND_V6(1), FP32_RAND_V7(1), FP32_RAND_V1(1) } },                                        \
-            { /* =>      */ { FP32_QNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V5(1), FP32_RAND_V6(1), FP32_RAND_V7(1), FP32_RAND_V1(1) } },                                        \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                                              \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                               \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                               \
-              /*xcpt?    */ false, false },                                                                                                                                                                   \
-          { { /*src2     */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(0), FP32_RAND_V6(1) } },                  \
-            { /*src1     */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V1(0) } },                  \
-            { /* =>      */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V1(0) } },                  \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                                              \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                               \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                               \
-              /*xcpt?    */ false, false },                                                                                                                                                                   \
-          { { /*src2     */ { FP32_QNAN_V(0, FP32_FRAC_V0),       FP32_RAND_V0(1), FP32_RAND_V7(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } },                  \
-            { /*src1     */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_RAND_V1(0), FP32_RAND_V7(0), FP32_RAND_V2(1), FP32_RAND_V6(1), FP32_RAND_V3(1), FP32_RAND_V5(0), FP32_RAND_V4(1) } },                  \
-            { /* =>      */ { FP32_QNAN_V(0, FP32_FRAC_V0),       FP32_RAND_V1(0), FP32_RAND_V7(0), FP32_RAND_V2(1), FP32_RAND_V6(1), FP32_RAND_V3(1), FP32_RAND_V5(0), FP32_RAND_V4(1) } },                  \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                                              \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                               \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                               \
-              /*xcpt?    */ false, false },                                                                                                                                                                   \
-    /* QNan, SNan (Masked). */                                                                                                                                                                                \
-          { { /*src2     */ { FP32_QNAN(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V2(0), FP32_RAND_V2(1), FP32_RAND_V1(0), FP32_RAND_V0(1) } },                                        \
-            { /*src1     */ { FP32_SNAN(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },                                        \
-            { /* =>      */ { FP32_QNAN(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },                                        \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                                              \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                               \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                               \
-              /*xcpt?    */ false, false },                                                                                                                                                                   \
-          { { /*src2     */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V1(1), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(1) } },                  \
-            { /*src1     */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V3(0) } },                  \
-            { /* =>      */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V3(0) } },                  \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                                              \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                               \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                               \
-              /*xcpt?    */ false, false },                                                                                                                                                                   \
-          { { /*src2     */ { FP32_QNAN_V(0, FP32_FRAC_V0),       FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V1(1), FP32_RAND_V0(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(1) } },                  \
-            { /*src1     */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V1(0) } },                  \
-            { /* =>      */ { FP32_QNAN_V(0, FP32_FRAC_V0),       FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V1(0) } },                  \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                                              \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                               \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                               \
-              /*xcpt?    */ false, false },                                                                                                                                                                   \
-    /* SNan, QNan (Masked). */                                                                                                                                                                                \
-          { { /*src2     */ { FP32_SNAN(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V1(1), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(1) } },                                        \
-            { /*src1     */ { FP32_QNAN(0), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V3(0) } },                                        \
-            { /* =>      */ { FP32_SNAN(0), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V3(0) } },                                        \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,                                                                                                                                               \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,                                                                                                                                \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,                                                                                                                                \
-              /*xcpt?    */ false, false },                                                                                                                                                                   \
-          { { /*src2     */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V7(1) } },                  \
-            { /*src1     */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_RAND_V2(0), FP32_RAND_V4(0), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V2(0) } },                  \
-            { /* =>      */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_RAND_V2(0), FP32_RAND_V4(0), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V2(0) } },                  \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                                              \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                               \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                               \
-              /*xcpt?    */ false, false },                                                                                                                                                                   \
-          { { /*src2     */ { FP32_SNAN_V(0, FP32_FRAC_V1), FP32_RAND_V1(1), FP32_RAND_V7(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } },                        \
-            { /*src1     */ { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V0(1), FP32_RAND_V2(0), FP32_RAND_V3(1) } },                        \
-            { /* =>      */ { FP32_SNAN_V(0, FP32_FRAC_V1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V0(1), FP32_RAND_V2(0), FP32_RAND_V3(1) } },                        \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                                              \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                               \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                               \
-              /*xcpt?    */ false, false },                                                                                                                                                                   \
-    /* SNan, SNan (Masked). */                                                                                                                                                                                \
-          { { /*src2     */ { FP32_SNAN(0), FP32_RAND_V1(1), FP32_RAND_V7(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } },                                        \
-            { /*src1     */ { FP32_SNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V7(0) } },                                        \
-            { /* =>      */ { FP32_SNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V7(0) } },                                        \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                                              \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                               \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                               \
-              /*xcpt?    */ false, false },                                                                                                                                                                   \
-          { { /*src2     */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_RAND_V1(0), FP32_RAND_V7(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V1(1), FP32_RAND_V2(1) } },                  \
-            { /*src1     */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_RAND_V7(0), FP32_RAND_V5(0), FP32_RAND_V7(1), FP32_RAND_V6(1), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V2(1) } },                  \
-            { /* =>      */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_RAND_V7(0), FP32_RAND_V5(0), FP32_RAND_V7(1), FP32_RAND_V6(1), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V2(1) } },                  \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                                              \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                               \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                               \
-              /*xcpt?    */ false, false },                                                                                                                                                                   \
-          { { /*src2     */ { FP32_SNAN_V(0, FP32_FRAC_V1), FP32_RAND_V1(1), FP32_RAND_V6(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } },                        \
-            { /*src1     */ { FP32_SNAN_V(0, FP32_FRAC_V4), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V0(1) } },                        \
-            { /* =>      */ { FP32_SNAN_V(0, FP32_FRAC_V1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V0(1) } },                        \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                                              \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                               \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                               \
-              /*xcpt?    */ false, false },                                                                                                                                                                   \
-    /* QNan, Normal (Unmasked). */                                                                                                                                                                            \
-          { { /*src2     */ { FP32_QNAN(0), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } },                                        \
-            { /*src1     */ { FP32_1(0),    FP32_RAND_V2(1), FP32_RAND_V4(1), FP32_RAND_V6(1), FP32_RAND_V2(1), FP32_RAND_V7(0), FP32_RAND_V3(0), FP32_RAND_V4(1) } },                                        \
-            { /* =>      */ { FP32_QNAN(0), FP32_RAND_V2(1), FP32_RAND_V4(1), FP32_RAND_V6(1), FP32_RAND_V2(1), FP32_RAND_V7(0), FP32_RAND_V3(0), FP32_RAND_V4(1) } },                                        \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                                              \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                               \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                               \
-              /*xcpt?    */ false, false },                                                                                                                                                                   \
-    /* SNan, Normal (Masked). */                                                                                                                                                                              \
-          { { /*src2     */ { FP32_SNAN(1), FP32_RAND_V0(1), FP32_RAND_V2(1), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } },                                        \
-            { /*src1     */ { FP32_1(0),    FP32_RAND_V0(1), FP32_RAND_V1(1), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V6(0), FP32_RAND_V7(0), FP32_RAND_V1(1) } },                                        \
-            { /* =>      */ { FP32_SNAN(1), FP32_RAND_V0(1), FP32_RAND_V1(1), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V6(0), FP32_RAND_V7(0), FP32_RAND_V1(1) } },                                        \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                                              \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                               \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                                               \
-              /*xcpt?    */ false, false },                                                                                                                                                                   \
-    /* QNan, QNan (Unmasked). */                                                                                                                                                                              \
-    /*0 */{ { /*src2     */ { FP32_QNAN(0), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V2(0), FP32_RAND_V1(1), FP32_RAND_V7(0), FP32_RAND_V2(1) } },                                        \
-            { /*src1     */ { FP32_QNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V5(1), FP32_RAND_V6(1), FP32_RAND_V7(1), FP32_RAND_V1(1) } },                                        \
-            { /* =>      */ { FP32_QNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V5(1), FP32_RAND_V6(1), FP32_RAND_V7(1), FP32_RAND_V1(1) } },                                        \
-              /*mxcsr:in */ 0,                                                                                                                                                                                \
-              /*128:out  */ X86_MXCSR_IE,                                                                                                                                                                     \
-              /*256:out  */ X86_MXCSR_IE,                                                                                                                                                                     \
-              /*xcpt?    */ true, true },                                                                                                                                                                     \
-          { { /*src2     */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(0), FP32_RAND_V6(1) } },                  \
-            { /*src1     */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MIN), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V1(0) } },                  \
-            { /* =>      */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V1(0) } },                  \
-              /*mxcsr:in */ 0,                                                                                                                                                                                \
-              /*128:out  */ X86_MXCSR_IE,                                                                                                                                                                     \
-              /*256:out  */ X86_MXCSR_IE,                                                                                                                                                                     \
-              /*xcpt?    */ true, true },                                                                                                                                                                     \
-          { { /*src2     */ { FP32_QNAN_V(0, FP32_FRAC_V0),       FP32_RAND_V0(1), FP32_RAND_V7(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } },                  \
-            { /*src1     */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_RAND_V1(0), FP32_RAND_V7(0), FP32_RAND_V2(1), FP32_RAND_V6(1), FP32_RAND_V3(1), FP32_RAND_V5(0), FP32_RAND_V4(1) } },                  \
-            { /* =>      */ { FP32_QNAN_V(0, FP32_FRAC_V0),       FP32_RAND_V1(0), FP32_RAND_V7(0), FP32_RAND_V2(1), FP32_RAND_V6(1), FP32_RAND_V3(1), FP32_RAND_V5(0), FP32_RAND_V4(1) } },                  \
-              /*mxcsr:in */ 0,                                                                                                                                                                                \
-              /*128:out  */ X86_MXCSR_IE,                                                                                                                                                                     \
-              /*256:out  */ X86_MXCSR_IE,                                                                                                                                                                     \
-              /*xcpt?    */ true, true },                                                                                                                                                                     \
-    /* QNan, SNan (Unmasked). */                                                                                                                                                                              \
-          { { /*src2     */ { FP32_QNAN(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V2(0), FP32_RAND_V2(1), FP32_RAND_V1(0), FP32_RAND_V0(1) } },                                        \
-            { /*src1     */ { FP32_SNAN(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },                                        \
-            { /* =>      */ { FP32_QNAN(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },                                        \
-              /*mxcsr:in */ 0,                                                                                                                                                                                \
-              /*128:out  */ X86_MXCSR_IE,                                                                                                                                                                     \
-              /*256:out  */ X86_MXCSR_IE,                                                                                                                                                                     \
-              /*xcpt?    */ true, true },                                                                                                                                                                     \
-          { { /*src2     */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V1(1), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(1) } },                  \
-            { /*src1     */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V3(0) } },                  \
-            { /* =>      */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V3(0) } },                  \
-              /*mxcsr:in */ 0,                                                                                                                                                                                \
-              /*128:out  */ X86_MXCSR_IE,                                                                                                                                                                     \
-              /*256:out  */ X86_MXCSR_IE,                                                                                                                                                                     \
-              /*xcpt?    */ true, true },                                                                                                                                                                     \
-          { { /*src2     */ { FP32_QNAN_V(0, FP32_FRAC_V0),       FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V1(1), FP32_RAND_V0(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(1) } },                  \
-            { /*src1     */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V1(0) } },                  \
-            { /* =>      */ { FP32_QNAN_V(0, FP32_FRAC_V0),       FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V1(0) } },                  \
-              /*mxcsr:in */ 0,                                                                                                                                                                                \
-              /*128:out  */ X86_MXCSR_IE,                                                                                                                                                                     \
-              /*256:out  */ X86_MXCSR_IE,                                                                                                                                                                     \
-              /*xcpt?    */ true, true },                                                                                                                                                                     \
-    /* SNan, QNan (Unmasked). */                                                                                                                                                                              \
-          { { /*src2     */ { FP32_SNAN(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V1(1), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(1) } },                                        \
-            { /*src1     */ { FP32_QNAN(0), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V3(0) } },                                        \
-            { /* =>      */ { FP32_SNAN(0), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V3(0) } },                                        \
-              /*mxcsr:in */ X86_MXCSR_FZ,                                                                                                                                                                     \
-              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_IE,                                                                                                                                                      \
-              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_IE,                                                                                                                                                      \
-              /*xcpt?    */ true, true },                                                                                                                                                                     \
-          { { /*src2     */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V7(1) } },                  \
-            { /*src1     */ { FP32_QNAN_V(0, FP32_FRAC_NORM_MAX), FP32_RAND_V2(0), FP32_RAND_V4(0), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V2(0) } },                  \
-            { /* =>      */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_RAND_V2(0), FP32_RAND_V4(0), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V2(0) } },                  \
-              /*mxcsr:in */ 0,                                                                                                                                                                                \
-              /*128:out  */ X86_MXCSR_IE,                                                                                                                                                                     \
-              /*256:out  */ X86_MXCSR_IE,                                                                                                                                                                     \
-              /*xcpt?    */ true, true },                                                                                                                                                                     \
-          { { /*src2     */ { FP32_SNAN_V(0, FP32_FRAC_V1), FP32_RAND_V1(1), FP32_RAND_V7(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } },                        \
-            { /*src1     */ { FP32_QNAN_V(0, FP32_FRAC_V6), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V0(1), FP32_RAND_V2(0), FP32_RAND_V3(1) } },                        \
-            { /* =>      */ { FP32_SNAN_V(0, FP32_FRAC_V1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V0(1), FP32_RAND_V2(0), FP32_RAND_V3(1) } },                        \
-              /*mxcsr:in */ 0,                                                                                                                                                                                \
-              /*128:out  */ X86_MXCSR_IE,                                                                                                                                                                     \
-              /*256:out  */ X86_MXCSR_IE,                                                                                                                                                                     \
-              /*xcpt?    */ true, true },                                                                                                                                                                     \
-    /* SNan, SNan (Unmasked). */                                                                                                                                                                              \
-          { { /*src2     */ { FP32_SNAN(0), FP32_RAND_V1(1), FP32_RAND_V7(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } },                                        \
-            { /*src1     */ { FP32_SNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V7(0) } },                                        \
-            { /* =>      */ { FP32_SNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V7(0) } },                                        \
-              /*mxcsr:in */ 0,                                                                                                                                                                                \
-              /*128:out  */ X86_MXCSR_IE,                                                                                                                                                                     \
-              /*256:out  */ X86_MXCSR_IE,                                                                                                                                                                     \
-              /*xcpt?    */ true, true },                                                                                                                                                                     \
-          { { /*src2     */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_RAND_V1(0), FP32_RAND_V7(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V1(1), FP32_RAND_V2(1) } },                  \
-            { /*src1     */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MAX), FP32_RAND_V7(0), FP32_RAND_V5(0), FP32_RAND_V7(1), FP32_RAND_V6(1), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V2(1) } },                  \
-            { /* =>      */ { FP32_SNAN_V(0, FP32_FRAC_NORM_MIN), FP32_RAND_V7(0), FP32_RAND_V5(0), FP32_RAND_V7(1), FP32_RAND_V6(1), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V2(1) } },                  \
-              /*mxcsr:in */ 0,                                                                                                                                                                                \
-              /*128:out  */ X86_MXCSR_IE,                                                                                                                                                                     \
-              /*256:out  */ X86_MXCSR_IE,                                                                                                                                                                     \
-              /*xcpt?    */ true, true },                                                                                                                                                                     \
-          { { /*src2     */ { FP32_SNAN_V(0, FP32_FRAC_V1), FP32_RAND_V1(1), FP32_RAND_V6(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } },                        \
-            { /*src1     */ { FP32_SNAN_V(0, FP32_FRAC_V4), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V0(1) } },                        \
-            { /* =>      */ { FP32_SNAN_V(0, FP32_FRAC_V1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V0(1) } },                        \
-              /*mxcsr:in */ 0,                                                                                                                                                                                \
-              /*128:out  */ X86_MXCSR_IE,                                                                                                                                                                     \
-              /*256:out  */ X86_MXCSR_IE,                                                                                                                                                                     \
-              /*xcpt?    */ true, true },                                                                                                                                                                     \
-    /* QNan, Normal (Unmasked). */                                                                                                                                                                            \
-          { { /*src2     */ { FP32_QNAN(0), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } },                                        \
-            { /*src1     */ { FP32_1(0),    FP32_RAND_V2(1), FP32_RAND_V4(1), FP32_RAND_V6(1), FP32_RAND_V2(1), FP32_RAND_V7(0), FP32_RAND_V3(0), FP32_RAND_V4(1) } },                                        \
-            { /* =>      */ { FP32_QNAN(0), FP32_RAND_V2(1), FP32_RAND_V4(1), FP32_RAND_V6(1), FP32_RAND_V2(1), FP32_RAND_V7(0), FP32_RAND_V3(0), FP32_RAND_V4(1) } },                                        \
-              /*mxcsr:in */ 0,                                                                                                                                                                                \
-              /*128:out  */ X86_MXCSR_IE,                                                                                                                                                                     \
-              /*256:out  */ X86_MXCSR_IE,                                                                                                                                                                     \
-              /*xcpt?    */ true, true },                                                                                                                                                                     \
-    /* SNan, Normal (Masked). */                                                                                                                                                                              \
-          { { /*src2     */ { FP32_SNAN(1), FP32_RAND_V0(1), FP32_RAND_V2(1), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } },                                        \
-            { /*src1     */ { FP32_1(0),    FP32_RAND_V0(1), FP32_RAND_V1(1), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V6(0), FP32_RAND_V7(0), FP32_RAND_V1(1) } },                                        \
-            { /* =>      */ { FP32_SNAN(1), FP32_RAND_V0(1), FP32_RAND_V1(1), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V6(0), FP32_RAND_V7(0), FP32_RAND_V1(1) } },                                        \
-              /*mxcsr:in */ 0,                                                                                                                                                                                \
-              /*128:out  */ X86_MXCSR_IE,                                                                                                                                                                     \
-              /*256:out  */ X86_MXCSR_IE,                                                                                                                                                                     \
-              /*xcpt?    */ true, true },                                                                                                                                                                     \
+    /* QNan, QNan (Masked). */                                                                                                                                             \
+    /*0 */{ { /*src2     */ { FP32_QNAN(0), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V2(0), FP32_RAND_V1(1), FP32_RAND_V7(0), FP32_RAND_V2(1) } },     \
+            { /*src1     */ { FP32_QNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V5(1), FP32_RAND_V6(1), FP32_RAND_V7(1), FP32_RAND_V1(1) } },     \
+            { /* =>      */ { FP32_QNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V5(1), FP32_RAND_V6(1), FP32_RAND_V7(1), FP32_RAND_V1(1) } },     \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                           \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                            \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                            \
+              /*xcpt?    */ false, false },                                                                                                                                \
+          { { /*src2     */ { FP32_QNAN_MAX(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(0), FP32_RAND_V6(1) } }, \
+            { /*src1     */ { FP32_QNAN(0),     FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V1(0) } }, \
+            { /* =>      */ { FP32_QNAN_MAX(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V1(0) } }, \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                           \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                            \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                            \
+              /*xcpt?    */ false, false },                                                                                                                                \
+          { { /*src2     */ { FP32_QNAN_V0(0),  FP32_RAND_V0(1), FP32_RAND_V7(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } }, \
+            { /*src1     */ { FP32_QNAN_MAX(0), FP32_RAND_V1(0), FP32_RAND_V7(0), FP32_RAND_V2(1), FP32_RAND_V6(1), FP32_RAND_V3(1), FP32_RAND_V5(0), FP32_RAND_V4(1) } }, \
+            { /* =>      */ { FP32_QNAN_V0(0),  FP32_RAND_V1(0), FP32_RAND_V7(0), FP32_RAND_V2(1), FP32_RAND_V6(1), FP32_RAND_V3(1), FP32_RAND_V5(0), FP32_RAND_V4(1) } }, \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                           \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                            \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                            \
+              /*xcpt?    */ false, false },                                                                                                                                \
+    /* QNan, SNan (Masked). */                                                                                                                                             \
+          { { /*src2     */ { FP32_QNAN(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V2(0), FP32_RAND_V2(1), FP32_RAND_V1(0), FP32_RAND_V0(1) } },     \
+            { /*src1     */ { FP32_SNAN(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },     \
+            { /* =>      */ { FP32_QNAN(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },     \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                           \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                            \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                            \
+              /*xcpt?    */ false, false },                                                                                                                                \
+          { { /*src2     */ { FP32_QNAN_MAX(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V1(1), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, \
+            { /*src1     */ { FP32_SNAN(0),     FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V3(0) } }, \
+            { /* =>      */ { FP32_QNAN_MAX(0), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V3(0) } }, \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                           \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                            \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                            \
+              /*xcpt?    */ false, false },                                                                                                                                \
+          { { /*src2     */ { FP32_QNAN_V0(0),  FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V1(1), FP32_RAND_V0(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, \
+            { /*src1     */ { FP32_SNAN_MAX(0), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V1(0) } }, \
+            { /* =>      */ { FP32_QNAN_V0(0),  FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V1(0) } }, \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                           \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                            \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                            \
+              /*xcpt?    */ false, false },                                                                                                                                \
+    /* SNan, QNan (Masked). */                                                                                                                                             \
+          { { /*src2     */ { FP32_SNAN(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V1(1), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(1) } },     \
+            { /*src1     */ { FP32_QNAN(0), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V3(0) } },     \
+            { /* =>      */ { FP32_SNAN(0), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V3(0) } },     \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,                                                                                                            \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,                                                                                             \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,                                                                                             \
+              /*xcpt?    */ false, false },                                                                                                                                \
+          { { /*src2     */ { FP32_SNAN(0),     FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V7(1) } }, \
+            { /*src1     */ { FP32_QNAN_MAX(0), FP32_RAND_V2(0), FP32_RAND_V4(0), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V2(0) } }, \
+            { /* =>      */ { FP32_SNAN(0),     FP32_RAND_V2(0), FP32_RAND_V4(0), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V2(0) } }, \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                           \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                            \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                            \
+              /*xcpt?    */ false, false },                                                                                                                                \
+          { { /*src2     */ { FP32_SNAN_V1(0), FP32_RAND_V1(1), FP32_RAND_V7(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } },  \
+            { /*src1     */ { FP32_QNAN_V6(0), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V0(1), FP32_RAND_V2(0), FP32_RAND_V3(1) } },  \
+            { /* =>      */ { FP32_SNAN_V1(0), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V0(1), FP32_RAND_V2(0), FP32_RAND_V3(1) } },  \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                           \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                            \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                            \
+              /*xcpt?    */ false, false },                                                                                                                                \
+    /* SNan, SNan (Masked). */                                                                                                                                             \
+          { { /*src2     */ { FP32_SNAN(0), FP32_RAND_V1(1), FP32_RAND_V7(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } },     \
+            { /*src1     */ { FP32_SNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V7(0) } },     \
+            { /* =>      */ { FP32_SNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V7(0) } },     \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                           \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                            \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                            \
+              /*xcpt?    */ false, false },                                                                                                                                \
+          { { /*src2     */ { FP32_SNAN(0),     FP32_RAND_V1(0), FP32_RAND_V7(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V1(1), FP32_RAND_V2(1) } }, \
+            { /*src1     */ { FP32_SNAN_MAX(0), FP32_RAND_V7(0), FP32_RAND_V5(0), FP32_RAND_V7(1), FP32_RAND_V6(1), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V2(1) } }, \
+            { /* =>      */ { FP32_SNAN(0),     FP32_RAND_V7(0), FP32_RAND_V5(0), FP32_RAND_V7(1), FP32_RAND_V6(1), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V2(1) } }, \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                           \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                            \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                            \
+              /*xcpt?    */ false, false },                                                                                                                                \
+          { { /*src2     */ { FP32_SNAN_V1(0), FP32_RAND_V1(1), FP32_RAND_V6(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } },  \
+            { /*src1     */ { FP32_SNAN_V4(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V0(1) } },  \
+            { /* =>      */ { FP32_SNAN_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V0(1) } },  \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                           \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                            \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                            \
+              /*xcpt?    */ false, false },                                                                                                                                \
+    /* QNan, Normal (Unmasked). */                                                                                                                                         \
+          { { /*src2     */ { FP32_QNAN(0), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } },     \
+            { /*src1     */ { FP32_1(0),    FP32_RAND_V2(1), FP32_RAND_V4(1), FP32_RAND_V6(1), FP32_RAND_V2(1), FP32_RAND_V7(0), FP32_RAND_V3(0), FP32_RAND_V4(1) } },     \
+            { /* =>      */ { FP32_QNAN(0), FP32_RAND_V2(1), FP32_RAND_V4(1), FP32_RAND_V6(1), FP32_RAND_V2(1), FP32_RAND_V7(0), FP32_RAND_V3(0), FP32_RAND_V4(1) } },     \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                           \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                            \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                            \
+              /*xcpt?    */ false, false },                                                                                                                                \
+    /* SNan, Normal (Masked). */                                                                                                                                           \
+          { { /*src2     */ { FP32_SNAN(1), FP32_RAND_V0(1), FP32_RAND_V2(1), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } },     \
+            { /*src1     */ { FP32_1(0),    FP32_RAND_V0(1), FP32_RAND_V1(1), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V6(0), FP32_RAND_V7(0), FP32_RAND_V1(1) } },     \
+            { /* =>      */ { FP32_SNAN(1), FP32_RAND_V0(1), FP32_RAND_V1(1), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V6(0), FP32_RAND_V7(0), FP32_RAND_V1(1) } },     \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                           \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                            \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                            \
+              /*xcpt?    */ false, false },                                                                                                                                \
+    /* QNan, QNan (Unmasked). */                                                                                                                                           \
+    /*0 */{ { /*src2     */ { FP32_QNAN(0), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V2(0), FP32_RAND_V1(1), FP32_RAND_V7(0), FP32_RAND_V2(1) } },     \
+            { /*src1     */ { FP32_QNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V5(1), FP32_RAND_V6(1), FP32_RAND_V7(1), FP32_RAND_V1(1) } },     \
+            { /* =>      */ { FP32_QNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V5(1), FP32_RAND_V6(1), FP32_RAND_V7(1), FP32_RAND_V1(1) } },     \
+              /*mxcsr:in */ 0,                                                                                                                                             \
+              /*128:out  */ X86_MXCSR_IE,                                                                                                                                  \
+              /*256:out  */ X86_MXCSR_IE,                                                                                                                                  \
+              /*xcpt?    */ true, true },                                                                                                                                  \
+          { { /*src2     */ { FP32_QNAN_MAX(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(0), FP32_RAND_V6(1) } }, \
+            { /*src1     */ { FP32_QNAN(0),     FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V1(0) } }, \
+            { /* =>      */ { FP32_QNAN_MAX(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V1(0) } }, \
+              /*mxcsr:in */ 0,                                                                                                                                             \
+              /*128:out  */ X86_MXCSR_IE,                                                                                                                                  \
+              /*256:out  */ X86_MXCSR_IE,                                                                                                                                  \
+              /*xcpt?    */ true, true },                                                                                                                                  \
+          { { /*src2     */ { FP32_QNAN_V0(0),  FP32_RAND_V0(1), FP32_RAND_V7(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } }, \
+            { /*src1     */ { FP32_QNAN_MAX(0), FP32_RAND_V1(0), FP32_RAND_V7(0), FP32_RAND_V2(1), FP32_RAND_V6(1), FP32_RAND_V3(1), FP32_RAND_V5(0), FP32_RAND_V4(1) } }, \
+            { /* =>      */ { FP32_QNAN_V0(0),  FP32_RAND_V1(0), FP32_RAND_V7(0), FP32_RAND_V2(1), FP32_RAND_V6(1), FP32_RAND_V3(1), FP32_RAND_V5(0), FP32_RAND_V4(1) } }, \
+              /*mxcsr:in */ 0,                                                                                                                                             \
+              /*128:out  */ X86_MXCSR_IE,                                                                                                                                  \
+              /*256:out  */ X86_MXCSR_IE,                                                                                                                                  \
+              /*xcpt?    */ true, true },                                                                                                                                  \
+    /* QNan, SNan (Unmasked). */                                                                                                                                           \
+          { { /*src2     */ { FP32_QNAN(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V2(0), FP32_RAND_V2(1), FP32_RAND_V1(0), FP32_RAND_V0(1) } },     \
+            { /*src1     */ { FP32_SNAN(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },     \
+            { /* =>      */ { FP32_QNAN(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },     \
+              /*mxcsr:in */ 0,                                                                                                                                             \
+              /*128:out  */ X86_MXCSR_IE,                                                                                                                                  \
+              /*256:out  */ X86_MXCSR_IE,                                                                                                                                  \
+              /*xcpt?    */ true, true },                                                                                                                                  \
+          { { /*src2     */ { FP32_QNAN_MAX(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V1(1), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, \
+            { /*src1     */ { FP32_SNAN(0),     FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V3(0) } }, \
+            { /* =>      */ { FP32_QNAN_MAX(0), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V3(0) } }, \
+              /*mxcsr:in */ 0,                                                                                                                                             \
+              /*128:out  */ X86_MXCSR_IE,                                                                                                                                  \
+              /*256:out  */ X86_MXCSR_IE,                                                                                                                                  \
+              /*xcpt?    */ true, true },                                                                                                                                  \
+          { { /*src2     */ { FP32_QNAN_V0(0),  FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V1(1), FP32_RAND_V0(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, \
+            { /*src1     */ { FP32_SNAN_MAX(0), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V1(0) } }, \
+            { /* =>      */ { FP32_QNAN_V0(0),  FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V1(0) } }, \
+              /*mxcsr:in */ 0,                                                                                                                                             \
+              /*128:out  */ X86_MXCSR_IE,                                                                                                                                  \
+              /*256:out  */ X86_MXCSR_IE,                                                                                                                                  \
+              /*xcpt?    */ true, true },                                                                                                                                  \
+    /* SNan, QNan (Unmasked). */                                                                                                                                           \
+          { { /*src2     */ { FP32_SNAN(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V1(1), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(1) } },     \
+            { /*src1     */ { FP32_QNAN(0), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V3(0) } },     \
+            { /* =>      */ { FP32_SNAN(0), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V3(0) } },     \
+              /*mxcsr:in */ X86_MXCSR_FZ,                                                                                                                                  \
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_IE,                                                                                                                   \
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_IE,                                                                                                                   \
+              /*xcpt?    */ true, true },                                                                                                                                  \
+          { { /*src2     */ { FP32_SNAN(0),     FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V7(1) } }, \
+            { /*src1     */ { FP32_QNAN_MAX(0), FP32_RAND_V2(0), FP32_RAND_V4(0), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V2(0) } }, \
+            { /* =>      */ { FP32_SNAN(0),     FP32_RAND_V2(0), FP32_RAND_V4(0), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V2(0) } }, \
+              /*mxcsr:in */ 0,                                                                                                                                             \
+              /*128:out  */ X86_MXCSR_IE,                                                                                                                                  \
+              /*256:out  */ X86_MXCSR_IE,                                                                                                                                  \
+              /*xcpt?    */ true, true },                                                                                                                                  \
+          { { /*src2     */ { FP32_SNAN_V1(0), FP32_RAND_V1(1), FP32_RAND_V7(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } },  \
+            { /*src1     */ { FP32_QNAN_V6(0), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V0(1), FP32_RAND_V2(0), FP32_RAND_V3(1) } },  \
+            { /* =>      */ { FP32_SNAN_V1(0), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V0(1), FP32_RAND_V2(0), FP32_RAND_V3(1) } },  \
+              /*mxcsr:in */ 0,                                                                                                                                             \
+              /*128:out  */ X86_MXCSR_IE,                                                                                                                                  \
+              /*256:out  */ X86_MXCSR_IE,                                                                                                                                  \
+              /*xcpt?    */ true, true },                                                                                                                                  \
+    /* SNan, SNan (Unmasked). */                                                                                                                                           \
+          { { /*src2     */ { FP32_SNAN(0), FP32_RAND_V1(1), FP32_RAND_V7(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } },     \
+            { /*src1     */ { FP32_SNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V7(0) } },     \
+            { /* =>      */ { FP32_SNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V7(0) } },     \
+              /*mxcsr:in */ 0,                                                                                                                                             \
+              /*128:out  */ X86_MXCSR_IE,                                                                                                                                  \
+              /*256:out  */ X86_MXCSR_IE,                                                                                                                                  \
+              /*xcpt?    */ true, true },                                                                                                                                  \
+          { { /*src2     */ { FP32_SNAN(0),     FP32_RAND_V1(0), FP32_RAND_V7(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V1(1), FP32_RAND_V2(1) } }, \
+            { /*src1     */ { FP32_SNAN_MAX(0), FP32_RAND_V7(0), FP32_RAND_V5(0), FP32_RAND_V7(1), FP32_RAND_V6(1), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V2(1) } }, \
+            { /* =>      */ { FP32_SNAN(0),     FP32_RAND_V7(0), FP32_RAND_V5(0), FP32_RAND_V7(1), FP32_RAND_V6(1), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V2(1) } }, \
+              /*mxcsr:in */ 0,                                                                                                                                             \
+              /*128:out  */ X86_MXCSR_IE,                                                                                                                                  \
+              /*256:out  */ X86_MXCSR_IE,                                                                                                                                  \
+              /*xcpt?    */ true, true },                                                                                                                                  \
+          { { /*src2     */ { FP32_SNAN_V1(0), FP32_RAND_V1(1), FP32_RAND_V6(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } },  \
+            { /*src1     */ { FP32_SNAN_V4(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V0(1) } },  \
+            { /* =>      */ { FP32_SNAN_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V0(1) } },  \
+              /*mxcsr:in */ 0,                                                                                                                                             \
+              /*128:out  */ X86_MXCSR_IE,                                                                                                                                  \
+              /*256:out  */ X86_MXCSR_IE,                                                                                                                                  \
+              /*xcpt?    */ true, true },                                                                                                                                  \
+    /* QNan, Normal (Unmasked). */                                                                                                                                         \
+          { { /*src2     */ { FP32_QNAN(0), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } },     \
+            { /*src1     */ { FP32_1(0),    FP32_RAND_V2(1), FP32_RAND_V4(1), FP32_RAND_V6(1), FP32_RAND_V2(1), FP32_RAND_V7(0), FP32_RAND_V3(0), FP32_RAND_V4(1) } },     \
+            { /* =>      */ { FP32_QNAN(0), FP32_RAND_V2(1), FP32_RAND_V4(1), FP32_RAND_V6(1), FP32_RAND_V2(1), FP32_RAND_V7(0), FP32_RAND_V3(0), FP32_RAND_V4(1) } },     \
+              /*mxcsr:in */ 0,                                                                                                                                             \
+              /*128:out  */ X86_MXCSR_IE,                                                                                                                                  \
+              /*256:out  */ X86_MXCSR_IE,                                                                                                                                  \
+              /*xcpt?    */ true, true },                                                                                                                                  \
+    /* SNan, Normal (Masked). */                                                                                                                                           \
+          { { /*src2     */ { FP32_SNAN(1), FP32_RAND_V0(1), FP32_RAND_V2(1), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } },     \
+            { /*src1     */ { FP32_1(0),    FP32_RAND_V0(1), FP32_RAND_V1(1), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V6(0), FP32_RAND_V7(0), FP32_RAND_V1(1) } },     \
+            { /* =>      */ { FP32_SNAN(1), FP32_RAND_V0(1), FP32_RAND_V1(1), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V6(0), FP32_RAND_V7(0), FP32_RAND_V1(1) } },     \
+              /*mxcsr:in */ 0,                                                                                                                                             \
+              /*128:out  */ X86_MXCSR_IE,                                                                                                                                  \
+              /*256:out  */ X86_MXCSR_IE,                                                                                                                                  \
+              /*xcpt?    */ true, true },                                                                                                                                  \
 
 /**
@@ -11455,7 +11458,7 @@
               /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
               /*xcpt?    */ false, false },
-          { { /*src2     */ { FP32_0(0), FP32_INF(0), FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN(1),      FP32_QNAN(1),      FP32_INF(1),       FP32_RAND_V7(0)   } },
-            { /*src1     */ { FP32_0(0), FP32_INF(1), FP32_QNAN(0), FP32_SNAN(1), FP32_QNAN_V(0, 1), FP32_QNAN_V(1, 1), FP32_SNAN_V(1, 1), FP32_SNAN_V(0, 1) } },
-            { /* =>      */ { FP32_0(0), FP32_INF(1), FP32_QNAN(0), FP32_SNAN(1), FP32_QNAN_V(0, 1), FP32_QNAN_V(1, 1), FP32_SNAN_V(1, 1), FP32_SNAN_V(0, 1) } },
+          { { /*src2     */ { FP32_0(0), FP32_INF(0), FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN(1),      FP32_QNAN(1),      FP32_INF(1),      FP32_RAND_V7(0)  } },
+            { /*src1     */ { FP32_0(0), FP32_INF(1), FP32_QNAN(0), FP32_SNAN(1), FP32_QNAN_V(0, 1), FP32_QNAN_V(1, 1), FP32_SNAN(1), FP32_SNAN(0) } },
+            { /* =>      */ { FP32_0(0), FP32_INF(1), FP32_QNAN(0), FP32_SNAN(1), FP32_QNAN_V(0, 1), FP32_QNAN_V(1, 1), FP32_SNAN(1), FP32_SNAN(0) } },
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
               /*128:out  */ X86_MXCSR_XCPT_MASK,
@@ -11550,6 +11553,6 @@
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_INF(0), FP32_RAND_V3(1), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V4(1), FP32_RAND_V5(1),   FP32_RAND_V7(1),   FP32_RAND_V0(1) } },
-            { /*src1     */ { FP32_INF(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V5(1), FP32_RAND_V6(0), FP32_SNAN_V(0, 1), FP32_SNAN_V(1, 1), FP32_RAND_V2(1) } },
-            { /* =>      */ { FP32_INF(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V5(1), FP32_RAND_V6(0), FP32_SNAN_V(0, 1), FP32_SNAN_V(1, 1), FP32_RAND_V2(1) } },
+            { /*src1     */ { FP32_INF(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V5(1), FP32_RAND_V6(0), FP32_SNAN(0), FP32_SNAN(1), FP32_RAND_V2(1) } },
+            { /* =>      */ { FP32_INF(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V5(1), FP32_RAND_V6(0), FP32_SNAN(0), FP32_SNAN(1), FP32_RAND_V2(1) } },
               /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
               /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
@@ -11557,6 +11560,6 @@
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_INF(0), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V4(0), FP32_RAND_V5(1),   FP32_RAND_V7(1),   FP32_RAND_V0(1) } },
-            { /*src1     */ { FP32_INF(0), FP32_RAND_V0(1), FP32_RAND_V0(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_SNAN_V(1, 1), FP32_QNAN_V(1, 1), FP32_RAND_V3(1) } },
-            { /* =>      */ { FP32_INF(0), FP32_RAND_V0(1), FP32_RAND_V0(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_SNAN_V(1, 1), FP32_QNAN_V(1, 1), FP32_RAND_V3(1) } },
+            { /*src1     */ { FP32_INF(0), FP32_RAND_V0(1), FP32_RAND_V0(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_SNAN(1), FP32_QNAN_V(1, 1), FP32_RAND_V3(1) } },
+            { /* =>      */ { FP32_INF(0), FP32_RAND_V0(1), FP32_RAND_V0(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_SNAN(1), FP32_QNAN_V(1, 1), FP32_RAND_V3(1) } },
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
               /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
@@ -11693,6 +11696,6 @@
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_V(0, 0, 0x7d)/*0.25*/, FP32_RAND_V2(1), FP32_RAND_V5(0), FP32_RAND_V6(1), FP32_RAND_V4(0), FP32_RAND_V3(1),   FP32_RAND_V7(0),   FP32_RAND_V1(1) } },
-            { /*src1     */ { FP32_V(0, 0, 0x7e)/*0.50*/, FP32_RAND_V0(0), FP32_RAND_V5(0), FP32_RAND_V7(0), FP32_RAND_V2(1), FP32_SNAN_V(1, 1), FP32_SNAN_V(0, 1), FP32_RAND_V3(0) } },
-            { /* =>      */ { FP32_V(0, 0, 0x7e)/*0.50*/, FP32_RAND_V0(0), FP32_RAND_V5(0), FP32_RAND_V7(0), FP32_RAND_V2(1), FP32_SNAN_V(1, 1), FP32_SNAN_V(0, 1), FP32_RAND_V3(0) } },
+            { /*src1     */ { FP32_V(0, 0, 0x7e)/*0.50*/, FP32_RAND_V0(0), FP32_RAND_V5(0), FP32_RAND_V7(0), FP32_RAND_V2(1), FP32_SNAN(1), FP32_SNAN(0), FP32_RAND_V3(0) } },
+            { /* =>      */ { FP32_V(0, 0, 0x7e)/*0.50*/, FP32_RAND_V0(0), FP32_RAND_V5(0), FP32_RAND_V7(0), FP32_RAND_V2(1), FP32_SNAN(1), FP32_SNAN(0), FP32_RAND_V3(0) } },
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
@@ -13014,6 +13017,6 @@
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_0(0), FP32_INF(0), FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN(1),      FP32_QNAN(1),      FP32_INF(1),       FP32_RAND_V7(0)   } },
-            { /*src1     */ { FP32_0(0), FP32_INF(1), FP32_QNAN(0), FP32_SNAN(1), FP32_QNAN_V(0, 1), FP32_QNAN_V(1, 1), FP32_SNAN_V(1, 1), FP32_SNAN_V(0, 1) } },
-            { /* =>      */ { FP32_0(0), FP32_INF(1), FP32_QNAN(0), FP32_SNAN(1), FP32_QNAN_V(0, 1), FP32_QNAN_V(1, 1), FP32_SNAN_V(1, 1), FP32_SNAN_V(0, 1) } },
+            { /*src1     */ { FP32_0(0), FP32_INF(1), FP32_QNAN(0), FP32_SNAN(1), FP32_QNAN_V(0, 1), FP32_QNAN_V(1, 1), FP32_SNAN(1), FP32_SNAN(0) } },
+            { /* =>      */ { FP32_0(0), FP32_INF(1), FP32_QNAN(0), FP32_SNAN(1), FP32_QNAN_V(0, 1), FP32_QNAN_V(1, 1), FP32_SNAN(1), FP32_SNAN(0) } },
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
               /*128:out  */ X86_MXCSR_XCPT_MASK,
@@ -13108,6 +13111,6 @@
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_INF(0), FP32_RAND_V3(1), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V4(1), FP32_RAND_V5(1),   FP32_RAND_V7(1),   FP32_RAND_V0(1) } },
-            { /*src1     */ { FP32_INF(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V5(1), FP32_RAND_V6(0), FP32_SNAN_V(0, 1), FP32_SNAN_V(1, 1), FP32_RAND_V2(1) } },
-            { /* =>      */ { FP32_INF(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V5(1), FP32_RAND_V6(0), FP32_SNAN_V(0, 1), FP32_SNAN_V(1, 1), FP32_RAND_V2(1) } },
+            { /*src1     */ { FP32_INF(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V5(1), FP32_RAND_V6(0), FP32_SNAN(0), FP32_SNAN(1), FP32_RAND_V2(1) } },
+            { /* =>      */ { FP32_INF(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V5(1), FP32_RAND_V6(0), FP32_SNAN(0), FP32_SNAN(1), FP32_RAND_V2(1) } },
               /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
               /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
@@ -13115,6 +13118,6 @@
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_INF(0), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V4(0), FP32_RAND_V5(1),   FP32_RAND_V7(1),   FP32_RAND_V0(1) } },
-            { /*src1     */ { FP32_INF(0), FP32_RAND_V0(1), FP32_RAND_V0(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_SNAN_V(1, 1), FP32_QNAN_V(1, 1), FP32_RAND_V3(1) } },
-            { /* =>      */ { FP32_INF(0), FP32_RAND_V0(1), FP32_RAND_V0(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_SNAN_V(1, 1), FP32_QNAN_V(1, 1), FP32_RAND_V3(1) } },
+            { /*src1     */ { FP32_INF(0), FP32_RAND_V0(1), FP32_RAND_V0(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_SNAN(1), FP32_QNAN_V(1, 1), FP32_RAND_V3(1) } },
+            { /* =>      */ { FP32_INF(0), FP32_RAND_V0(1), FP32_RAND_V0(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_SNAN(1), FP32_QNAN_V(1, 1), FP32_RAND_V3(1) } },
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
               /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
@@ -13251,6 +13254,6 @@
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_V(0, 0, 0x7d)/*0.25*/, FP32_RAND_V2(1), FP32_RAND_V5(0), FP32_RAND_V6(1), FP32_RAND_V4(0), FP32_RAND_V3(1),   FP32_RAND_V7(0),   FP32_RAND_V1(1) } },
-            { /*src1     */ { FP32_V(0, 0, 0x7e)/*0.50*/, FP32_RAND_V0(0), FP32_RAND_V5(0), FP32_RAND_V7(0), FP32_RAND_V2(1), FP32_SNAN_V(1, 1), FP32_SNAN_V(0, 1), FP32_RAND_V3(0) } },
-            { /* =>      */ { FP32_V(0, 0, 0x7d)/*0.25*/, FP32_RAND_V0(0), FP32_RAND_V5(0), FP32_RAND_V7(0), FP32_RAND_V2(1), FP32_SNAN_V(1, 1), FP32_SNAN_V(0, 1), FP32_RAND_V3(0) } },
+            { /*src1     */ { FP32_V(0, 0, 0x7e)/*0.50*/, FP32_RAND_V0(0), FP32_RAND_V5(0), FP32_RAND_V7(0), FP32_RAND_V2(1), FP32_SNAN(1), FP32_SNAN(0), FP32_RAND_V3(0) } },
+            { /* =>      */ { FP32_V(0, 0, 0x7d)/*0.25*/, FP32_RAND_V0(0), FP32_RAND_V5(0), FP32_RAND_V7(0), FP32_RAND_V2(1), FP32_SNAN(1), FP32_SNAN(0), FP32_RAND_V3(0) } },
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
