Changeset 106214 in vbox for trunk/src/VBox/ValidationKit/bootsectors
- Timestamp:
- Oct 3, 2024 10:30:23 AM (2 months ago)
- File:
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- 1 edited
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trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32
r106213 r106214 628 628 **/ 629 629 #define FP32_TABLE_D1_PS_INVALIDS \ 630 /* 0*/{ { /*src2 */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \630 /* 0*/{ { /*src2 */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \ 631 631 { /*src1 */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } }, \ 632 632 { /* => */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } }, \ … … 715 715 /** 716 716 * Table D-1: Packed double-precision floating-point invalid values. 717 * For instructions: addpd, subpd, mulpd, divpd, addsubpd , haddpd, hsubpd.717 * For instructions: addpd, subpd, mulpd, divpd, addsubpd. 718 718 **/ 719 719 #define FP64_TABLE_D1_PD_INVALIDS \ 720 /* 0*/{ { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \720 /* 0*/{ { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \ 721 721 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, \ 722 722 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, \ … … 809 809 #define FP32_TABLE_D1_SS_INVALIDS \ 810 810 /* QNan, QNan (Masked). */ \ 811 /* 0*/{ { /*src2 */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \811 /* 0*/{ { /*src2 */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \ 812 812 { /*src1 */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } }, \ 813 813 { /* => */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } }, \ … … 1024 1024 #define FP64_TABLE_D1_SD_INVALIDS \ 1025 1025 /* QNan, QNan (Masked). */ \ 1026 /* 0*/{ { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \1026 /* 0*/{ { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \ 1027 1027 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, \ 1028 1028 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, \ … … 1238 1238 **/ 1239 1239 #define FP32_TABLE_D1_H_PS_INVALIDS \ 1240 /* 0*/{ { /*src2 */ { FP32_QNAN_MAX(0), FP32_QNAN(0), FP32_QNAN_V0(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V3(0), FP32_QNAN_V5(0) } }, \1240 /* 0*/{ { /*src2 */ { FP32_QNAN_MAX(0), FP32_QNAN(0), FP32_QNAN_V0(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V3(0), FP32_QNAN_V5(0) } }, \ 1241 1241 { /*src1 */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } }, \ 1242 1242 { /* => */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0), FP32_QNAN_V6(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0) } }, \ … … 1328 1328 **/ 1329 1329 #define FP64_TABLE_D1_H_PD_INVALIDS \ 1330 /* 0*/{ { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \1330 /* 0*/{ { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \ 1331 1331 { /*src1 */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } }, \ 1332 1332 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V0) } }, \ … … 1384 1384 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, \ 1385 1385 /*xcpt? */ true, true }, \ 1386 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2) } }, \1387 { /*src1 */ { FP64_SNAN(0), FP64_QNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V3) } }, \1388 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \1389 /*mxcsr:in */ 0, \1390 /*128:out */ X86_MXCSR_IE, \1391 /*256:out */ X86_MXCSR_IE, \1392 /*xcpt? */ true, true }, \1393 1386 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN) } }, \ 1394 1387 { /*src1 */ { FP64_SNAN(0), FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX) } }, \ … … 1398 1391 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, \ 1399 1392 /*xcpt? */ true, true }, \ 1400 { { /*src2 */ { FP64_QNAN(0), FP64_NORM_V1(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \ 1401 { /*src1 */ { FP64_QNAN(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V2(1) } }, \ 1402 { /* => */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } }, \ 1403 /*mxcsr:in */ 0, \ 1404 /*128:out */ 0, \ 1405 /*256:out */ 0, \ 1406 /*xcpt? */ false, false }, \ 1407 /*11*/{ { /*src2 */ { FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_1(0), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_NORM_V3(0) } }, \ 1393 /* 9*/{ { /*src2 */ { FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_1(0), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_NORM_V3(0) } }, \ 1408 1394 { /*src1 */ { FP64_SNAN(0), FP64_1(1), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_NORM_V2(1) } }, \ 1409 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V( 0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \1395 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \ 1410 1396 /*mxcsr:in */ X86_MXCSR_RC_UP, \ 1411 1397 /*128:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, \ … … 1418 1404 **/ 1419 1405 #define FP32_TABLE_D9_PS_INVALIDS \ 1420 /* 0*/{ { /*src2 */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \1406 /* 0*/{ { /*src2 */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \ 1421 1407 { /*src1 */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } }, \ 1422 1408 { /* => */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \ … … 1494 1480 **/ 1495 1481 #define FP64_TABLE_D9_PD_INVALIDS \ 1496 /* 0*/{ { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \1482 /* 0*/{ { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \ 1497 1483 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, \ 1498 1484 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \ … … 1571 1557 #define FP32_TABLE_D9_SS_INVALIDS \ 1572 1558 /* QNan, QNan (Masked). */ \ 1573 /* 0*/{ { /*src2 */ { FP32_QNAN(0), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V2(0), FP32_RAND_V1(1), FP32_RAND_V7(0), FP32_RAND_V2(1) } }, \1559 /* 0*/{ { /*src2 */ { FP32_QNAN(0), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V2(0), FP32_RAND_V1(1), FP32_RAND_V7(0), FP32_RAND_V2(1) } }, \ 1574 1560 { /*src1 */ { FP32_QNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V5(1), FP32_RAND_V6(1), FP32_RAND_V7(1), FP32_RAND_V1(1) } }, \ 1575 1561 { /* => */ { FP32_QNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V5(1), FP32_RAND_V6(1), FP32_RAND_V7(1), FP32_RAND_V1(1) } }, \ … … 1658 1644 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1659 1645 /*xcpt? */ false, false }, \ 1660 /* QNan, Normal ( Unmasked). */\1646 /* QNan, Normal (Masked). */ \ 1661 1647 { { /*src2 */ { FP32_QNAN(0), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } }, \ 1662 1648 { /*src1 */ { FP32_1(0), FP32_RAND_V2(1), FP32_RAND_V4(1), FP32_RAND_V6(1), FP32_RAND_V2(1), FP32_RAND_V7(0), FP32_RAND_V3(0), FP32_RAND_V4(1) } }, \ … … 1675 1661 /*xcpt? */ false, false }, \ 1676 1662 /* QNan, QNan (Unmasked). */ \ 1677 /*0 */{ { /*src2 */ { FP32_QNAN(0), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V2(0), FP32_RAND_V1(1), FP32_RAND_V7(0), FP32_RAND_V2(1) } }, \1663 { { /*src2 */ { FP32_QNAN(0), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V2(0), FP32_RAND_V1(1), FP32_RAND_V7(0), FP32_RAND_V2(1) } }, \ 1678 1664 { /*src1 */ { FP32_QNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V5(1), FP32_RAND_V6(1), FP32_RAND_V7(1), FP32_RAND_V1(1) } }, \ 1679 1665 { /* => */ { FP32_QNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V5(1), FP32_RAND_V6(1), FP32_RAND_V7(1), FP32_RAND_V1(1) } }, \ … … 1770 1756 /*256:out */ X86_MXCSR_IE, \ 1771 1757 /*xcpt? */ true, true }, \ 1772 /* SNan, Normal ( Masked). */\1758 /* SNan, Normal (Unmasked). */ \ 1773 1759 { { /*src2 */ { FP32_SNAN(1), FP32_RAND_V0(1), FP32_RAND_V2(1), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } }, \ 1774 1760 { /*src1 */ { FP32_1(0), FP32_RAND_V0(1), FP32_RAND_V1(1), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V6(0), FP32_RAND_V7(0), FP32_RAND_V1(1) } }, \ … … 1785 1771 #define FP64_TABLE_D9_SD_INVALIDS \ 1786 1772 /* QNan, QNan (Masked). */ \ 1787 /* 0*/{ { /*src2 */ { FP64_QNAN(0), FP64_RAND_V2(0), FP64_RAND_V0(1), FP64_RAND_V1(0) } }, \1773 /* 0*/{ { /*src2 */ { FP64_QNAN(0), FP64_RAND_V2(0), FP64_RAND_V0(1), FP64_RAND_V1(0) } }, \ 1788 1774 { /*src1 */ { FP64_QNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, \ 1789 1775 { /* => */ { FP64_QNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, \ … … 1872 1858 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1873 1859 /*xcpt? */ false, false }, \ 1874 /* QNan, Normal ( Unmasked). */\1860 /* QNan, Normal (Masked). */ \ 1875 1861 { { /*src2 */ { FP64_QNAN(0), FP64_RAND_V3(1), FP64_RAND_V2(1), FP64_RAND_V2(0) } }, \ 1876 1862 { /*src1 */ { FP64_1(0), FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V1(1) } }, \ … … 1889 1875 /*xcpt? */ false, false }, \ 1890 1876 /* QNan, QNan (Unmasked). */ \ 1891 /* 0*/{ { /*src2 */ { FP64_QNAN(0), FP64_RAND_V2(0), FP64_RAND_V0(1), FP64_RAND_V1(0) } }, \1877 /* 0*/{ { /*src2 */ { FP64_QNAN(0), FP64_RAND_V2(0), FP64_RAND_V0(1), FP64_RAND_V1(0) } }, \ 1892 1878 { /*src1 */ { FP64_QNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, \ 1893 1879 { /* => */ { FP64_QNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, \ … … 1984 1970 /*256:out */ X86_MXCSR_IE, \ 1985 1971 /*xcpt? */ true, true }, \ 1986 /* SNan, Normal ( Masked). */\1972 /* SNan, Normal (Unmasked). */ \ 1987 1973 { { /*src2 */ { FP64_SNAN(1), FP64_RAND_V0(1), FP64_RAND_V2(1), FP64_RAND_V2(0) } }, \ 1988 1974 { /*src1 */ { FP64_1(0), FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V3(1) } }, \ … … 3650 3636 /*256:out */ 0, 3651 3637 /*xcpt? */ false, false }, 3652 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },3653 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },3654 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },3655 /*mxcsr:in */ 0,3656 /*128:out */ 0,3657 /*256:out */ 0,3658 /*xcpt? */ false, false },3659 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },3660 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },3661 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },3662 /*mxcsr:in */ X86_MXCSR_RC_ZERO,3663 /*128:out */ X86_MXCSR_RC_ZERO,3664 /*256:out */ X86_MXCSR_RC_ZERO,3665 /*xcpt? */ false, false },3666 { { /*src2 */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } },3667 { /*src1 */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } },3668 { /* => */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } },3669 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,3670 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,3671 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,3672 /*xcpt? */ false, false },3673 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } },3674 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } },3675 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } },3676 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,3677 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,3678 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,3679 /*xcpt? */ false, false },3680 { { /*src2 */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } },3681 { /*src1 */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } },3682 { /* => */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } },3683 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,3684 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,3685 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,3686 /*xcpt? */ false, false },3638 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 3639 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 3640 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 3641 /*mxcsr:in */ 0, 3642 /*128:out */ 0, 3643 /*256:out */ 0, 3644 /*xcpt? */ false, false }, 3645 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 3646 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 3647 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 3648 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 3649 /*128:out */ X86_MXCSR_RC_ZERO, 3650 /*256:out */ X86_MXCSR_RC_ZERO, 3651 /*xcpt? */ false, false }, 3652 { { /*src2 */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } }, 3653 { /*src1 */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } }, 3654 { /* => */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } }, 3655 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 3656 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 3657 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 3658 /*xcpt? */ false, false }, 3659 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } }, 3660 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } }, 3661 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } }, 3662 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 3663 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 3664 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 3665 /*xcpt? */ false, false }, 3666 { { /*src2 */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } }, 3667 { /*src1 */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } }, 3668 { /* => */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } }, 3669 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 3670 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 3671 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 3672 /*xcpt? */ false, false }, 3687 3673 /* 3688 3674 * Infinity. … … 3858 3844 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 3859 3845 /*xcpt? */ false, false }, 3860 { { /*src2 */ { FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },3846 { { /*src2 */ { FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 3861 3847 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 3862 3848 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, … … 3986 3972 * Infinity. 3987 3973 */ 3988 /*5*/{ { /*src2 */ { FP64_INF(0), FP64_0(0), FP64_0(0), FP64_0(0) } },3974 /* 5*/{ { /*src2 */ { FP64_INF(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 3989 3975 { /*src1 */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, 3990 3976 { /* => */ { FP64_QNAN(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, … … 4170 4156 /*xcpt? */ false, false }, 4171 4157 #ifdef TODO_X86_MXCSR_UE_HW /** @todo THIS FAILS ON IEM: X86_MXCSR_UE not set in 128:out or 256:out */ 4172 4158 /* this is what works on HW (i7-10700) (same as below, plus 256:out:_UE) */ 4173 4159 /*--|28*/{ { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 4174 4160 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_DENORM_MAX(0), FP64_0(0) } }, … … 4180 4166 #endif /* TODO_X86_MXCSR_UE_HW */ 4181 4167 #ifdef TODO_X86_MXCSR_UE_IEM 4182 4168 /* for comparison, this is what works on IEM (same as above, minus 256:out:_UE) */ 4183 4169 /*--|28*/{ { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 4184 4170 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_DENORM_MAX(0), FP64_0(0) } }, … … 5061 5047 /*256:out */ X86_MXCSR_DAZ, 5062 5048 /*xcpt? */ false, false }, 5063 { { /*src2 */ { FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },5049 { { /*src2 */ { FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 5064 5050 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 5065 5051 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, … … 5154 5140 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 5155 5141 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 5156 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,5157 /*128:out */ X86_MXCSR_XCPT_MASK,5158 /*256:out */ X86_MXCSR_XCPT_MASK,5159 /*xcpt? */ false, false },5160 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },5161 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },5162 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },5163 5142 /*mxcsr:in */ 0, 5164 5143 /*128:out */ 0, … … 5196 5175 * Infinity. 5197 5176 */ 5198 /* 6*/{ { /*src2 */ { FP64_INF(0), FP64_INF(1), FP64_INF(0), FP64_INF(1) } },5177 /* 5*/{ { /*src2 */ { FP64_INF(0), FP64_INF(1), FP64_INF(0), FP64_INF(1) } }, 5199 5178 { /*src1 */ { FP64_INF(1), FP64_INF(0), FP64_0(0), FP64_0(0) } }, 5200 5179 { /* => */ { FP64_QNAN(1), FP64_QNAN(1), FP64_0(0), FP64_QNAN(1) } }, … … 5210 5189 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 5211 5190 /*xcpt? */ false, false }, 5212 { { /*src2 */ { FP64_INF(0), FP64_INF(1), FP64_INF(0),FP64_INF(1) } },5213 { /*src1 */ { FP64_INF(1), FP64_INF(0), FP64_0(0),FP64_0(0) } },5214 { /* => */ { FP64_QNAN(1), FP64_ 0(0), FP64_QNAN(1),FP64_QNAN(1) } },5191 { { /*src2 */ { FP64_INF(0), FP64_INF(1), FP64_INF(0), FP64_INF(1) } }, 5192 { /*src1 */ { FP64_INF(1), FP64_INF(0), FP64_0(0), FP64_0(0) } }, 5193 { /* => */ { FP64_QNAN(1), FP64_QNAN(1), FP64_0(0), FP64_QNAN(1) } }, 5215 5194 /*mxcsr:in */ X86_MXCSR_FZ, 5216 5195 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_IE, … … 5234 5213 * Overflow, Precision. 5235 5214 */ 5236 /*1 1*/{ { /*src2 */ { FP64_0(0), FP64_0(0), FP64_NORM_MIN(1), FP64_NORM_MIN(1) } },5215 /*10*/{ { /*src2 */ { FP64_0(0), FP64_0(0), FP64_NORM_MIN(1), FP64_NORM_MIN(1) } }, 5237 5216 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1) } }, 5238 { /* => */ { FP64_0(0), FP64_0(0), FP64_ 0(0), FP64_0(0)} },5217 { /* => */ { FP64_0(0), FP64_0(0), FP64_INF(1), FP64_V(1, 0, 2) } }, 5239 5218 /*mxcsr:in */ 0, 5240 5219 /*128:out */ 0, 5241 /*256:out */ X86_MXCSR_OE ,5220 /*256:out */ X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY, 5242 5221 /*xcpt? */ false, true }, 5243 5222 { { /*src2 */ { FP64_NORM_MIN(1), FP64_NORM_MIN(1), FP64_NORM_MAX(0), FP64_NORM_MAX(0) } }, … … 5245 5224 { /* => */ { FP64_INF(1), FP64_V(1, FP32_FRAC_NORM_MIN, FP32_EXP_NORM_MIN + 1), FP64_INF(1), FP64_INF(0) } }, 5246 5225 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM, 5247 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE ,5248 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE ,5226 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY, 5227 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY, 5249 5228 /*xcpt? */ false, false }, 5250 5229 { { /*src2 */ { FP64_NORM_MAX(1), FP64_NORM_MAX(0), FP64_0(0), FP64_0(0) } }, … … 5252 5231 { /* => */ { FP64_NORM_MAX(0), FP64_0(0), FP64_NORM_MAX(1), FP64_0(0) } }, 5253 5232 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO, 5254 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE ,5255 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE ,5233 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY, 5234 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY, 5256 5235 /*xcpt? */ false, false }, 5257 5236 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_0(0), FP64_NORM_MIN(1) } }, … … 5259 5238 { /* => */ { FP64_INF(0), FP64_0(0), FP64_V(1, 0, FP32_EXP_NORM_MIN + 1), FP64_NORM_MIN(1) } }, 5260 5239 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP, 5261 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE ,5262 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE ,5240 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY, 5241 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY, 5263 5242 /*xcpt? */ false, false }, 5264 5243 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_0(0), FP64_NORM_MAX(0) } }, … … 5273 5252 { /* => */ { FP64_V(1, 0, FP32_EXP_NORM_MIN + 1), FP64_NORM_MAX(0), FP64_V(0, 0, FP32_EXP_NORM_MIN + 1), FP64_NORM_MAX(0) } }, 5274 5253 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO, 5275 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE ,5276 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE ,5254 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY, 5255 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY, 5277 5256 /*xcpt? */ false, false }, 5278 5257 { { /*src2 */ { FP64_0(0), FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MIN(0) } }, … … 5280 5259 { /* => */ { FP64_V(1, FP64_FRAC_NORM_MAX, FP64_EXP_NORM_MAX), FP64_NORM_MAX(0), FP64_V(1, 0, FP32_EXP_NORM_MIN + 1), FP64_0(0) } }, 5281 5260 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO, 5282 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE ,5283 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE ,5261 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY, 5262 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY, 5284 5263 /*xcpt? */ false, false }, 5285 5264 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1) } }, 5286 5265 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_NORM_MAX(0), FP64_NORM_MAX(0) } }, 5287 { /* => */ { FP64_0(0), FP64_0(0), FP64_NORM_MAX(0), FP64_ NORM_MAX(1)} },5266 { /* => */ { FP64_0(0), FP64_0(0), FP64_NORM_MAX(0), FP64_0(0) } }, 5288 5267 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 5289 5268 /*128:out */ X86_MXCSR_RC_ZERO, 5290 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE ,5269 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY, 5291 5270 /*xcpt? */ false, true }, 5292 5271 { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(1) } }, … … 5300 5279 * Normals. 5301 5280 */ 5302 /* 20*/{ { /*src2 */ { FP64_NORM_MIN(0), FP64_NORM_MIN(1), FP64_NORM_V2(1), FP64_NORM_V2(0) } },5281 /*19*/{ { /*src2 */ { FP64_NORM_MIN(0), FP64_NORM_MIN(1), FP64_NORM_V2(1), FP64_NORM_V2(0) } }, 5303 5282 { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_V1(0), FP64_NORM_V1(1) } }, 5304 5283 { /* => */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_0(1) } }, … … 5345 5324 * Denormals. 5346 5325 */ 5347 /*2 6*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_DENORM_MAX(0), FP64_0(0) } },5326 /*25*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_DENORM_MAX(0), FP64_0(0) } }, 5348 5327 { /*src1 */ { FP64_0(0), FP64_DENORM_MAX(1), FP64_0(0), FP64_DENORM_MAX(1) } }, 5349 5328 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 5350 5329 /*mxcsr:in */ 0, 5351 /*128:out */ X86_MXCSR_DE, 5352 /*256:out */ X86_MXCSR_DE, 5330 /*128:out */ X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED, 5331 /*256:out */ X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED, 5332 /*xcpt? */ true, true }, 5333 #ifdef TODO_X86_MXCSR_UE_IEM /** @todo THIS FAILS ON IEM: X86_MXCSR_UE not set in 128:out or 256:out */ 5334 /*--|26*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_DENORM_MAX(0), FP64_0(0) } }, 5335 { /*src1 */ { FP64_0(0), FP64_DENORM_MAX(1), FP64_0(0), FP64_DENORM_MAX(1) } }, 5336 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 5337 /*mxcsr:in */ X86_MXCSR_DM, 5338 /*128:out */ X86_MXCSR_DM | X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 5339 /*256:out */ X86_MXCSR_DM | X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 5340 /*xcpt? */ true, true }, 5341 #endif /* TODO_X86_MXCSR_UE_IEM */ 5342 /*26|27*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_DENORM_MAX(0), FP64_0(0) } }, 5343 { /*src1 */ { FP64_0(0), FP64_DENORM_MAX(1), FP64_0(0), FP64_DENORM_MAX(1) } }, 5344 { /* => */ { FP64_DENORM_MAX(1), FP64_DENORM_MAX(0), FP64_DENORM_MAX(1), FP64_DENORM_MAX(0) } }, 5345 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_UM, 5346 /*128:out */ X86_MXCSR_DM | X86_MXCSR_UM | X86_MXCSR_DE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 5347 /*256:out */ X86_MXCSR_DM | X86_MXCSR_UM | X86_MXCSR_DE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 5353 5348 /*xcpt? */ true, true }, 5354 5349 { { /*src2 */ { FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(1), FP64_DENORM_MIN(1) } }, … … 5363 5358 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 5364 5359 /*mxcsr:in */ 0, 5365 /*128:out */ X86_MXCSR_DE, 5366 /*256:out */ X86_MXCSR_DE, 5360 /*128:out */ X86_MXCSR_DE | BS3_MXCSR_DM_FIXED, 5361 /*256:out */ X86_MXCSR_DE | BS3_MXCSR_DM_FIXED, 5362 /*xcpt? */ true, true }, 5363 #ifdef TODO_X86_MXCSR_UE_IEM /** @todo THIS FAILS ON IEM: X86_MXCSR_UE not set in 128:out or 256:out *AND* different output values */ 5364 /*--|30*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 5365 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0) } }, 5366 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, /* result on HW (i7-10700) */ 5367 // IEM: { /* => */ { FP64_0(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_0(0) } }, /* result on IEM */ 5368 /*mxcsr:in */ X86_MXCSR_DM, 5369 /*128:out */ X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 5370 /*256:out */ X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 5371 /*xcpt? */ true, true }, 5372 #endif /* TODO_X86_MXCSR_UE_IEM */ 5373 /*29|31*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 5374 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0) } }, 5375 { /* => */ { FP64_0(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_0(0) } }, 5376 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_UM, 5377 /*128:out */ X86_MXCSR_DE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 5378 /*256:out */ X86_MXCSR_DE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 5367 5379 /*xcpt? */ true, true }, 5368 5380 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_DENORM_MIN(1), FP64_DENORM_MAX(1) } }, … … 5378 5390 /*mxcsr:in */ 0, 5379 5391 /*128:out */ 0, 5380 /*256:out */ X86_MXCSR_DE ,5392 /*256:out */ X86_MXCSR_DE | BS3_MXCSR_DM_FIXED, 5381 5393 /*xcpt? */ false, true }, 5394 #ifdef TODO_X86_MXCSR_UE_IEM /** @todo THIS FAILS ON IEM: X86_MXCSR_UE not set in 128:out or 256:out */ 5395 /*--|34*/{ { /*src2 */ { FP64_0(0), FP64_0(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } }, 5396 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_DENORM_MIN(1), FP64_DENORM_MIN(1) } }, 5397 { /* => */ { FP64_0(0), FP64_0(0), FP64_V(1, 2, 0), FP64_V(0, 0xffffffffffffe, 1) } }, 5398 /*mxcsr:in */ X86_MXCSR_DM, 5399 /*128:out */ X86_MXCSR_DM, 5400 /*256:out */ X86_MXCSR_DM | X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 5401 /*xcpt? */ false, true }, 5402 #endif /* TODO_X86_MXCSR_UE_IEM */ 5403 /*32|35*/{ { /*src2 */ { FP64_0(0), FP64_0(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } }, 5404 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_DENORM_MIN(1), FP64_DENORM_MIN(1) } }, 5405 { /* => */ { FP64_0(0), FP64_0(0), FP64_V(1, 2, 0), FP64_V(0, 0xffffffffffffe, 1) } }, 5406 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_UM, 5407 /*128:out */ X86_MXCSR_DM | X86_MXCSR_UM, 5408 /*256:out */ X86_MXCSR_DM | X86_MXCSR_UM | X86_MXCSR_DE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 5409 /*xcpt? */ false, true }, 5382 5410 /* 5383 5411 * Invalids. 5384 5412 */ 5385 /*31*/ FP64_TABLE_D1_H_PD_INVALIDS5413 /*33|36*/ FP64_TABLE_D1_H_PD_INVALIDS 5386 5414 /** @todo Underflow; Precision; Rounding; FZ etc. */ 5387 5415 }; … … 5433 5461 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 5434 5462 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode); 5435 return bs3CpuInstr4_WorkerTestType1 (bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,5463 return bs3CpuInstr4_WorkerTestType1A(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 5436 5464 g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2)); 5437 5465 } … … 5776 5804 /*256:out */ X86_MXCSR_XCPT_MASK, 5777 5805 /*xcpt? */ false, false }, 5778 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },5779 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },5780 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },5806 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 5807 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 5808 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 5781 5809 /*mxcsr:in */ 0, 5782 5810 /*128:out */ 0, 5783 5811 /*256:out */ 0, 5784 5812 /*xcpt? */ false, false }, 5785 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },5786 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },5787 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },5813 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 5814 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 5815 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 5788 5816 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 5789 5817 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 5790 5818 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 5791 5819 /*xcpt? */ false, false }, 5792 { { /*src2 */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } },5793 { /*src1 */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } },5794 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },5820 { { /*src2 */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, 5821 { /*src1 */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, 5822 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 5795 5823 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 5796 5824 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 5797 5825 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 5798 5826 /*xcpt? */ false, false }, 5799 { { /*src2 */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(1) } },5800 { /*src1 */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(1) } },5801 { /* => */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_0(1) } },5827 { { /*src2 */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(1) } }, 5828 { /*src1 */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(1) } }, 5829 { /* => */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_0(1) } }, 5802 5830 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 5803 5831 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 5804 5832 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 5805 5833 /*xcpt? */ false, false }, 5806 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },5807 { /*src1 */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(0) } },5808 { /* => */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_0(1) } },5834 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 5835 { /*src1 */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(0) } }, 5836 { /* => */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_0(1) } }, 5809 5837 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 5810 5838 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, … … 5992 6020 /*xcpt? */ true, true }, 5993 6021 #ifdef TODO_X86_MXCSR_UE_HW /** @todo THIS FAILS ON IEM: X86_MXCSR_UE not set in 128:out or 256:out */ 5994 6022 /* this is what works on HW (i7-10700) (same as below, plus 256:out:_UE) */ 5995 6023 /*--|30*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 5996 6024 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, … … 6002 6030 #endif /* TODO_X86_MXCSR_UE_HW */ 6003 6031 #ifdef TODO_X86_MXCSR_UE_IEM 6004 6032 /* for comparison, this is what works on IEM (same as above, minus 256:out:_UE) */ 6005 6033 /*--|30*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 6006 6034 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, … … 6960 6988 /*256:out */ X86_MXCSR_DAZ, 6961 6989 /*xcpt? */ false, false }, 6962 { { /*src2 */ { FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },6990 { { /*src2 */ { FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 6963 6991 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 6964 6992 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, … … 7053 7081 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 7054 7082 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 7055 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,7056 /*128:out */ X86_MXCSR_XCPT_MASK,7057 /*256:out */ X86_MXCSR_XCPT_MASK,7058 /*xcpt? */ false, false },7059 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },7060 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },7061 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },7062 7083 /*mxcsr:in */ 0, 7063 7084 /*128:out */ 0, … … 7142 7163 /*12*/{ { /*src2 */ { FP64_0(0), FP64_0(0), FP64_NORM_MIN(0), FP64_NORM_MAX(0) } }, 7143 7164 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_NORM_MIN(1), FP64_NORM_MAX(1) } }, 7144 { /* => */ { FP64_0(0), FP64_0(0), FP64_ 0(0), FP64_0(0)} },7165 { /* => */ { FP64_0(0), FP64_0(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1) } }, 7145 7166 /*mxcsr:in */ 0, 7146 7167 /*128:out */ 0, … … 7157 7178 { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } }, 7158 7179 { /* => */ { FP64_0(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_1(0) } }, 7159 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO, 7160 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, 7161 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, 7180 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 7181 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | BS3_MXCSR_OM_FIXED, 7182 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | BS3_MXCSR_OM_FIXED, 7183 /*xcpt? */ false, false }, 7184 { { /*src2 */ { FP64_NORM_MAX(1), FP64_NORM_MAX(0), FP64_2(0), FP64_1(0) } }, 7185 { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } }, 7186 { /* => */ { FP64_0(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_1(0) } }, 7187 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_RC_ZERO, 7188 /*128:out */ X86_MXCSR_OM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_OM_FIXED, 7189 /*256:out */ X86_MXCSR_OM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_OM_FIXED, 7162 7190 /*xcpt? */ false, false }, 7163 7191 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_0(0), FP64_NORM_MIN(1) } }, 7164 7192 { /*src1 */ { FP64_0(0), FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MIN(0) } }, 7165 7193 { /* => */ { FP64_NORM_MAX(1), FP64_INF(0), FP64_V(1, 0, FP64_EXP_NORM_MIN + 1), FP64_NORM_MIN(0) } }, 7166 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP, 7167 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE, 7168 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE, 7194 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 7195 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_OE | BS3_MXCSR_OM_FIXED, 7196 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_OE | BS3_MXCSR_OM_FIXED, 7197 /*xcpt? */ false, false }, 7198 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_0(0), FP64_NORM_MIN(1) } }, 7199 { /*src1 */ { FP64_0(0), FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MIN(0) } }, 7200 { /* => */ { FP64_NORM_MAX(1), FP64_INF(0), FP64_V(1, 0, FP64_EXP_NORM_MIN + 1), FP64_NORM_MIN(0) } }, 7201 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_RC_UP, 7202 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_OM_FIXED, 7203 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_OM_FIXED, 7169 7204 /*xcpt? */ false, false }, 7170 7205 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_0(0), FP64_NORM_MAX(0) } }, … … 7182 7217 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, 7183 7218 /*xcpt? */ false, true }, 7184 { { /*src2 */ { FP64_0(0), FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MIN(0) } },7185 { /*src1 */ { FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MIN(1), FP64_1(1) } },7186 { /* => */ { FP64_0(0), FP64_NORM_MAX(1), FP64_ INF(0), FP64_NORM_MAX(1) } },7219 { { /*src2 */ { FP64_0(0), FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MIN(0) } }, 7220 { /*src1 */ { FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MIN(1), FP64_1(1) } }, 7221 { /* => */ { FP64_0(0), FP64_NORM_MAX(1), FP64_1(0), FP64_V(1, 0, FP64_EXP_NORM_MIN + 1) } }, 7187 7222 /*mxcsr:in */ 0, 7188 7223 /*128:out */ 0, … … 7206 7241 * Denormals. 7207 7242 */ 7208 /*2 1*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_DENORM_MAX(0), FP64_0(0) } },7243 /*23*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_DENORM_MAX(0), FP64_0(0) } }, 7209 7244 { /*src1 */ { FP64_0(0), FP64_DENORM_MAX(1), FP64_0(0), FP64_DENORM_MAX(1) } }, 7210 7245 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 7211 7246 /*mxcsr:in */ 0, 7212 /*128:out */ X86_MXCSR_DE, 7213 /*256:out */ X86_MXCSR_DE, 7247 /*128:out */ X86_MXCSR_DE | BS3_MXCSR_DM_FIXED, 7248 /*256:out */ X86_MXCSR_DE | BS3_MXCSR_DM_FIXED, 7249 /*xcpt? */ true, true }, 7250 #ifdef TODO_X86_MXCSR_UE_IEM /** @todo THIS FAILS ON IEM: X86_MXCSR_UE not set in 128:out or 256:out *AND* different output values */ 7251 /*--|24*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_DENORM_MAX(0), FP64_0(0) } }, 7252 { /*src1 */ { FP64_0(0), FP64_DENORM_MAX(1), FP64_0(0), FP64_DENORM_MAX(1) } }, 7253 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, /* result on HW (i7-10700) */ 7254 // IEM: { /* => */ { FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } }, /* result on IEM */ 7255 /*mxcsr:in */ X86_MXCSR_DM, 7256 /*128:out */ X86_MXCSR_DM | X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 7257 /*256:out */ X86_MXCSR_DM | X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 7258 /*xcpt? */ true, true }, 7259 #endif /* TODO_X86_MXCSR_UE_IEM */ 7260 /*24|25*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_DENORM_MAX(0), FP64_0(0) } }, 7261 { /*src1 */ { FP64_0(0), FP64_DENORM_MAX(1), FP64_0(0), FP64_DENORM_MAX(1) } }, 7262 { /* => */ { FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } }, 7263 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_UM, 7264 /*128:out */ X86_MXCSR_DM | X86_MXCSR_UM | X86_MXCSR_DE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 7265 /*256:out */ X86_MXCSR_DM | X86_MXCSR_UM | X86_MXCSR_DE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 7214 7266 /*xcpt? */ true, true }, 7215 7267 { { /*src2 */ { FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(1), FP64_DENORM_MIN(1) } }, … … 7220 7272 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK, 7221 7273 /*xcpt? */ false, false }, 7222 7274 /*26|27*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 7223 7275 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0) } }, 7224 7276 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 7225 7277 /*mxcsr:in */ 0, 7226 /*128:out */ X86_MXCSR_DE, 7227 /*256:out */ X86_MXCSR_DE, 7278 /*128:out */ X86_MXCSR_DE | BS3_MXCSR_DM_FIXED, 7279 /*256:out */ X86_MXCSR_DE | BS3_MXCSR_DM_FIXED, 7280 /*xcpt? */ true, true }, 7281 #ifdef TODO_X86_MXCSR_UE_IEM /** @todo THIS FAILS ON IEM: X86_MXCSR_UE not set in 128:out or 256:out *AND* different output values */ 7282 /*--|28*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 7283 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0) } }, 7284 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, /* result on HW (i7-10700) */ 7285 // IEM: { /* => */ { FP64_0(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_0(0) } }, /* result on IEM */ 7286 /*mxcsr:in */ X86_MXCSR_DM, 7287 /*128:out */ X86_MXCSR_DM | X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 7288 /*256:out */ X86_MXCSR_DM | X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 7289 /*xcpt? */ true, true }, 7290 #endif /* TODO_X86_MXCSR_UE_IEM */ 7291 /*27|29*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 7292 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0) } }, 7293 { /* => */ { FP64_0(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_0(0) } }, 7294 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_UM, 7295 /*128:out */ X86_MXCSR_DM | X86_MXCSR_UM | X86_MXCSR_DE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 7296 /*256:out */ X86_MXCSR_DM | X86_MXCSR_UM | X86_MXCSR_DE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 7228 7297 /*xcpt? */ true, true }, 7229 7298 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_DENORM_MIN(1), FP64_DENORM_MAX(1) } }, … … 7244 7313 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_DENORM_MIN(1), FP64_DENORM_MIN(1) } }, 7245 7314 { /* => */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_0(1) } }, 7246 /*mxcsr:in */ X86_MXCSR_ XCPT_FLAGS | X86_MXCSR_RC_DOWN,7247 /*128:out */ X86_MXCSR_ XCPT_FLAGS | X86_MXCSR_RC_DOWN,7248 /*256:out */ X86_MXCSR_ XCPT_FLAGS | X86_MXCSR_RC_DOWN | X86_MXCSR_DE,7315 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 7316 /*128:out */ X86_MXCSR_RC_DOWN, 7317 /*256:out */ X86_MXCSR_RC_DOWN | X86_MXCSR_DE, 7249 7318 /*xcpt? */ false, true }, 7250 7319 /* 7251 7320 * Invalids. 7252 7321 */ 7253 /*27*/ FP64_TABLE_D1_H_PD_INVALIDS7322 /*31|33*/ FP64_TABLE_D1_H_PD_INVALIDS 7254 7323 /** @todo Underflow; Precision; Rounding; FZ etc. */ 7255 7324 }; … … 7301 7370 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 7302 7371 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode); 7303 return bs3CpuInstr4_WorkerTestType1 (bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,7372 return bs3CpuInstr4_WorkerTestType1A(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 7304 7373 g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2)); 7305 7374 } … … 7319 7388 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 7320 7389 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 7321 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,7322 /*128:out */ X86_MXCSR_XCPT_MASK,7323 /*256:out */ X86_MXCSR_XCPT_MASK,7324 /*xcpt? */ false, false },7390 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 7391 /*128:out */ X86_MXCSR_XCPT_MASK, 7392 /*256:out */ X86_MXCSR_XCPT_MASK, 7393 /*xcpt? */ false, false }, 7325 7394 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 7326 7395 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, … … 7686 7755 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 7687 7756 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 7688 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,7689 /*128:out */ X86_MXCSR_XCPT_MASK,7690 /*256:out */ X86_MXCSR_XCPT_MASK,7691 /*xcpt? */ false, false },7692 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },7693 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },7694 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },7695 /*mxcsr:in */ 0,7696 /*128:out */ 0,7697 /*256:out */ 0,7698 /*xcpt? */ false, false },7699 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },7700 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },7701 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },7702 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,7703 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,7704 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,7705 /*xcpt? */ false, false },7706 { { /*src2 */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } },7707 { /*src1 */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } },7708 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },7709 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,7710 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,7711 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,7712 /*xcpt? */ false, false },7713 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(0) } },7714 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(0) } },7715 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },7716 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,7717 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,7718 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,7719 /*xcpt? */ false, false },7720 { { /*src2 */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } },7721 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(1) } },7722 { /* => */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(0) } },7723 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,7724 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,7725 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,7726 /*xcpt? */ false, false },7727 { { /*src2 */ { FP64_NORM_V0(0), FP64_NORM_V1(1), FP64_0(0), FP64_NORM_V3(1) } },7728 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_NORM_V2(1), FP64_0(1) } },7729 { /* => */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(0) } },7730 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,7731 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,7732 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,7733 /*xcpt? */ false, false },7757 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 7758 /*128:out */ X86_MXCSR_XCPT_MASK, 7759 /*256:out */ X86_MXCSR_XCPT_MASK, 7760 /*xcpt? */ false, false }, 7761 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 7762 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 7763 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 7764 /*mxcsr:in */ 0, 7765 /*128:out */ 0, 7766 /*256:out */ 0, 7767 /*xcpt? */ false, false }, 7768 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 7769 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 7770 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 7771 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 7772 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 7773 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 7774 /*xcpt? */ false, false }, 7775 { { /*src2 */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, 7776 { /*src1 */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, 7777 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 7778 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 7779 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 7780 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 7781 /*xcpt? */ false, false }, 7782 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(0) } }, 7783 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(0) } }, 7784 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 7785 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 7786 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 7787 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 7788 /*xcpt? */ false, false }, 7789 { { /*src2 */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } }, 7790 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(1) } }, 7791 { /* => */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(0) } }, 7792 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 7793 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 7794 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 7795 /*xcpt? */ false, false }, 7796 { { /*src2 */ { FP64_NORM_V0(0), FP64_NORM_V1(1), FP64_0(0), FP64_NORM_V3(1) } }, 7797 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_NORM_V2(1), FP64_0(1) } }, 7798 { /* => */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(0) } }, 7799 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 7800 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 7801 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 7802 /*xcpt? */ false, false }, 7734 7803 /* 7735 7804 * Infinity. … … 7738 7807 { /*src1 */ { FP64_INF(1), FP64_0(0), FP64_INF(0), FP64_0(0) } }, 7739 7808 { /* => */ { FP64_INF(1), FP64_0(0), FP64_INF(1), FP64_0(0) } }, 7740 /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,7741 /*128:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,7742 /*256:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,7743 /*xcpt? */ false, false },7809 /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM, 7810 /*128:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM, 7811 /*256:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM, 7812 /*xcpt? */ false, false }, 7744 7813 { { /*src2 */ { FP64_INF(0), FP64_INF(0), FP64_INF(1), FP64_INF(1) } }, 7745 7814 { /*src1 */ { FP64_INF(1), FP64_INF(0), FP64_INF(1), FP64_INF(0) } }, 7746 7815 { /* => */ { FP64_INF(1), FP64_INF(0), FP64_INF(0), FP64_INF(1) } }, 7747 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,7748 /*128:out */ X86_MXCSR_XCPT_MASK,7749 /*256:out */ X86_MXCSR_XCPT_MASK,7750 /*xcpt? */ false, false },7816 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 7817 /*128:out */ X86_MXCSR_XCPT_MASK, 7818 /*256:out */ X86_MXCSR_XCPT_MASK, 7819 /*xcpt? */ false, false }, 7751 7820 { { /*src2 */ { FP64_INF(0), FP64_INF(1), FP64_0(1), FP64_INF(0) } }, 7752 7821 { /*src1 */ { FP64_INF(1), FP64_INF(0), FP64_0(1), FP64_INF(0) } }, 7753 7822 { /* => */ { FP64_INF(1), FP64_INF(1), FP64_0(0), FP64_INF(0) } }, 7754 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,7755 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,7756 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,7757 /*xcpt? */ false, false },7823 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 7824 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 7825 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 7826 /*xcpt? */ false, false }, 7758 7827 { { /*src2 */ { FP64_INF(0), FP64_INF(1), FP64_0(1), FP64_INF(0) } }, 7759 7828 { /*src1 */ { FP64_INF(1), FP64_INF(0), FP64_0(1), FP64_INF(0) } }, 7760 7829 { /* => */ { FP64_INF(1), FP64_INF(1), FP64_0(0), FP64_INF(0) } }, 7761 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,7762 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,7763 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,7764 /*xcpt? */ false, false },7830 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 7831 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 7832 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 7833 /*xcpt? */ false, false }, 7765 7834 { { /*src2 */ { FP64_INF(0), FP64_INF(0), FP64_1(0), FP64_INF(0) } }, 7766 7835 { /*src1 */ { FP64_1(0), FP64_NORM_V0(0), FP64_INF(0), FP64_NORM_V1(0) } }, 7767 7836 { /* => */ { FP64_INF(0), FP64_INF(0), FP64_INF(0), FP64_INF(0) } }, 7768 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,7769 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,7770 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,7771 /*xcpt? */ false, false },7837 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 7838 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 7839 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 7840 /*xcpt? */ false, false }, 7772 7841 { { /*src2 */ { FP64_INF(1), FP64_INF(0), FP64_NORM_V3(0), FP64_INF(1) } }, 7773 7842 { /*src1 */ { FP64_1(1), FP64_NORM_V3(1), FP64_INF(1), FP64_NORM_V1(1) } }, 7774 7843 { /* => */ { FP64_INF(0), FP64_INF(1), FP64_INF(1), FP64_INF(0) } }, 7775 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,7776 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,7777 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,7778 /*xcpt? */ false, false },7844 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 7845 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 7846 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 7847 /*xcpt? */ false, false }, 7779 7848 /* 7780 7849 * Normals. … … 7783 7852 { /*src1 */ { FP64_1(0), FP64_V(0, 0x2d69a80000000, 0x413)/* 1234586.50*/, FP64_V(1, 0x4000000000000, 0x400)/* -2.50*/, FP64_V(0, 0xb800000000000, 0x402)/* 13.75000*/ } }, 7784 7853 { /* => */ { FP64_V(0, 0xe66f500000000, 0x40d)/*31131.828125*/, FP64_V(0, 0xfb74e1d800000, 0x41a)/*266053390.75*/, FP64_V(0, 0x549270a11c760, 0x42c)/* 46807863534478.75*/, FP64_V(0, 0x3c30944926c00, 0x424)/*169753086244.84375*/ } }, 7785 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,7786 /*128:out */ X86_MXCSR_XCPT_MASK,7787 /*256:out */ X86_MXCSR_XCPT_MASK,7788 /*xcpt? */ false, false },7854 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 7855 /*128:out */ X86_MXCSR_XCPT_MASK, 7856 /*256:out */ X86_MXCSR_XCPT_MASK, 7857 /*xcpt? */ false, false }, 7789 7858 { { /*src2 */ { FP64_NORM_MAX(1), FP64_NORM_V3(1), FP64_1(0), FP64_1(1) } }, 7790 7859 { /*src1 */ { FP64_1(1), FP64_1(0), FP64_NORM_V1(0), FP64_NORM_MIN(1) } }, 7791 7860 { /* => */ { FP64_NORM_MAX(0), FP64_NORM_V3(1), FP64_NORM_V1(0), FP64_NORM_MIN(0) } }, 7792 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,7793 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,7794 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,7795 /*xcpt? */ false, false },7861 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 7862 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 7863 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 7864 /*xcpt? */ false, false }, 7796 7865 { { /*src2 */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_V(1, 0x68b83b1ed4000, 0x41e)/*-3025935759.4140625*/, FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646*/, FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/ } }, 7797 7866 { /*src1 */ { FP64_V(0, 0x8000000000000, 0x3fe)/* 0.75*/, FP64_V(1, 0, 0x400)/* -2.0000000*/, FP64_1(0), FP64_V(0, 0x8000000000000, 0x400)/* 3.00*/ } }, 7798 7867 { /* => */ { FP64_V(0, 0x4da20a80c6990, 0x42e)/*183416666481484.50*/, FP64_V(0, 0x68b83b1ed4000, 0x41f)/* 6051871518.8281250*/, FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646*/, FP64_V(0, 0x4a6a82b05f744, 0x42f)/*363296296296308.25*/ } }, 7799 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,7800 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,7801 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,7802 /*xcpt? */ false, false },7868 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 7869 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 7870 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 7871 /*xcpt? */ false, false }, 7803 7872 { { /*src2 */ { FP64_1(0), FP64_1(0), FP64_NORM_SAFE_INT_MIN(0), FP64_1(0) } }, 7804 7873 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_1(0), FP64_NORM_SAFE_INT_MIN(1) } }, 7805 7874 { /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(1) } }, 7806 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,7807 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,7808 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,7809 /*xcpt? */ false, false },7875 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 7876 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 7877 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 7878 /*xcpt? */ false, false }, 7810 7879 { { /*src2 */ { FP64_NORM_V0(0), FP64_NORM_V1(1), FP64_NORM_V2(0), FP64_NORM_V3(1) } }, 7811 7880 { /*src1 */ { FP64_1(0), FP64_1(1), FP64_1(1), FP64_1(1) } }, 7812 7881 { /* => */ { FP64_NORM_V0(0), FP64_NORM_V1(0), FP64_NORM_V2(1), FP64_NORM_V3(0) } }, 7813 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,7814 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,7815 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,7816 /*xcpt? */ false, false },7882 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 7883 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 7884 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 7885 /*xcpt? */ false, false }, 7817 7886 /** @todo More Normals. */ 7818 7887 /* … … 7822 7891 { /*src1 */ { FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0), FP64_DENORM_MAX(0) } }, 7823 7892 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 7824 /*mxcsr:in */ 0,7825 /*128:out */ X86_MXCSR_DE,7826 /*256:out */ X86_MXCSR_DE,7827 /*xcpt? */ true, true },7893 /*mxcsr:in */ 0, 7894 /*128:out */ X86_MXCSR_DE, 7895 /*256:out */ X86_MXCSR_DE, 7896 /*xcpt? */ true, true }, 7828 7897 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0) } }, 7829 7898 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_DENORM_MIN(0) } }, 7830 7899 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 7831 /*mxcsr:in */ X86_MXCSR_FZ,7832 /*128:out */ X86_MXCSR_FZ,7833 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_DE,7834 /*xcpt? */ false, true },7900 /*mxcsr:in */ X86_MXCSR_FZ, 7901 /*128:out */ X86_MXCSR_FZ, 7902 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_DE, 7903 /*xcpt? */ false, true }, 7835 7904 { { /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0) } }, 7836 7905 { /*src1 */ { FP64_0(0), FP64_DENORM_MAX(0), FP64_0(0), FP64_DENORM_MIN(0) } }, 7837 7906 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 7838 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ,7839 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ,7840 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ,7841 /*xcpt? */ false, false },7907 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 7908 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 7909 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 7910 /*xcpt? */ false, false }, 7842 7911 { { /*src2 */ { FP64_DENORM_MAX(0), FP64_1(0), FP64_DENORM_MIN(0), FP64_1(0) } }, 7843 7912 { /*src1 */ { FP64_1(0), FP64_DENORM_MAX(0), FP64_1(0), FP64_DENORM_MIN(0) } }, … … 8373 8442 { /*src1 */ { FP64_1(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } }, 8374 8443 { /* => */ { FP64_V(0, 0xe66f500000000, 0x40d)/*31131.828125*/, FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } }, 8375 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,8376 /*128:out */ X86_MXCSR_XCPT_MASK,8377 /*256:out */ X86_MXCSR_XCPT_MASK,8378 /*xcpt? */ false, false },8444 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 8445 /*128:out */ X86_MXCSR_XCPT_MASK, 8446 /*256:out */ X86_MXCSR_XCPT_MASK, 8447 /*xcpt? */ false, false }, 8379 8448 { { /*src2 */ { FP64_V(0, 0xaf00000000000, 0x406)/* 215.50*/, FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } }, 8380 8449 { /*src1 */ { FP64_V(0, 0x2d69a80000000, 0x413)/* 1234586.50*/, FP64_RAND_V1(0), FP64_RAND_V1(1), FP64_RAND_V0(1) } }, 8381 8450 { /* => */ { FP64_V(0, 0xfb74e1d800000, 0x41a)/*266053390.75*/, FP64_RAND_V1(0), FP64_RAND_V1(1), FP64_RAND_V0(1) } }, 8382 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,8383 /*128:out */ X86_MXCSR_XCPT_MASK,8384 /*256:out */ X86_MXCSR_XCPT_MASK,8385 /*xcpt? */ false, false },8451 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 8452 /*128:out */ X86_MXCSR_XCPT_MASK, 8453 /*256:out */ X86_MXCSR_XCPT_MASK, 8454 /*xcpt? */ false, false }, 8386 8455 { { /*src2 */ { FP64_V(1, 0x107526e749f80, 0x42b)/*-18723145413791.50*/, FP64_RAND_V3(0), FP64_RAND_V1(0), FP64_RAND_V1(1) } }, 8387 8456 { /*src1 */ { FP64_V(1, 0x4000000000000, 0x400)/* -2.50*/, FP64_RAND_V0(0), FP64_RAND_V2(1), FP64_RAND_V2(1) } }, 8388 8457 { /* => */ { FP64_V(0, 0x549270a11c760, 0x42c)/* 46807863534478.75*/, FP64_RAND_V0(0), FP64_RAND_V2(1), FP64_RAND_V2(1) } }, 8389 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,8390 /*128:out */ X86_MXCSR_XCPT_MASK,8391 /*256:out */ X86_MXCSR_XCPT_MASK,8392 /*xcpt? */ false, false },8458 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 8459 /*128:out */ X86_MXCSR_XCPT_MASK, 8460 /*256:out */ X86_MXCSR_XCPT_MASK, 8461 /*xcpt? */ false, false }, 8393 8462 { { /*src2 */ { FP64_V(0, 0x6fee0e4bd0000, 0x420)/* 12345678999.62500*/, FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 8394 8463 { /*src1 */ { FP64_V(0, 0xb800000000000, 0x402)/* 13.75000*/, FP64_RAND_V2(0), FP64_RAND_V1(1), FP64_RAND_V3(1) } }, 8395 8464 { /* => */ { FP64_V(0, 0x3c30944926c00, 0x424)/*169753086244.84375*/, FP64_RAND_V2(0), FP64_RAND_V1(1), FP64_RAND_V3(1) } }, 8396 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,8397 /*128:out */ X86_MXCSR_XCPT_MASK,8398 /*256:out */ X86_MXCSR_XCPT_MASK,8399 /*xcpt? */ false, false },8465 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 8466 /*128:out */ X86_MXCSR_XCPT_MASK, 8467 /*256:out */ X86_MXCSR_XCPT_MASK, 8468 /*xcpt? */ false, false }, 8400 8469 { { /*src2 */ { FP64_NORM_MAX(1), FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } }, 8401 8470 { /*src1 */ { FP64_1(1), FP64_RAND_V1(1), FP64_RAND_V0(0), FP64_RAND_V2(0) } }, 8402 8471 { /* => */ { FP64_NORM_MAX(0), FP64_RAND_V1(1), FP64_RAND_V0(0), FP64_RAND_V2(0) } }, 8403 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,8404 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,8405 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,8406 /*xcpt? */ false, false },8472 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 8473 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 8474 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 8475 /*xcpt? */ false, false }, 8407 8476 { { /*src2 */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_RAND_V2(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 8408 8477 { /*src1 */ { FP64_V(0, 0x8000000000000, 0x3fe)/* 0.75*/, FP64_RAND_V1(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } }, 8409 8478 { /* => */ { FP64_V(0, 0x4da20a80c6990, 0x42e)/*183416666481484.50*/, FP64_RAND_V1(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } }, 8410 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,8411 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,8412 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,8413 /*xcpt? */ false, false },8479 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 8480 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 8481 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 8482 /*xcpt? */ false, false }, 8414 8483 { { /*src2 */ { FP64_V(1, 0x68b83b1ed4000, 0x41e)/*-3025935759.4140625*/, FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, 8415 8484 { /*src1 */ { FP64_V(1, 0, 0x400)/* -2.0000000*/, FP64_RAND_V2(0), FP64_RAND_V1(1), FP64_RAND_V3(1) } }, 8416 8485 { /* => */ { FP64_V(0, 0x68b83b1ed4000, 0x41f)/* 6051871518.8281250*/, FP64_RAND_V2(0), FP64_RAND_V1(1), FP64_RAND_V3(1) } }, 8417 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,8418 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,8419 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,8420 /*xcpt? */ false, false },8486 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 8487 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 8488 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 8489 /*xcpt? */ false, false }, 8421 8490 { { /*src2 */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 8422 8491 { /*src1 */ { FP64_V(0, 0x8000000000000, 0x400)/* 3.00*/, FP64_RAND_V1(1), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 8423 8492 { /* => */ { FP64_V(0, 0x4a6a82b05f744, 0x42f)/*363296296296308.25*/, FP64_RAND_V1(1), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 8424 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,8425 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,8426 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,8427 /*xcpt? */ false, false },8493 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 8494 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 8495 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 8496 /*xcpt? */ false, false }, 8428 8497 { { /*src2 */ { FP64_1(0), FP64_0(0), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_MAX(1) } }, 8429 8498 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_INF(1), FP64_NORM_SAFE_INT_MIN(1) } }, 8430 8499 { /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_INF(1), FP64_NORM_SAFE_INT_MIN(1) } }, 8431 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,8432 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,8433 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,8434 /*xcpt? */ false, false },8500 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 8501 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 8502 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 8503 /*xcpt? */ false, false }, 8435 8504 { { /*src2 */ { FP64_NORM_V0(0), FP64_NORM_V1(1), FP64_NORM_V2(0), FP64_NORM_V3(1) } }, 8436 8505 { /*src1 */ { FP64_1(0), FP64_SNAN(0), FP64_SNAN(1), FP64_QNAN(0) } }, 8437 8506 { /* => */ { FP64_NORM_V0(0), FP64_SNAN(0), FP64_SNAN(1), FP64_QNAN(0) } }, 8438 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,8439 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,8440 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,8441 /*xcpt? */ false, false },8507 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 8508 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 8509 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 8510 /*xcpt? */ false, false }, 8442 8511 /* 8443 8512 * Denormals. … … 8446 8515 { /*src1 */ { FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0), FP64_DENORM_MAX(0) } }, 8447 8516 { /* => */ { FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0), FP64_DENORM_MAX(0) } }, 8448 /*mxcsr:in */ 0,8449 /*128:out */ X86_MXCSR_DE,8450 /*256:out */ X86_MXCSR_DE,8451 /*xcpt? */ true, true },8517 /*mxcsr:in */ 0, 8518 /*128:out */ X86_MXCSR_DE, 8519 /*256:out */ X86_MXCSR_DE, 8520 /*xcpt? */ true, true }, 8452 8521 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 8453 8522 { /*src1 */ { FP64_DENORM_MIN(0), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 8454 8523 { /* => */ { FP64_0(0), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 8455 /*mxcsr:in */ X86_MXCSR_FZ,8456 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_DE,8457 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_DE,8458 /*xcpt? */ true, true },8524 /*mxcsr:in */ X86_MXCSR_FZ, 8525 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_DE, 8526 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_DE, 8527 /*xcpt? */ true, true }, 8459 8528 { { /*src2 */ { FP64_DENORM_MAX(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 8460 8529 { /*src1 */ { FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 8461 8530 { /* => */ { FP64_0(0), FP64_RAND_V1(1), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 8462 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ,8463 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ,8464 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ,8465 /*xcpt? */ false, false },8531 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 8532 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 8533 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 8534 /*xcpt? */ false, false }, 8466 8535 { { /*src2 */ { FP64_DENORM_MAX(0), FP64_RAND_V2(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 8467 8536 { /*src1 */ { FP64_1(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V3(1) } }, … … 8993 9062 { /*src1 */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } }, 8994 9063 { /* => */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(0) } }, 8995 /*mxcsr:in */ 0,8996 /*128:out */ 0,8997 /*256:out */ 0,8998 /*xcpt? */ false, false },9064 /*mxcsr:in */ 0, 9065 /*128:out */ 0, 9066 /*256:out */ 0, 9067 /*xcpt? */ false, false }, 8999 9068 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(1) } }, 9000 9069 { /*src1 */ { FP64_INF(0), FP64_INF(1), FP64_INF(0), FP64_INF(1) } }, 9001 9070 { /* => */ { FP64_INF(0), FP64_INF(1), FP64_INF(1), FP64_INF(0) } }, 9002 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,9003 /*128:out */ X86_MXCSR_XCPT_MASK,9004 /*256:out */ X86_MXCSR_XCPT_MASK,9005 /*xcpt? */ false, false },9071 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 9072 /*128:out */ X86_MXCSR_XCPT_MASK, 9073 /*256:out */ X86_MXCSR_XCPT_MASK, 9074 /*xcpt? */ false, false }, 9006 9075 { { /*src2 */ { FP64_INF(0), FP64_INF(0), FP64_INF(1), FP64_INF(1) } }, 9007 9076 { /*src1 */ { FP64_INF(0), FP64_INF(1), FP64_INF(0), FP64_INF(1) } }, 9008 9077 { /* => */ { FP64_QNAN(1), FP64_QNAN(1), FP64_QNAN(1), FP64_QNAN(1) } }, 9009 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,9010 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,9011 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,9012 /*xcpt? */ true, true },9078 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 9079 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 9080 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 9081 /*xcpt? */ true, true }, 9013 9082 { { /*src2 */ { FP64_INF(0), FP64_INF(0), FP64_INF(1), FP64_INF(1) } }, 9014 9083 { /*src1 */ { FP64_INF(0), FP64_INF(1), FP64_INF(0), FP64_INF(1) } }, 9015 9084 { /* => */ { FP64_QNAN(1), FP64_QNAN(1), FP64_QNAN(1), FP64_QNAN(1) } }, 9016 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,9017 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,9018 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,9019 /*xcpt? */ false, false },9085 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 9086 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 9087 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 9088 /*xcpt? */ false, false }, 9020 9089 { { /*src2 */ { FP64_INF(0), FP64_INF(0), FP64_1(1), FP64_NORM_V1(1) } }, 9021 9090 { /*src1 */ { FP64_1(0), FP64_NORM_V0(1), FP64_INF(0), FP64_INF(1) } }, 9022 9091 { /* => */ { FP64_0(0), FP64_0(1), FP64_INF(1), FP64_INF(0) } }, 9023 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,9024 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,9025 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,9026 /*xcpt? */ false, false },9092 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 9093 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 9094 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 9095 /*xcpt? */ false, false }, 9027 9096 { { /*src2 */ { FP64_INF(0), FP64_INF(0), FP64_1(1), FP64_NORM_V2(1) } }, 9028 9097 { /*src1 */ { FP64_1(0), FP64_NORM_V3(1), FP64_INF(0), FP64_INF(1) } }, 9029 9098 { /* => */ { FP64_0(0), FP64_0(1), FP64_INF(1), FP64_INF(0) } }, 9030 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,9031 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,9032 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,9033 /*xcpt? */ false, false },9099 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 9100 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 9101 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 9102 /*xcpt? */ false, false }, 9034 9103 /* 9035 9104 * Normals. … … 9038 9107 { /*src1 */ { FP64_V(0, 0xe66f500000000, 0x40d)/*31131.828125*/, FP64_V(0, 0xfb74e1d800000, 0x41a)/*266053390.75*/, FP64_V(0, 0x549270a11c760, 0x42c)/* 46807863534478.75*/, FP64_V(0, 0x3c30944926c00, 0x424)/*169753086244.84375*/ } }, 9039 9108 { /* => */ { FP64_1(0), FP64_V(0, 0x2d69a80000000, 0x413)/* 1234586.50*/, FP64_V(1, 0x4000000000000, 0x400)/* -2.50*/, FP64_V(0, 0xb800000000000, 0x402)/* 13.75000*/ } }, 9040 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,9041 /*128:out */ X86_MXCSR_XCPT_MASK,9042 /*256:out */ X86_MXCSR_XCPT_MASK,9043 /*xcpt? */ false, false },9109 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 9110 /*128:out */ X86_MXCSR_XCPT_MASK, 9111 /*256:out */ X86_MXCSR_XCPT_MASK, 9112 /*xcpt? */ false, false }, 9044 9113 { { /*src2 */ { FP64_NORM_MAX(1), FP64_NORM_V3(1), FP64_1(0), FP64_1(1) } }, 9045 9114 { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_V3(1), FP64_NORM_V1(0), FP64_NORM_MIN(0) } }, 9046 9115 { /* => */ { FP64_1(1), FP64_1(0), FP64_NORM_V1(0), FP64_NORM_MIN(1) } }, 9047 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,9048 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,9049 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,9050 /*xcpt? */ false, false },9116 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 9117 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 9118 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 9119 /*xcpt? */ false, false }, 9051 9120 { { /*src2 */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_V(1, 0x68b83b1ed4000, 0x41e)/*-3025935759.4140625*/, FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646*/, FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/ } }, 9052 9121 { /*src1 */ { FP64_V(0, 0x4da20a80c6990, 0x42e)/*183416666481484.50*/, FP64_V(0, 0x68b83b1ed4000, 0x41f)/* 6051871518.8281250*/, FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646*/, FP64_V(0, 0x4a6a82b05f744, 0x42f)/*363296296296308.25*/ } }, 9053 9122 { /* => */ { FP64_V(0, 0x8000000000000, 0x3fe)/* 0.75*/, FP64_V(1, 0, 0x400)/* -2.0000000*/, FP64_1(0), FP64_V(0, 0x8000000000000, 0x400)/* 3.00*/ } }, 9054 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,9055 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,9056 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,9057 /*xcpt? */ false, false },9123 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 9124 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 9125 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 9126 /*xcpt? */ false, false }, 9058 9127 { { /*src2 */ { FP64_1(0), FP64_1(0), FP64_NORM_SAFE_INT_MIN(0), FP64_1(0) } }, 9059 9128 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(1) } }, 9060 9129 { /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_1(0), FP64_NORM_SAFE_INT_MIN(1) } }, 9061 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,9062 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,9063 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,9064 /*xcpt? */ false, false },9130 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 9131 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 9132 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 9133 /*xcpt? */ false, false }, 9065 9134 { { /*src2 */ { FP64_NORM_V0(0), FP64_NORM_V1(1), FP64_NORM_V2(0), FP64_NORM_V3(1) } }, 9066 9135 { /*src1 */ { FP64_NORM_V0(0), FP64_NORM_V1(0), FP64_NORM_V2(1), FP64_NORM_V3(0) } }, 9067 9136 { /* => */ { FP64_1(0), FP64_1(1), FP64_1(1), FP64_1(1) } }, 9068 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,9069 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,9070 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,9071 /*xcpt? */ false, false },9137 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 9138 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 9139 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 9140 /*xcpt? */ false, false }, 9072 9141 /** @todo More Normals. */ 9073 9142 /* … … 9077 9146 { /*src1 */ { FP64_0(1), FP64_DENORM_MIN(1), FP64_0(0), FP64_DENORM_MAX(0),} }, 9078 9147 { /* => */ { FP64_0(0), FP64_1(1), FP64_0(1), FP64_1(0) } }, 9079 /*mxcsr:in */ 0,9080 /*128:out */ X86_MXCSR_DE,9081 /*256:out */ X86_MXCSR_DE,9082 /*xcpt? */ true, true },9148 /*mxcsr:in */ 0, 9149 /*128:out */ X86_MXCSR_DE, 9150 /*256:out */ X86_MXCSR_DE, 9151 /*xcpt? */ true, true }, 9083 9152 { { /*src2 */ { FP64_1(0), FP64_1(1), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0) } }, 9084 9153 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 9085 9154 { /* => */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(0) } }, 9086 /*mxcsr:in */ X86_MXCSR_FZ,9087 /*128:out */ X86_MXCSR_FZ,9088 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_DE,9089 /*xcpt? */ false, true },9155 /*mxcsr:in */ X86_MXCSR_FZ, 9156 /*128:out */ X86_MXCSR_FZ, 9157 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_DE, 9158 /*xcpt? */ false, true }, 9090 9159 { { /*src2 */ { FP64_1(0), FP64_1(1), FP64_1(0), FP64_1(0) } }, 9091 9160 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0) } }, 9092 9161 { /* => */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(0) } }, 9093 /*mxcsr:in */ X86_MXCSR_FZ,9094 /*128:out */ X86_MXCSR_FZ,9095 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_DE | X86_MXCSR_UE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* i7-10700, IEM */,9096 /*xcpt? */ false, true },9162 /*mxcsr:in */ X86_MXCSR_FZ, 9163 /*128:out */ X86_MXCSR_FZ, 9164 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_DE | X86_MXCSR_UE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* i7-10700, IEM */, 9165 /*xcpt? */ false, true }, 9097 9166 #ifdef TODO_X86_MXCSR_UE /** @todo THIS FAILS ON IEM: X86_MXCSR_UE not set in 256:out */ 9098 9167 /*--|21*/{ { /*src2 */ { FP64_1(0), FP64_1(1), FP64_1(0), FP64_1(0) } }, 9099 9168 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0) } }, 9100 9169 { /* => */ { FP64_0(0), FP64_0(1), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0) } }, 9101 /*mxcsr:in */ 0,9102 /*128:out */ 0,9103 /*256:out */ X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_UM_FIXED,9104 /*xcpt? */ false, false },9170 /*mxcsr:in */ 0, 9171 /*128:out */ 0, 9172 /*256:out */ X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_UM_FIXED, 9173 /*xcpt? */ false, false }, 9105 9174 #endif /* TODO_X86_MXCSR_UE */ 9106 9175 /*21|22*/{ { /*src2 */ { FP64_1(0), FP64_1(1), FP64_1(0), FP64_1(0) } }, 9107 9176 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0) } }, 9108 9177 { /* => */ { FP64_0(0), FP64_0(1), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0) } }, 9109 /*mxcsr:in */ X86_MXCSR_UM,9110 /*128:out */ X86_MXCSR_UM,9111 /*256:out */ X86_MXCSR_DE | BS3_MXCSR_UM_FIXED,9112 /*xcpt? */ false, false },9178 /*mxcsr:in */ X86_MXCSR_UM, 9179 /*128:out */ X86_MXCSR_UM, 9180 /*256:out */ X86_MXCSR_DE | BS3_MXCSR_UM_FIXED, 9181 /*xcpt? */ false, false }, 9113 9182 #ifdef TODO_X86_MXCSR_UE /** @todo THIS FAILS ON IEM: X86_MXCSR_UE not set in 256:out */ 9114 9183 /*--|23*/{ { /*src2 */ { FP64_1(0), FP64_1(1), FP64_1(0), FP64_1(0) } }, 9115 9184 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0) } }, 9116 9185 { /* => */ { FP64_0(0), FP64_0(1), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0) } }, 9117 /*mxcsr:in */ X86_MXCSR_DM,9118 /*128:out */ X86_MXCSR_DM,9119 /*256:out */ X86_MXCSR_DM | X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_UM_FIXED,9120 /*xcpt? */ false, true },9186 /*mxcsr:in */ X86_MXCSR_DM, 9187 /*128:out */ X86_MXCSR_DM, 9188 /*256:out */ X86_MXCSR_DM | X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_UM_FIXED, 9189 /*xcpt? */ false, true }, 9121 9190 #endif /* TODO_X86_MXCSR_UE */ 9122 9191 /*22|24*/{ { /*src2 */ { FP64_1(0), FP64_1(1), FP64_1(0), FP64_1(0) } }, 9123 9192 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0) } }, 9124 9193 { /* => */ { FP64_0(0), FP64_0(1), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0) } }, 9125 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_UM,9126 /*128:out */ X86_MXCSR_DM | X86_MXCSR_UM,9127 /*256:out */ X86_MXCSR_DM | X86_MXCSR_UM | X86_MXCSR_DE | BS3_MXCSR_UM_FIXED,9128 /*xcpt? */ false, true },9194 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_UM, 9195 /*128:out */ X86_MXCSR_DM | X86_MXCSR_UM, 9196 /*256:out */ X86_MXCSR_DM | X86_MXCSR_UM | X86_MXCSR_DE | BS3_MXCSR_UM_FIXED, 9197 /*xcpt? */ false, true }, 9129 9198 { { /*src2 */ { FP64_1(0), FP64_1(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0) } }, 9130 9199 { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_0(0), FP64_1(1) } }, 9131 9200 { /* => */ { FP64_0(0), FP64_0(0), FP64_QNAN(1), FP64_INF(1) } }, 9132 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ,9133 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ,9134 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE | X86_MXCSR_ZE,9135 /*xcpt? */ false, true },9201 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 9202 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 9203 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE | X86_MXCSR_ZE, 9204 /*xcpt? */ false, true }, 9136 9205 { { /*src2 */ { FP64_1(0), FP64_1(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0),} }, 9137 9206 { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_1(0), FP64_1(0) } }, … … 9711 9780 { /*src1 */ { FP64_V(0, 0xe66f500000000, 0x40d)/*31131.828125*/, FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } }, 9712 9781 { /* => */ { FP64_1(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } }, 9713 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,9714 /*128:out */ X86_MXCSR_XCPT_MASK,9715 /*256:out */ X86_MXCSR_XCPT_MASK,9716 /*xcpt? */ false, false },9782 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 9783 /*128:out */ X86_MXCSR_XCPT_MASK, 9784 /*256:out */ X86_MXCSR_XCPT_MASK, 9785 /*xcpt? */ false, false }, 9717 9786 { { /*src2 */ { FP64_V(0, 0xaf00000000000, 0x406)/* 215.50*/, FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } }, 9718 9787 { /*src1 */ { FP64_V(0, 0xfb74e1d800000, 0x41a)/*266053390.75*/, FP64_RAND_V1(0), FP64_RAND_V1(1), FP64_RAND_V0(1) } }, 9719 9788 { /* => */ { FP64_V(0, 0x2d69a80000000, 0x413)/* 1234586.50*/, FP64_RAND_V1(0), FP64_RAND_V1(1), FP64_RAND_V0(1) } }, 9720 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,9721 /*128:out */ X86_MXCSR_XCPT_MASK,9722 /*256:out */ X86_MXCSR_XCPT_MASK,9723 /*xcpt? */ false, false },9789 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 9790 /*128:out */ X86_MXCSR_XCPT_MASK, 9791 /*256:out */ X86_MXCSR_XCPT_MASK, 9792 /*xcpt? */ false, false }, 9724 9793 { { /*src2 */ { FP64_V(1, 0x107526e749f80, 0x42b)/*-18723145413791.50*/, FP64_RAND_V3(0), FP64_RAND_V1(0), FP64_RAND_V1(1) } }, 9725 9794 { /*src1 */ { FP64_V(0, 0x549270a11c760, 0x42c)/* 46807863534478.75*/, FP64_RAND_V0(0), FP64_RAND_V2(1), FP64_RAND_V2(1) } }, 9726 9795 { /* => */ { FP64_V(1, 0x4000000000000, 0x400)/* -2.50*/, FP64_RAND_V0(0), FP64_RAND_V2(1), FP64_RAND_V2(1) } }, 9727 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,9728 /*128:out */ X86_MXCSR_XCPT_MASK,9729 /*256:out */ X86_MXCSR_XCPT_MASK,9730 /*xcpt? */ false, false },9796 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 9797 /*128:out */ X86_MXCSR_XCPT_MASK, 9798 /*256:out */ X86_MXCSR_XCPT_MASK, 9799 /*xcpt? */ false, false }, 9731 9800 { { /*src2 */ { FP64_V(0, 0x6fee0e4bd0000, 0x420)/* 12345678999.62500*/, FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 9732 9801 { /*src1 */ { FP64_V(0, 0x3c30944926c00, 0x424)/*169753086244.84375*/, FP64_RAND_V2(0), FP64_RAND_V1(1), FP64_RAND_V3(1) } }, 9733 9802 { /* => */ { FP64_V(0, 0xb800000000000, 0x402)/* 13.75000*/, FP64_RAND_V2(0), FP64_RAND_V1(1), FP64_RAND_V3(1) } }, 9734 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,9735 /*128:out */ X86_MXCSR_XCPT_MASK,9736 /*256:out */ X86_MXCSR_XCPT_MASK,9737 /*xcpt? */ false, false },9803 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 9804 /*128:out */ X86_MXCSR_XCPT_MASK, 9805 /*256:out */ X86_MXCSR_XCPT_MASK, 9806 /*xcpt? */ false, false }, 9738 9807 { { /*src2 */ { FP64_NORM_MAX(1), FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } }, 9739 9808 { /*src1 */ { FP64_NORM_MAX(0), FP64_RAND_V1(1), FP64_RAND_V0(0), FP64_RAND_V2(0) } }, 9740 9809 { /* => */ { FP64_1(1), FP64_RAND_V1(1), FP64_RAND_V0(0), FP64_RAND_V2(0) } }, 9741 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,9742 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,9743 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,9744 /*xcpt? */ false, false },9810 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 9811 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 9812 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 9813 /*xcpt? */ false, false }, 9745 9814 { { /*src2 */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_RAND_V2(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 9746 9815 { /*src1 */ { FP64_V(0, 0x4da20a80c6990, 0x42e)/*183416666481484.50*/, FP64_RAND_V1(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } }, 9747 9816 { /* => */ { FP64_V(0, 0x8000000000000, 0x3fe)/* 0.75*/, FP64_RAND_V1(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } }, 9748 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,9749 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,9750 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,9751 /*xcpt? */ false, false },9817 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 9818 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 9819 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 9820 /*xcpt? */ false, false }, 9752 9821 { { /*src2 */ { FP64_V(1, 0x68b83b1ed4000, 0x41e)/*-3025935759.4140625*/, FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, 9753 9822 { /*src1 */ { FP64_V(0, 0x68b83b1ed4000, 0x41f)/* 6051871518.8281250*/, FP64_RAND_V2(0), FP64_RAND_V1(1), FP64_RAND_V3(1) } }, 9754 9823 { /* => */ { FP64_V(1, 0, 0x400)/* -2.0000000*/, FP64_RAND_V2(0), FP64_RAND_V1(1), FP64_RAND_V3(1) } }, 9755 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,9756 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,9757 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,9758 /*xcpt? */ false, false },9824 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 9825 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 9826 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 9827 /*xcpt? */ false, false }, 9759 9828 { { /*src2 */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 9760 9829 { /*src1 */ { FP64_V(0, 0x4a6a82b05f744, 0x42f)/*363296296296308.25*/, FP64_RAND_V1(1), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 9761 9830 { /* => */ { FP64_V(0, 0x8000000000000, 0x400)/* 3.00*/, FP64_RAND_V1(1), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 9762 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,9763 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,9764 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,9765 /*xcpt? */ false, false },9831 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 9832 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 9833 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 9834 /*xcpt? */ false, false }, 9766 9835 { { /*src2 */ { FP64_1(0), FP64_0(0), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_MAX(1) } }, 9767 9836 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_INF(1), FP64_NORM_SAFE_INT_MIN(1) } }, 9768 9837 { /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_INF(1), FP64_NORM_SAFE_INT_MIN(1) } }, 9769 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,9770 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,9771 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,9772 /*xcpt? */ false, false },9838 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 9839 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 9840 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 9841 /*xcpt? */ false, false }, 9773 9842 { { /*src2 */ { FP64_NORM_V0(0), FP64_NORM_V1(1), FP64_NORM_V2(0), FP64_NORM_V3(1) } }, 9774 9843 { /*src1 */ { FP64_NORM_V0(0), FP64_SNAN(0), FP64_SNAN(1), FP64_QNAN(0) } }, 9775 9844 { /* => */ { FP64_1(0), FP64_SNAN(0), FP64_SNAN(1), FP64_QNAN(0) } }, 9776 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,9777 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,9778 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,9779 /*xcpt? */ false, false },9845 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 9846 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 9847 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 9848 /*xcpt? */ false, false }, 9780 9849 /* 9781 9850 * Denormals. … … 9785 9854 { /*src1 */ { FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0), FP64_DENORM_MAX(0) } }, 9786 9855 { /* => */ { FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0), FP64_DENORM_MAX(0) } }, 9787 /*mxcsr:in */ 0,9788 /*128:out */ X86_MXCSR_DE,9789 /*256:out */ X86_MXCSR_DE,9790 /*xcpt? */ true, true },9856 /*mxcsr:in */ 0, 9857 /*128:out */ X86_MXCSR_DE, 9858 /*256:out */ X86_MXCSR_DE, 9859 /*xcpt? */ true, true }, 9791 9860 { { /* MASKED: 0 / DENORM_MAX = 0 &_DE */ 9792 9861 /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0) } }, 9793 9862 { /*src1 */ { FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0), FP64_DENORM_MAX(0) } }, 9794 9863 { /* => */ { FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0), FP64_DENORM_MAX(0) } }, 9795 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,9796 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,9797 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,9798 /*xcpt? */ false, false },9864 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 9865 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, 9866 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, 9867 /*xcpt? */ false, false }, 9799 9868 { { /* UNMASKED: DENORM_MAX / -0 = -INF &&_ZE */ 9800 9869 /*src2 */ { FP64_0(1), FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0) } }, 9801 9870 { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_0(0), FP64_DENORM_MAX(0) } }, 9802 9871 { /* => */ { FP64_INF(1), FP64_DENORM_MIN(0), FP64_0(0), FP64_DENORM_MAX(0) } }, 9803 /*mxcsr:in */ 0,9804 /*128:out */ X86_MXCSR_ZE,9805 /*256:out */ X86_MXCSR_ZE,9806 /*xcpt? */ true, true },9872 /*mxcsr:in */ 0, 9873 /*128:out */ X86_MXCSR_ZE, 9874 /*256:out */ X86_MXCSR_ZE, 9875 /*xcpt? */ true, true }, 9807 9876 { { /* MASKED: -DENORM_MAX / -0 = INF &_ZE */ 9808 9877 /*src2 */ { FP64_0(1), FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0) } }, 9809 9878 { /*src1 */ { FP64_DENORM_MAX(1), FP64_DENORM_MIN(0), FP64_0(0), FP64_DENORM_MAX(0) } }, 9810 9879 { /* => */ { FP64_INF(0), FP64_DENORM_MIN(0), FP64_0(0), FP64_DENORM_MAX(0) } }, 9811 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,9812 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_ZE,9813 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_ZE,9814 /*xcpt? */ false, false },9880 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 9881 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_ZE, 9882 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_ZE, 9883 /*xcpt? */ false, false }, 9815 9884 { { /* MASKED: -DENORM_MAX / DENORM_MIN = (-huge) &_DE */ 9816 9885 /*src2 */ { FP64_DENORM_MIN(0), FP64_0(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 9817 9886 { /*src1 */ { FP64_DENORM_MAX(1), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 9818 9887 { /* => */ { FP64_V(1, 0xffffffffffffe, 0x432)/*-4503599627370495.0*/, FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 9819 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,9820 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP | X86_MXCSR_DE,9821 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP | X86_MXCSR_DE,9822 /*xcpt? */ false, false },9888 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, 9889 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP | X86_MXCSR_DE, 9890 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP | X86_MXCSR_DE, 9891 /*xcpt? */ false, false }, 9823 9892 { { /* UNMASKED: -DENORM_MAX / -DENORM_MIN = (huge) &&_DE */ 9824 9893 /*src2 */ { FP64_DENORM_MIN(1), FP64_0(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 9825 9894 { /*src1 */ { FP64_DENORM_MAX(1), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 9826 9895 { /* => */ { FP64_V(0, 0xffffffffffffe, 0x432)/*4503599627370495.0*/, FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 9827 /*mxcsr:in */ X86_MXCSR_RC_UP,9828 /*128:out */ X86_MXCSR_RC_UP | X86_MXCSR_DE,9829 /*256:out */ X86_MXCSR_RC_UP | X86_MXCSR_DE,9830 /*xcpt? */ true, true },9896 /*mxcsr:in */ X86_MXCSR_RC_UP, 9897 /*128:out */ X86_MXCSR_RC_UP | X86_MXCSR_DE, 9898 /*256:out */ X86_MXCSR_RC_UP | X86_MXCSR_DE, 9899 /*xcpt? */ true, true }, 9831 9900 { { /* MASKED: -DENORM_MIN / DENORM_MAX = (-tiny) &_DE,_PE */ 9832 9901 /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 9833 9902 { /*src1 */ { FP64_DENORM_MIN(1), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 9834 9903 { /* => */ { FP64_V(1, 0x0000000000001, 0x3cb)/*-22204460492503135739e-35*/, FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 9835 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,9836 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_PE,9837 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_PE,9838 /*xcpt? */ false, false },9904 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 9905 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_PE, 9906 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_PE, 9907 /*xcpt? */ false, false }, 9839 9908 { { /* MASKED: -0 / DENORM_MIN = -0 &_DE */ 9840 9909 /*src2 */ { FP64_DENORM_MIN(0), FP64_0(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 9841 9910 { /*src1 */ { FP64_0(1), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 9842 9911 { /* => */ { FP64_0(1), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 9843 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,9844 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,9845 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,9846 /*xcpt? */ false, false },9912 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 9913 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, 9914 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, 9915 /*xcpt? */ false, false }, 9847 9916 { { /* MASKED: -0.25 / DENORM_MAX = (-HUGE) &_DE &_PE */ 9848 9917 /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 9849 9918 { /*src1 */ { FP64_V(1, 0, 0x3fd)/*0.25*/, FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 9850 9919 { /* => */ { FP64_V(1, 1, 0x7fb)/*1.1XYZe307*/, FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 9851 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,9852 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_PE,9853 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_PE,9854 /*xcpt? */ false, false },9920 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 9921 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_PE, 9922 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_PE, 9923 /*xcpt? */ false, false }, 9855 9924 { { /* MASKED: 42.0 / DENORM_MIN = INF &_DE &_PE &_OE */ 9856 9925 /*src2 */ { FP64_DENORM_MIN(0), FP64_0(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 9857 9926 { /*src1 */ { FP64_V(0, 0x5000000000000, 0x404)/*42.0*/, FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 9858 9927 { /* => */ { FP64_INF(0), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 9859 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,9860 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_OE,9861 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_OE,9862 /*xcpt? */ false, false },9928 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 9929 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_OE, 9930 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_OE, 9931 /*xcpt? */ false, false }, 9863 9932 { { /* ~OMASKED: 42.0 / DENORM_MIN = INF &_DE &&_OE */ 9864 9933 /*src2 */ { FP64_DENORM_MIN(0), FP64_0(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 9865 9934 { /*src1 */ { FP64_V(0, 0x5000000000000, 0x404)/*42.0*/, FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 9866 9935 { /* => */ { FP64_INF(0), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 9867 /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_OM,9868 /*128:out */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_OM) | X86_MXCSR_DE | X86_MXCSR_OE,9869 /*256:out */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_OM) | X86_MXCSR_DE | X86_MXCSR_OE,9870 /*xcpt? */ true, true },9936 /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_OM, 9937 /*128:out */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_OM) | X86_MXCSR_DE | X86_MXCSR_OE, 9938 /*256:out */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_OM) | X86_MXCSR_DE | X86_MXCSR_OE, 9939 /*xcpt? */ true, true }, 9871 9940 { { /* DAZ+MASK: 42.0 / DENORM_MIN = INF &_ZE */ 9872 9941 /*src2 */ { FP64_DENORM_MIN(0), FP64_0(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 9873 9942 { /*src1 */ { FP64_V(0, 0x5000000000000, 0x404)/*42.0*/, FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 9874 9943 { /* => */ { FP64_INF(0), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 9875 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,9876 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_ZE | X86_MXCSR_DAZ,9877 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_ZE | X86_MXCSR_DAZ,9878 /*xcpt? */ false, false },9944 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ, 9945 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_ZE | X86_MXCSR_DAZ, 9946 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_ZE | X86_MXCSR_DAZ, 9947 /*xcpt? */ false, false }, 9879 9948 { { /* MASKED: DENORM_MAX / -42.0 = -5e-310 &_DE &_PE &_UE */ 9880 9949 /*src2 */ { FP64_V(1, 0x5000000000000, 0x404)/*-42.0*/, FP64_0(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 9881 9950 { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 9882 9951 { /* => */ { FP64_V(1, 0x618618618618, 0)/*-5.29XYZe-310*/, FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 9883 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,9884 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_UE,9885 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_UE,9886 /*xcpt? */ false, false },9952 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 9953 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_UE, 9954 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_UE, 9955 /*xcpt? */ false, false }, 9887 9956 #ifdef TODO_X86_MXCSR_PE /** @todo THIS FAILS ON IEM: X86_MXCSR_PE not set in 128:out */ 9888 9957 { { /* ~UMASKED: DENORM_MAX / 42.0 = 5e-310 &_DE &_PE &&_UE */ … … 9890 9959 { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 9891 9960 { /* => */ { FP64_V(0, 0x618618618618, 0)/*-5.29XYZe-310*/, FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 9892 /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_UM,9893 /*128:out */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_UM) | X86_MXCSR_PE | X86_MXCSR_DE | X86_MXCSR_UE, // | BS3_MXCSR_PE_FUZZY /* IEM: when converted to Worker1A */9894 /*256:out */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_UM) | X86_MXCSR_PE | X86_MXCSR_DE | X86_MXCSR_UE,9895 /*xcpt? */ true, true },9961 /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_UM, 9962 /*128:out */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_UM) | X86_MXCSR_PE | X86_MXCSR_DE | X86_MXCSR_UE, // | BS3_MXCSR_PE_FUZZY /* IEM: when converted to Worker1A */ 9963 /*256:out */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_UM) | X86_MXCSR_PE | X86_MXCSR_DE | X86_MXCSR_UE, 9964 /*xcpt? */ true, true }, 9896 9965 #endif /* TODO_X86_MXCSR_PE */ 9897 9966 { { /* DAZ+MASK: DENORM_MAX / -42.0 = -0 &- */ … … 9899 9968 { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 9900 9969 { /* => */ { FP64_0(1), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 9901 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,9902 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,9903 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,9904 /*xcpt? */ false, false },9970 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ, 9971 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ, 9972 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ, 9973 /*xcpt? */ false, false }, 9905 9974 { { /* DAZ+FZ+M: DENORM_MAX / -42.0 = -0 &- */ 9906 9975 /*src2 */ { FP64_V(1, 0x5000000000000, 0x404)/*-42.0*/, FP64_0(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 9907 9976 { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 9908 9977 { /* => */ { FP64_0(1), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 9909 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ,9910 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ,9911 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ,9912 /*xcpt? */ false, false },9978 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ, 9979 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ, 9980 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ, 9981 /*xcpt? */ false, false }, 9913 9982 /** @todo how to usefully test FZ, RC_{NEAREST,UP,DOWN,ZERO} ? */ 9914 9983 … … 9977 10046 /*256:out */ 0, 9978 10047 /*xcpt? */ false, false }, 9979 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },9980 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },9981 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },9982 /*mxcsr:in */ 0,9983 /*128:out */ 0,9984 /*256:out */ 0,9985 /*xcpt? */ false, false },9986 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },9987 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },9988 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },9989 /*mxcsr:in */ X86_MXCSR_RC_ZERO,9990 /*128:out */ X86_MXCSR_RC_ZERO,9991 /*256:out */ X86_MXCSR_RC_ZERO,9992 /*xcpt? */ false, false },9993 { { /*src2 */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } },9994 { /*src1 */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } },9995 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } },9996 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,9997 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,9998 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,9999 /*xcpt? */ false, false },10000 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } },10001 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } },10002 { /* => */ { FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } },10003 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,10004 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,10005 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,10006 /*xcpt? */ false, false },10007 { { /*src2 */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } },10008 { /*src1 */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } },10009 { /* => */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } },10010 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,10011 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,10012 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,10013 /*xcpt? */ false, false },10014 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1) } },10015 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1) } },10016 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } },10017 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,10018 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,10019 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,10020 /*xcpt? */ false, false },10021 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1) } },10022 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1) } },10023 { /* => */ { FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1) } },10024 /*mxcsr:in */ X86_MXCSR_XCPT_FLAGS | X86_MXCSR_RC_DOWN,10025 /*128:out */ X86_MXCSR_XCPT_FLAGS | X86_MXCSR_RC_DOWN,10026 /*256:out */ X86_MXCSR_XCPT_FLAGS | X86_MXCSR_RC_DOWN,10027 /*xcpt? */ false, false },10028 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1) } },10029 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1) } },10030 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } },10031 /*mxcsr:in */ X86_MXCSR_XCPT_FLAGS | X86_MXCSR_RC_ZERO,10032 /*128:out */ X86_MXCSR_XCPT_FLAGS | X86_MXCSR_RC_ZERO,10033 /*256:out */ X86_MXCSR_XCPT_FLAGS | X86_MXCSR_RC_ZERO,10034 /*xcpt? */ false, false },10048 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 10049 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 10050 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 10051 /*mxcsr:in */ 0, 10052 /*128:out */ 0, 10053 /*256:out */ 0, 10054 /*xcpt? */ false, false }, 10055 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 10056 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 10057 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 10058 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 10059 /*128:out */ X86_MXCSR_RC_ZERO, 10060 /*256:out */ X86_MXCSR_RC_ZERO, 10061 /*xcpt? */ false, false }, 10062 { { /*src2 */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } }, 10063 { /*src1 */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } }, 10064 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } }, 10065 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 10066 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 10067 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 10068 /*xcpt? */ false, false }, 10069 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } }, 10070 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } }, 10071 { /* => */ { FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } }, 10072 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 10073 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 10074 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 10075 /*xcpt? */ false, false }, 10076 { { /*src2 */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } }, 10077 { /*src1 */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } }, 10078 { /* => */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } }, 10079 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 10080 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 10081 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 10082 /*xcpt? */ false, false }, 10083 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1) } }, 10084 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1) } }, 10085 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } }, 10086 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 10087 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 10088 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 10089 /*xcpt? */ false, false }, 10090 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1) } }, 10091 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1) } }, 10092 { /* => */ { FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1) } }, 10093 /*mxcsr:in */ X86_MXCSR_XCPT_FLAGS | X86_MXCSR_RC_DOWN, 10094 /*128:out */ X86_MXCSR_XCPT_FLAGS | X86_MXCSR_RC_DOWN, 10095 /*256:out */ X86_MXCSR_XCPT_FLAGS | X86_MXCSR_RC_DOWN, 10096 /*xcpt? */ false, false }, 10097 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1) } }, 10098 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1) } }, 10099 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } }, 10100 /*mxcsr:in */ X86_MXCSR_XCPT_FLAGS | X86_MXCSR_RC_ZERO, 10101 /*128:out */ X86_MXCSR_XCPT_FLAGS | X86_MXCSR_RC_ZERO, 10102 /*256:out */ X86_MXCSR_XCPT_FLAGS | X86_MXCSR_RC_ZERO, 10103 /*xcpt? */ false, false }, 10035 10104 /* 10036 10105 * Infinity. … … 10335 10404 /*256:out */ 0, 10336 10405 /*xcpt? */ false, false }, 10337 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 10338 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 10339 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 10340 /*mxcsr:in */ 0, 10341 /*128:out */ 0, 10342 /*256:out */ 0, 10343 /*xcpt? */ false, false }, 10344 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 10345 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 10346 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 10347 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 10348 /*128:out */ X86_MXCSR_RC_ZERO, 10349 /*256:out */ X86_MXCSR_RC_ZERO, 10350 /*xcpt? */ false, false }, 10351 { { /*src2 */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, 10352 { /*src1 */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, 10353 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 10354 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 10355 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 10356 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 10357 /*xcpt? */ false, false }, 10358 { { /*src2 */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } }, 10359 { /*src1 */ { FP64_0(1), FP64_0(0), FP64_0(1), FP64_0(0) } }, 10360 { /* => */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_0(1) } }, 10361 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 10362 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 10363 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 10364 /*xcpt? */ false, false }, 10365 { { /*src2 */ { FP64_0(1), FP64_0(0), FP64_0(1), FP64_0(0) } }, 10366 { /*src1 */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } }, 10367 { /* => */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } }, 10368 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 10369 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 10370 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 10371 /*xcpt? */ false, false }, 10372 { { /*src2 */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } }, 10373 { /*src1 */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } }, 10374 { /* => */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } }, 10375 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 10376 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 10377 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 10378 /*xcpt? */ false, false }, 10379 { { /*src2 */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_0(1) } }, 10380 { /*src1 */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_0(1) } }, 10381 { /* => */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } }, 10382 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 10383 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 10384 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 10385 /*xcpt? */ false, false }, 10386 { { /*src2 */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(1) } }, 10387 { /*src1 */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, 10388 { /* => */ { FP64_0(1), FP64_0(1), FP64_0(0), FP64_0(1) } }, 10389 /*mxcsr:in */ X86_MXCSR_XCPT_FLAGS | X86_MXCSR_RC_DOWN, 10390 /*128:out */ X86_MXCSR_XCPT_FLAGS | X86_MXCSR_RC_DOWN, 10391 /*256:out */ X86_MXCSR_XCPT_FLAGS | X86_MXCSR_RC_DOWN, 10392 /*xcpt? */ false, false }, 10393 { { /*src2 */ { FP64_0(1), FP64_0(0), FP64_0(1), FP64_0(1) } }, 10394 { /*src1 */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } }, 10395 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(1) } }, 10396 /*mxcsr:in */ X86_MXCSR_XCPT_FLAGS | X86_MXCSR_RC_ZERO, 10397 /*128:out */ X86_MXCSR_XCPT_FLAGS | X86_MXCSR_RC_ZERO, 10398 /*256:out */ X86_MXCSR_XCPT_FLAGS | X86_MXCSR_RC_ZERO, 10399 /*xcpt? */ false, false }, 10406 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 10407 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 10408 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 10409 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 10410 /*128:out */ X86_MXCSR_RC_ZERO, 10411 /*256:out */ X86_MXCSR_RC_ZERO, 10412 /*xcpt? */ false, false }, 10413 { { /*src2 */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, 10414 { /*src1 */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, 10415 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 10416 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 10417 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 10418 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 10419 /*xcpt? */ false, false }, 10420 { { /*src2 */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } }, 10421 { /*src1 */ { FP64_0(1), FP64_0(0), FP64_0(1), FP64_0(0) } }, 10422 { /* => */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_0(1) } }, 10423 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 10424 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 10425 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 10426 /*xcpt? */ false, false }, 10427 { { /*src2 */ { FP64_0(1), FP64_0(0), FP64_0(1), FP64_0(0) } }, 10428 { /*src1 */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } }, 10429 { /* => */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } }, 10430 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 10431 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 10432 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 10433 /*xcpt? */ false, false }, 10434 { { /*src2 */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } }, 10435 { /*src1 */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } }, 10436 { /* => */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } }, 10437 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 10438 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 10439 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 10440 /*xcpt? */ false, false }, 10441 { { /*src2 */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_0(1) } }, 10442 { /*src1 */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_0(1) } }, 10443 { /* => */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } }, 10444 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 10445 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 10446 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 10447 /*xcpt? */ false, false }, 10448 { { /*src2 */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(1) } }, 10449 { /*src1 */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, 10450 { /* => */ { FP64_0(1), FP64_0(1), FP64_0(0), FP64_0(1) } }, 10451 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 10452 /*128:out */ X86_MXCSR_RC_DOWN, 10453 /*256:out */ X86_MXCSR_RC_DOWN, 10454 /*xcpt? */ false, false }, 10455 { { /*src2 */ { FP64_0(1), FP64_0(0), FP64_0(1), FP64_0(1) } }, 10456 { /*src1 */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } }, 10457 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(1) } }, 10458 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 10459 /*128:out */ X86_MXCSR_RC_ZERO, 10460 /*256:out */ X86_MXCSR_RC_ZERO, 10461 /*xcpt? */ false, false }, 10400 10462 /* 10401 10463 * Infinity. 10402 10464 */ 10403 /* 10*/{ { /*src2 */ { FP64_INF(0), FP64_INF(0), FP64_INF(0), FP64_INF(0) } },10465 /* 9*/{ { /*src2 */ { FP64_INF(0), FP64_INF(0), FP64_INF(0), FP64_INF(0) } }, 10404 10466 { /*src1 */ { FP64_INF(0), FP64_INF(0), FP64_INF(1), FP64_INF(1) } }, 10405 10467 { /* => */ { FP64_QNAN(1), FP64_INF(0), FP64_INF(1), FP64_QNAN(1) } }, … … 10414 10476 /*128:out */ X86_MXCSR_IM | X86_MXCSR_IE, 10415 10477 /*256:out */ X86_MXCSR_IM | X86_MXCSR_IE, 10416 /*xcpt? */ false, false },10417 { { /*src2 */ { FP64_INF(0), FP64_INF(0), FP64_INF(0), FP64_INF(0) } },10418 { /*src1 */ { FP64_INF(0), FP64_INF(0), FP64_INF(1), FP64_INF(1) } },10419 { /* => */ { FP64_QNAN(1), FP64_INF(0), FP64_INF(1), FP64_QNAN(1) } },10420 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,10421 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,10422 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,10423 /*xcpt? */ false, false },10424 { { /*src2 */ { FP64_INF(1), FP64_INF(1), FP64_INF(1), FP64_INF(1) } },10425 { /*src1 */ { FP64_INF(0), FP64_INF(0), FP64_INF(1), FP64_INF(1) } },10426 { /* => */ { FP64_INF(0), FP64_QNAN(1), FP64_QNAN(1), FP64_INF(1) } },10427 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,10428 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,10429 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,10430 10478 /*xcpt? */ false, false }, 10431 10479 { { /*src2 */ { FP64_INF(0), FP64_INF(0), FP64_INF(0), FP64_INF(0) } }, … … 10502 10550 * Overflow, Precision. 10503 10551 */ 10504 /*2 4*/{ { /*src2 */ { FP64_0(0), FP64_0(0), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } },10552 /*21*/{ { /*src2 */ { FP64_0(0), FP64_0(0), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } }, 10505 10553 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } }, 10506 10554 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_INF(0) } }, 10507 10555 /*mxcsr:in */ 0, 10508 10556 /*128:out */ 0, 10509 /*256:out */ X86_MXCSR_OE ,10557 /*256:out */ X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY, 10510 10558 /*xcpt? */ false, true }, 10511 10559 { { /*src2 */ { FP64_NORM_MIN(0), FP64_NORM_MAX(0), FP64_1(0), FP64_NORM_MAX(1) } }, … … 10520 10568 { /* => */ { FP64_NORM_MAX(1), FP64_2(0), FP64_NORM_V3(1), FP64_NORM_MAX(0) } }, 10521 10569 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO, 10522 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE ,10523 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE ,10570 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY, 10571 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY, 10524 10572 /*xcpt? */ false, false }, 10525 10573 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_V3(0), FP64_NORM_MAX(0) } }, … … 10528 10576 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 10529 10577 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 10530 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE ,10578 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY, 10531 10579 /*xcpt? */ false, false }, 10532 10580 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_0(0), FP64_NORM_MAX(0) } }, … … 10541 10589 { /* => */ { FP64_0(1), FP64_NORM_MAX(0), FP64_INF(1), FP64_NORM_V2(1) } }, 10542 10590 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 10543 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_OE | X86_MXCSR_PE ,10544 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_OE | X86_MXCSR_PE ,10591 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY, 10592 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY, 10545 10593 /*xcpt? */ false, false }, 10546 10594 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } }, 10547 10595 { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } }, 10548 { /* => */ { FP64_ NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0)} },10596 { /* => */ { FP64_0(0), FP64_INF(1), FP64_0(0), FP64_INF(0) } }, 10549 10597 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 10550 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OE ,10551 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OE ,10598 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY, 10599 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY, 10552 10600 /*xcpt? */ true, true }, 10553 10601 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } }, … … 10555 10603 { /* => */ { FP64_0(0), FP64_NORM_MAX(1), FP64_0(0), FP64_NORM_MAX(0) } }, 10556 10604 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO, 10557 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE ,10558 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE ,10605 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY, 10606 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY, 10559 10607 /*xcpt? */ false, false }, 10560 10608 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } }, … … 10562 10610 { /* => */ { FP64_0(0), FP64_NORM_MAX(1), FP64_0(0), FP64_INF(0) } }, 10563 10611 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP, 10564 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE, 10565 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE, 10566 /*xcpt? */ false, false }, 10567 { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_MAX(0), FP64_0(0), FP64_NORM_SAFE_INT_MAX(1) } }, 10568 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_MAX(1), FP64_0(0), FP64_NORM_SAFE_INT_MAX(1) } }, 10569 { /* => */ { FP64_V(0, FP64_FRAC_NORM_MAX, FP64_EXP_SAFE_INT_MAX), FP64_NORM_MAX(1), FP64_0(0), FP64_V(1, FP64_FRAC_NORM_MAX, FP64_EXP_SAFE_INT_MAX) } }, 10570 /*mxcsr:in */ 0, 10571 /*128:out */ X86_MXCSR_PE, 10572 /*256:out */ X86_MXCSR_PE, 10573 /*xcpt? */ true, true }, 10612 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY, 10613 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY, 10614 /*xcpt? */ false, false }, 10574 10615 { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_MAX(0), FP64_0(0), FP64_NORM_SAFE_INT_MAX(1) } }, 10575 10616 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_MAX(1), FP64_0(0), FP64_NORM_SAFE_INT_MAX(1) } }, … … 10582 10623 * Normals. 10583 10624 */ 10584 /*3 5*/{ { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_V1(0), FP64_NORM_MAX(1) } },10625 /*31*/{ { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_V1(0), FP64_NORM_MAX(1) } }, 10585 10626 { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_V1(0), FP64_NORM_MAX(0) } }, 10586 10627 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, … … 10635 10676 * Denormals. 10636 10677 */ 10637 /* 42*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_DENORM_MAX(1), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } },10678 /*38*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_DENORM_MAX(1), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } }, 10638 10679 { /*src1 */ { FP64_0(0), FP64_DENORM_MAX(1), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } }, 10639 10680 { /* => */ { FP64_DENORM_MAX(1), FP64_V(1, FP64_FRAC_NORM_MAX - 1, FP64_EXP_NORM_MIN), FP64_0(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_NORM_MIN) } }, 10640 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 10641 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, 10642 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, 10643 /*xcpt? */ false, false }, 10681 /*mxcsr:in */ 0, 10682 /*128:out */ X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 10683 /*256:out */ X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 10684 /*xcpt? */ false, false }, 10685 { { /*src2 */ { FP64_DENORM_MAX(0), FP64_DENORM_MAX(1), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } }, 10686 { /*src1 */ { FP64_0(0), FP64_DENORM_MAX(1), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } }, 10687 { /* => */ { FP64_DENORM_MAX(1), FP64_V(1, FP64_FRAC_NORM_MAX - 1, FP64_EXP_NORM_MIN), FP64_0(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_NORM_MIN) } }, 10688 /*mxcsr:in */ X86_MXCSR_UM, 10689 /*128:out */ X86_MXCSR_UM | X86_MXCSR_DE | BS3_MXCSR_UM_FIXED, 10690 /*256:out */ X86_MXCSR_UM | X86_MXCSR_DE | BS3_MXCSR_UM_FIXED, 10691 /*xcpt? */ false, false }, 10692 #ifdef TODO_X86_MXCSR_UE_IEM /** @todo THIS FAILS ON IEM: X86_MXCSR_UE not set in 128:out or 256:out */ 10693 /*--|40*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_DENORM_MAX(1), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } }, 10694 { /*src1 */ { FP64_0(0), FP64_DENORM_MAX(1), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } }, 10695 { /* => */ { FP64_DENORM_MAX(1), FP64_V(1, FP64_FRAC_NORM_MAX - 1, FP64_EXP_NORM_MIN), FP64_0(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_NORM_MIN) } }, 10696 /*mxcsr:in */ X86_MXCSR_DM, 10697 /*128:out */ X86_MXCSR_DM | X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 10698 /*256:out */ X86_MXCSR_DM | X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 10699 /*xcpt? */ false, false }, 10700 #endif /* TODO_X86_MXCSR_UE_IEM */ 10701 /*40|41*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } }, 10702 { /*src1 */ { FP64_0(0), FP64_DENORM_MAX(1), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } }, 10703 { /* => */ { FP64_DENORM_MAX(1), FP64_DENORM_MAX(1), FP64_0(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_NORM_MIN) } }, 10704 /*mxcsr:in */ 0, 10705 /*128:out */ X86_MXCSR_DE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 10706 /*256:out */ X86_MXCSR_DE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 10707 /*xcpt? */ true, true }, 10644 10708 { { /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } }, 10645 10709 { /*src1 */ { FP64_0(0), FP64_DENORM_MAX(1), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } }, 10646 10710 { /* => */ { FP64_DENORM_MAX(1), FP64_DENORM_MAX(1), FP64_0(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_NORM_MIN) } }, 10711 /*mxcsr:in */ X86_MXCSR_UM, 10712 /*128:out */ X86_MXCSR_UM | X86_MXCSR_DE | BS3_MXCSR_UM_FIXED, 10713 /*256:out */ X86_MXCSR_UM | X86_MXCSR_DE | BS3_MXCSR_UM_FIXED, 10714 /*xcpt? */ true, true }, 10715 #ifdef TODO_X86_MXCSR_UE_IEM /** @todo THIS FAILS ON IEM: X86_MXCSR_UE not set in 128:out or 256:out */ 10716 /*--|43*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } }, 10717 { /*src1 */ { FP64_0(0), FP64_DENORM_MAX(1), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } }, 10718 { /* => */ { FP64_DENORM_MAX(1), FP64_DENORM_MAX(1), FP64_0(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_NORM_MIN) } }, 10719 /*mxcsr:in */ X86_MXCSR_DM, 10720 /*128:out */ X86_MXCSR_DM | X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 10721 /*256:out */ X86_MXCSR_DM | X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 10722 /*xcpt? */ true, true }, 10723 #endif /* TODO_X86_MXCSR_UE_IEM */ 10724 /*42|44*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_DENORM_MAX(1), FP64_0(0), FP64_0(0) } }, 10725 { /*src1 */ { FP64_0(0), FP64_DENORM_MAX(1), FP64_DENORM_MAX(0), FP64_DENORM_MAX(1) } }, 10726 { /* => */ { FP64_DENORM_MAX(1), FP64_V(1, FP64_FRAC_NORM_MAX - 1, FP64_EXP_NORM_MIN), FP64_DENORM_MAX(0), FP64_DENORM_MAX(1) } }, 10647 10727 /*mxcsr:in */ 0, 10648 /*128:out */ X86_MXCSR_DE ,10649 /*256:out */ X86_MXCSR_DE ,10728 /*128:out */ X86_MXCSR_DE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 10729 /*256:out */ X86_MXCSR_DE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 10650 10730 /*xcpt? */ true, true }, 10651 10731 { { /*src2 */ { FP64_DENORM_MAX(0), FP64_DENORM_MAX(1), FP64_0(0), FP64_0(0) } }, 10652 10732 { /*src1 */ { FP64_0(0), FP64_DENORM_MAX(1), FP64_DENORM_MAX(0), FP64_DENORM_MAX(1) } }, 10653 10733 { /* => */ { FP64_DENORM_MAX(1), FP64_V(1, FP64_FRAC_NORM_MAX - 1, FP64_EXP_NORM_MIN), FP64_DENORM_MAX(0), FP64_DENORM_MAX(1) } }, 10734 /*mxcsr:in */ X86_MXCSR_UM, 10735 /*128:out */ X86_MXCSR_UM | X86_MXCSR_DE | BS3_MXCSR_UM_FIXED, 10736 /*256:out */ X86_MXCSR_UM | X86_MXCSR_DE | BS3_MXCSR_UM_FIXED, 10737 /*xcpt? */ true, true }, 10738 #ifdef TODO_X86_MXCSR_UE_IEM /** @todo THIS FAILS ON IEM: X86_MXCSR_UE not set in 128:out or 256:out */ 10739 /*--|46*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_DENORM_MAX(1), FP64_0(0), FP64_0(0) } }, 10740 { /*src1 */ { FP64_0(0), FP64_DENORM_MAX(1), FP64_DENORM_MAX(0), FP64_DENORM_MAX(1) } }, 10741 { /* => */ { FP64_DENORM_MAX(1), FP64_V(1, FP64_FRAC_NORM_MAX - 1, FP64_EXP_NORM_MIN), FP64_DENORM_MAX(0), FP64_DENORM_MAX(1) } }, 10742 /*mxcsr:in */ X86_MXCSR_DM, 10743 /*128:out */ X86_MXCSR_DM | X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 10744 /*256:out */ X86_MXCSR_DM | X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 10745 /*xcpt? */ true, true }, 10746 #endif /* TODO_X86_MXCSR_UE_IEM */ 10747 /*44|47*/{ { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0)} }, 10748 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_DENORM_MAX(0), FP64_0(0)} }, 10749 { /* => */ { FP64_0(0), FP64_0(0), FP64_DENORM_MAX(0), FP64_0(0)} }, 10654 10750 /*mxcsr:in */ 0, 10655 /*128:out */ X86_MXCSR_DE,10656 /*256:out */ X86_MXCSR_DE ,10657 /*xcpt? */ true, true },10751 /*128:out */ 0, 10752 /*256:out */ X86_MXCSR_DE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 10753 /*xcpt? */ false, false }, 10658 10754 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0)} }, 10659 10755 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_DENORM_MAX(0), FP64_0(0)} }, 10660 10756 { /* => */ { FP64_0(0), FP64_0(0), FP64_DENORM_MAX(0), FP64_0(0)} }, 10661 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 10662 /*128:out */ X86_MXCSR_XCPT_MASK, 10663 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, 10664 /*xcpt? */ false, false }, 10665 { { /*src2 */ { FP64_DENORM_MIN(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } }, 10757 /*mxcsr:in */ X86_MXCSR_UM, 10758 /*128:out */ X86_MXCSR_UM, 10759 /*256:out */ X86_MXCSR_UM | X86_MXCSR_DE | BS3_MXCSR_UM_FIXED, 10760 /*xcpt? */ false, false }, 10761 #ifdef TODO_X86_MXCSR_UE_IEM /** @todo THIS FAILS ON IEM: X86_MXCSR_UE not set in 128:out or 256:out */ 10762 /*--|49*/{ { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0)} }, 10763 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_DENORM_MAX(0), FP64_0(0)} }, 10764 { /* => */ { FP64_0(0), FP64_0(0), FP64_DENORM_MAX(0), FP64_0(0)} }, 10765 /*mxcsr:in */ X86_MXCSR_DM, 10766 /*128:out */ X86_MXCSR_DM, 10767 /*256:out */ X86_MXCSR_DM | X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 10768 /*xcpt? */ false, false }, 10769 #endif /* TODO_X86_MXCSR_UE_IEM */ 10770 /*46|50*/{ { /*src2 */ { FP64_DENORM_MIN(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } }, 10666 10771 { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } }, 10667 10772 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, … … 10737 10842 * Invalids. 10738 10843 */ 10739 /*56*/ FP64_TABLE_D1_PD_INVALIDS10844 /*56|60*/ FP64_TABLE_D1_PD_INVALIDS 10740 10845 /** @todo Underflow; Precision; Rounding; FZ etc. */ 10741 10846 }; … … 10787 10892 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 10788 10893 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode); 10789 return bs3CpuInstr4_WorkerTestType1 (bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,10894 return bs3CpuInstr4_WorkerTestType1A(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 10790 10895 g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2)); 10791 10896 } … … 10868 10973 * Infinity. 10869 10974 */ 10870 /* 9*/{ { /*src2 */ { FP32_INF(0), FP32_0(0), FP32_INF(0), FP32_0(1), FP32_INF(1), FP32_0(0), FP32_INF(1), FP32_0(0) } },10975 /* 9*/{ { /*src2 */ { FP32_INF(0), FP32_0(0), FP32_INF(0), FP32_0(1), FP32_INF(1), FP32_0(0), FP32_INF(1), FP32_0(0) } }, 10871 10976 { /*src1 */ { FP32_0(0), FP32_INF(0), FP32_0(1), FP32_INF(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_INF(1) } }, 10872 10977 { /* => */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, … … 11188 11293 * Infinity. 11189 11294 */ 11190 /* 9*/{ { /*src2 */ { FP64_INF(0), FP64_0(0), FP64_INF(0), FP64_0(1) } },11295 /* 9*/{ { /*src2 */ { FP64_INF(0), FP64_0(0), FP64_INF(0), FP64_0(1) } }, 11191 11296 { /*src1 */ { FP64_0(0), FP64_INF(0), FP64_0(1), FP64_INF(0) } }, 11192 11297 { /* => */ { FP64_INF(0), FP64_INF(0), FP64_INF(0), FP64_INF(0) } }, … … 12426 12531 * Infinity. 12427 12532 */ 12428 /* 9*/{ { /*src2 */ { FP32_INF(0), FP32_0(0), FP32_INF(1), FP32_0(1), FP32_INF(1), FP32_0(0), FP32_INF(1), FP32_0(0) } },12533 /* 9*/{ { /*src2 */ { FP32_INF(0), FP32_0(0), FP32_INF(1), FP32_0(1), FP32_INF(1), FP32_0(0), FP32_INF(1), FP32_0(0) } }, 12429 12534 { /*src1 */ { FP32_0(0), FP32_INF(0), FP32_0(0), FP32_INF(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_INF(1) } }, 12430 12535 { /* => */ { FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(1), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1) } }, … … 12595 12700 /*xcpt? */ false, false }, 12596 12701 { { /*src2 */ { FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 12597 12598 12599 12600 12601 12602 12702 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 12703 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 12704 /*mxcsr:in */ 0, 12705 /*128:out */ X86_MXCSR_DE, 12706 /*256:out */ X86_MXCSR_DE, 12707 /*xcpt? */ true, true }, 12603 12708 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(1) } }, 12604 12709 { /*src1 */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, … … 12746 12851 * Infinity. 12747 12852 */ 12748 /* 9*/{ { /*src2 */ { FP64_INF(0), FP64_0(0), FP64_INF(0), FP64_0(1) } },12853 /* 9*/{ { /*src2 */ { FP64_INF(0), FP64_0(0), FP64_INF(0), FP64_0(1) } }, 12749 12854 { /*src1 */ { FP64_0(0), FP64_INF(0), FP64_0(1), FP64_INF(1) } }, 12750 12855 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_INF(1) } },
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