- Timestamp:
- Oct 3, 2024 2:52:52 PM (7 months ago)
- svn:sync-xref-src-repo-rev:
- 164999
- File:
-
- 1 edited
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trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32
r106214 r106215 196 196 /* 197 197 * Single-precision floating-point invalids. 198 * 1 to 0x3fffff fractional part for SNANs and 0x400000 to 0x7fffff for QNAN. 199 * The QNAN initialization macro ensures the range for QNAN is correct by OR'ing 0x400000. 198 * The range must be valid for both QNAN and SNANs (see compile time assertions below). 200 199 */ 201 200 #define FP32_FRAC_INV_V0 0x3fffff … … 207 206 #define FP32_FRAC_INV_V6 0x3ebebe 208 207 #define FP32_FRAC_INV_V7 0x000001 208 AssertCompile(FP32_FRAC_INV_V0 <= FP32_FRAC_SNAN_MAX && FP32_FRAC_INV_V0 >= FP32_FRAC_SNAN_MIN); 209 AssertCompile(FP32_FRAC_INV_V1 <= FP32_FRAC_SNAN_MAX && FP32_FRAC_INV_V1 >= FP32_FRAC_SNAN_MIN); 210 AssertCompile(FP32_FRAC_INV_V2 <= FP32_FRAC_SNAN_MAX && FP32_FRAC_INV_V2 >= FP32_FRAC_SNAN_MIN); 211 AssertCompile(FP32_FRAC_INV_V3 <= FP32_FRAC_SNAN_MAX && FP32_FRAC_INV_V3 >= FP32_FRAC_SNAN_MIN); 212 AssertCompile(FP32_FRAC_INV_V4 <= FP32_FRAC_SNAN_MAX && FP32_FRAC_INV_V4 >= FP32_FRAC_SNAN_MIN); 213 AssertCompile(FP32_FRAC_INV_V5 <= FP32_FRAC_SNAN_MAX && FP32_FRAC_INV_V5 >= FP32_FRAC_SNAN_MIN); 214 AssertCompile(FP32_FRAC_INV_V6 <= FP32_FRAC_SNAN_MAX && FP32_FRAC_INV_V6 >= FP32_FRAC_SNAN_MIN); 215 AssertCompile(FP32_FRAC_INV_V7 <= FP32_FRAC_SNAN_MAX && FP32_FRAC_INV_V7 >= FP32_FRAC_SNAN_MIN); 209 216 /* Single-precision floating-point signalling NANs (SNAN). */ 210 217 #define FP32_SNAN_V0(a_Sign) RTFLOAT32U_INIT_SNAN_EX(a_Sign, FP32_FRAC_INV_V0) … … 265 272 /** The min fraction value for a double-precision floating-point denormal. */ 266 273 #define FP64_FRAC_DENORM_MIN 1 274 /** The max fraction value for a single-precision floating-point signalling NAN. */ 275 #define FP64_FRAC_SNAN_MAX 0x7ffffffffffff 276 /** The min fraction value for a single-precision floating-point signalling NAN. */ 277 #define FP64_FRAC_SNAN_MIN 1 278 /** The max fraction value for a single-precision floating-point quiet NAN. */ 279 #define FP64_FRAC_QNAN_MAX 0xfffffffffffff 280 /** The min fraction value for a single-precision floating-point quiet NAN. */ 281 #define FP64_FRAC_QNAN_MIN 0x8000000000000 267 282 268 283 #define FP64_NORM_MAX(a_Sign) RTFLOAT64U_INIT_C(a_Sign, FP64_FRAC_NORM_MAX, FP64_EXP_NORM_MAX) … … 275 290 #define FP64_QNAN(a_Sign) RTFLOAT64U_INIT_QNAN(a_Sign) 276 291 #define FP64_QNAN_V(a_Sign, a_Val) RTFLOAT64U_INIT_QNAN_EX(a_Sign, a_Val) 292 #define FP64_QNAN_MAX(a_Sign) RTFLOAT64U_INIT_QNAN_EX(a_Sign, FP64_FRAC_QNAN_MAX) 277 293 #define FP64_SNAN(a_Sign) RTFLOAT64U_INIT_SNAN(a_Sign) 278 294 #define FP64_SNAN_V(a_Sign, a_Val) RTFLOAT64U_INIT_SNAN_EX(a_Sign, a_Val) 295 #define FP64_SNAN_MAX(a_Sign) RTFLOAT64U_INIT_SNAN_EX(a_Sign, FP64_FRAC_SNAN_MAX) 279 296 /** @todo Move this to iprt/types.h after renaming it to RTFLOAT64U_MAKE? */ 280 297 #ifdef RT_BIG_ENDIAN … … 339 356 /** The maximum denormal value. */ 340 357 #define FP64_DENORM_MIN(a_Sign) RTFLOAT64U_INIT_C(a_Sign, FP64_FRAC_DENORM_MIN, 0) 358 359 /* 360 * Double-precision floating-point invalids. 361 * The range must be valid for both QNAN and SNANs (see compile time assertions below). 362 */ 363 #define FP64_FRAC_INV_V0 0x7ffffffffffff 364 #define FP64_FRAC_INV_V1 0x3ca5cadecab1e 365 #define FP64_FRAC_INV_V2 0x10adedb0771e5 366 #define FP64_FRAC_INV_V3 0x0000000000001 367 AssertCompile(FP64_FRAC_INV_V0 < FP64_FRAC_QNAN_MIN && FP64_FRAC_INV_V0 >= FP64_FRAC_SNAN_MIN); 368 AssertCompile(FP64_FRAC_INV_V1 < FP64_FRAC_QNAN_MIN && FP64_FRAC_INV_V1 >= FP64_FRAC_SNAN_MIN); 369 AssertCompile(FP64_FRAC_INV_V2 < FP64_FRAC_QNAN_MIN && FP64_FRAC_INV_V2 >= FP64_FRAC_SNAN_MIN); 370 AssertCompile(FP64_FRAC_INV_V3 < FP64_FRAC_QNAN_MIN && FP64_FRAC_INV_V3 >= FP64_FRAC_SNAN_MIN); 371 /* Double-precision floating-point signalling NANs (SNAN). */ 372 #define FP64_SNAN_V0(a_Sign) RTFLOAT64U_INIT_SNAN_EX(a_Sign, FP64_FRAC_INV_V0) 373 #define FP64_SNAN_V1(a_Sign) RTFLOAT64U_INIT_SNAN_EX(a_Sign, FP64_FRAC_INV_V1) 374 #define FP64_SNAN_V2(a_Sign) RTFLOAT64U_INIT_SNAN_EX(a_Sign, FP64_FRAC_INV_V2) 375 #define FP64_SNAN_V3(a_Sign) RTFLOAT64U_INIT_SNAN_EX(a_Sign, FP64_FRAC_INV_V3) 376 /* Double-precision floating-point quiet NANs (QNAN). */ 377 #define FP64_QNAN_V0(a_Sign) RTFLOAT64U_INIT_QNAN_EX(a_Sign, FP64_FRAC_INV_V0) 378 #define FP64_QNAN_V1(a_Sign) RTFLOAT64U_INIT_QNAN_EX(a_Sign, FP64_FRAC_INV_V1) 379 #define FP64_QNAN_V2(a_Sign) RTFLOAT64U_INIT_QNAN_EX(a_Sign, FP64_FRAC_INV_V2) 380 #define FP64_QNAN_V3(a_Sign) RTFLOAT64U_INIT_QNAN_EX(a_Sign, FP64_FRAC_INV_V3) 341 381 342 382 /* … … 718 758 **/ 719 759 #define FP64_TABLE_D1_PD_INVALIDS \ 720 /* 0*/{ { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } },\721 { /*src1 */ { FP64_QNAN(0), FP64_QNAN _V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } },\722 { /* => */ { FP64_QNAN(0), FP64_QNAN _V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } },\723 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 724 /*128:out */ X86_MXCSR_XCPT_MASK, 725 /*256:out */ X86_MXCSR_XCPT_MASK, 726 /*xcpt? */ false, false }, 727 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2) } }, \728 { /*src1 */ { FP64_SNAN(0), FP64_SNAN _V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1) } }, \729 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \730 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 731 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 732 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 733 /*xcpt? */ false, false }, 734 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN _V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V1) } },\735 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } },\736 { /* => */ { FP64_QNAN(0), FP64_QNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } },\737 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 738 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 739 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 740 /*xcpt? */ false, false }, 741 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN _V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } },\742 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V0) } },\743 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V0) } },\744 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 745 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 746 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 747 /*xcpt? */ false, false }, 748 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_ V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } },\749 { /*src1 */ { FP64_1(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },\750 { /* => */ { FP64_QNAN(0), FP64_QNAN_ V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } },\751 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 752 /*128:out */ X86_MXCSR_XCPT_MASK, 753 /*256:out */ X86_MXCSR_XCPT_MASK, 754 /*xcpt? */ false, false }, 755 { { /*src2 */ { FP64_SNAN(1), FP64_SNAN_ V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V1) } },\756 { /*src1 */ { FP64_1(0), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },\757 { /* => */ { FP64_QNAN_V(1, 1), FP64_QNAN_ V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } },\758 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 759 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 760 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 761 /*xcpt? */ false, false }, 762 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2) } },\763 { /*src1 */ { FP64_QNAN(0), FP64_QNAN _V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3) } },\764 { /* => */ { FP64_QNAN(0), FP64_QNAN _V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3) } },\765 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 766 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 767 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 768 /*xcpt? */ false, false }, 769 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP32_FRAC_V1) } }, \770 { /*src1 */ { FP64_SNAN(0), FP64_SNAN _V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP32_FRAC_V2) } }, \771 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP32_FRAC_V2) } }, \772 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 773 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 774 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 775 /*xcpt? */ true, true }, 776 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN _V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } },\777 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },\778 { /* => */ { FP64_QNAN(0), FP64_QNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },\779 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 780 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 781 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 782 /*xcpt? */ true, true }, 783 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN _V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } },\784 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } },\785 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V3) } },\786 /*mxcsr:in */ X86_MXCSR_RC_UP, 787 /*128:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, 788 /*256:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, 789 /*xcpt? */ true, true }, 790 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_ V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } },\791 { /*src1 */ { FP64_1(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_NORM_V2(1) } },\792 { /* => */ { FP64_QNAN(0), FP64_QNAN_ V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V1) } },\793 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 794 /*128:out */ X86_MXCSR_RC_DOWN, 795 /*256:out */ X86_MXCSR_RC_DOWN, 796 /*xcpt? */ false, false }, 797 /*11*/{ { /*src2 */ { FP64_SNAN(1), FP64_SNAN_ V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V2) } },\798 { /*src1 */ { FP64_1(0), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_NORM_V2(1) } },\799 { /* => */ { FP64_QNAN_V(1, 1), FP64_QNAN_ V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },\800 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 801 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 802 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 803 /*xcpt? */ true, true }, 760 /*0 */{ { /*src2 */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V0(0), FP64_QNAN_V1(0) } }, \ 761 { /*src1 */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V2(0) } }, \ 762 { /* => */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V2(0) } }, \ 763 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 764 /*128:out */ X86_MXCSR_XCPT_MASK, \ 765 /*256:out */ X86_MXCSR_XCPT_MASK, \ 766 /*xcpt? */ false, false }, \ 767 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V0(0), FP64_QNAN_V2(0) } }, \ 768 { /*src1 */ { FP64_SNAN(0), FP64_SNAN(0), FP64_SNAN_MAX(0), FP64_SNAN_V1(0) } }, \ 769 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_MAX(0), FP64_QNAN_V1(0) } }, \ 770 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 771 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 772 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 773 /*xcpt? */ false, false }, \ 774 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN(0), FP64_SNAN_V0(0), FP64_SNAN_V1(0) } }, \ 775 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V2(0), FP64_QNAN_V3(0) } }, \ 776 { /* => */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V2(0), FP64_QNAN_V3(0) } }, \ 777 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 778 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 779 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 780 /*xcpt? */ false, false }, \ 781 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN(0), FP64_SNAN_V1(0), FP64_SNAN_V2(0) } }, \ 782 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_MAX(0), FP64_SNAN_V3(0), FP64_SNAN_V0(0) } }, \ 783 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_MAX(0), FP64_QNAN_V3(0), FP64_QNAN_V0(0) } }, \ 784 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 785 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 786 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 787 /*xcpt? */ false, false }, \ 788 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_MAX(1), FP64_NORM_V0(1), FP64_QNAN_V1(0) } }, \ 789 { /*src1 */ { FP64_1(0), FP64_1(1), FP64_QNAN_V0(1), FP64_NORM_V2(1) } }, \ 790 { /* => */ { FP64_QNAN(0), FP64_QNAN_MAX(1), FP64_QNAN_V0(1), FP64_QNAN_V1(0) } }, \ 791 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 792 /*128:out */ X86_MXCSR_XCPT_MASK, \ 793 /*256:out */ X86_MXCSR_XCPT_MASK, \ 794 /*xcpt? */ false, false }, \ 795 { { /*src2 */ { FP64_SNAN(1), FP64_SNAN_MAX(1), FP64_NORM_V0(1), FP64_SNAN_V1(0) } }, \ 796 { /*src1 */ { FP64_1(0), FP64_1(0), FP64_SNAN_V0(1), FP64_NORM_V2(1) } }, \ 797 { /* => */ { FP64_QNAN_V(1, 1), FP64_QNAN_MAX(1), FP64_QNAN_V0(1), FP64_QNAN_V1(0) } }, \ 798 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 799 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 800 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 801 /*xcpt? */ false, false }, \ 802 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V0(0), FP64_QNAN_V2(0) } }, \ 803 { /*src1 */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V3(0) } }, \ 804 { /* => */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V3(0) } }, \ 805 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, \ 806 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, \ 807 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, \ 808 /*xcpt? */ false, false }, \ 809 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V0(0), FP64_QNAN_V1(0) } }, \ 810 { /*src1 */ { FP64_SNAN(0), FP64_SNAN(0), FP64_SNAN_MAX(0), FP64_SNAN_V2(0) } }, \ 811 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_MAX(0), FP64_QNAN_V2(0) } }, \ 812 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, \ 813 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, \ 814 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, \ 815 /*xcpt? */ true, true }, \ 816 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN(0), FP64_SNAN_V1(0), FP64_SNAN_V1(0) } }, \ 817 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V3(0), FP64_QNAN_V2(0) } }, \ 818 { /* => */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V3(0), FP64_QNAN_V2(0) } }, \ 819 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, \ 820 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, \ 821 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, \ 822 /*xcpt? */ true, true }, \ 823 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN(0), FP64_SNAN_V1(0), FP64_SNAN_V2(0) } }, \ 824 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_MAX(0), FP64_SNAN_V0(0), FP64_SNAN_V3(0) } }, \ 825 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_MAX(0), FP64_QNAN_V0(0), FP64_QNAN_V3(0) } }, \ 826 /*mxcsr:in */ X86_MXCSR_RC_UP, \ 827 /*128:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, \ 828 /*256:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, \ 829 /*xcpt? */ true, true }, \ 830 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_MAX(1), FP64_NORM_V0(1), FP64_QNAN_V1(0) } }, \ 831 { /*src1 */ { FP64_1(0), FP64_1(1), FP64_QNAN_V3(1), FP64_NORM_V2(1) } }, \ 832 { /* => */ { FP64_QNAN(0), FP64_QNAN_MAX(1), FP64_QNAN_V3(1), FP64_QNAN_V1(0) } }, \ 833 /*mxcsr:in */ X86_MXCSR_RC_DOWN, \ 834 /*128:out */ X86_MXCSR_RC_DOWN, \ 835 /*256:out */ X86_MXCSR_RC_DOWN, \ 836 /*xcpt? */ false, false }, \ 837 /*11*/{ { /*src2 */ { FP64_SNAN(1), FP64_SNAN_MAX(1), FP64_NORM_V0(1), FP64_SNAN_V2(0) } }, \ 838 { /*src1 */ { FP64_1(0), FP64_1(0), FP64_SNAN_V3(1), FP64_NORM_V2(1) } }, \ 839 { /* => */ { FP64_QNAN_V(1, 1), FP64_QNAN_MAX(1), FP64_QNAN_V3(1), FP64_QNAN_V2(0) } }, \ 840 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, \ 841 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, \ 842 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, \ 843 /*xcpt? */ true, true }, \ 804 844 805 845 /** … … 1023 1063 **/ 1024 1064 #define FP64_TABLE_D1_SD_INVALIDS \ 1025 /* QNan, QNan (Masked). */ 1026 /* 0*/{ { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } },\1027 { /*src1 */ { FP64_QNAN(0), FP64_QNAN _V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } },\1028 { /* => */ { FP64_QNAN(0), FP64_QNAN _V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } },\1029 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1030 /*128:out */ X86_MXCSR_XCPT_MASK, 1031 /*256:out */ X86_MXCSR_XCPT_MASK, 1032 /*xcpt? */ false, false }, 1033 { { /*src2 */ { FP64_QNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_INF(0) } },\1034 { /*src1 */ { FP64_QNAN _V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_SNAN(1) } },\1035 { /* => */ { FP64_QNAN _V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_SNAN(1) } },\1036 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1037 /*128:out */ X86_MXCSR_XCPT_MASK, 1038 /*256:out */ X86_MXCSR_XCPT_MASK, 1039 /*xcpt? */ false, false }, 1040 { { /*src2 */ { FP64_QNAN_V (0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_INF(1) } },\1041 { /*src1 */ { FP64_QNAN_V (0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN(0) } },\1042 { /* => */ { FP64_QNAN_V (0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN(0) } },\1043 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1044 /*128:out */ X86_MXCSR_XCPT_MASK, 1045 /*256:out */ X86_MXCSR_XCPT_MASK, 1046 /*xcpt? */ false, false }, 1047 /* QNan, SNan (Masked). */ 1048 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V (0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } },\1049 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V (1, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP64_FRAC_V2) } },\1050 { /* => */ { FP64_QNAN_V(0, 1), FP64_ QNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP64_FRAC_V2) } },\1051 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1052 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1053 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1054 /*xcpt? */ false, false }, 1055 { { /*src2 */ { FP64_QNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \1056 { /*src1 */ { FP64_SNAN _V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(1, FP64_FRAC_NORM_MIN), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2) } }, \1057 { /* => */ { FP64_QNAN_V(0, 1), FP64_SNAN_V(1, FP64_FRAC_NORM_MIN), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2) } }, \1058 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1059 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1060 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1061 /*xcpt? */ false, false }, 1062 { { /*src2 */ { FP64_QNAN_V (0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_INF(0) } },\1063 { /*src1 */ { FP64_SNAN_V (0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN(1) } },\1064 { /* => */ { FP64_ SNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN(1) } },\1065 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1066 /*128:out */ X86_MXCSR_XCPT_MASK ,\1067 /*256:out */ X86_MXCSR_XCPT_MASK ,\1068 /*xcpt? */ false, false }, 1069 /* SNan, QNan (Masked). */ 1070 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN _V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP64_FRAC_V1) } },\1071 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(1, FP64_FRAC_V2) } },\1072 { /* => */ { FP64_QNAN(0), FP64_QNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(1, FP64_FRAC_V2) } },\1073 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1074 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1075 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1076 /*xcpt? */ false, false }, 1077 { { /*src2 */ { FP64_SNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } },\1078 { /*src1 */ { FP64_QNAN _V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },\1079 { /* => */ { FP64_QNAN _V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },\1080 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1081 /*128:out */ X86_MXCSR_XCPT_MASK ,\1082 /*256:out */ X86_MXCSR_XCPT_MASK ,\1083 /*xcpt? */ false, false }, 1084 { { /*src2 */ { FP64_SNAN_V (0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } },\1085 { /*src1 */ { FP64_QNAN_V (0, FP64_FRAC_V1), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3) } },\1086 { /* => */ { FP64_QNAN_V (0, FP64_FRAC_V1), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3) } },\1087 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1088 /*128:out */ X86_MXCSR_XCPT_MASK ,\1089 /*256:out */ X86_MXCSR_XCPT_MASK ,\1090 /*xcpt? */ false, false }, 1091 /* SNan, SNan (Masked). */ 1092 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN _V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } },\1093 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } },\1094 { /* => */ { FP64_QNAN_V(0, 1), FP64_SNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } },\1095 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1096 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1097 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1098 /*xcpt? */ false, false }, 1099 { { /*src2 */ { FP64_SNAN _V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } },\1100 { /*src1 */ { FP64_SNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3) } },\1101 { /* => */ { FP64_ SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3) } },\1102 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1103 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1104 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1105 /*xcpt? */ false, false }, 1106 { { /*src2 */ { FP64_SNAN_V (0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } },\1107 { /*src1 */ { FP64_SNAN_V (0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } },\1108 { /* => */ { FP64_QNAN_V (0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } },\1109 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1110 /*128:out */ X86_MXCSR_XCPT_MASK ,\1111 /*256:out */ X86_MXCSR_XCPT_MASK ,\1112 /*xcpt? */ false, false }, 1113 /* QNan, Norm FP (Masked). */ 1114 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_ V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } },\1115 { /*src1 */ { FP64_1(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },\1116 { /* => */ { FP64_QNAN(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },\1117 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1118 /*128:out */ X86_MXCSR_XCPT_MASK, 1119 /*256:out */ X86_MXCSR_XCPT_MASK, 1120 /*xcpt? */ false, false }, 1121 /* SNan, Norm FP (Masked). */ 1122 { { /*src2 */ { FP64_SNAN(1), FP64_SNAN_ V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V1) } },\1123 { /*src1 */ { FP64_1(0), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },\1124 { /* => */ { FP64_QNAN_V(1, 1), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },\1125 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1126 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1127 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1128 /*xcpt? */ false, false }, 1129 /* QNan, QNan (Unmasked). */ 1130 /*14*/{ { /*src2 */ { FP64_QNAN(0), FP64_QNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } },\1131 { /*src1 */ { FP64_QNAN(0), FP64_QNAN _V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } },\1132 { /* => */ { FP64_QNAN(0), FP64_QNAN _V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } },\1133 /*mxcsr:in */ 0, 1134 /*128:out */ 0, 1135 /*256:out */ 0, 1136 /*xcpt? */ false, false }, 1137 { { /*src2 */ { FP64_QNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } },\1138 { /*src1 */ { FP64_QNAN _V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2) } },\1139 { /* => */ { FP64_QNAN _V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2) } },\1140 /*mxcsr:in */ 0, 1141 /*128:out */ 0, 1142 /*256:out */ 0, 1143 /*xcpt? */ false, false }, 1144 { { /*src2 */ { FP64_QNAN_V (0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } },\1145 { /*src1 */ { FP64_QNAN_V (0, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(1, FP64_FRAC_V0) } },\1146 { /* => */ { FP64_QNAN_V (0, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(1, FP64_FRAC_V0) } },\1147 /*mxcsr:in */ 0, 1148 /*128:out */ 0, 1149 /*256:out */ 0, 1150 /*xcpt? */ false, false }, 1151 1152 /* QNan, SNan (Unmasked). */ 1153 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V (0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } },\1154 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V (1, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V2) } },\1155 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V (1, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V2) } },\1156 /*mxcsr:in */ 0, 1157 /*128:out */ X86_MXCSR_IE, 1158 /*256:out */ X86_MXCSR_IE, 1159 /*xcpt? */ true, true }, 1160 { { /*src2 */ { FP64_QNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \1161 { /*src1 */ { FP64_SNAN _V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2) } }, \1162 { /* => */ { FP64_QNAN_V(0, 1), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2) } }, \1163 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 1164 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, 1165 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, 1166 /*xcpt? */ true, true }, 1167 { { /*src2 */ { FP64_QNAN_V (0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } },\1168 { /*src1 */ { FP64_SNAN_V (0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } },\1169 { /* => */ { FP64_ SNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } },\1170 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 1171 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO ,\1172 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO ,\1173 /*xcpt? */ false, false },\1174 /* SNan, QNan (Unmasked). */ 1175 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN _V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } },\1176 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },\1177 { /* => */ { FP64_QNAN(0), FP64_QNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },\1178 /*mxcsr:in */ X86_MXCSR_DAZ, 1179 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_IE, 1180 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_IE, 1181 /*xcpt? */ true, true }, 1182 { { /*src2 */ { FP64_SNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP64_FRAC_V1) } },\1183 { /*src1 */ { FP64_QNAN _V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V0) } },\1184 { /* => */ { FP64_QNAN _V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V0) } },\1185 /*mxcsr:in */ X86_MXCSR_RC_UP, 1186 /*128:out */ X86_MXCSR_RC_UP ,\1187 /*256:out */ X86_MXCSR_RC_UP ,\1188 /*xcpt? */ false, false },\1189 { { /*src2 */ { FP64_SNAN_V (0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP64_FRAC_V1) } },\1190 { /*src1 */ { FP64_QNAN_V (0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3) } },\1191 { /* => */ { FP64_QNAN_V (0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3) } },\1192 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 1193 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN ,\1194 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN ,\1195 /*xcpt? */ false, false },\1196 /* SNan, SNan (Unmasked). */ 1197 /*23*/{ { /*src2 */ { FP64_SNAN(0), FP64_SNAN _V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } },\1198 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V0) } },\1199 { /* => */ { FP64_QNAN_V(0, 1), FP64_SNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V0) } },\1200 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 1201 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE, 1202 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE, 1203 /*xcpt? */ true, true }, 1204 { { /*src2 */ { FP64_SNAN _V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP32_FRAC_V2) } },\1205 { /*src1 */ { FP64_SNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(1, FP32_FRAC_V3) } },\1206 { /* => */ { FP64_ SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(1, FP32_FRAC_V3) } },\1207 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 1208 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 1209 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 1210 /*xcpt? */ true, true }, 1211 { { /*src2 */ { FP64_SNAN_V (0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V2) } },\1212 { /*src1 */ { FP64_SNAN_V (0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V3) } },\1213 { /* => */ { FP64_QNAN_V (0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V3) } },\1214 /*mxcsr:in */ 0, 1215 /*128:out */ 0,\1216 /*256:out */ 0,\1217 /*xcpt? */ false, false },\1218 /* QNan, Norm FP (Unmasked). */ 1219 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_ V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } },\1220 { /*src1 */ { FP64_1(0), FP64_INF(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },\1221 { /* => */ { FP64_QNAN(0), FP64_INF(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },\1222 /*mxcsr:in */ X86_MXCSR_FZ, 1223 /*128:out */ X86_MXCSR_FZ, 1224 /*256:out */ X86_MXCSR_FZ, 1225 /*xcpt? */ false, false }, 1226 /* SNan, Norm FP (Unmasked). */ 1227 /*27*/{ { /*src2 */ { FP64_SNAN(1), FP64_SNAN_ V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V1) } },\1228 { /*src1 */ { FP64_1(0), FP64_INF(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },\1229 { /* => */ { FP64_QNAN_V(1, 1), FP64_INF(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },\1230 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 1231 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 1232 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 1233 /*xcpt? */ true, true }, 1065 /* QNan, QNan (Masked). */ \ 1066 /*0 */{ { /*src2 */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V0(0), FP64_QNAN_V1(0) } }, \ 1067 { /*src1 */ { FP64_QNAN(0), FP64_QNAN(1), FP64_QNAN_MAX(1), FP64_QNAN_V2(0) } }, \ 1068 { /* => */ { FP64_QNAN(0), FP64_QNAN(1), FP64_QNAN_MAX(1), FP64_QNAN_V2(0) } }, \ 1069 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1070 /*128:out */ X86_MXCSR_XCPT_MASK, \ 1071 /*256:out */ X86_MXCSR_XCPT_MASK, \ 1072 /*xcpt? */ false, false }, \ 1073 { { /*src2 */ { FP64_QNAN_MAX(0), FP64_QNAN_V1(1), FP64_QNAN_V2(0), FP64_INF(0) } }, \ 1074 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V2(1), FP64_QNAN_V3(1), FP64_SNAN(1) } }, \ 1075 { /* => */ { FP64_QNAN(0), FP64_QNAN_V2(1), FP64_QNAN_V3(1), FP64_SNAN(1) } }, \ 1076 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1077 /*128:out */ X86_MXCSR_XCPT_MASK, \ 1078 /*256:out */ X86_MXCSR_XCPT_MASK, \ 1079 /*xcpt? */ false, false }, \ 1080 { { /*src2 */ { FP64_QNAN_V1(0), FP64_QNAN_V1(0), FP64_QNAN_V2(0), FP64_INF(1) } }, \ 1081 { /*src1 */ { FP64_QNAN_V0(0), FP64_QNAN_V2(0), FP64_QNAN_V3(1), FP64_QNAN(0) } }, \ 1082 { /* => */ { FP64_QNAN_V0(0), FP64_QNAN_V2(0), FP64_QNAN_V3(1), FP64_QNAN(0) } }, \ 1083 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1084 /*128:out */ X86_MXCSR_XCPT_MASK, \ 1085 /*256:out */ X86_MXCSR_XCPT_MASK, \ 1086 /*xcpt? */ false, false }, \ 1087 /* QNan, SNan (Masked). */ \ 1088 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V1(0), FP64_QNAN_V2(0), FP64_QNAN_V3(0) } }, \ 1089 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V2(1), FP64_SNAN_V1(0), FP64_SNAN_V2(1) } }, \ 1090 { /* => */ { FP64_QNAN_V(0, 1), FP64_SNAN_V2(1), FP64_SNAN_V1(0), FP64_SNAN_V2(1) } }, \ 1091 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1092 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1093 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1094 /*xcpt? */ false, false }, \ 1095 { { /*src2 */ { FP64_QNAN_MAX(0), FP64_QNAN_MAX(0), FP64_QNAN_V0(0), FP64_QNAN_V1(0) } }, \ 1096 { /*src1 */ { FP64_SNAN(0), FP64_SNAN(1), FP64_SNAN_MAX(1), FP64_SNAN_V2(0) } }, \ 1097 { /* => */ { FP64_QNAN_V(0, 1), FP64_SNAN(1), FP64_SNAN_MAX(1), FP64_SNAN_V2(0) } }, \ 1098 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1099 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1100 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1101 /*xcpt? */ false, false }, \ 1102 { { /*src2 */ { FP64_QNAN_V1(0), FP64_QNAN_MAX(0), FP64_QNAN_V0(0), FP64_INF(0) } }, \ 1103 { /*src1 */ { FP64_SNAN_V2(0), FP64_QNAN(0), FP64_QNAN_MAX(1), FP64_QNAN(1) } }, \ 1104 { /* => */ { FP64_QNAN_V2(0), FP64_QNAN(0), FP64_QNAN_MAX(1), FP64_QNAN(1) } }, \ 1105 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1106 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1107 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1108 /*xcpt? */ false, false }, \ 1109 /* SNan, QNan (Masked). */ \ 1110 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN(0), FP64_SNAN_V1(0), FP64_SNAN_V1(1) } }, \ 1111 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V3(1), FP64_QNAN_V2(1) } }, \ 1112 { /* => */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V3(1), FP64_QNAN_V2(1) } }, \ 1113 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1114 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1115 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1116 /*xcpt? */ false, false }, \ 1117 { { /*src2 */ { FP64_SNAN_MAX(0), FP64_SNAN_MAX(1), FP64_SNAN_V1(0), FP64_SNAN_V1(0) } }, \ 1118 { /*src1 */ { FP64_QNAN(0), FP64_QNAN(1), FP64_QNAN_V3(1), FP64_QNAN_V2(0) } }, \ 1119 { /* => */ { FP64_QNAN(0), FP64_QNAN(1), FP64_QNAN_V3(1), FP64_QNAN_V2(0) } }, \ 1120 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1121 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1122 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1123 /*xcpt? */ false, false }, \ 1124 { { /*src2 */ { FP64_SNAN_V0(0), FP64_SNAN_MAX(0), FP64_SNAN_V1(0), FP64_SNAN_V1(0) } }, \ 1125 { /*src1 */ { FP64_QNAN_V1(0), FP64_QNAN(1), FP64_QNAN_V2(1), FP64_QNAN_V3(1) } }, \ 1126 { /* => */ { FP64_QNAN_V1(0), FP64_QNAN(1), FP64_QNAN_V2(1), FP64_QNAN_V3(1) } }, \ 1127 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1128 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1129 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1130 /*xcpt? */ false, false }, \ 1131 /* SNan, SNan (Masked). */ \ 1132 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN(0), FP64_SNAN_V1(0), FP64_SNAN_V2(0) } }, \ 1133 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_MAX(0), FP64_SNAN_V0(0), FP64_SNAN_V3(0) } }, \ 1134 { /* => */ { FP64_QNAN_V(0, 1), FP64_SNAN_MAX(0), FP64_SNAN_V0(0), FP64_SNAN_V3(0) } }, \ 1135 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1136 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1137 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1138 /*xcpt? */ false, false }, \ 1139 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V2(0), FP64_SNAN_V1(0), FP64_SNAN_V2(0) } }, \ 1140 { /*src1 */ { FP64_SNAN_MAX(0), FP64_SNAN_V0(0), FP64_SNAN_V2(0), FP64_SNAN_V3(1) } }, \ 1141 { /* => */ { FP64_QNAN_MAX(0), FP64_SNAN_V0(0), FP64_SNAN_V2(0), FP64_SNAN_V3(1) } }, \ 1142 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1143 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1144 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1145 /*xcpt? */ false, false }, \ 1146 { { /*src2 */ { FP64_SNAN_V1(0), FP64_SNAN_V2(0), FP64_SNAN_V1(0), FP64_SNAN_V2(0) } }, \ 1147 { /*src1 */ { FP64_SNAN_V0(0), FP64_SNAN_V3(0), FP64_SNAN_V0(0), FP64_SNAN_V3(0) } }, \ 1148 { /* => */ { FP64_QNAN_V0(0), FP64_SNAN_V3(0), FP64_SNAN_V0(0), FP64_SNAN_V3(0) } }, \ 1149 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1150 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1151 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1152 /*xcpt? */ false, false }, \ 1153 /* QNan, Norm FP (Masked). */ \ 1154 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_MAX(1), FP64_NORM_V0(1), FP64_QNAN_V1(0) } }, \ 1155 { /*src1 */ { FP64_1(0), FP64_1(1), FP64_QNAN_V0(1), FP64_NORM_V2(1) } }, \ 1156 { /* => */ { FP64_QNAN(0), FP64_1(1), FP64_QNAN_V0(1), FP64_NORM_V2(1) } }, \ 1157 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1158 /*128:out */ X86_MXCSR_XCPT_MASK, \ 1159 /*256:out */ X86_MXCSR_XCPT_MASK, \ 1160 /*xcpt? */ false, false }, \ 1161 /* SNan, Norm FP (Masked). */ \ 1162 { { /*src2 */ { FP64_SNAN(1), FP64_SNAN_MAX(1), FP64_NORM_V0(1), FP64_SNAN_V1(0) } }, \ 1163 { /*src1 */ { FP64_1(0), FP64_1(0), FP64_SNAN_V0(1), FP64_NORM_V2(1) } }, \ 1164 { /* => */ { FP64_QNAN_V(1, 1), FP64_1(0), FP64_SNAN_V0(1), FP64_NORM_V2(1) } }, \ 1165 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1166 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1167 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1168 /*xcpt? */ false, false }, \ 1169 /* QNan, QNan (Unmasked). */ \ 1170 /*14*/{ { /*src2 */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V0(0), FP64_QNAN_V1(0) } }, \ 1171 { /*src1 */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V2(0) } }, \ 1172 { /* => */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V2(0) } }, \ 1173 /*mxcsr:in */ 0, \ 1174 /*128:out */ 0, \ 1175 /*256:out */ 0, \ 1176 /*xcpt? */ false, false }, \ 1177 { { /*src2 */ { FP64_QNAN_MAX(0), FP64_QNAN_V1(0), FP64_QNAN_V2(0), FP64_QNAN_V3(0) } }, \ 1178 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V2(0), FP64_QNAN_V0(0), FP64_QNAN_V2(0) } }, \ 1179 { /* => */ { FP64_QNAN(0), FP64_QNAN_V2(0), FP64_QNAN_V0(0), FP64_QNAN_V2(0) } }, \ 1180 /*mxcsr:in */ 0, \ 1181 /*128:out */ 0, \ 1182 /*256:out */ 0, \ 1183 /*xcpt? */ false, false }, \ 1184 { { /*src2 */ { FP64_QNAN_V1(0), FP64_QNAN_V1(0), FP64_QNAN_V2(0), FP64_QNAN_V3(0) } }, \ 1185 { /*src1 */ { FP64_QNAN_V2(0), FP64_QNAN_V2(1), FP64_QNAN_V0(0), FP64_QNAN_V0(1) } }, \ 1186 { /* => */ { FP64_QNAN_V2(0), FP64_QNAN_V2(1), FP64_QNAN_V0(0), FP64_QNAN_V0(1) } }, \ 1187 /*mxcsr:in */ 0, \ 1188 /*128:out */ 0, \ 1189 /*256:out */ 0, \ 1190 /*xcpt? */ false, false }, \ 1191 \ 1192 /* QNan, SNan (Unmasked). */ \ 1193 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V1(0), FP64_QNAN_V2(0), FP64_QNAN_V3(0) } }, \ 1194 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V2(1), FP64_SNAN_V3(1), FP64_SNAN_V2(0) } }, \ 1195 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V2(1), FP64_SNAN_V3(1), FP64_SNAN_V2(0) } }, \ 1196 /*mxcsr:in */ 0, \ 1197 /*128:out */ X86_MXCSR_IE, \ 1198 /*256:out */ X86_MXCSR_IE, \ 1199 /*xcpt? */ true, true }, \ 1200 { { /*src2 */ { FP64_QNAN_MAX(0), FP64_QNAN_MAX(0), FP64_QNAN_V0(0), FP64_QNAN_V1(0) } }, \ 1201 { /*src1 */ { FP64_SNAN(0), FP64_SNAN(0), FP64_SNAN_MAX(0), FP64_SNAN_V2(0) } }, \ 1202 { /* => */ { FP64_QNAN_V(0, 1), FP64_SNAN(0), FP64_SNAN_MAX(0), FP64_SNAN_V2(0) } }, \ 1203 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, \ 1204 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, \ 1205 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, \ 1206 /*xcpt? */ true, true }, \ 1207 { { /*src2 */ { FP64_QNAN_V1(0), FP64_QNAN_MAX(0), FP64_QNAN_V0(0), FP64_QNAN_V1(0) } }, \ 1208 { /*src1 */ { FP64_SNAN_V2(0), FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V2(0) } }, \ 1209 { /* => */ { FP64_QNAN_V2(0), FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V2(0) } }, \ 1210 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, \ 1211 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, \ 1212 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, \ 1213 /*xcpt? */ true, true }, \ 1214 /* SNan, QNan (Unmasked). */ \ 1215 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN(0), FP64_SNAN_V1(0), FP64_SNAN_V1(0) } }, \ 1216 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V3(0), FP64_QNAN_V2(0) } }, \ 1217 { /* => */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V3(0), FP64_QNAN_V2(0) } }, \ 1218 /*mxcsr:in */ X86_MXCSR_DAZ, \ 1219 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_IE, \ 1220 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_IE, \ 1221 /*xcpt? */ true, true }, \ 1222 { { /*src2 */ { FP64_SNAN_MAX(0), FP64_SNAN_MAX(0), FP64_SNAN_V1(0), FP64_SNAN_V1(1) } }, \ 1223 { /*src1 */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_V2(1), FP64_QNAN_V0(1) } }, \ 1224 { /* => */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_V2(1), FP64_QNAN_V0(1) } }, \ 1225 /*mxcsr:in */ X86_MXCSR_RC_UP, \ 1226 /*128:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, \ 1227 /*256:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, \ 1228 /*xcpt? */ true, true }, \ 1229 { { /*src2 */ { FP64_SNAN_V0(0), FP64_SNAN_MAX(0), FP64_SNAN_V1(0), FP64_SNAN_V1(1) } }, \ 1230 { /*src1 */ { FP64_QNAN_V3(0), FP64_QNAN(0), FP64_QNAN_V2(1), FP64_QNAN_V3(1) } }, \ 1231 { /* => */ { FP64_QNAN_V3(0), FP64_QNAN(0), FP64_QNAN_V2(1), FP64_QNAN_V3(1) } }, \ 1232 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, \ 1233 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, \ 1234 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, \ 1235 /*xcpt? */ true, true }, \ 1236 /* SNan, SNan (Unmasked). */ \ 1237 /*23*/{ { /*src2 */ { FP64_SNAN(0), FP64_SNAN(0), FP64_SNAN_V1(0), FP64_SNAN_V2(0) } }, \ 1238 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_MAX(0), FP64_SNAN_V2(0), FP64_SNAN_V0(1) } }, \ 1239 { /* => */ { FP64_QNAN_V(0, 1), FP64_SNAN_MAX(0), FP64_SNAN_V2(0), FP64_SNAN_V0(1) } }, \ 1240 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, \ 1241 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE, \ 1242 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE, \ 1243 /*xcpt? */ true, true }, \ 1244 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V2(0), FP64_SNAN_V1(0), FP64_SNAN_V2(1) } }, \ 1245 { /*src1 */ { FP64_SNAN_MAX(0), FP64_SNAN_V0(0), FP64_SNAN_V2(1), FP64_SNAN_V3(1) } }, \ 1246 { /* => */ { FP64_QNAN_MAX(0), FP64_SNAN_V0(0), FP64_SNAN_V2(1), FP64_SNAN_V3(1) } }, \ 1247 /*mxcsr:in */ X86_MXCSR_RC_ZERO, \ 1248 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE, \ 1249 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE, \ 1250 /*xcpt? */ true, true }, \ 1251 { { /*src2 */ { FP64_SNAN_V1(0), FP64_SNAN_V2(0), FP64_SNAN_V0(1), FP64_SNAN_V2(0) } }, \ 1252 { /*src1 */ { FP64_SNAN_V2(0), FP64_SNAN_V3(1), FP64_SNAN_V3(1), FP64_SNAN_V3(0) } }, \ 1253 { /* => */ { FP64_QNAN_V2(0), FP64_SNAN_V3(1), FP64_SNAN_V3(1), FP64_SNAN_V3(0) } }, \ 1254 /*mxcsr:in */ 0, \ 1255 /*128:out */ X86_MXCSR_IE, \ 1256 /*256:out */ X86_MXCSR_IE, \ 1257 /*xcpt? */ true, true }, \ 1258 /* QNan, Norm FP (Unmasked). */ \ 1259 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_MAX(1), FP64_NORM_V0(1), FP64_QNAN_V1(0) } }, \ 1260 { /*src1 */ { FP64_1(0), FP64_INF(1), FP64_QNAN_V0(1), FP64_NORM_V2(1) } }, \ 1261 { /* => */ { FP64_QNAN(0), FP64_INF(1), FP64_QNAN_V0(1), FP64_NORM_V2(1) } }, \ 1262 /*mxcsr:in */ X86_MXCSR_FZ, \ 1263 /*128:out */ X86_MXCSR_FZ, \ 1264 /*256:out */ X86_MXCSR_FZ, \ 1265 /*xcpt? */ false, false }, \ 1266 /* SNan, Norm FP (Unmasked). */ \ 1267 /*27*/{ { /*src2 */ { FP64_SNAN(1), FP64_SNAN_MAX(1), FP64_NORM_V0(1), FP64_SNAN_V1(0) } }, \ 1268 { /*src1 */ { FP64_1(0), FP64_INF(0), FP64_SNAN_V0(1), FP64_NORM_V2(1) } }, \ 1269 { /* => */ { FP64_QNAN_V(1, 1), FP64_INF(0), FP64_SNAN_V0(1), FP64_NORM_V2(1) } }, \ 1270 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, \ 1271 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, \ 1272 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, \ 1273 /*xcpt? */ true, true }, \ 1234 1274 1235 1275 /** … … 1328 1368 **/ 1329 1369 #define FP64_TABLE_D1_H_PD_INVALIDS \ 1330 /* 0*/{ { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \ 1331 { /*src1 */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } }, \ 1332 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V0) } }, \ 1333 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1334 /*128:out */ X86_MXCSR_XCPT_MASK, \ 1335 /*256:out */ X86_MXCSR_XCPT_MASK, \ 1336 /*xcpt? */ false, false }, \ 1337 { { /*src2 */ { FP64_QNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \ 1338 { /*src1 */ { FP64_QNAN(0), FP64_SNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V2) } }, \ 1339 { /* => */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } }, \ 1340 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1341 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1342 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1343 /*xcpt? */ false, false }, \ 1344 { { /*src2 */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2) } }, \ 1345 { /*src1 */ { FP64_SNAN(0), FP64_QNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V3) } }, \ 1346 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \ 1347 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1348 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1349 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1350 /*xcpt? */ false, false }, \ 1351 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN) } }, \ 1352 { /*src1 */ { FP64_SNAN(0), FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX) } }, \ 1353 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } }, \ 1354 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1355 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1356 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1357 /*xcpt? */ false, false }, \ 1358 { { /*src2 */ { FP64_QNAN(0), FP64_NORM_V1(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \ 1359 { /*src1 */ { FP64_QNAN(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V2(1) } }, \ 1360 { /* => */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } }, \ 1361 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1362 /*128:out */ X86_MXCSR_XCPT_MASK, \ 1363 /*256:out */ X86_MXCSR_XCPT_MASK, \ 1364 /*xcpt? */ false, false }, \ 1365 { { /*src2 */ { FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_1(0), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_NORM_V3(0) } }, \ 1366 { /*src1 */ { FP64_SNAN(0), FP64_1(1), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_NORM_V2(1) } }, \ 1367 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \ 1368 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1369 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1370 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1371 /*xcpt? */ false, false }, \ 1372 { { /*src2 */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \ 1373 { /*src1 */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } }, \ 1374 { /* => */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V0) } }, \ 1375 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, \ 1376 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, \ 1377 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, \ 1378 /*xcpt? */ false, false }, \ 1379 { { /*src2 */ { FP64_QNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \ 1380 { /*src1 */ { FP64_QNAN(0), FP64_SNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V2) } }, \ 1381 { /* => */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } }, \ 1382 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, \ 1383 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, \ 1384 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, \ 1385 /*xcpt? */ true, true }, \ 1386 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN) } }, \ 1387 { /*src1 */ { FP64_SNAN(0), FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX) } }, \ 1388 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } }, \ 1389 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, \ 1390 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, \ 1391 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, \ 1392 /*xcpt? */ true, true }, \ 1393 /* 9*/{ { /*src2 */ { FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_1(0), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_NORM_V3(0) } }, \ 1394 { /*src1 */ { FP64_SNAN(0), FP64_1(1), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_NORM_V2(1) } }, \ 1395 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \ 1396 /*mxcsr:in */ X86_MXCSR_RC_UP, \ 1397 /*128:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, \ 1398 /*256:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, \ 1399 /*xcpt? */ true, true }, \ 1370 /*0 */{ { /*src2 */ { FP64_QNAN_MAX(0), FP64_QNAN(0), FP64_QNAN_V0(0), FP64_QNAN_V1(0) } }, \ 1371 { /*src1 */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_MAX(0) } }, \ 1372 { /* => */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN(0), FP64_QNAN_V0(0) } }, \ 1373 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1374 /*128:out */ X86_MXCSR_XCPT_MASK, \ 1375 /*256:out */ X86_MXCSR_XCPT_MASK, \ 1376 /*xcpt? */ false, false }, \ 1377 { { /*src2 */ { FP64_QNAN(0), FP64_SNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V1(0) } }, \ 1378 { /*src1 */ { FP64_QNAN(0), FP64_SNAN(0), FP64_QNAN(0), FP64_SNAN_V2(0) } }, \ 1379 { /* => */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_MAX(0) } }, \ 1380 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1381 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1382 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1383 /*xcpt? */ false, false }, \ 1384 { { /*src2 */ { FP64_SNAN_MAX(0), FP64_QNAN_V2(0), FP64_SNAN_V1(0), FP64_QNAN_V2(0) } }, \ 1385 { /*src1 */ { FP64_SNAN(0), FP64_QNAN(0), FP64_SNAN(0), FP64_QNAN_V3(0) } }, \ 1386 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_MAX(0), FP64_QNAN_V(0, 1), FP64_QNAN_V1(0) } }, \ 1387 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1388 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1389 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1390 /*xcpt? */ false, false }, \ 1391 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_MAX(0), FP64_SNAN_MAX(0), FP64_SNAN(0) } }, \ 1392 { /*src1 */ { FP64_SNAN(0), FP64_SNAN(0), FP64_SNAN(0), FP64_SNAN_MAX(0) } }, \ 1393 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_MAX(0) } }, \ 1394 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1395 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1396 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1397 /*xcpt? */ false, false }, \ 1398 { { /*src2 */ { FP64_QNAN(0), FP64_NORM_V1(0), FP64_QNAN_MAX(0), FP64_QNAN_V1(0) } }, \ 1399 { /*src1 */ { FP64_QNAN(0), FP64_1(1), FP64_QNAN_MAX(1), FP64_NORM_V2(1) } }, \ 1400 { /* => */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_MAX(1), FP64_QNAN_MAX(0) } }, \ 1401 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1402 /*128:out */ X86_MXCSR_XCPT_MASK, \ 1403 /*256:out */ X86_MXCSR_XCPT_MASK, \ 1404 /*xcpt? */ false, false }, \ 1405 { { /*src2 */ { FP64_SNAN_MAX(1), FP64_1(0), FP64_SNAN_V1(0), FP64_NORM_V3(0) } }, \ 1406 { /*src1 */ { FP64_SNAN(0), FP64_1(1), FP64_SNAN_MAX(0), FP64_NORM_V2(1) } }, \ 1407 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_MAX(1), FP64_QNAN_MAX(0), FP64_QNAN_V1(0) } }, \ 1408 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1409 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1410 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1411 /*xcpt? */ false, false }, \ 1412 { { /*src2 */ { FP64_QNAN_MAX(0), FP64_QNAN(0), FP64_QNAN_V0(0), FP64_QNAN_V1(0) } }, \ 1413 { /*src1 */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_MAX(0) } }, \ 1414 { /* => */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN(0), FP64_QNAN_V0(0) } }, \ 1415 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, \ 1416 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, \ 1417 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, \ 1418 /*xcpt? */ false, false }, \ 1419 { { /*src2 */ { FP64_QNAN(0), FP64_SNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V1(0) } }, \ 1420 { /*src1 */ { FP64_QNAN(0), FP64_SNAN(0), FP64_QNAN(0), FP64_SNAN_V2(0) } }, \ 1421 { /* => */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_MAX(0) } }, \ 1422 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, \ 1423 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, \ 1424 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, \ 1425 /*xcpt? */ true, true }, \ 1426 { { /*src2 */ { FP64_SNAN_MAX(0), FP64_QNAN_V2(0), FP64_SNAN_V1(0), FP64_QNAN_V2(0) } }, \ 1427 { /*src1 */ { FP64_SNAN(0), FP64_QNAN(0), FP64_SNAN(0), FP64_QNAN_V3(0) } }, \ 1428 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_MAX(0), FP64_QNAN_V(0, 1), FP64_QNAN_V1(0) } }, \ 1429 /*mxcsr:in */ 0, \ 1430 /*128:out */ X86_MXCSR_IE, \ 1431 /*256:out */ X86_MXCSR_IE, \ 1432 /*xcpt? */ true, true }, \ 1433 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_MAX(0), FP64_SNAN_MAX(0), FP64_SNAN(0) } }, \ 1434 { /*src1 */ { FP64_SNAN(0), FP64_SNAN(0), FP64_SNAN(0), FP64_SNAN_MAX(0) } }, \ 1435 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_MAX(0) } }, \ 1436 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, \ 1437 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, \ 1438 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, \ 1439 /*xcpt? */ true, true }, \ 1440 { { /*src2 */ { FP64_QNAN(0), FP64_NORM_V1(0), FP64_QNAN_MAX(0), FP64_QNAN_V1(0) } }, \ 1441 { /*src1 */ { FP64_QNAN(0), FP64_1(1), FP64_QNAN_MAX(1), FP64_NORM_V2(1) } }, \ 1442 { /* => */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_MAX(1), FP64_QNAN_MAX(0) } }, \ 1443 /*mxcsr:in */ 0, \ 1444 /*128:out */ 0, \ 1445 /*256:out */ 0, \ 1446 /*xcpt? */ false, false }, \ 1447 /*11*/{ { /*src2 */ { FP64_SNAN_MAX(1), FP64_1(0), FP64_SNAN_V1(0), FP64_NORM_V3(0) } }, \ 1448 { /*src1 */ { FP64_SNAN(0), FP64_1(1), FP64_SNAN_MAX(0), FP64_NORM_V2(1) } }, \ 1449 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_MAX(1), FP64_QNAN_MAX(0), FP64_QNAN_V1(0) } }, \ 1450 /*mxcsr:in */ X86_MXCSR_RC_UP, \ 1451 /*128:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, \ 1452 /*256:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, \ 1453 /*xcpt? */ true, true }, \ 1400 1454 1401 1455 /** … … 1480 1534 **/ 1481 1535 #define FP64_TABLE_D9_PD_INVALIDS \ 1482 /* 0*/{ { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \1483 { /*src1 */ { FP64_QNAN(0), FP64_QNAN _V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, \1484 { /* => */ { FP64_QNAN(0), FP64_QNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \1485 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1486 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1487 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1488 /*xcpt? */ false, false }, 1489 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \1490 { /*src1 */ { FP64_SNAN(0), FP64_SNAN _V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2) } }, \1491 { /* => */ { FP64_QNAN(0), FP64_QNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \1492 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1493 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1494 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1495 /*xcpt? */ false, false }, 1496 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN _V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } },\1497 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } },\1498 { /* => */ { FP64_SNAN(0), FP64_SNAN _V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } },\1499 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, 1500 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, 1501 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, 1502 /*xcpt? */ false, false }, 1503 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN _V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } },\1504 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V3) } },\1505 { /* => */ { FP64_SNAN(0), FP64_SNAN _V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } },\1506 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1507 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1508 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1509 /*xcpt? */ false, false }, 1510 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_ V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } },\1511 { /*src1 */ { FP64_1(0), FP64_1(1), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },\1512 { /* => */ { FP64_QNAN(0), FP64_QNAN_ V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_QNAN_V(0, FP64_FRAC_V1) } },\1513 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1514 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1515 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1516 /*xcpt? */ false, false }, 1517 { { /*src2 */ { FP64_SNAN(1), FP64_SNAN_ V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V1) } },\1518 { /*src1 */ { FP64_1(0), FP64_1(0), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1) } },\1519 { /* => */ { FP64_SNAN(1), FP64_SNAN_ V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1), FP64_SNAN_V(0, FP64_FRAC_V1) } },\1520 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1521 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1522 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1523 /*xcpt? */ false, false }, 1524 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \1525 { /*src1 */ { FP64_QNAN(0), FP64_QNAN _V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, \1526 { /* => */ { FP64_QNAN(0), FP64_QNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \1527 /*mxcsr:in */ 0, 1528 /*128:out */ X86_MXCSR_IE, 1529 /*256:out */ X86_MXCSR_IE, 1530 /*xcpt? */ true, true }, 1531 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \1532 { /*src1 */ { FP64_SNAN(0), FP64_SNAN _V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2) } }, \1533 { /* => */ { FP64_QNAN(0), FP64_QNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \1534 /*mxcsr:in */ 0, 1535 /*128:out */ X86_MXCSR_IE, 1536 /*256:out */ X86_MXCSR_IE, 1537 /*xcpt? */ true, true }, 1538 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN _V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } },\1539 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } },\1540 { /* => */ { FP64_SNAN(0), FP64_SNAN(0), FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V1) } },\1541 /*mxcsr:in */ 0, 1542 /*128:out */ X86_MXCSR_IE, 1543 /*256:out */ X86_MXCSR_IE, 1544 /*xcpt? */ true, true }, 1545 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN _V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } },\1546 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V3) } },\1547 { /* => */ { FP64_SNAN(0), FP64_SNAN _V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } },\1548 /*mxcsr:in */ 0, 1549 /*128:out */ X86_MXCSR_IE, 1550 /*256:out */ X86_MXCSR_IE, 1551 /*xcpt? */ true, true }, 1536 /*0 */{ { /*src2 */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V0(0), FP64_QNAN_V1(0) } }, \ 1537 { /*src1 */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V2(0) } }, \ 1538 { /* => */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V0(0), FP64_QNAN_V1(0) } }, \ 1539 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1540 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1541 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1542 /*xcpt? */ false, false }, \ 1543 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V0(0), FP64_QNAN_V1(0) } }, \ 1544 { /*src1 */ { FP64_SNAN(0), FP64_SNAN(0), FP64_SNAN_MAX(0), FP64_SNAN_V2(0) } }, \ 1545 { /* => */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V0(0), FP64_QNAN_V1(0) } }, \ 1546 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1547 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1548 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1549 /*xcpt? */ false, false }, \ 1550 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN(0), FP64_SNAN_V1(0), FP64_SNAN_V1(0) } }, \ 1551 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V2(0), FP64_QNAN_V3(0) } }, \ 1552 { /* => */ { FP64_SNAN(0), FP64_SNAN(0), FP64_SNAN_V1(0), FP64_SNAN_V1(0) } }, \ 1553 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, \ 1554 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, \ 1555 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, \ 1556 /*xcpt? */ false, false }, \ 1557 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN(0), FP64_SNAN_V1(0), FP64_SNAN_V2(0) } }, \ 1558 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_MAX(0), FP64_SNAN_V2(0), FP64_SNAN_V3(0) } }, \ 1559 { /* => */ { FP64_SNAN(0), FP64_SNAN(0), FP64_SNAN_V1(0), FP64_SNAN_V2(0) } }, \ 1560 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1561 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1562 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1563 /*xcpt? */ false, false }, \ 1564 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_MAX(1), FP64_NORM_V0(1), FP64_QNAN_V1(0) } }, \ 1565 { /*src1 */ { FP64_1(0), FP64_1(1), FP64_QNAN_V0(1), FP64_NORM_V2(1) } }, \ 1566 { /* => */ { FP64_QNAN(0), FP64_QNAN_MAX(1), FP64_NORM_V0(1), FP64_QNAN_V1(0) } }, \ 1567 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1568 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1569 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1570 /*xcpt? */ false, false }, \ 1571 { { /*src2 */ { FP64_SNAN(1), FP64_SNAN_MAX(1), FP64_NORM_V0(1), FP64_SNAN_V1(0) } }, \ 1572 { /*src1 */ { FP64_1(0), FP64_1(0), FP64_SNAN_V0(1), FP64_NORM_V2(1) } }, \ 1573 { /* => */ { FP64_SNAN(1), FP64_SNAN_MAX(1), FP64_NORM_V0(1), FP64_SNAN_V1(0) } }, \ 1574 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1575 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1576 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1577 /*xcpt? */ false, false }, \ 1578 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V0(0), FP64_QNAN_V1(0) } }, \ 1579 { /*src1 */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V2(0) } }, \ 1580 { /* => */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V0(0), FP64_QNAN_V1(0) } }, \ 1581 /*mxcsr:in */ 0, \ 1582 /*128:out */ X86_MXCSR_IE, \ 1583 /*256:out */ X86_MXCSR_IE, \ 1584 /*xcpt? */ true, true }, \ 1585 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V0(0), FP64_QNAN_V1(0) } }, \ 1586 { /*src1 */ { FP64_SNAN(0), FP64_SNAN(0), FP64_SNAN_MAX(0), FP64_SNAN_V2(0) } }, \ 1587 { /* => */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V0(0), FP64_QNAN_V1(0) } }, \ 1588 /*mxcsr:in */ 0, \ 1589 /*128:out */ X86_MXCSR_IE, \ 1590 /*256:out */ X86_MXCSR_IE, \ 1591 /*xcpt? */ true, true }, \ 1592 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN(0), FP64_SNAN_V1(0), FP64_SNAN_V1(0) } }, \ 1593 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V2(0), FP64_QNAN_V3(0) } }, \ 1594 { /* => */ { FP64_SNAN(0), FP64_SNAN(0), FP64_SNAN_V1(0), FP64_SNAN_V1(0) } }, \ 1595 /*mxcsr:in */ 0, \ 1596 /*128:out */ X86_MXCSR_IE, \ 1597 /*256:out */ X86_MXCSR_IE, \ 1598 /*xcpt? */ true, true }, \ 1599 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN(0), FP64_SNAN_V1(0), FP64_SNAN_V2(0) } }, \ 1600 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_MAX(0), FP64_SNAN_V2(0), FP64_SNAN_V3(0) } }, \ 1601 { /* => */ { FP64_SNAN(0), FP64_SNAN(0), FP64_SNAN_V1(0), FP64_SNAN_V2(0) } }, \ 1602 /*mxcsr:in */ 0, \ 1603 /*128:out */ X86_MXCSR_IE, \ 1604 /*256:out */ X86_MXCSR_IE, \ 1605 /*xcpt? */ true, true }, \ 1552 1606 1553 1607 /** … … 1770 1824 **/ 1771 1825 #define FP64_TABLE_D9_SD_INVALIDS \ 1772 /* QNan, QNan (Masked). */ 1773 /* 0*/{ { /*src2 */ { FP64_QNAN(0), FP64_RAND_V2(0), FP64_RAND_V0(1), FP64_RAND_V1(0) } },\1774 { /*src1 */ { FP64_QNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, 1775 { /* => */ { FP64_QNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, 1776 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1777 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1778 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1779 /*xcpt? */ false, false }, 1780 { { /*src2 */ { FP64_QNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(0) } }, \1781 { /*src1 */ { FP64_QNAN _V(0, FP64_FRAC_NORM_MIN),FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V3(1) } }, \1782 { /* => */ { FP64_QNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V3(1) } }, \1783 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1784 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1785 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1786 /*xcpt? */ false, false }, 1787 { { /*src2 */ { FP64_QNAN_V (0, FP64_FRAC_V0),FP64_RAND_V0(1), FP64_RAND_V0(1), FP64_RAND_V2(0) } }, \1788 { /*src1 */ { FP64_QNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_RAND_V1(0), FP64_RAND_V0(0), FP64_RAND_V2(1) } }, \1789 { /* => */ { FP64_QNAN_V (0, FP64_FRAC_V0),FP64_RAND_V1(0), FP64_RAND_V0(0), FP64_RAND_V2(1) } }, \1790 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1791 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1792 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1793 /*xcpt? */ false, false }, 1794 /* QNan, SNan (Masked). */ 1795 { { /*src2 */ { FP64_QNAN(0), FP64_RAND_V1(0), FP64_RAND_V3(1), FP64_RAND_V2(0) } }, 1796 { /*src1 */ { FP64_SNAN(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(0) } }, 1797 { /* => */ { FP64_QNAN(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(0) } }, 1798 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1799 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1800 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1801 /*xcpt? */ false, false }, 1802 { { /*src2 */ { FP64_QNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_RAND_V2(1), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, \1803 { /*src1 */ { FP64_SNAN _V(0, FP64_FRAC_NORM_MIN),FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, \1804 { /* => */ { FP64_QNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, \1805 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1806 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1807 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1808 /*xcpt? */ false, false }, 1809 { { /*src2 */ { FP64_QNAN_V (0, FP64_FRAC_V0),FP64_RAND_V1(1), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, \1810 { /*src1 */ { FP64_SNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_RAND_V3(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } }, \1811 { /* => */ { FP64_QNAN_V (0, FP64_FRAC_V0),FP64_RAND_V3(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } }, \1812 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1813 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1814 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1815 /*xcpt? */ false, false }, 1816 /* SNan, QNan (Masked). */ 1817 { { /*src2 */ { FP64_SNAN(0), FP64_RAND_V2(1), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, 1818 { /*src1 */ { FP64_QNAN(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, 1819 { /* => */ { FP64_SNAN(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, 1820 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, 1821 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, 1822 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, 1823 /*xcpt? */ false, false }, 1824 { { /*src2 */ { FP64_SNAN _V(0, FP64_FRAC_NORM_MIN),FP64_RAND_V1(1), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, \1825 { /*src1 */ { FP64_QNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_RAND_V2(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, \1826 { /* => */ { FP64_SNAN _V(0, FP64_FRAC_NORM_MIN),FP64_RAND_V2(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, \1827 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1828 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1829 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1830 /*xcpt? */ false, false }, 1831 { { /*src2 */ { FP64_SNAN_V (0, FP64_FRAC_V1), FP64_RAND_V1(1), FP64_RAND_V0(1), FP64_RAND_V2(0) } },\1832 { /*src1 */ { FP64_QNAN_V (0, FP64_FRAC_V1), FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } },\1833 { /* => */ { FP64_SNAN_V (0, FP64_FRAC_V1), FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } },\1834 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1835 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1836 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1837 /*xcpt? */ false, false }, 1838 /* SNan, SNan (Masked). */ 1839 { { /*src2 */ { FP64_SNAN(0), FP64_RAND_V1(1), FP64_RAND_V0(1), FP64_RAND_V2(0) } }, 1840 { /*src1 */ { FP64_SNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, 1841 { /* => */ { FP64_SNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, 1842 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1843 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1844 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1845 /*xcpt? */ false, false }, 1846 { { /*src2 */ { FP64_SNAN _V(0, FP64_FRAC_NORM_MIN),FP64_RAND_V1(0), FP64_RAND_V0(1), FP64_RAND_V2(1) } }, \1847 { /*src1 */ { FP64_SNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_RAND_V0(0), FP64_RAND_V3(0), FP64_RAND_V0(1) } }, \1848 { /* => */ { FP64_SNAN _V(0, FP64_FRAC_NORM_MIN),FP64_RAND_V0(0), FP64_RAND_V3(0), FP64_RAND_V0(1) } }, \1849 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1850 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1851 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1852 /*xcpt? */ false, false }, 1853 { { /*src2 */ { FP64_SNAN_V (0, FP64_FRAC_V1), FP64_RAND_V1(1), FP64_RAND_V1(1), FP64_RAND_V2(0) } },\1854 { /*src1 */ { FP64_SNAN_V (0, FP64_FRAC_V2), FP64_RAND_V2(1), FP64_RAND_V3(1), FP64_RAND_V1(1) } },\1855 { /* => */ { FP64_SNAN_V (0, FP64_FRAC_V1), FP64_RAND_V2(1), FP64_RAND_V3(1), FP64_RAND_V1(1) } },\1856 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1857 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1858 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1859 /*xcpt? */ false, false }, 1860 /* QNan, Normal ( Masked). */\1861 { { /*src2 */ { FP64_QNAN(0), FP64_RAND_V3(1), FP64_RAND_V2(1), FP64_RAND_V2(0) } }, 1862 { /*src1 */ { FP64_1(0), FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V1(1) } }, 1863 { /* => */ { FP64_QNAN(0), FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V1(1) } }, 1864 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1865 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1866 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1867 /*xcpt? */ false, false }, 1868 /* SNan, Normal (Masked). */ 1869 { { /*src2 */ { FP64_SNAN(1), FP64_RAND_V0(1), FP64_RAND_V2(1), FP64_RAND_V2(0) } }, 1870 { /*src1 */ { FP64_1(0), FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V3(1) } }, 1871 { /* => */ { FP64_SNAN(1), FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V3(1) } }, 1872 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 1873 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1874 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, 1875 /*xcpt? */ false, false }, 1876 /* QNan, QNan (Unmasked). */ 1877 /* 0*/{ { /*src2 */ { FP64_QNAN(0), FP64_RAND_V2(0), FP64_RAND_V0(1), FP64_RAND_V1(0) } },\1878 { /*src1 */ { FP64_QNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, 1879 { /* => */ { FP64_QNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, 1880 /*mxcsr:in */ 0, 1881 /*128:out */ X86_MXCSR_IE, 1882 /*256:out */ X86_MXCSR_IE, 1883 /*xcpt? */ true, true }, 1884 { { /*src2 */ { FP64_QNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(0) } }, \1885 { /*src1 */ { FP64_QNAN _V(0, FP64_FRAC_NORM_MIN),FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V3(1) } }, \1886 { /* => */ { FP64_QNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V3(1) } }, \1887 /*mxcsr:in */ 0, 1888 /*128:out */ X86_MXCSR_IE, 1889 /*256:out */ X86_MXCSR_IE, 1890 /*xcpt? */ true, true }, 1891 { { /*src2 */ { FP64_QNAN_V (0, FP64_FRAC_V0),FP64_RAND_V0(1), FP64_RAND_V0(1), FP64_RAND_V2(0) } }, \1892 { /*src1 */ { FP64_QNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_RAND_V1(0), FP64_RAND_V0(0), FP64_RAND_V2(1) } }, \1893 { /* => */ { FP64_QNAN_V (0, FP64_FRAC_V0),FP64_RAND_V1(0), FP64_RAND_V0(0), FP64_RAND_V2(1) } }, \1894 /*mxcsr:in */ 0, 1895 /*128:out */ X86_MXCSR_IE, 1896 /*256:out */ X86_MXCSR_IE, 1897 /*xcpt? */ true, true }, 1898 /* QNan, SNan (Unmasked). */ 1899 { { /*src2 */ { FP64_QNAN(0), FP64_RAND_V1(0), FP64_RAND_V3(1), FP64_RAND_V2(0) } }, 1900 { /*src1 */ { FP64_SNAN(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(0) } }, 1901 { /* => */ { FP64_QNAN(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(0) } }, 1902 /*mxcsr:in */ 0, 1903 /*128:out */ X86_MXCSR_IE, 1904 /*256:out */ X86_MXCSR_IE, 1905 /*xcpt? */ true, true }, 1906 { { /*src2 */ { FP64_QNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_RAND_V2(1), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, \1907 { /*src1 */ { FP64_SNAN _V(0, FP64_FRAC_NORM_MIN),FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, \1908 { /* => */ { FP64_QNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, \1909 /*mxcsr:in */ 0, 1910 /*128:out */ X86_MXCSR_IE, 1911 /*256:out */ X86_MXCSR_IE, 1912 /*xcpt? */ true, true }, 1913 { { /*src2 */ { FP64_QNAN_V (0, FP64_FRAC_V0),FP64_RAND_V1(1), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, \1914 { /*src1 */ { FP64_SNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_RAND_V3(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } }, \1915 { /* => */ { FP64_QNAN_V (0, FP64_FRAC_V0),FP64_RAND_V3(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } }, \1916 /*mxcsr:in */ 0, 1917 /*128:out */ X86_MXCSR_IE, 1918 /*256:out */ X86_MXCSR_IE, 1919 /*xcpt? */ true, true }, 1920 /* SNan, QNan (Unmasked). */ 1921 { { /*src2 */ { FP64_SNAN(0), FP64_RAND_V2(1), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, 1922 { /*src1 */ { FP64_QNAN(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, 1923 { /* => */ { FP64_SNAN(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, 1924 /*mxcsr:in */ X86_MXCSR_FZ, 1925 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_IE, 1926 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_IE, 1927 /*xcpt? */ true, true }, 1928 { { /*src2 */ { FP64_SNAN _V(0, FP64_FRAC_NORM_MIN),FP64_RAND_V1(1), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, \1929 { /*src1 */ { FP64_QNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_RAND_V2(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, \1930 { /* => */ { FP64_SNAN _V(0, FP64_FRAC_NORM_MIN),FP64_RAND_V2(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, \1931 /*mxcsr:in */ 0, 1932 /*128:out */ X86_MXCSR_IE, 1933 /*256:out */ X86_MXCSR_IE, 1934 /*xcpt? */ true, true }, 1935 { { /*src2 */ { FP64_SNAN_V (0, FP64_FRAC_V1), FP64_RAND_V1(1), FP64_RAND_V0(1), FP64_RAND_V2(0) } },\1936 { /*src1 */ { FP64_QNAN_V (0, FP64_FRAC_V1), FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } },\1937 { /* => */ { FP64_SNAN_V (0, FP64_FRAC_V1), FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } },\1938 /*mxcsr:in */ 0, 1939 /*128:out */ X86_MXCSR_IE, 1940 /*256:out */ X86_MXCSR_IE, 1941 /*xcpt? */ true, true }, 1942 /* SNan, SNan (Unmasked). */ 1943 { { /*src2 */ { FP64_SNAN(0), FP64_RAND_V1(1), FP64_RAND_V0(1), FP64_RAND_V2(0) } }, 1944 { /*src1 */ { FP64_SNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, 1945 { /* => */ { FP64_SNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, 1946 /*mxcsr:in */ 0, 1947 /*128:out */ X86_MXCSR_IE, 1948 /*256:out */ X86_MXCSR_IE, 1949 /*xcpt? */ true, true }, 1950 { { /*src2 */ { FP64_SNAN _V(0, FP64_FRAC_NORM_MIN),FP64_RAND_V1(0), FP64_RAND_V0(1), FP64_RAND_V2(1) } }, \1951 { /*src1 */ { FP64_SNAN_ V(0, FP64_FRAC_NORM_MAX), FP64_RAND_V0(0), FP64_RAND_V3(0), FP64_RAND_V0(1) } }, \1952 { /* => */ { FP64_SNAN _V(0, FP64_FRAC_NORM_MIN),FP64_RAND_V0(0), FP64_RAND_V3(0), FP64_RAND_V0(1) } }, \1953 /*mxcsr:in */ 0, 1954 /*128:out */ X86_MXCSR_IE, 1955 /*256:out */ X86_MXCSR_IE, 1956 /*xcpt? */ true, true }, 1957 { { /*src2 */ { FP64_SNAN_V (0, FP64_FRAC_V1), FP64_RAND_V1(1), FP64_RAND_V1(1), FP64_RAND_V2(0) } },\1958 { /*src1 */ { FP64_SNAN_V (0, FP64_FRAC_V2), FP64_RAND_V2(1), FP64_RAND_V3(1), FP64_RAND_V1(1) } },\1959 { /* => */ { FP64_SNAN_V (0, FP64_FRAC_V1), FP64_RAND_V2(1), FP64_RAND_V3(1), FP64_RAND_V1(1) } },\1960 /*mxcsr:in */ 0, 1961 /*128:out */ X86_MXCSR_IE, 1962 /*256:out */ X86_MXCSR_IE, 1963 /*xcpt? */ true, true }, 1964 /* QNan, Normal (Unmasked). */ 1965 { { /*src2 */ { FP64_QNAN(0), FP64_RAND_V3(1), FP64_RAND_V2(1), FP64_RAND_V2(0) } }, 1966 { /*src1 */ { FP64_1(0), FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V1(1) } }, 1967 { /* => */ { FP64_QNAN(0), FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V1(1) } }, 1968 /*mxcsr:in */ 0, 1969 /*128:out */ X86_MXCSR_IE, 1970 /*256:out */ X86_MXCSR_IE, 1971 /*xcpt? */ true, true }, 1972 /* SNan, Normal ( Unmasked). */\1973 { { /*src2 */ { FP64_SNAN(1), FP64_RAND_V0(1), FP64_RAND_V2(1), FP64_RAND_V2(0) } }, 1974 { /*src1 */ { FP64_1(0), FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V3(1) } }, 1975 { /* => */ { FP64_SNAN(1), FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V3(1) } }, 1976 /*mxcsr:in */ 0, 1977 /*128:out */ X86_MXCSR_IE, 1978 /*256:out */ X86_MXCSR_IE, 1979 /*xcpt? */ true, true }, 1826 /* QNan, QNan (Masked). */ \ 1827 /*0 */{ { /*src2 */ { FP64_QNAN(0), FP64_RAND_V2(0), FP64_RAND_V0(1), FP64_RAND_V1(0) } }, \ 1828 { /*src1 */ { FP64_QNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, \ 1829 { /* => */ { FP64_QNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, \ 1830 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1831 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1832 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1833 /*xcpt? */ false, false }, \ 1834 { { /*src2 */ { FP64_QNAN_MAX(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(0) } }, \ 1835 { /*src1 */ { FP64_QNAN(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V3(1) } }, \ 1836 { /* => */ { FP64_QNAN_MAX(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V3(1) } }, \ 1837 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1838 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1839 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1840 /*xcpt? */ false, false }, \ 1841 { { /*src2 */ { FP64_QNAN_V0(0), FP64_RAND_V0(1), FP64_RAND_V0(1), FP64_RAND_V2(0) } }, \ 1842 { /*src1 */ { FP64_QNAN_MAX(0), FP64_RAND_V1(0), FP64_RAND_V0(0), FP64_RAND_V2(1) } }, \ 1843 { /* => */ { FP64_QNAN_V0(0), FP64_RAND_V1(0), FP64_RAND_V0(0), FP64_RAND_V2(1) } }, \ 1844 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1845 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1846 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1847 /*xcpt? */ false, false }, \ 1848 /* QNan, SNan (Masked). */ \ 1849 { { /*src2 */ { FP64_QNAN(0), FP64_RAND_V1(0), FP64_RAND_V3(1), FP64_RAND_V2(0) } }, \ 1850 { /*src1 */ { FP64_SNAN(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(0) } }, \ 1851 { /* => */ { FP64_QNAN(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(0) } }, \ 1852 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1853 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1854 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1855 /*xcpt? */ false, false }, \ 1856 { { /*src2 */ { FP64_QNAN_MAX(0), FP64_RAND_V2(1), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, \ 1857 { /*src1 */ { FP64_SNAN(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, \ 1858 { /* => */ { FP64_QNAN_MAX(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, \ 1859 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1860 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1861 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1862 /*xcpt? */ false, false }, \ 1863 { { /*src2 */ { FP64_QNAN_V0(0), FP64_RAND_V1(1), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, \ 1864 { /*src1 */ { FP64_SNAN_MAX(0), FP64_RAND_V3(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } }, \ 1865 { /* => */ { FP64_QNAN_V0(0), FP64_RAND_V3(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } }, \ 1866 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1867 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1868 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1869 /*xcpt? */ false, false }, \ 1870 /* SNan, QNan (Masked). */ \ 1871 { { /*src2 */ { FP64_SNAN(0), FP64_RAND_V2(1), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, \ 1872 { /*src1 */ { FP64_QNAN(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, \ 1873 { /* => */ { FP64_SNAN(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, \ 1874 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, \ 1875 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, \ 1876 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, \ 1877 /*xcpt? */ false, false }, \ 1878 { { /*src2 */ { FP64_SNAN(0), FP64_RAND_V1(1), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, \ 1879 { /*src1 */ { FP64_QNAN_MAX(0), FP64_RAND_V2(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, \ 1880 { /* => */ { FP64_SNAN(0), FP64_RAND_V2(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, \ 1881 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1882 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1883 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1884 /*xcpt? */ false, false }, \ 1885 { { /*src2 */ { FP64_SNAN_V1(0), FP64_RAND_V1(1), FP64_RAND_V0(1), FP64_RAND_V2(0) } }, \ 1886 { /*src1 */ { FP64_QNAN_V1(0), FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } }, \ 1887 { /* => */ { FP64_SNAN_V1(0), FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } }, \ 1888 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1889 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1890 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1891 /*xcpt? */ false, false }, \ 1892 /* SNan, SNan (Masked). */ \ 1893 { { /*src2 */ { FP64_SNAN(0), FP64_RAND_V1(1), FP64_RAND_V0(1), FP64_RAND_V2(0) } }, \ 1894 { /*src1 */ { FP64_SNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, \ 1895 { /* => */ { FP64_SNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, \ 1896 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1897 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1898 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1899 /*xcpt? */ false, false }, \ 1900 { { /*src2 */ { FP64_SNAN(0), FP64_RAND_V1(0), FP64_RAND_V0(1), FP64_RAND_V2(1) } }, \ 1901 { /*src1 */ { FP64_SNAN_MAX(0), FP64_RAND_V0(0), FP64_RAND_V3(0), FP64_RAND_V0(1) } }, \ 1902 { /* => */ { FP64_SNAN(0), FP64_RAND_V0(0), FP64_RAND_V3(0), FP64_RAND_V0(1) } }, \ 1903 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1904 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1905 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1906 /*xcpt? */ false, false }, \ 1907 { { /*src2 */ { FP64_SNAN_V1(0), FP64_RAND_V1(1), FP64_RAND_V1(1), FP64_RAND_V2(0) } }, \ 1908 { /*src1 */ { FP64_SNAN_V2(0), FP64_RAND_V2(1), FP64_RAND_V3(1), FP64_RAND_V1(1) } }, \ 1909 { /* => */ { FP64_SNAN_V1(0), FP64_RAND_V2(1), FP64_RAND_V3(1), FP64_RAND_V1(1) } }, \ 1910 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1911 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1912 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1913 /*xcpt? */ false, false }, \ 1914 /* QNan, Normal (Unmasked). */ \ 1915 { { /*src2 */ { FP64_QNAN(0), FP64_RAND_V3(1), FP64_RAND_V2(1), FP64_RAND_V2(0) } }, \ 1916 { /*src1 */ { FP64_1(0), FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V1(1) } }, \ 1917 { /* => */ { FP64_QNAN(0), FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V1(1) } }, \ 1918 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1919 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1920 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1921 /*xcpt? */ false, false }, \ 1922 /* SNan, Normal (Masked). */ \ 1923 { { /*src2 */ { FP64_SNAN(1), FP64_RAND_V0(1), FP64_RAND_V2(1), FP64_RAND_V2(0) } }, \ 1924 { /*src1 */ { FP64_1(0), FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V3(1) } }, \ 1925 { /* => */ { FP64_SNAN(1), FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V3(1) } }, \ 1926 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1927 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1928 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1929 /*xcpt? */ false, false }, \ 1930 /* QNan, QNan (Unmasked). */ \ 1931 /*0 */{ { /*src2 */ { FP64_QNAN(0), FP64_RAND_V2(0), FP64_RAND_V0(1), FP64_RAND_V1(0) } }, \ 1932 { /*src1 */ { FP64_QNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, \ 1933 { /* => */ { FP64_QNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, \ 1934 /*mxcsr:in */ 0, \ 1935 /*128:out */ X86_MXCSR_IE, \ 1936 /*256:out */ X86_MXCSR_IE, \ 1937 /*xcpt? */ true, true }, \ 1938 { { /*src2 */ { FP64_QNAN_MAX(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(0) } }, \ 1939 { /*src1 */ { FP64_QNAN(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V3(1) } }, \ 1940 { /* => */ { FP64_QNAN_MAX(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V3(1) } }, \ 1941 /*mxcsr:in */ 0, \ 1942 /*128:out */ X86_MXCSR_IE, \ 1943 /*256:out */ X86_MXCSR_IE, \ 1944 /*xcpt? */ true, true }, \ 1945 { { /*src2 */ { FP64_QNAN_V0(0), FP64_RAND_V0(1), FP64_RAND_V0(1), FP64_RAND_V2(0) } }, \ 1946 { /*src1 */ { FP64_QNAN_MAX(0), FP64_RAND_V1(0), FP64_RAND_V0(0), FP64_RAND_V2(1) } }, \ 1947 { /* => */ { FP64_QNAN_V0(0), FP64_RAND_V1(0), FP64_RAND_V0(0), FP64_RAND_V2(1) } }, \ 1948 /*mxcsr:in */ 0, \ 1949 /*128:out */ X86_MXCSR_IE, \ 1950 /*256:out */ X86_MXCSR_IE, \ 1951 /*xcpt? */ true, true }, \ 1952 /* QNan, SNan (Unmasked). */ \ 1953 { { /*src2 */ { FP64_QNAN(0), FP64_RAND_V1(0), FP64_RAND_V3(1), FP64_RAND_V2(0) } }, \ 1954 { /*src1 */ { FP64_SNAN(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(0) } }, \ 1955 { /* => */ { FP64_QNAN(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(0) } }, \ 1956 /*mxcsr:in */ 0, \ 1957 /*128:out */ X86_MXCSR_IE, \ 1958 /*256:out */ X86_MXCSR_IE, \ 1959 /*xcpt? */ true, true }, \ 1960 { { /*src2 */ { FP64_QNAN_MAX(0), FP64_RAND_V2(1), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, \ 1961 { /*src1 */ { FP64_SNAN(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, \ 1962 { /* => */ { FP64_QNAN_MAX(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, \ 1963 /*mxcsr:in */ 0, \ 1964 /*128:out */ X86_MXCSR_IE, \ 1965 /*256:out */ X86_MXCSR_IE, \ 1966 /*xcpt? */ true, true }, \ 1967 { { /*src2 */ { FP64_QNAN_V0(0), FP64_RAND_V1(1), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, \ 1968 { /*src1 */ { FP64_SNAN_MAX(0), FP64_RAND_V3(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } }, \ 1969 { /* => */ { FP64_QNAN_V0(0), FP64_RAND_V3(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } }, \ 1970 /*mxcsr:in */ 0, \ 1971 /*128:out */ X86_MXCSR_IE, \ 1972 /*256:out */ X86_MXCSR_IE, \ 1973 /*xcpt? */ true, true }, \ 1974 /* SNan, QNan (Unmasked). */ \ 1975 { { /*src2 */ { FP64_SNAN(0), FP64_RAND_V2(1), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, \ 1976 { /*src1 */ { FP64_QNAN(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, \ 1977 { /* => */ { FP64_SNAN(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, \ 1978 /*mxcsr:in */ X86_MXCSR_FZ, \ 1979 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_IE, \ 1980 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_IE, \ 1981 /*xcpt? */ true, true }, \ 1982 { { /*src2 */ { FP64_SNAN(0), FP64_RAND_V1(1), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, \ 1983 { /*src1 */ { FP64_QNAN_MAX(0), FP64_RAND_V2(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, \ 1984 { /* => */ { FP64_SNAN(0), FP64_RAND_V2(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, \ 1985 /*mxcsr:in */ 0, \ 1986 /*128:out */ X86_MXCSR_IE, \ 1987 /*256:out */ X86_MXCSR_IE, \ 1988 /*xcpt? */ true, true }, \ 1989 { { /*src2 */ { FP64_SNAN_V1(0), FP64_RAND_V1(1), FP64_RAND_V0(1), FP64_RAND_V2(0) } }, \ 1990 { /*src1 */ { FP64_QNAN_V1(0), FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } }, \ 1991 { /* => */ { FP64_SNAN_V1(0), FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } }, \ 1992 /*mxcsr:in */ 0, \ 1993 /*128:out */ X86_MXCSR_IE, \ 1994 /*256:out */ X86_MXCSR_IE, \ 1995 /*xcpt? */ true, true }, \ 1996 /* SNan, SNan (Unmasked). */ \ 1997 { { /*src2 */ { FP64_SNAN(0), FP64_RAND_V1(1), FP64_RAND_V0(1), FP64_RAND_V2(0) } }, \ 1998 { /*src1 */ { FP64_SNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, \ 1999 { /* => */ { FP64_SNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, \ 2000 /*mxcsr:in */ 0, \ 2001 /*128:out */ X86_MXCSR_IE, \ 2002 /*256:out */ X86_MXCSR_IE, \ 2003 /*xcpt? */ true, true }, \ 2004 { { /*src2 */ { FP64_SNAN(0), FP64_RAND_V1(0), FP64_RAND_V0(1), FP64_RAND_V2(1) } }, \ 2005 { /*src1 */ { FP64_SNAN_MAX(0), FP64_RAND_V0(0), FP64_RAND_V3(0), FP64_RAND_V0(1) } }, \ 2006 { /* => */ { FP64_SNAN(0), FP64_RAND_V0(0), FP64_RAND_V3(0), FP64_RAND_V0(1) } }, \ 2007 /*mxcsr:in */ 0, \ 2008 /*128:out */ X86_MXCSR_IE, \ 2009 /*256:out */ X86_MXCSR_IE, \ 2010 /*xcpt? */ true, true }, \ 2011 { { /*src2 */ { FP64_SNAN_V1(0), FP64_RAND_V1(1), FP64_RAND_V1(1), FP64_RAND_V2(0) } }, \ 2012 { /*src1 */ { FP64_SNAN_V2(0), FP64_RAND_V2(1), FP64_RAND_V3(1), FP64_RAND_V1(1) } }, \ 2013 { /* => */ { FP64_SNAN_V1(0), FP64_RAND_V2(1), FP64_RAND_V3(1), FP64_RAND_V1(1) } }, \ 2014 /*mxcsr:in */ 0, \ 2015 /*128:out */ X86_MXCSR_IE, \ 2016 /*256:out */ X86_MXCSR_IE, \ 2017 /*xcpt? */ true, true }, \ 2018 /* QNan, Normal (Unmasked). */ \ 2019 { { /*src2 */ { FP64_QNAN(0), FP64_RAND_V3(1), FP64_RAND_V2(1), FP64_RAND_V2(0) } }, \ 2020 { /*src1 */ { FP64_1(0), FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V1(1) } }, \ 2021 { /* => */ { FP64_QNAN(0), FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V1(1) } }, \ 2022 /*mxcsr:in */ 0, \ 2023 /*128:out */ X86_MXCSR_IE, \ 2024 /*256:out */ X86_MXCSR_IE, \ 2025 /*xcpt? */ true, true }, \ 2026 /* SNan, Normal (Masked). */ \ 2027 { { /*src2 */ { FP64_SNAN(1), FP64_RAND_V0(1), FP64_RAND_V2(1), FP64_RAND_V2(0) } }, \ 2028 { /*src1 */ { FP64_1(0), FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V3(1) } }, \ 2029 { /* => */ { FP64_SNAN(1), FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V3(1) } }, \ 2030 /*mxcsr:in */ 0, \ 2031 /*128:out */ X86_MXCSR_IE, \ 2032 /*256:out */ X86_MXCSR_IE, \ 2033 /*xcpt? */ true, true }, \ 1980 2034 1981 2035 … … 12191 12245 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 12192 12246 /*xcpt? */ false, false }, 12193 { { /*src2 */ { FP64_NORM_V2(0), FP64_SNAN _V(0, 1), FP64_RAND_V2(0), FP64_RAND_V3(0) } },12247 { { /*src2 */ { FP64_NORM_V2(0), FP64_SNAN(0), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, 12194 12248 { /*src1 */ { FP64_INF(0), FP64_RAND_V2(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, 12195 12249 { /* => */ { FP64_INF(0), FP64_RAND_V2(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, … … 12387 12441 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, 12388 12442 /*xcpt? */ false, false }, 12389 { { /*src2 */ { FP64_DENORM_MIN(1), FP64_INF(0), FP64_QNAN(1), FP64_SNAN _V(1,1) } },12443 { { /*src2 */ { FP64_DENORM_MIN(1), FP64_INF(0), FP64_QNAN(1), FP64_SNAN(1) } }, 12390 12444 { /*src1 */ { FP64_DENORM_MIN(1), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } }, 12391 12445 { /* => */ { FP64_DENORM_MIN(1), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } }, … … 13749 13803 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 13750 13804 /*xcpt? */ false, false }, 13751 { { /*src2 */ { FP64_NORM_V2(0), FP64_SNAN _V(0, 1), FP64_RAND_V2(0), FP64_RAND_V3(0) } },13805 { { /*src2 */ { FP64_NORM_V2(0), FP64_SNAN(0), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, 13752 13806 { /*src1 */ { FP64_INF(0), FP64_RAND_V2(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, 13753 13807 { /* => */ { FP64_NORM_V2(0), FP64_RAND_V2(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, … … 13945 13999 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, 13946 14000 /*xcpt? */ false, false }, 13947 { { /*src2 */ { FP64_DENORM_MIN(1), FP64_INF(0), FP64_QNAN(1), FP64_SNAN _V(1,1) } },14001 { { /*src2 */ { FP64_DENORM_MIN(1), FP64_INF(0), FP64_QNAN(1), FP64_SNAN(1) } }, 13948 14002 { /*src1 */ { FP64_DENORM_MIN(1), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } }, 13949 14003 { /* => */ { FP64_DENORM_MIN(1), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } },
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