Index: trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32
===================================================================
--- trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32	(revision 106214)
+++ trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32	(revision 106215)
@@ -196,6 +196,5 @@
 /*
  * Single-precision floating-point invalids.
- * 1 to 0x3fffff fractional part for SNANs and 0x400000 to 0x7fffff for QNAN.
- * The QNAN initialization macro ensures the range for QNAN is correct by OR'ing 0x400000.
+ * The range must be valid for both QNAN and SNANs (see compile time assertions below).
  */
 #define FP32_FRAC_INV_V0                    0x3fffff
@@ -207,4 +206,12 @@
 #define FP32_FRAC_INV_V6                    0x3ebebe
 #define FP32_FRAC_INV_V7                    0x000001
+AssertCompile(FP32_FRAC_INV_V0 <= FP32_FRAC_SNAN_MAX && FP32_FRAC_INV_V0 >= FP32_FRAC_SNAN_MIN);
+AssertCompile(FP32_FRAC_INV_V1 <= FP32_FRAC_SNAN_MAX && FP32_FRAC_INV_V1 >= FP32_FRAC_SNAN_MIN);
+AssertCompile(FP32_FRAC_INV_V2 <= FP32_FRAC_SNAN_MAX && FP32_FRAC_INV_V2 >= FP32_FRAC_SNAN_MIN);
+AssertCompile(FP32_FRAC_INV_V3 <= FP32_FRAC_SNAN_MAX && FP32_FRAC_INV_V3 >= FP32_FRAC_SNAN_MIN);
+AssertCompile(FP32_FRAC_INV_V4 <= FP32_FRAC_SNAN_MAX && FP32_FRAC_INV_V4 >= FP32_FRAC_SNAN_MIN);
+AssertCompile(FP32_FRAC_INV_V5 <= FP32_FRAC_SNAN_MAX && FP32_FRAC_INV_V5 >= FP32_FRAC_SNAN_MIN);
+AssertCompile(FP32_FRAC_INV_V6 <= FP32_FRAC_SNAN_MAX && FP32_FRAC_INV_V6 >= FP32_FRAC_SNAN_MIN);
+AssertCompile(FP32_FRAC_INV_V7 <= FP32_FRAC_SNAN_MAX && FP32_FRAC_INV_V7 >= FP32_FRAC_SNAN_MIN);
 /* Single-precision floating-point signalling NANs (SNAN). */
 #define FP32_SNAN_V0(a_Sign)                RTFLOAT32U_INIT_SNAN_EX(a_Sign, FP32_FRAC_INV_V0)
@@ -265,4 +272,12 @@
 /** The min fraction value for a double-precision floating-point denormal. */
 #define FP64_FRAC_DENORM_MIN                1
+/** The max fraction value for a single-precision floating-point signalling NAN. */
+#define FP64_FRAC_SNAN_MAX                  0x7ffffffffffff
+/** The min fraction value for a single-precision floating-point signalling NAN. */
+#define FP64_FRAC_SNAN_MIN                  1
+/** The max fraction value for a single-precision floating-point quiet NAN. */
+#define FP64_FRAC_QNAN_MAX                  0xfffffffffffff
+/** The min fraction value for a single-precision floating-point quiet NAN. */
+#define FP64_FRAC_QNAN_MIN                  0x8000000000000
 
 #define FP64_NORM_MAX(a_Sign)               RTFLOAT64U_INIT_C(a_Sign, FP64_FRAC_NORM_MAX, FP64_EXP_NORM_MAX)
@@ -275,6 +290,8 @@
 #define FP64_QNAN(a_Sign)                   RTFLOAT64U_INIT_QNAN(a_Sign)
 #define FP64_QNAN_V(a_Sign, a_Val)          RTFLOAT64U_INIT_QNAN_EX(a_Sign, a_Val)
+#define FP64_QNAN_MAX(a_Sign)               RTFLOAT64U_INIT_QNAN_EX(a_Sign, FP64_FRAC_QNAN_MAX)
 #define FP64_SNAN(a_Sign)                   RTFLOAT64U_INIT_SNAN(a_Sign)
 #define FP64_SNAN_V(a_Sign, a_Val)          RTFLOAT64U_INIT_SNAN_EX(a_Sign, a_Val)
+#define FP64_SNAN_MAX(a_Sign)               RTFLOAT64U_INIT_SNAN_EX(a_Sign, FP64_FRAC_SNAN_MAX)
 /** @todo Move this to iprt/types.h after renaming it to RTFLOAT64U_MAKE? */
 #ifdef RT_BIG_ENDIAN
@@ -339,4 +356,27 @@
 /** The maximum denormal value. */
 #define FP64_DENORM_MIN(a_Sign)             RTFLOAT64U_INIT_C(a_Sign, FP64_FRAC_DENORM_MIN, 0)
+
+/*
+ * Double-precision floating-point invalids.
+ * The range must be valid for both QNAN and SNANs (see compile time assertions below).
+ */
+#define FP64_FRAC_INV_V0                    0x7ffffffffffff
+#define FP64_FRAC_INV_V1                    0x3ca5cadecab1e
+#define FP64_FRAC_INV_V2                    0x10adedb0771e5
+#define FP64_FRAC_INV_V3                    0x0000000000001
+AssertCompile(FP64_FRAC_INV_V0 < FP64_FRAC_QNAN_MIN && FP64_FRAC_INV_V0 >= FP64_FRAC_SNAN_MIN);
+AssertCompile(FP64_FRAC_INV_V1 < FP64_FRAC_QNAN_MIN && FP64_FRAC_INV_V1 >= FP64_FRAC_SNAN_MIN);
+AssertCompile(FP64_FRAC_INV_V2 < FP64_FRAC_QNAN_MIN && FP64_FRAC_INV_V2 >= FP64_FRAC_SNAN_MIN);
+AssertCompile(FP64_FRAC_INV_V3 < FP64_FRAC_QNAN_MIN && FP64_FRAC_INV_V3 >= FP64_FRAC_SNAN_MIN);
+/* Double-precision floating-point signalling NANs (SNAN). */
+#define FP64_SNAN_V0(a_Sign)                RTFLOAT64U_INIT_SNAN_EX(a_Sign, FP64_FRAC_INV_V0)
+#define FP64_SNAN_V1(a_Sign)                RTFLOAT64U_INIT_SNAN_EX(a_Sign, FP64_FRAC_INV_V1)
+#define FP64_SNAN_V2(a_Sign)                RTFLOAT64U_INIT_SNAN_EX(a_Sign, FP64_FRAC_INV_V2)
+#define FP64_SNAN_V3(a_Sign)                RTFLOAT64U_INIT_SNAN_EX(a_Sign, FP64_FRAC_INV_V3)
+/* Double-precision floating-point quiet NANs (QNAN). */
+#define FP64_QNAN_V0(a_Sign)                RTFLOAT64U_INIT_QNAN_EX(a_Sign, FP64_FRAC_INV_V0)
+#define FP64_QNAN_V1(a_Sign)                RTFLOAT64U_INIT_QNAN_EX(a_Sign, FP64_FRAC_INV_V1)
+#define FP64_QNAN_V2(a_Sign)                RTFLOAT64U_INIT_QNAN_EX(a_Sign, FP64_FRAC_INV_V2)
+#define FP64_QNAN_V3(a_Sign)                RTFLOAT64U_INIT_QNAN_EX(a_Sign, FP64_FRAC_INV_V3)
 
 /*
@@ -718,88 +758,88 @@
  **/
 #define FP64_TABLE_D1_PD_INVALIDS \
-    /* 0*/{ { /*src2     */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0),       FP64_QNAN_V(0, FP64_FRAC_V1) } },      \
-            { /*src1     */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } },      \
-            { /* =>      */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } },      \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                           \
-              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                                                                           \
-              /*256:out  */ X86_MXCSR_XCPT_MASK,                                                                                                           \
-              /*xcpt?    */ false, false },                                                                                                                \
-          { { /*src2     */ { FP64_QNAN(0),      FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0),       FP64_QNAN_V(0, FP64_FRAC_V2) } }, \
-            { /*src1     */ { FP64_SNAN(0),      FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1) } }, \
-            { /* =>      */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1),                  FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } }, \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                           \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                            \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                            \
-              /*xcpt?    */ false, false },                                                                                                                \
-          { { /*src2     */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V1) } },            \
-            { /*src1     */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } },            \
-            { /* =>      */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } },            \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                           \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                            \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                            \
-              /*xcpt?    */ false, false },                                                                                                                \
-          { { /*src2     */ { FP64_SNAN(0),      FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } },       \
-            { /*src1     */ { FP64_SNAN(0),      FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V0) } },       \
-            { /* =>      */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V0) } },       \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                           \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                            \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                            \
-              /*xcpt?    */ false, false },                                                                                                                \
-          { { /*src2     */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1),              FP64_QNAN_V(0, FP64_FRAC_V1) } },            \
-            { /*src1     */ { FP64_1(0),    FP64_1(1),                          FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1)              } },            \
-            { /* =>      */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } },            \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                           \
-              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                                                                           \
-              /*256:out  */ X86_MXCSR_XCPT_MASK,                                                                                                           \
-              /*xcpt?    */ false, false },                                                                                                                \
-          { { /*src2     */ { FP64_SNAN(1),      FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1),              FP64_SNAN_V(0, FP64_FRAC_V1) } },       \
-            { /*src1     */ { FP64_1(0),         FP64_1(0),                          FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1)              } },       \
-            { /* =>      */ { FP64_QNAN_V(1, 1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V1) } },       \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                           \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                            \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                            \
-              /*xcpt?    */ false, false },                                                                                                                \
-          { { /*src2     */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0),       FP64_QNAN_V(0, FP64_FRAC_V2) } },      \
-            { /*src1     */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3) } },      \
-            { /* =>      */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3) } },      \
-              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,                                                                                              \
-              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,                                                                                              \
-              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,                                                                                              \
-              /*xcpt?    */ false, false },                                                                                                                \
-          { { /*src2     */ { FP64_QNAN(0),      FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0),       FP64_QNAN_V(0, FP32_FRAC_V1) } }, \
-            { /*src1     */ { FP64_SNAN(0),      FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP32_FRAC_V2) } }, \
-            { /* =>      */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1),                  FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP32_FRAC_V2) } }, \
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,                                                                              \
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,                                                               \
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,                                                               \
-              /*xcpt?    */ true, true },                                                                                                                  \
-          { { /*src2     */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } },            \
-            { /*src1     */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },            \
-            { /* =>      */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },            \
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,                                                                              \
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,                                                               \
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,                                                               \
-              /*xcpt?    */ true, true },                                                                                                                  \
-          { { /*src2     */ { FP64_SNAN(0),      FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } },       \
-            { /*src1     */ { FP64_SNAN(0),      FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } },       \
-            { /* =>      */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V3) } },       \
-              /*mxcsr:in */ X86_MXCSR_RC_UP,                                                                                                               \
-              /*128:out  */ X86_MXCSR_RC_UP | X86_MXCSR_IE,                                                                                                \
-              /*256:out  */ X86_MXCSR_RC_UP | X86_MXCSR_IE,                                                                                                \
-              /*xcpt?    */ true, true },                                                                                                                  \
-          { { /*src2     */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1),              FP64_QNAN_V(0, FP64_FRAC_V1) } },            \
-            { /*src1     */ { FP64_1(0),    FP64_1(1),                          FP64_QNAN_V(1, FP64_FRAC_V3), FP64_NORM_V2(1)              } },            \
-            { /* =>      */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V1) } },            \
-              /*mxcsr:in */ X86_MXCSR_RC_DOWN,                                                                                                             \
-              /*128:out  */ X86_MXCSR_RC_DOWN,                                                                                                             \
-              /*256:out  */ X86_MXCSR_RC_DOWN,                                                                                                             \
-              /*xcpt?    */ false, false },                                                                                                                \
-    /*11*/{ { /*src2     */ { FP64_SNAN(1),      FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1),              FP64_SNAN_V(0, FP64_FRAC_V2) } },       \
-            { /*src1     */ { FP64_1(0),         FP64_1(0),                          FP64_SNAN_V(1, FP64_FRAC_V3), FP64_NORM_V2(1)              } },       \
-            { /* =>      */ { FP64_QNAN_V(1, 1), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },       \
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,                                                                                             \
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,                                                                              \
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,                                                                              \
-              /*xcpt?    */ true, true },                                                                                                                  \
+    /*0 */{ { /*src2     */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V0(0),  FP64_QNAN_V1(0) } },       \
+            { /*src1     */ { FP64_QNAN(0), FP64_QNAN(0),     FP64_QNAN_MAX(0), FP64_QNAN_V2(0) } },       \
+            { /* =>      */ { FP64_QNAN(0), FP64_QNAN(0),     FP64_QNAN_MAX(0), FP64_QNAN_V2(0) } },       \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                           \
+              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                           \
+              /*256:out  */ X86_MXCSR_XCPT_MASK,                                                           \
+              /*xcpt?    */ false, false },                                                                \
+          { { /*src2     */ { FP64_QNAN(0),      FP64_QNAN_MAX(0),  FP64_QNAN_V0(0),  FP64_QNAN_V2(0) } }, \
+            { /*src1     */ { FP64_SNAN(0),      FP64_SNAN(0),      FP64_SNAN_MAX(0), FP64_SNAN_V1(0) } }, \
+            { /* =>      */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_MAX(0), FP64_QNAN_V1(0) } }, \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                           \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                            \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                            \
+              /*xcpt?    */ false, false },                                                                \
+          { { /*src2     */ { FP64_SNAN(0), FP64_SNAN(0),     FP64_SNAN_V0(0), FP64_SNAN_V1(0) } },        \
+            { /*src1     */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V2(0), FP64_QNAN_V3(0) } },        \
+            { /* =>      */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V2(0), FP64_QNAN_V3(0) } },        \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                           \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                            \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                            \
+              /*xcpt?    */ false, false },                                                                \
+          { { /*src2     */ { FP64_SNAN(0),      FP64_SNAN(0),     FP64_SNAN_V1(0), FP64_SNAN_V2(0) } },   \
+            { /*src1     */ { FP64_SNAN(0),      FP64_SNAN_MAX(0), FP64_SNAN_V3(0), FP64_SNAN_V0(0) } },   \
+            { /* =>      */ { FP64_QNAN_V(0, 1), FP64_QNAN_MAX(0), FP64_QNAN_V3(0), FP64_QNAN_V0(0) } },   \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                           \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                            \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                            \
+              /*xcpt?    */ false, false },                                                                \
+          { { /*src2     */ { FP64_QNAN(0), FP64_QNAN_MAX(1), FP64_NORM_V0(1), FP64_QNAN_V1(0) } },        \
+            { /*src1     */ { FP64_1(0),    FP64_1(1),        FP64_QNAN_V0(1), FP64_NORM_V2(1) } },        \
+            { /* =>      */ { FP64_QNAN(0), FP64_QNAN_MAX(1), FP64_QNAN_V0(1), FP64_QNAN_V1(0) } },        \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                           \
+              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                           \
+              /*256:out  */ X86_MXCSR_XCPT_MASK,                                                           \
+              /*xcpt?    */ false, false },                                                                \
+          { { /*src2     */ { FP64_SNAN(1),      FP64_SNAN_MAX(1), FP64_NORM_V0(1), FP64_SNAN_V1(0) } },   \
+            { /*src1     */ { FP64_1(0),         FP64_1(0),        FP64_SNAN_V0(1), FP64_NORM_V2(1) } },   \
+            { /* =>      */ { FP64_QNAN_V(1, 1), FP64_QNAN_MAX(1), FP64_QNAN_V0(1), FP64_QNAN_V1(0) } },   \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                           \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                            \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                            \
+              /*xcpt?    */ false, false },                                                                \
+          { { /*src2     */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V0(0),  FP64_QNAN_V2(0) } },       \
+            { /*src1     */ { FP64_QNAN(0), FP64_QNAN(0),     FP64_QNAN_MAX(0), FP64_QNAN_V3(0) } },       \
+            { /* =>      */ { FP64_QNAN(0), FP64_QNAN(0),     FP64_QNAN_MAX(0), FP64_QNAN_V3(0) } },       \
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,                                              \
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,                                              \
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,                                              \
+              /*xcpt?    */ false, false },                                                                \
+          { { /*src2     */ { FP64_QNAN(0),      FP64_QNAN_MAX(0),  FP64_QNAN_V0(0),  FP64_QNAN_V1(0) } }, \
+            { /*src1     */ { FP64_SNAN(0),      FP64_SNAN(0),      FP64_SNAN_MAX(0), FP64_SNAN_V2(0) } }, \
+            { /* =>      */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_MAX(0), FP64_QNAN_V2(0) } }, \
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,                              \
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,               \
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,               \
+              /*xcpt?    */ true, true },                                                                  \
+          { { /*src2     */ { FP64_SNAN(0), FP64_SNAN(0),     FP64_SNAN_V1(0), FP64_SNAN_V1(0) } },        \
+            { /*src1     */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V3(0), FP64_QNAN_V2(0) } },        \
+            { /* =>      */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V3(0), FP64_QNAN_V2(0) } },        \
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,                              \
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,               \
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,               \
+              /*xcpt?    */ true, true },                                                                  \
+          { { /*src2     */ { FP64_SNAN(0),      FP64_SNAN(0),     FP64_SNAN_V1(0), FP64_SNAN_V2(0) } },   \
+            { /*src1     */ { FP64_SNAN(0),      FP64_SNAN_MAX(0), FP64_SNAN_V0(0), FP64_SNAN_V3(0) } },   \
+            { /* =>      */ { FP64_QNAN_V(0, 1), FP64_QNAN_MAX(0), FP64_QNAN_V0(0), FP64_QNAN_V3(0) } },   \
+              /*mxcsr:in */ X86_MXCSR_RC_UP,                                                               \
+              /*128:out  */ X86_MXCSR_RC_UP | X86_MXCSR_IE,                                                \
+              /*256:out  */ X86_MXCSR_RC_UP | X86_MXCSR_IE,                                                \
+              /*xcpt?    */ true, true },                                                                  \
+          { { /*src2     */ { FP64_QNAN(0), FP64_QNAN_MAX(1), FP64_NORM_V0(1), FP64_QNAN_V1(0) } },        \
+            { /*src1     */ { FP64_1(0),    FP64_1(1),        FP64_QNAN_V3(1), FP64_NORM_V2(1) } },        \
+            { /* =>      */ { FP64_QNAN(0), FP64_QNAN_MAX(1), FP64_QNAN_V3(1), FP64_QNAN_V1(0) } },        \
+              /*mxcsr:in */ X86_MXCSR_RC_DOWN,                                                             \
+              /*128:out  */ X86_MXCSR_RC_DOWN,                                                             \
+              /*256:out  */ X86_MXCSR_RC_DOWN,                                                             \
+              /*xcpt?    */ false, false },                                                                \
+    /*11*/{ { /*src2     */ { FP64_SNAN(1),      FP64_SNAN_MAX(1), FP64_NORM_V0(1), FP64_SNAN_V2(0) } },   \
+            { /*src1     */ { FP64_1(0),         FP64_1(0),        FP64_SNAN_V3(1), FP64_NORM_V2(1) } },   \
+            { /* =>      */ { FP64_QNAN_V(1, 1), FP64_QNAN_MAX(1), FP64_QNAN_V3(1), FP64_QNAN_V2(0) } },   \
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,                                             \
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,                              \
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,                              \
+              /*xcpt?    */ true, true },                                                                  \
 
 /**
@@ -1023,213 +1063,213 @@
  **/
 #define FP64_TABLE_D1_SD_INVALIDS \
-    /* QNan, QNan (Masked). */                                                                                                                                              \
-    /* 0*/{ { /*src2     */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0),       FP64_QNAN_V(0, FP64_FRAC_V1) } },                       \
-            { /*src1     */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } },                       \
-            { /* =>      */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } },                       \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                            \
-              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                            \
-              /*256:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                            \
-              /*xcpt?    */ false, false },                                                                                                                                 \
-          { { /*src2     */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_INF(0)  } },                             \
-            { /*src1     */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_SNAN(1) } },                             \
-            { /* =>      */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_SNAN(1) } },                             \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                            \
-              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                            \
-              /*256:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                            \
-              /*xcpt?    */ false, false },                                                                                                                                 \
-          { { /*src2     */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_INF(1)  } },                                   \
-            { /*src1     */ { FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN(0) } },                                   \
-            { /* =>      */ { FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN(0) } },                                   \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                            \
-              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                            \
-              /*256:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                            \
-              /*xcpt?    */ false, false },                                                                                                                                 \
-    /* QNan, SNan (Masked). */                                                                                                                                              \
-          { { /*src2     */ { FP64_QNAN(0),      FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } },                              \
-            { /*src1     */ { FP64_SNAN(0),      FP64_SNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP64_FRAC_V2) } },                              \
-            { /* =>      */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP64_FRAC_V2) } },                              \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                            \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                             \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                             \
-              /*xcpt?    */ false, false },                                                                                                                                 \
-          { { /*src2     */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0),       FP64_QNAN_V(0, FP64_FRAC_V1) } }, \
-            { /*src1     */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(1, FP64_FRAC_NORM_MIN), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2) } }, \
-            { /* =>      */ { FP64_QNAN_V(0, 1),                  FP64_SNAN_V(1, FP64_FRAC_NORM_MIN), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2) } }, \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                            \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                             \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                             \
-              /*xcpt?    */ false, false },                                                                                                                                 \
-          { { /*src2     */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0),       FP64_INF(0)  } },                       \
-            { /*src1     */ { FP64_SNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN(1) } },                       \
-            { /* =>      */ { FP64_SNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN(1) } },                       \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                            \
-              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                            \
-              /*256:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                            \
-              /*xcpt?    */ false, false },                                                                                                                                 \
-    /* SNan, QNan (Masked). */                                                                                                                                              \
-          { { /*src2     */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP64_FRAC_V1) } },                             \
-            { /*src1     */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(1, FP64_FRAC_V2) } },                             \
-            { /* =>      */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(1, FP64_FRAC_V2) } },                             \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                            \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                             \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                             \
-              /*xcpt?    */ false, false },                                                                                                                                 \
-          { { /*src2     */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } },       \
-            { /*src1     */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },       \
-            { /* =>      */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },       \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                            \
-              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                            \
-              /*256:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                            \
-              /*xcpt?    */ false, false },                                                                                                                                 \
-          { { /*src2     */ { FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } },             \
-            { /*src1     */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3) } },             \
-            { /* =>      */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(1, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3) } },             \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                            \
-              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                            \
-              /*256:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                            \
-              /*xcpt?    */ false, false },                                                                                                                                 \
-    /* SNan, SNan (Masked). */                                                                                                                                              \
-          { { /*src2     */ { FP64_SNAN(0),      FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } },                        \
-            { /*src1     */ { FP64_SNAN(0),      FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } },                        \
-            { /* =>      */ { FP64_QNAN_V(0, 1), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } },                        \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                            \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                             \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                             \
-              /*xcpt?    */ false, false },                                                                                                                                 \
-          { { /*src2     */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } },             \
-            { /*src1     */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3) } },             \
-            { /* =>      */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3) } },             \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                            \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                             \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                             \
-              /*xcpt?    */ false, false },                                                                                                                                 \
-          { { /*src2     */ { FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } },                   \
-            { /*src1     */ { FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } },                   \
-            { /* =>      */ { FP64_QNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V3) } },                   \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                            \
-              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                            \
-              /*256:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                            \
-              /*xcpt?    */ false, false },                                                                                                                                 \
-    /* QNan, Norm FP (Masked). */                                                                                                                                           \
-          { { /*src2     */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1),              FP64_QNAN_V(0, FP64_FRAC_V1) } },                             \
-            { /*src1     */ { FP64_1(0),    FP64_1(1),                          FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1)              } },                             \
-            { /* =>      */ { FP64_QNAN(0), FP64_1(1),                          FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1)              } },                             \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                            \
-              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                            \
-              /*256:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                            \
-              /*xcpt?    */ false, false },                                                                                                                                 \
-    /* SNan, Norm FP (Masked). */                                                                                                                                           \
-          { { /*src2     */ { FP64_SNAN(1),      FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1),              FP64_SNAN_V(0, FP64_FRAC_V1) } },                        \
-            { /*src1     */ { FP64_1(0),         FP64_1(0),                          FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1)              } },                        \
-            { /* =>      */ { FP64_QNAN_V(1, 1), FP64_1(0),                          FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1)              } },                        \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                            \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                             \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                             \
-              /*xcpt?    */ false, false },                                                                                                                                 \
-    /* QNan, QNan (Unmasked). */                                                                                                                                            \
-    /*14*/{ { /*src2     */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0),       FP64_QNAN_V(0, FP64_FRAC_V1) } },                       \
-            { /*src1     */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } },                       \
-            { /* =>      */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } },                       \
-              /*mxcsr:in */ 0,                                                                                                                                              \
-              /*128:out  */ 0,                                                                                                                                              \
-              /*256:out  */ 0,                                                                                                                                              \
-              /*xcpt?    */ false, false },                                                                                                                                 \
-          { { /*src2     */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } },             \
-            { /*src1     */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2) } },             \
-            { /* =>      */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(0, FP64_FRAC_V2) } },             \
-              /*mxcsr:in */ 0,                                                                                                                                              \
-              /*128:out  */ 0,                                                                                                                                              \
-              /*256:out  */ 0,                                                                                                                                              \
-              /*xcpt?    */ false, false },                                                                                                                                 \
-          { { /*src2     */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } },                   \
-            { /*src1     */ { FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(1, FP64_FRAC_V0) } },                   \
-            { /* =>      */ { FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V0), FP64_QNAN_V(1, FP64_FRAC_V0) } },                   \
-              /*mxcsr:in */ 0,                                                                                                                                              \
-              /*128:out  */ 0,                                                                                                                                              \
-              /*256:out  */ 0,                                                                                                                                              \
-              /*xcpt?    */ false, false },                                                                                                                                 \
-                                                                                                                                                                            \
-    /* QNan, SNan (Unmasked). */                                                                                                                                            \
-          { { /*src2     */ { FP64_QNAN(0),      FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } },                              \
-            { /*src1     */ { FP64_SNAN(0),      FP64_SNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V2) } },                              \
-            { /* =>      */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V2) } },                              \
-              /*mxcsr:in */ 0,                                                                                                                                              \
-              /*128:out  */ X86_MXCSR_IE,                                                                                                                                   \
-              /*256:out  */ X86_MXCSR_IE,                                                                                                                                   \
-              /*xcpt?    */ true, true },                                                                                                                                   \
-          { { /*src2     */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0),       FP64_QNAN_V(0, FP64_FRAC_V1) } }, \
-            { /*src1     */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2) } }, \
-            { /* =>      */ { FP64_QNAN_V(0, 1),                  FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2) } }, \
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,                                                                                               \
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,                                                                                \
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,                                                                                \
-              /*xcpt?    */ true, true },                                                                                                                                   \
-          { { /*src2     */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0),       FP64_QNAN_V(0, FP64_FRAC_V1) } },       \
-            { /*src1     */ { FP64_SNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } },       \
-            { /* =>      */ { FP64_SNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } },       \
-              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,                                                                                                               \
-              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,                                                                                                               \
-              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,                                                                                                               \
-              /*xcpt?    */ false, false },                                                                                                                                 \
-    /* SNan, QNan (Unmasked). */                                                                                                                                            \
-          { { /*src2     */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } },                             \
-            { /*src1     */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },                             \
-            { /* =>      */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_V2) } },                             \
-              /*mxcsr:in */ X86_MXCSR_DAZ,                                                                                                                                  \
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_IE,                                                                                                                   \
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_IE,                                                                                                                   \
-              /*xcpt?    */ true, true },                                                                                                                                   \
-          { { /*src2     */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP64_FRAC_V1) } },       \
-            { /*src1     */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V0) } },       \
-            { /* =>      */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V0) } },       \
-              /*mxcsr:in */ X86_MXCSR_RC_UP,                                                                                                                                \
-              /*128:out  */ X86_MXCSR_RC_UP,                                                                                                                                \
-              /*256:out  */ X86_MXCSR_RC_UP,                                                                                                                                \
-              /*xcpt?    */ false, false },                                                                                                                                 \
-          { { /*src2     */ { FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP64_FRAC_V1) } },             \
-            { /*src1     */ { FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3) } },             \
-            { /* =>      */ { FP64_QNAN_V(0, FP64_FRAC_V3), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(1, FP64_FRAC_V2), FP64_QNAN_V(1, FP64_FRAC_V3) } },             \
-              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,                                                                                                               \
-              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,                                                                                                               \
-              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,                                                                                                               \
-              /*xcpt?    */ false, false },                                                                                                                                 \
-    /* SNan, SNan (Unmasked). */                                                                                                                                            \
-    /*23*/{ { /*src2     */ { FP64_SNAN(0),      FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } },                        \
-            { /*src1     */ { FP64_SNAN(0),      FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V0) } },                        \
-            { /* =>      */ { FP64_QNAN_V(0, 1), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V0) } },                        \
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ,                                                                                                                   \
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE,                                                                                                    \
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE,                                                                                                    \
-              /*xcpt?    */ true, true },                                                                                                                                   \
-          { { /*src2     */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(1, FP32_FRAC_V2) } },             \
-            { /*src1     */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(1, FP32_FRAC_V3) } },             \
-            { /* =>      */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V0), FP64_SNAN_V(1, FP64_FRAC_V2), FP64_SNAN_V(1, FP32_FRAC_V3) } },             \
-              /*mxcsr:in */ X86_MXCSR_RC_ZERO,                                                                                                                              \
-              /*128:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE,                                                                                                               \
-              /*256:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE,                                                                                                               \
-              /*xcpt?    */ true, true },                                                                                                                                   \
-          { { /*src2     */ { FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V0), FP64_SNAN_V(0, FP64_FRAC_V2) } },                   \
-            { /*src1     */ { FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V3) } },                   \
-            { /* =>      */ { FP64_QNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(1, FP64_FRAC_V3), FP64_SNAN_V(0, FP64_FRAC_V3) } },                   \
-              /*mxcsr:in */ 0,                                                                                                                                              \
-              /*128:out  */ 0,                                                                                                                                              \
-              /*256:out  */ 0,                                                                                                                                              \
-              /*xcpt?    */ false, false },                                                                                                                                 \
-    /* QNan, Norm FP (Unmasked). */                                                                                                                                         \
-          { { /*src2     */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1),              FP64_QNAN_V(0, FP64_FRAC_V1) } },                             \
-            { /*src1     */ { FP64_1(0),    FP64_INF(1),                        FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1)              } },                             \
-            { /* =>      */ { FP64_QNAN(0), FP64_INF(1),                        FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1)              } },                             \
-              /*mxcsr:in */ X86_MXCSR_FZ,                                                                                                                                   \
-              /*128:out  */ X86_MXCSR_FZ,                                                                                                                                   \
-              /*256:out  */ X86_MXCSR_FZ,                                                                                                                                   \
-              /*xcpt?    */ false, false },                                                                                                                                 \
-    /* SNan, Norm FP (Unmasked). */                                                                                                                                         \
-    /*27*/{ { /*src2     */ { FP64_SNAN(1),      FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1),              FP64_SNAN_V(0, FP64_FRAC_V1) } },                        \
-            { /*src1     */ { FP64_1(0),         FP64_INF(0),                        FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1)              } },                        \
-            { /* =>      */ { FP64_QNAN_V(1, 1), FP64_INF(0),                        FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1)              } },                        \
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,                                                                                               \
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,                                                                                \
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,                                                                                \
-              /*xcpt?    */ true, true },                                                                                                                                   \
+    /* QNan, QNan (Masked). */                                                                            \
+    /*0 */{ { /*src2     */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V0(0),  FP64_QNAN_V1(0) } },      \
+            { /*src1     */ { FP64_QNAN(0), FP64_QNAN(1),     FP64_QNAN_MAX(1), FP64_QNAN_V2(0) } },      \
+            { /* =>      */ { FP64_QNAN(0), FP64_QNAN(1),     FP64_QNAN_MAX(1), FP64_QNAN_V2(0) } },      \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                          \
+              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                          \
+              /*256:out  */ X86_MXCSR_XCPT_MASK,                                                          \
+              /*xcpt?    */ false, false },                                                               \
+          { { /*src2     */ { FP64_QNAN_MAX(0), FP64_QNAN_V1(1), FP64_QNAN_V2(0), FP64_INF(0)  } },       \
+            { /*src1     */ { FP64_QNAN(0),     FP64_QNAN_V2(1), FP64_QNAN_V3(1), FP64_SNAN(1) } },       \
+            { /* =>      */ { FP64_QNAN(0),     FP64_QNAN_V2(1), FP64_QNAN_V3(1), FP64_SNAN(1) } },       \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                          \
+              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                          \
+              /*256:out  */ X86_MXCSR_XCPT_MASK,                                                          \
+              /*xcpt?    */ false, false },                                                               \
+          { { /*src2     */ { FP64_QNAN_V1(0), FP64_QNAN_V1(0), FP64_QNAN_V2(0), FP64_INF(1)  } },        \
+            { /*src1     */ { FP64_QNAN_V0(0), FP64_QNAN_V2(0), FP64_QNAN_V3(1), FP64_QNAN(0) } },        \
+            { /* =>      */ { FP64_QNAN_V0(0), FP64_QNAN_V2(0), FP64_QNAN_V3(1), FP64_QNAN(0) } },        \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                          \
+              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                          \
+              /*256:out  */ X86_MXCSR_XCPT_MASK,                                                          \
+              /*xcpt?    */ false, false },                                                               \
+    /* QNan, SNan (Masked). */                                                                            \
+          { { /*src2     */ { FP64_QNAN(0),      FP64_QNAN_V1(0), FP64_QNAN_V2(0), FP64_QNAN_V3(0) } },   \
+            { /*src1     */ { FP64_SNAN(0),      FP64_SNAN_V2(1), FP64_SNAN_V1(0), FP64_SNAN_V2(1) } },   \
+            { /* =>      */ { FP64_QNAN_V(0, 1), FP64_SNAN_V2(1), FP64_SNAN_V1(0), FP64_SNAN_V2(1) } },   \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                          \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                           \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                           \
+              /*xcpt?    */ false, false },                                                               \
+          { { /*src2     */ { FP64_QNAN_MAX(0),  FP64_QNAN_MAX(0), FP64_QNAN_V0(0),  FP64_QNAN_V1(0) } }, \
+            { /*src1     */ { FP64_SNAN(0),      FP64_SNAN(1),     FP64_SNAN_MAX(1), FP64_SNAN_V2(0) } }, \
+            { /* =>      */ { FP64_QNAN_V(0, 1), FP64_SNAN(1),     FP64_SNAN_MAX(1), FP64_SNAN_V2(0) } }, \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                          \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                           \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                           \
+              /*xcpt?    */ false, false },                                                               \
+          { { /*src2     */ { FP64_QNAN_V1(0), FP64_QNAN_MAX(0), FP64_QNAN_V0(0),  FP64_INF(0)  } },      \
+            { /*src1     */ { FP64_SNAN_V2(0), FP64_QNAN(0),     FP64_QNAN_MAX(1), FP64_QNAN(1) } },      \
+            { /* =>      */ { FP64_QNAN_V2(0), FP64_QNAN(0),     FP64_QNAN_MAX(1), FP64_QNAN(1) } },      \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                          \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                           \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                           \
+              /*xcpt?    */ false, false },                                                               \
+    /* SNan, QNan (Masked). */                                                                            \
+          { { /*src2     */ { FP64_SNAN(0), FP64_SNAN(0),     FP64_SNAN_V1(0), FP64_SNAN_V1(1) } },       \
+            { /*src1     */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V3(1), FP64_QNAN_V2(1) } },       \
+            { /* =>      */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V3(1), FP64_QNAN_V2(1) } },       \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                          \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                           \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                           \
+              /*xcpt?    */ false, false },                                                               \
+          { { /*src2     */ { FP64_SNAN_MAX(0), FP64_SNAN_MAX(1), FP64_SNAN_V1(0), FP64_SNAN_V1(0) } },   \
+            { /*src1     */ { FP64_QNAN(0),     FP64_QNAN(1),     FP64_QNAN_V3(1), FP64_QNAN_V2(0) } },   \
+            { /* =>      */ { FP64_QNAN(0),     FP64_QNAN(1),     FP64_QNAN_V3(1), FP64_QNAN_V2(0) } },   \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                          \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                           \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                           \
+              /*xcpt?    */ false, false },                                                               \
+          { { /*src2     */ { FP64_SNAN_V0(0), FP64_SNAN_MAX(0), FP64_SNAN_V1(0), FP64_SNAN_V1(0) } },    \
+            { /*src1     */ { FP64_QNAN_V1(0), FP64_QNAN(1),     FP64_QNAN_V2(1), FP64_QNAN_V3(1) } },    \
+            { /* =>      */ { FP64_QNAN_V1(0), FP64_QNAN(1),     FP64_QNAN_V2(1), FP64_QNAN_V3(1) } },    \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                          \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                           \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                           \
+              /*xcpt?    */ false, false },                                                               \
+    /* SNan, SNan (Masked). */                                                                            \
+          { { /*src2     */ { FP64_SNAN(0),      FP64_SNAN(0),     FP64_SNAN_V1(0), FP64_SNAN_V2(0) } },  \
+            { /*src1     */ { FP64_SNAN(0),      FP64_SNAN_MAX(0), FP64_SNAN_V0(0), FP64_SNAN_V3(0) } },  \
+            { /* =>      */ { FP64_QNAN_V(0, 1), FP64_SNAN_MAX(0), FP64_SNAN_V0(0), FP64_SNAN_V3(0) } },  \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                          \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                           \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                           \
+              /*xcpt?    */ false, false },                                                               \
+          { { /*src2     */ { FP64_SNAN(0),     FP64_SNAN_V2(0), FP64_SNAN_V1(0), FP64_SNAN_V2(0) } },    \
+            { /*src1     */ { FP64_SNAN_MAX(0), FP64_SNAN_V0(0), FP64_SNAN_V2(0), FP64_SNAN_V3(1) } },    \
+            { /* =>      */ { FP64_QNAN_MAX(0), FP64_SNAN_V0(0), FP64_SNAN_V2(0), FP64_SNAN_V3(1) } },    \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                          \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                           \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                           \
+              /*xcpt?    */ false, false },                                                               \
+          { { /*src2     */ { FP64_SNAN_V1(0), FP64_SNAN_V2(0), FP64_SNAN_V1(0), FP64_SNAN_V2(0) } },     \
+            { /*src1     */ { FP64_SNAN_V0(0), FP64_SNAN_V3(0), FP64_SNAN_V0(0), FP64_SNAN_V3(0) } },     \
+            { /* =>      */ { FP64_QNAN_V0(0), FP64_SNAN_V3(0), FP64_SNAN_V0(0), FP64_SNAN_V3(0) } },     \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                          \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                           \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                           \
+              /*xcpt?    */ false, false },                                                               \
+    /* QNan, Norm FP (Masked). */                                                                         \
+          { { /*src2     */ { FP64_QNAN(0), FP64_QNAN_MAX(1), FP64_NORM_V0(1), FP64_QNAN_V1(0) } },       \
+            { /*src1     */ { FP64_1(0),    FP64_1(1),        FP64_QNAN_V0(1), FP64_NORM_V2(1) } },       \
+            { /* =>      */ { FP64_QNAN(0), FP64_1(1),        FP64_QNAN_V0(1), FP64_NORM_V2(1) } },       \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                          \
+              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                          \
+              /*256:out  */ X86_MXCSR_XCPT_MASK,                                                          \
+              /*xcpt?    */ false, false },                                                               \
+    /* SNan, Norm FP (Masked). */                                                                         \
+          { { /*src2     */ { FP64_SNAN(1),      FP64_SNAN_MAX(1), FP64_NORM_V0(1), FP64_SNAN_V1(0) } },  \
+            { /*src1     */ { FP64_1(0),         FP64_1(0),        FP64_SNAN_V0(1), FP64_NORM_V2(1) } },  \
+            { /* =>      */ { FP64_QNAN_V(1, 1), FP64_1(0),        FP64_SNAN_V0(1), FP64_NORM_V2(1) } },  \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                          \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                           \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                           \
+              /*xcpt?    */ false, false },                                                               \
+    /* QNan, QNan (Unmasked). */                                                                          \
+    /*14*/{ { /*src2     */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V0(0),  FP64_QNAN_V1(0) } },      \
+            { /*src1     */ { FP64_QNAN(0), FP64_QNAN(0),     FP64_QNAN_MAX(0), FP64_QNAN_V2(0) } },      \
+            { /* =>      */ { FP64_QNAN(0), FP64_QNAN(0),     FP64_QNAN_MAX(0), FP64_QNAN_V2(0) } },      \
+              /*mxcsr:in */ 0,                                                                            \
+              /*128:out  */ 0,                                                                            \
+              /*256:out  */ 0,                                                                            \
+              /*xcpt?    */ false, false },                                                               \
+          { { /*src2     */ { FP64_QNAN_MAX(0), FP64_QNAN_V1(0), FP64_QNAN_V2(0), FP64_QNAN_V3(0) } },    \
+            { /*src1     */ { FP64_QNAN(0),     FP64_QNAN_V2(0), FP64_QNAN_V0(0), FP64_QNAN_V2(0) } },    \
+            { /* =>      */ { FP64_QNAN(0),     FP64_QNAN_V2(0), FP64_QNAN_V0(0), FP64_QNAN_V2(0) } },    \
+              /*mxcsr:in */ 0,                                                                            \
+              /*128:out  */ 0,                                                                            \
+              /*256:out  */ 0,                                                                            \
+              /*xcpt?    */ false, false },                                                               \
+          { { /*src2     */ { FP64_QNAN_V1(0), FP64_QNAN_V1(0), FP64_QNAN_V2(0), FP64_QNAN_V3(0) } },     \
+            { /*src1     */ { FP64_QNAN_V2(0), FP64_QNAN_V2(1), FP64_QNAN_V0(0), FP64_QNAN_V0(1) } },     \
+            { /* =>      */ { FP64_QNAN_V2(0), FP64_QNAN_V2(1), FP64_QNAN_V0(0), FP64_QNAN_V0(1) } },     \
+              /*mxcsr:in */ 0,                                                                            \
+              /*128:out  */ 0,                                                                            \
+              /*256:out  */ 0,                                                                            \
+              /*xcpt?    */ false, false },                                                               \
+                                                                                                          \
+    /* QNan, SNan (Unmasked). */                                                                          \
+          { { /*src2     */ { FP64_QNAN(0),      FP64_QNAN_V1(0), FP64_QNAN_V2(0), FP64_QNAN_V3(0) } },   \
+            { /*src1     */ { FP64_SNAN(0),      FP64_SNAN_V2(1), FP64_SNAN_V3(1), FP64_SNAN_V2(0) } },   \
+            { /* =>      */ { FP64_QNAN_V(0, 1), FP64_QNAN_V2(1), FP64_SNAN_V3(1), FP64_SNAN_V2(0) } },   \
+              /*mxcsr:in */ 0,                                                                            \
+              /*128:out  */ X86_MXCSR_IE,                                                                 \
+              /*256:out  */ X86_MXCSR_IE,                                                                 \
+              /*xcpt?    */ true, true },                                                                 \
+          { { /*src2     */ { FP64_QNAN_MAX(0),  FP64_QNAN_MAX(0), FP64_QNAN_V0(0),  FP64_QNAN_V1(0) } }, \
+            { /*src1     */ { FP64_SNAN(0),      FP64_SNAN(0),     FP64_SNAN_MAX(0), FP64_SNAN_V2(0) } }, \
+            { /* =>      */ { FP64_QNAN_V(0, 1), FP64_SNAN(0),     FP64_SNAN_MAX(0), FP64_SNAN_V2(0) } }, \
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,                             \
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,              \
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,              \
+              /*xcpt?    */ true, true },                                                                 \
+          { { /*src2     */ { FP64_QNAN_V1(0), FP64_QNAN_MAX(0), FP64_QNAN_V0(0),  FP64_QNAN_V1(0) } },   \
+            { /*src1     */ { FP64_SNAN_V2(0), FP64_QNAN(0),     FP64_QNAN_MAX(0), FP64_QNAN_V2(0) } },   \
+            { /* =>      */ { FP64_QNAN_V2(0), FP64_QNAN(0),     FP64_QNAN_MAX(0), FP64_QNAN_V2(0) } },   \
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,                                             \
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,                              \
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,                              \
+              /*xcpt?    */ true, true },                                                                 \
+    /* SNan, QNan (Unmasked). */                                                                          \
+          { { /*src2     */ { FP64_SNAN(0), FP64_SNAN(0),     FP64_SNAN_V1(0), FP64_SNAN_V1(0) } },       \
+            { /*src1     */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V3(0), FP64_QNAN_V2(0) } },       \
+            { /* =>      */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V3(0), FP64_QNAN_V2(0) } },       \
+              /*mxcsr:in */ X86_MXCSR_DAZ,                                                                \
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_IE,                                                 \
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_IE,                                                 \
+              /*xcpt?    */ true, true },                                                                 \
+          { { /*src2     */ { FP64_SNAN_MAX(0), FP64_SNAN_MAX(0), FP64_SNAN_V1(0), FP64_SNAN_V1(1) } },   \
+            { /*src1     */ { FP64_QNAN(0),     FP64_QNAN(0),     FP64_QNAN_V2(1), FP64_QNAN_V0(1) } },   \
+            { /* =>      */ { FP64_QNAN(0),     FP64_QNAN(0),     FP64_QNAN_V2(1), FP64_QNAN_V0(1) } },   \
+              /*mxcsr:in */ X86_MXCSR_RC_UP,                                                              \
+              /*128:out  */ X86_MXCSR_RC_UP | X86_MXCSR_IE,                                               \
+              /*256:out  */ X86_MXCSR_RC_UP | X86_MXCSR_IE,                                               \
+              /*xcpt?    */ true, true },                                                                 \
+          { { /*src2     */ { FP64_SNAN_V0(0), FP64_SNAN_MAX(0), FP64_SNAN_V1(0), FP64_SNAN_V1(1) } },    \
+            { /*src1     */ { FP64_QNAN_V3(0), FP64_QNAN(0),     FP64_QNAN_V2(1), FP64_QNAN_V3(1) } },    \
+            { /* =>      */ { FP64_QNAN_V3(0), FP64_QNAN(0),     FP64_QNAN_V2(1), FP64_QNAN_V3(1) } },    \
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,                                             \
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,                              \
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,                              \
+              /*xcpt?    */ true, true },                                                                 \
+    /* SNan, SNan (Unmasked). */                                                                          \
+    /*23*/{ { /*src2     */ { FP64_SNAN(0),      FP64_SNAN(0),     FP64_SNAN_V1(0), FP64_SNAN_V2(0) } },  \
+            { /*src1     */ { FP64_SNAN(0),      FP64_SNAN_MAX(0), FP64_SNAN_V2(0), FP64_SNAN_V0(1) } },  \
+            { /* =>      */ { FP64_QNAN_V(0, 1), FP64_SNAN_MAX(0), FP64_SNAN_V2(0), FP64_SNAN_V0(1) } },  \
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ,                                                 \
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE,                                  \
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE,                                  \
+              /*xcpt?    */ true, true },                                                                 \
+          { { /*src2     */ { FP64_SNAN(0),     FP64_SNAN_V2(0), FP64_SNAN_V1(0), FP64_SNAN_V2(1) } },    \
+            { /*src1     */ { FP64_SNAN_MAX(0), FP64_SNAN_V0(0), FP64_SNAN_V2(1), FP64_SNAN_V3(1) } },    \
+            { /* =>      */ { FP64_QNAN_MAX(0), FP64_SNAN_V0(0), FP64_SNAN_V2(1), FP64_SNAN_V3(1) } },    \
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,                                                            \
+              /*128:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE,                                             \
+              /*256:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE,                                             \
+              /*xcpt?    */ true, true },                                                                 \
+          { { /*src2     */ { FP64_SNAN_V1(0), FP64_SNAN_V2(0), FP64_SNAN_V0(1), FP64_SNAN_V2(0) } },     \
+            { /*src1     */ { FP64_SNAN_V2(0), FP64_SNAN_V3(1), FP64_SNAN_V3(1), FP64_SNAN_V3(0) } },     \
+            { /* =>      */ { FP64_QNAN_V2(0), FP64_SNAN_V3(1), FP64_SNAN_V3(1), FP64_SNAN_V3(0) } },     \
+              /*mxcsr:in */ 0,                                                                            \
+              /*128:out  */ X86_MXCSR_IE,                                                                 \
+              /*256:out  */ X86_MXCSR_IE,                                                                 \
+              /*xcpt?    */ true, true },                                                                 \
+    /* QNan, Norm FP (Unmasked). */                                                                       \
+          { { /*src2     */ { FP64_QNAN(0), FP64_QNAN_MAX(1), FP64_NORM_V0(1), FP64_QNAN_V1(0) } },       \
+            { /*src1     */ { FP64_1(0),    FP64_INF(1),      FP64_QNAN_V0(1), FP64_NORM_V2(1) } },       \
+            { /* =>      */ { FP64_QNAN(0), FP64_INF(1),      FP64_QNAN_V0(1), FP64_NORM_V2(1) } },       \
+              /*mxcsr:in */ X86_MXCSR_FZ,                                                                 \
+              /*128:out  */ X86_MXCSR_FZ,                                                                 \
+              /*256:out  */ X86_MXCSR_FZ,                                                                 \
+              /*xcpt?    */ false, false },                                                               \
+    /* SNan, Norm FP (Unmasked). */                                                                       \
+    /*27*/{ { /*src2     */ { FP64_SNAN(1),      FP64_SNAN_MAX(1), FP64_NORM_V0(1), FP64_SNAN_V1(0) } },  \
+            { /*src1     */ { FP64_1(0),         FP64_INF(0),      FP64_SNAN_V0(1), FP64_NORM_V2(1) } },  \
+            { /* =>      */ { FP64_QNAN_V(1, 1), FP64_INF(0),      FP64_SNAN_V0(1), FP64_NORM_V2(1) } },  \
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,                             \
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,              \
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,              \
+              /*xcpt?    */ true, true },                                                                 \
 
 /**
@@ -1328,74 +1368,88 @@
  **/
 #define FP64_TABLE_D1_H_PD_INVALIDS \
-    /* 0*/{ { /*src2     */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V0),       FP64_QNAN_V(0, FP64_FRAC_V1)       } }, \
-            { /*src1     */ { FP64_QNAN(0),                       FP64_QNAN(0),                       FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } }, \
-            { /* =>      */ { FP64_QNAN(0),                       FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V0)       } }, \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                  \
-              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                                  \
-              /*256:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                                  \
-              /*xcpt?    */ false, false },                                                                                                                                       \
-          { { /*src2     */ { FP64_QNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1)       } },                       \
-            { /*src1     */ { FP64_QNAN(0), FP64_SNAN(0),                       FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V2)       } },                       \
-            { /* =>      */ { FP64_QNAN(0), FP64_QNAN(0),                       FP64_QNAN(0),                       FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } },                       \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                  \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                   \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                   \
-              /*xcpt?    */ false, false },                                                                                                                                       \
-          { { /*src2     */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2),       FP64_SNAN_V(0, FP64_FRAC_V1),       FP64_QNAN_V(0, FP64_FRAC_V2) } },       \
-            { /*src1     */ { FP64_SNAN(0),                       FP64_QNAN(0),                       FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V3) } },       \
-            { /* =>      */ { FP64_QNAN_V(0, 1),                  FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, 1),                  FP64_QNAN_V(0, FP64_FRAC_V1) } },       \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                  \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                   \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                   \
-              /*xcpt?    */ false, false },                                                                                                                                       \
-          { { /*src2     */ { FP64_SNAN(0),      FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN) } },                  \
-            { /*src1     */ { FP64_SNAN(0),      FP64_SNAN(0),                       FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX) } },                  \
-            { /* =>      */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1),                  FP64_QNAN_V(0, 1),                  FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } },                  \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                  \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                   \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                   \
-              /*xcpt?    */ false, false },                                                                                                                                       \
-          { { /*src2     */ { FP64_QNAN(0), FP64_NORM_V1(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1)       } },                                          \
-            { /*src1     */ { FP64_QNAN(0), FP64_1(1),       FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V2(1)                    } },                                          \
-            { /* =>      */ { FP64_QNAN(0), FP64_QNAN(0),    FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } },                                          \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                  \
-              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                                  \
-              /*256:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                                  \
-              /*xcpt?    */ false, false },                                                                                                                                       \
-          { { /*src2     */ { FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_1(0),                          FP64_SNAN_V(0, FP64_FRAC_V1),       FP64_NORM_V3(0)              } },       \
-            { /*src1     */ { FP64_SNAN(0),                       FP64_1(1),                          FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_NORM_V2(1)              } },       \
-            { /* =>      */ { FP64_QNAN_V(0, 1),                  FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } },       \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                  \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                   \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                   \
-              /*xcpt?    */ false, false },                                                                                                                                       \
-          { { /*src2     */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V0),       FP64_QNAN_V(0, FP64_FRAC_V1)       } }, \
-            { /*src1     */ { FP64_QNAN(0),                       FP64_QNAN(0),                       FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } }, \
-            { /* =>      */ { FP64_QNAN(0),                       FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V0)       } }, \
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,                                                                                                     \
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,                                                                                                     \
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,                                                                                                     \
-              /*xcpt?    */ false, false },                                                                                                                                       \
-          { { /*src2     */ { FP64_QNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1)       } },                       \
-            { /*src1     */ { FP64_QNAN(0), FP64_SNAN(0),                       FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V2)       } },                       \
-            { /* =>      */ { FP64_QNAN(0), FP64_QNAN(0),                       FP64_QNAN(0),                       FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } },                       \
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,                                                                                                                      \
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,                                                                                                       \
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,                                                                                                       \
-              /*xcpt?    */ true, true },                                                                                                                                         \
-          { { /*src2     */ { FP64_SNAN(0),      FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN) } },                  \
-            { /*src1     */ { FP64_SNAN(0),      FP64_SNAN(0),                       FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX) } },                  \
-            { /* =>      */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1),                  FP64_QNAN_V(0, 1),                  FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } },                  \
-              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,                                                                                                                       \
-              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,                                                                                                        \
-              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,                                                                                                        \
-              /*xcpt?    */ true, true },                                                                                                                                         \
-    /* 9*/{ { /*src2     */ { FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_1(0),                          FP64_SNAN_V(0, FP64_FRAC_V1),       FP64_NORM_V3(0)              } },       \
-            { /*src1     */ { FP64_SNAN(0),                       FP64_1(1),                          FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_NORM_V2(1)              } },       \
-            { /* =>      */ { FP64_QNAN_V(0, 1),                  FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } },       \
-              /*mxcsr:in */ X86_MXCSR_RC_UP,                                                                                                                                      \
-              /*128:out  */ X86_MXCSR_RC_UP | X86_MXCSR_IE,                                                                                                                       \
-              /*256:out  */ X86_MXCSR_RC_UP | X86_MXCSR_IE,                                                                                                                       \
-              /*xcpt?    */ true, true },                                                                                                                                         \
+    /*0 */{ { /*src2     */ { FP64_QNAN_MAX(0), FP64_QNAN(0),     FP64_QNAN_V0(0), FP64_QNAN_V1(0)  } },     \
+            { /*src1     */ { FP64_QNAN(0),     FP64_QNAN(0),     FP64_QNAN(0),    FP64_QNAN_MAX(0) } },     \
+            { /* =>      */ { FP64_QNAN(0),     FP64_QNAN_MAX(0), FP64_QNAN(0),    FP64_QNAN_V0(0)  } },     \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                             \
+              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                             \
+              /*256:out  */ X86_MXCSR_XCPT_MASK,                                                             \
+              /*xcpt?    */ false, false },                                                                  \
+          { { /*src2     */ { FP64_QNAN(0), FP64_SNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V1(0)  } },            \
+            { /*src1     */ { FP64_QNAN(0), FP64_SNAN(0), FP64_QNAN(0),     FP64_SNAN_V2(0)  } },            \
+            { /* =>      */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN(0),     FP64_QNAN_MAX(0) } },            \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                             \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                              \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                              \
+              /*xcpt?    */ false, false },                                                                  \
+          { { /*src2     */ { FP64_SNAN_MAX(0),  FP64_QNAN_V2(0),  FP64_SNAN_V1(0),   FP64_QNAN_V2(0) } },   \
+            { /*src1     */ { FP64_SNAN(0),      FP64_QNAN(0),     FP64_SNAN(0),      FP64_QNAN_V3(0) } },   \
+            { /* =>      */ { FP64_QNAN_V(0, 1), FP64_QNAN_MAX(0), FP64_QNAN_V(0, 1), FP64_QNAN_V1(0) } },   \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                             \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                              \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                              \
+              /*xcpt?    */ false, false },                                                                  \
+          { { /*src2     */ { FP64_SNAN(0),      FP64_SNAN_MAX(0),  FP64_SNAN_MAX(0),  FP64_SNAN(0)     } }, \
+            { /*src1     */ { FP64_SNAN(0),      FP64_SNAN(0),      FP64_SNAN(0),      FP64_SNAN_MAX(0) } }, \
+            { /* =>      */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_MAX(0) } }, \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                             \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                              \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                              \
+              /*xcpt?    */ false, false },                                                                  \
+          { { /*src2     */ { FP64_QNAN(0), FP64_NORM_V1(0), FP64_QNAN_MAX(0), FP64_QNAN_V1(0)  } },         \
+            { /*src1     */ { FP64_QNAN(0), FP64_1(1),       FP64_QNAN_MAX(1), FP64_NORM_V2(1)  } },         \
+            { /* =>      */ { FP64_QNAN(0), FP64_QNAN(0),    FP64_QNAN_MAX(1), FP64_QNAN_MAX(0) } },         \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                             \
+              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                             \
+              /*256:out  */ X86_MXCSR_XCPT_MASK,                                                             \
+              /*xcpt?    */ false, false },                                                                  \
+          { { /*src2     */ { FP64_SNAN_MAX(1),  FP64_1(0),        FP64_SNAN_V1(0),  FP64_NORM_V3(0) } },    \
+            { /*src1     */ { FP64_SNAN(0),      FP64_1(1),        FP64_SNAN_MAX(0), FP64_NORM_V2(1) } },    \
+            { /* =>      */ { FP64_QNAN_V(0, 1), FP64_QNAN_MAX(1), FP64_QNAN_MAX(0), FP64_QNAN_V1(0) } },    \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                             \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                              \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                              \
+              /*xcpt?    */ false, false },                                                                  \
+          { { /*src2     */ { FP64_QNAN_MAX(0), FP64_QNAN(0),     FP64_QNAN_V0(0), FP64_QNAN_V1(0)  } },     \
+            { /*src1     */ { FP64_QNAN(0),     FP64_QNAN(0),     FP64_QNAN(0),    FP64_QNAN_MAX(0) } },     \
+            { /* =>      */ { FP64_QNAN(0),     FP64_QNAN_MAX(0), FP64_QNAN(0),    FP64_QNAN_V0(0)  } },     \
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,                                \
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,                                \
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,                                \
+              /*xcpt?    */ false, false },                                                                  \
+          { { /*src2     */ { FP64_QNAN(0), FP64_SNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V1(0)  } },            \
+            { /*src1     */ { FP64_QNAN(0), FP64_SNAN(0), FP64_QNAN(0),     FP64_SNAN_V2(0)  } },            \
+            { /* =>      */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN(0),     FP64_QNAN_MAX(0) } },            \
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,                                                 \
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,                                  \
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,                                  \
+              /*xcpt?    */ true, true },                                                                    \
+          { { /*src2     */ { FP64_SNAN_MAX(0),  FP64_QNAN_V2(0),  FP64_SNAN_V1(0),   FP64_QNAN_V2(0) } },    \
+            { /*src1     */ { FP64_SNAN(0),      FP64_QNAN(0),     FP64_SNAN(0),      FP64_QNAN_V3(0) } },    \
+            { /* =>      */ { FP64_QNAN_V(0, 1), FP64_QNAN_MAX(0), FP64_QNAN_V(0, 1), FP64_QNAN_V1(0) } },    \
+              /*mxcsr:in */ 0,                                                                               \
+              /*128:out  */ X86_MXCSR_IE,                                                                    \
+              /*256:out  */ X86_MXCSR_IE,                                                                    \
+              /*xcpt?    */ true, true },                                                                    \
+          { { /*src2     */ { FP64_SNAN(0),      FP64_SNAN_MAX(0),  FP64_SNAN_MAX(0),  FP64_SNAN(0)     } }, \
+            { /*src1     */ { FP64_SNAN(0),      FP64_SNAN(0),      FP64_SNAN(0),      FP64_SNAN_MAX(0) } }, \
+            { /* =>      */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_MAX(0) } }, \
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,                                                  \
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,                                   \
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,                                   \
+              /*xcpt?    */ true, true },                                                                    \
+          { { /*src2     */ { FP64_QNAN(0), FP64_NORM_V1(0), FP64_QNAN_MAX(0), FP64_QNAN_V1(0)  } },         \
+            { /*src1     */ { FP64_QNAN(0), FP64_1(1),       FP64_QNAN_MAX(1), FP64_NORM_V2(1)  } },         \
+            { /* =>      */ { FP64_QNAN(0), FP64_QNAN(0),    FP64_QNAN_MAX(1), FP64_QNAN_MAX(0) } },         \
+              /*mxcsr:in */ 0,                                                                               \
+              /*128:out  */ 0,                                                                               \
+              /*256:out  */ 0,                                                                               \
+              /*xcpt?    */ false, false },                                                                  \
+    /*11*/{ { /*src2     */ { FP64_SNAN_MAX(1),  FP64_1(0),        FP64_SNAN_V1(0),  FP64_NORM_V3(0) } },    \
+            { /*src1     */ { FP64_SNAN(0),      FP64_1(1),        FP64_SNAN_MAX(0), FP64_NORM_V2(1) } },    \
+            { /* =>      */ { FP64_QNAN_V(0, 1), FP64_QNAN_MAX(1), FP64_QNAN_MAX(0), FP64_QNAN_V1(0) } },    \
+              /*mxcsr:in */ X86_MXCSR_RC_UP,                                                                 \
+              /*128:out  */ X86_MXCSR_RC_UP | X86_MXCSR_IE,                                                  \
+              /*256:out  */ X86_MXCSR_RC_UP | X86_MXCSR_IE,                                                  \
+              /*xcpt?    */ true, true },                                                                    \
 
 /**
@@ -1480,74 +1534,74 @@
  **/
 #define FP64_TABLE_D9_PD_INVALIDS \
-    /* 0*/{ { /*src2     */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0),       FP64_QNAN_V(0, FP64_FRAC_V1) } }, \
-            { /*src1     */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, \
-            { /* =>      */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0),       FP64_QNAN_V(0, FP64_FRAC_V1) } }, \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                      \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                       \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                       \
-              /*xcpt?    */ false, false },                                                                                                           \
-          { { /*src2     */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0),       FP64_QNAN_V(0, FP64_FRAC_V1) } }, \
-            { /*src1     */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2) } }, \
-            { /* =>      */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0),       FP64_QNAN_V(0, FP64_FRAC_V1) } }, \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                      \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                       \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                       \
-              /*xcpt?    */ false, false },                                                                                                           \
-          { { /*src2     */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } },       \
-            { /*src1     */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } },       \
-            { /* =>      */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } },       \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,                                                                                       \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,                                                                        \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,                                                                        \
-              /*xcpt?    */ false, false },                                                                                                           \
-          { { /*src2     */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } },       \
-            { /*src1     */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V3) } },       \
-            { /* =>      */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } },       \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                      \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                       \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                       \
-              /*xcpt?    */ false, false },                                                                                                           \
-          { { /*src2     */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1),              FP64_QNAN_V(0, FP64_FRAC_V1) } },       \
-            { /*src1     */ { FP64_1(0),    FP64_1(1),                          FP64_QNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1)              } },       \
-            { /* =>      */ { FP64_QNAN(0), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1),              FP64_QNAN_V(0, FP64_FRAC_V1) } },       \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                      \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                       \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                       \
-              /*xcpt?    */ false, false },                                                                                                           \
-          { { /*src2     */ { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1),              FP64_SNAN_V(0, FP64_FRAC_V1) } },       \
-            { /*src1     */ { FP64_1(0),    FP64_1(0),                          FP64_SNAN_V(1, FP64_FRAC_V0), FP64_NORM_V2(1)              } },       \
-            { /* =>      */ { FP64_SNAN(1), FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V0(1),              FP64_SNAN_V(0, FP64_FRAC_V1) } },       \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                      \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                       \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                       \
-              /*xcpt?    */ false, false },                                                                                                           \
-          { { /*src2     */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0),       FP64_QNAN_V(0, FP64_FRAC_V1) } }, \
-            { /*src1     */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2) } }, \
-            { /* =>      */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0),       FP64_QNAN_V(0, FP64_FRAC_V1) } }, \
-              /*mxcsr:in */ 0,                                                                                                                        \
-              /*128:out  */ X86_MXCSR_IE,                                                                                                             \
-              /*256:out  */ X86_MXCSR_IE,                                                                                                             \
-              /*xcpt?    */ true, true },                                                                                                             \
-          { { /*src2     */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0),       FP64_QNAN_V(0, FP64_FRAC_V1) } }, \
-            { /*src1     */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2) } }, \
-            { /* =>      */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V0),       FP64_QNAN_V(0, FP64_FRAC_V1) } }, \
-              /*mxcsr:in */ 0,                                                                                                                        \
-              /*128:out  */ X86_MXCSR_IE,                                                                                                             \
-              /*256:out  */ X86_MXCSR_IE,                                                                                                             \
-              /*xcpt?    */ true, true },                                                                                                             \
-          { { /*src2     */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V1) } },       \
-            { /*src1     */ { FP64_QNAN(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_QNAN_V(0, FP64_FRAC_V3) } },       \
-            { /* =>      */ { FP64_SNAN(0), FP64_SNAN(0),                       FP64_QNAN_V(0, FP64_FRAC_V1), FP64_QNAN_V(0, FP64_FRAC_V1) } },       \
-              /*mxcsr:in */ 0,                                                                                                                        \
-              /*128:out  */ X86_MXCSR_IE,                                                                                                             \
-              /*256:out  */ X86_MXCSR_IE,                                                                                                             \
-              /*xcpt?    */ true, true },                                                                                                             \
-          { { /*src2     */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } },       \
-            { /*src1     */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V3) } },       \
-            { /* =>      */ { FP64_SNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_SNAN_V(0, FP64_FRAC_V2) } },       \
-              /*mxcsr:in */ 0,                                                                                                                        \
-              /*128:out  */ X86_MXCSR_IE,                                                                                                             \
-              /*256:out  */ X86_MXCSR_IE,                                                                                                             \
-              /*xcpt?    */ true, true },                                                                                                             \
+    /*0 */{ { /*src2     */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V0(0),  FP64_QNAN_V1(0) } }, \
+            { /*src1     */ { FP64_QNAN(0), FP64_QNAN(0),     FP64_QNAN_MAX(0), FP64_QNAN_V2(0) } }, \
+            { /* =>      */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V0(0),  FP64_QNAN_V1(0) } }, \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                     \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                      \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                      \
+              /*xcpt?    */ false, false },                                                          \
+          { { /*src2     */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V0(0),  FP64_QNAN_V1(0) } }, \
+            { /*src1     */ { FP64_SNAN(0), FP64_SNAN(0),     FP64_SNAN_MAX(0), FP64_SNAN_V2(0) } }, \
+            { /* =>      */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V0(0),  FP64_QNAN_V1(0) } }, \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                     \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                      \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                      \
+              /*xcpt?    */ false, false },                                                          \
+          { { /*src2     */ { FP64_SNAN(0), FP64_SNAN(0),     FP64_SNAN_V1(0), FP64_SNAN_V1(0) } },  \
+            { /*src1     */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V2(0), FP64_QNAN_V3(0) } },  \
+            { /* =>      */ { FP64_SNAN(0), FP64_SNAN(0),     FP64_SNAN_V1(0), FP64_SNAN_V1(0) } },  \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,                                      \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,                       \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,                       \
+              /*xcpt?    */ false, false },                                                          \
+          { { /*src2     */ { FP64_SNAN(0), FP64_SNAN(0),     FP64_SNAN_V1(0), FP64_SNAN_V2(0) } },  \
+            { /*src1     */ { FP64_SNAN(0), FP64_SNAN_MAX(0), FP64_SNAN_V2(0), FP64_SNAN_V3(0) } },  \
+            { /* =>      */ { FP64_SNAN(0), FP64_SNAN(0),     FP64_SNAN_V1(0), FP64_SNAN_V2(0) } },  \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                     \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                      \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                      \
+              /*xcpt?    */ false, false },                                                          \
+          { { /*src2     */ { FP64_QNAN(0), FP64_QNAN_MAX(1), FP64_NORM_V0(1), FP64_QNAN_V1(0) } },  \
+            { /*src1     */ { FP64_1(0),    FP64_1(1),        FP64_QNAN_V0(1), FP64_NORM_V2(1) } },  \
+            { /* =>      */ { FP64_QNAN(0), FP64_QNAN_MAX(1), FP64_NORM_V0(1), FP64_QNAN_V1(0) } },  \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                     \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                      \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                      \
+              /*xcpt?    */ false, false },                                                          \
+          { { /*src2     */ { FP64_SNAN(1), FP64_SNAN_MAX(1), FP64_NORM_V0(1), FP64_SNAN_V1(0) } },  \
+            { /*src1     */ { FP64_1(0),    FP64_1(0),        FP64_SNAN_V0(1), FP64_NORM_V2(1) } },  \
+            { /* =>      */ { FP64_SNAN(1), FP64_SNAN_MAX(1), FP64_NORM_V0(1), FP64_SNAN_V1(0) } },  \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                     \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                      \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                      \
+              /*xcpt?    */ false, false },                                                          \
+          { { /*src2     */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V0(0),  FP64_QNAN_V1(0) } }, \
+            { /*src1     */ { FP64_QNAN(0), FP64_QNAN(0),     FP64_QNAN_MAX(0), FP64_QNAN_V2(0) } }, \
+            { /* =>      */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V0(0),  FP64_QNAN_V1(0) } }, \
+              /*mxcsr:in */ 0,                                                                       \
+              /*128:out  */ X86_MXCSR_IE,                                                            \
+              /*256:out  */ X86_MXCSR_IE,                                                            \
+              /*xcpt?    */ true, true },                                                            \
+          { { /*src2     */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V0(0),  FP64_QNAN_V1(0) } }, \
+            { /*src1     */ { FP64_SNAN(0), FP64_SNAN(0),     FP64_SNAN_MAX(0), FP64_SNAN_V2(0) } }, \
+            { /* =>      */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V0(0),  FP64_QNAN_V1(0) } }, \
+              /*mxcsr:in */ 0,                                                                       \
+              /*128:out  */ X86_MXCSR_IE,                                                            \
+              /*256:out  */ X86_MXCSR_IE,                                                            \
+              /*xcpt?    */ true, true },                                                            \
+          { { /*src2     */ { FP64_SNAN(0), FP64_SNAN(0),     FP64_SNAN_V1(0), FP64_SNAN_V1(0) } },  \
+            { /*src1     */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V2(0), FP64_QNAN_V3(0) } },  \
+            { /* =>      */ { FP64_SNAN(0), FP64_SNAN(0),     FP64_SNAN_V1(0), FP64_SNAN_V1(0) } },  \
+              /*mxcsr:in */ 0,                                                                       \
+              /*128:out  */ X86_MXCSR_IE,                                                            \
+              /*256:out  */ X86_MXCSR_IE,                                                            \
+              /*xcpt?    */ true, true },                                                            \
+          { { /*src2     */ { FP64_SNAN(0), FP64_SNAN(0),     FP64_SNAN_V1(0), FP64_SNAN_V2(0) } },  \
+            { /*src1     */ { FP64_SNAN(0), FP64_SNAN_MAX(0), FP64_SNAN_V2(0), FP64_SNAN_V3(0) } },  \
+            { /* =>      */ { FP64_SNAN(0), FP64_SNAN(0),     FP64_SNAN_V1(0), FP64_SNAN_V2(0) } },  \
+              /*mxcsr:in */ 0,                                                                       \
+              /*128:out  */ X86_MXCSR_IE,                                                            \
+              /*256:out  */ X86_MXCSR_IE,                                                            \
+              /*xcpt?    */ true, true },                                                            \
 
 /**
@@ -1770,212 +1824,212 @@
  **/
 #define FP64_TABLE_D9_SD_INVALIDS \
-    /* QNan, QNan (Masked). */                                                                                           \
-    /* 0*/{ { /*src2     */ { FP64_QNAN(0), FP64_RAND_V2(0), FP64_RAND_V0(1), FP64_RAND_V1(0) } },                       \
-            { /*src1     */ { FP64_QNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },                       \
-            { /* =>      */ { FP64_QNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },                       \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                         \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                          \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                          \
-              /*xcpt?    */ false, false },                                                                              \
-          { { /*src2     */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(0) } }, \
-            { /*src1     */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V3(1) } }, \
-            { /* =>      */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V3(1) } }, \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                         \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                          \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                          \
-              /*xcpt?    */ false, false },                                                                              \
-          { { /*src2     */ { FP64_QNAN_V(0, FP64_FRAC_V0),       FP64_RAND_V0(1), FP64_RAND_V0(1), FP64_RAND_V2(0) } }, \
-            { /*src1     */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_RAND_V1(0), FP64_RAND_V0(0), FP64_RAND_V2(1) } }, \
-            { /* =>      */ { FP64_QNAN_V(0, FP64_FRAC_V0),       FP64_RAND_V1(0), FP64_RAND_V0(0), FP64_RAND_V2(1) } }, \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                         \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                          \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                          \
-              /*xcpt?    */ false, false },                                                                              \
-    /* QNan, SNan (Masked). */                                                                                           \
-          { { /*src2     */ { FP64_QNAN(0), FP64_RAND_V1(0), FP64_RAND_V3(1), FP64_RAND_V2(0) } },                       \
-            { /*src1     */ { FP64_SNAN(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(0) } },                       \
-            { /* =>      */ { FP64_QNAN(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(0) } },                       \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                         \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                          \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                          \
-              /*xcpt?    */ false, false },                                                                              \
-          { { /*src2     */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_RAND_V2(1), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, \
-            { /*src1     */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, \
-            { /* =>      */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                         \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                          \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                          \
-              /*xcpt?    */ false, false },                                                                              \
-          { { /*src2     */ { FP64_QNAN_V(0, FP64_FRAC_V0),       FP64_RAND_V1(1), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, \
-            { /*src1     */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_RAND_V3(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } }, \
-            { /* =>      */ { FP64_QNAN_V(0, FP64_FRAC_V0),       FP64_RAND_V3(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } }, \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                         \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                          \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                          \
-              /*xcpt?    */ false, false },                                                                              \
-    /* SNan, QNan (Masked). */                                                                                           \
-          { { /*src2     */ { FP64_SNAN(0), FP64_RAND_V2(1), FP64_RAND_V3(0), FP64_RAND_V1(1) } },                       \
-            { /*src1     */ { FP64_QNAN(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } },                       \
-            { /* =>      */ { FP64_SNAN(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } },                       \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,                                                          \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,                                           \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,                                           \
-              /*xcpt?    */ false, false },                                                                              \
-          { { /*src2     */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_RAND_V1(1), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, \
-            { /*src1     */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_RAND_V2(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, \
-            { /* =>      */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_RAND_V2(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                         \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                          \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                          \
-              /*xcpt?    */ false, false },                                                                              \
-          { { /*src2     */ { FP64_SNAN_V(0, FP64_FRAC_V1), FP64_RAND_V1(1), FP64_RAND_V0(1), FP64_RAND_V2(0) } },       \
-            { /*src1     */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } },       \
-            { /* =>      */ { FP64_SNAN_V(0, FP64_FRAC_V1), FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } },       \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                         \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                          \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                          \
-              /*xcpt?    */ false, false },                                                                              \
-    /* SNan, SNan (Masked). */                                                                                           \
-          { { /*src2     */ { FP64_SNAN(0), FP64_RAND_V1(1), FP64_RAND_V0(1), FP64_RAND_V2(0) } },                       \
-            { /*src1     */ { FP64_SNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },                       \
-            { /* =>      */ { FP64_SNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },                       \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                         \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                          \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                          \
-              /*xcpt?    */ false, false },                                                                              \
-          { { /*src2     */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_RAND_V1(0), FP64_RAND_V0(1), FP64_RAND_V2(1) } }, \
-            { /*src1     */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_RAND_V0(0), FP64_RAND_V3(0), FP64_RAND_V0(1) } }, \
-            { /* =>      */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_RAND_V0(0), FP64_RAND_V3(0), FP64_RAND_V0(1) } }, \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                         \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                          \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                          \
-              /*xcpt?    */ false, false },                                                                              \
-          { { /*src2     */ { FP64_SNAN_V(0, FP64_FRAC_V1), FP64_RAND_V1(1), FP64_RAND_V1(1), FP64_RAND_V2(0) } },       \
-            { /*src1     */ { FP64_SNAN_V(0, FP64_FRAC_V2), FP64_RAND_V2(1), FP64_RAND_V3(1), FP64_RAND_V1(1) } },       \
-            { /* =>      */ { FP64_SNAN_V(0, FP64_FRAC_V1), FP64_RAND_V2(1), FP64_RAND_V3(1), FP64_RAND_V1(1) } },       \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                         \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                          \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                          \
-              /*xcpt?    */ false, false },                                                                              \
-    /* QNan, Normal (Masked). */                                                                                         \
-          { { /*src2     */ { FP64_QNAN(0), FP64_RAND_V3(1), FP64_RAND_V2(1), FP64_RAND_V2(0) } },                       \
-            { /*src1     */ { FP64_1(0),    FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V1(1) } },                       \
-            { /* =>      */ { FP64_QNAN(0), FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V1(1) } },                       \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                         \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                          \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                          \
-              /*xcpt?    */ false, false },                                                                              \
-    /* SNan, Normal (Masked). */                                                                                         \
-          { { /*src2     */ { FP64_SNAN(1), FP64_RAND_V0(1), FP64_RAND_V2(1), FP64_RAND_V2(0) } },                       \
-            { /*src1     */ { FP64_1(0),    FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V3(1) } },                       \
-            { /* =>      */ { FP64_SNAN(1), FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V3(1) } },                       \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                         \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                          \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                          \
-              /*xcpt?    */ false, false },                                                                              \
-    /* QNan, QNan (Unmasked). */                                                                                         \
-    /* 0*/{ { /*src2     */ { FP64_QNAN(0), FP64_RAND_V2(0), FP64_RAND_V0(1), FP64_RAND_V1(0) } },                       \
-            { /*src1     */ { FP64_QNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },                       \
-            { /* =>      */ { FP64_QNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },                       \
-              /*mxcsr:in */ 0,                                                                                           \
-              /*128:out  */ X86_MXCSR_IE,                                                                                \
-              /*256:out  */ X86_MXCSR_IE,                                                                                \
-              /*xcpt?    */ true, true },                                                                                \
-          { { /*src2     */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(0) } }, \
-            { /*src1     */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V3(1) } }, \
-            { /* =>      */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V3(1) } }, \
-              /*mxcsr:in */ 0,                                                                                           \
-              /*128:out  */ X86_MXCSR_IE,                                                                                \
-              /*256:out  */ X86_MXCSR_IE,                                                                                \
-              /*xcpt?    */ true, true },                                                                                \
-          { { /*src2     */ { FP64_QNAN_V(0, FP64_FRAC_V0),       FP64_RAND_V0(1), FP64_RAND_V0(1), FP64_RAND_V2(0) } }, \
-            { /*src1     */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_RAND_V1(0), FP64_RAND_V0(0), FP64_RAND_V2(1) } }, \
-            { /* =>      */ { FP64_QNAN_V(0, FP64_FRAC_V0),       FP64_RAND_V1(0), FP64_RAND_V0(0), FP64_RAND_V2(1) } }, \
-              /*mxcsr:in */ 0,                                                                                           \
-              /*128:out  */ X86_MXCSR_IE,                                                                                \
-              /*256:out  */ X86_MXCSR_IE,                                                                                \
-              /*xcpt?    */ true, true },                                                                                \
-    /* QNan, SNan (Unmasked). */                                                                                         \
-          { { /*src2     */ { FP64_QNAN(0), FP64_RAND_V1(0), FP64_RAND_V3(1), FP64_RAND_V2(0) } },                       \
-            { /*src1     */ { FP64_SNAN(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(0) } },                       \
-            { /* =>      */ { FP64_QNAN(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(0) } },                       \
-              /*mxcsr:in */ 0,                                                                                           \
-              /*128:out  */ X86_MXCSR_IE,                                                                                \
-              /*256:out  */ X86_MXCSR_IE,                                                                                \
-              /*xcpt?    */ true, true },                                                                                \
-          { { /*src2     */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_RAND_V2(1), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, \
-            { /*src1     */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, \
-            { /* =>      */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, \
-              /*mxcsr:in */ 0,                                                                                           \
-              /*128:out  */ X86_MXCSR_IE,                                                                                \
-              /*256:out  */ X86_MXCSR_IE,                                                                                \
-              /*xcpt?    */ true, true },                                                                                \
-          { { /*src2     */ { FP64_QNAN_V(0, FP64_FRAC_V0),       FP64_RAND_V1(1), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, \
-            { /*src1     */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_RAND_V3(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } }, \
-            { /* =>      */ { FP64_QNAN_V(0, FP64_FRAC_V0),       FP64_RAND_V3(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } }, \
-              /*mxcsr:in */ 0,                                                                                           \
-              /*128:out  */ X86_MXCSR_IE,                                                                                \
-              /*256:out  */ X86_MXCSR_IE,                                                                                \
-              /*xcpt?    */ true, true },                                                                                \
-    /* SNan, QNan (Unmasked). */                                                                                         \
-          { { /*src2     */ { FP64_SNAN(0), FP64_RAND_V2(1), FP64_RAND_V3(0), FP64_RAND_V1(1) } },                       \
-            { /*src1     */ { FP64_QNAN(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } },                       \
-            { /* =>      */ { FP64_SNAN(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } },                       \
-              /*mxcsr:in */ X86_MXCSR_FZ,                                                                                \
-              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_IE,                                                                 \
-              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_IE,                                                                 \
-              /*xcpt?    */ true, true },                                                                                \
-          { { /*src2     */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_RAND_V1(1), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, \
-            { /*src1     */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_RAND_V2(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, \
-            { /* =>      */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_RAND_V2(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, \
-              /*mxcsr:in */ 0,                                                                                           \
-              /*128:out  */ X86_MXCSR_IE,                                                                                \
-              /*256:out  */ X86_MXCSR_IE,                                                                                \
-              /*xcpt?    */ true, true },                                                                                \
-          { { /*src2     */ { FP64_SNAN_V(0, FP64_FRAC_V1), FP64_RAND_V1(1), FP64_RAND_V0(1), FP64_RAND_V2(0) } },       \
-            { /*src1     */ { FP64_QNAN_V(0, FP64_FRAC_V1), FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } },       \
-            { /* =>      */ { FP64_SNAN_V(0, FP64_FRAC_V1), FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } },       \
-              /*mxcsr:in */ 0,                                                                                           \
-              /*128:out  */ X86_MXCSR_IE,                                                                                \
-              /*256:out  */ X86_MXCSR_IE,                                                                                \
-              /*xcpt?    */ true, true },                                                                                \
-    /* SNan, SNan (Unmasked). */                                                                                         \
-          { { /*src2     */ { FP64_SNAN(0), FP64_RAND_V1(1), FP64_RAND_V0(1), FP64_RAND_V2(0) } },                       \
-            { /*src1     */ { FP64_SNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },                       \
-            { /* =>      */ { FP64_SNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },                       \
-              /*mxcsr:in */ 0,                                                                                           \
-              /*128:out  */ X86_MXCSR_IE,                                                                                \
-              /*256:out  */ X86_MXCSR_IE,                                                                                \
-              /*xcpt?    */ true, true },                                                                                \
-          { { /*src2     */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_RAND_V1(0), FP64_RAND_V0(1), FP64_RAND_V2(1) } }, \
-            { /*src1     */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_RAND_V0(0), FP64_RAND_V3(0), FP64_RAND_V0(1) } }, \
-            { /* =>      */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_RAND_V0(0), FP64_RAND_V3(0), FP64_RAND_V0(1) } }, \
-              /*mxcsr:in */ 0,                                                                                           \
-              /*128:out  */ X86_MXCSR_IE,                                                                                \
-              /*256:out  */ X86_MXCSR_IE,                                                                                \
-              /*xcpt?    */ true, true },                                                                                \
-          { { /*src2     */ { FP64_SNAN_V(0, FP64_FRAC_V1), FP64_RAND_V1(1), FP64_RAND_V1(1), FP64_RAND_V2(0) } },       \
-            { /*src1     */ { FP64_SNAN_V(0, FP64_FRAC_V2), FP64_RAND_V2(1), FP64_RAND_V3(1), FP64_RAND_V1(1) } },       \
-            { /* =>      */ { FP64_SNAN_V(0, FP64_FRAC_V1), FP64_RAND_V2(1), FP64_RAND_V3(1), FP64_RAND_V1(1) } },       \
-              /*mxcsr:in */ 0,                                                                                           \
-              /*128:out  */ X86_MXCSR_IE,                                                                                \
-              /*256:out  */ X86_MXCSR_IE,                                                                                \
-              /*xcpt?    */ true, true },                                                                                \
-    /* QNan, Normal (Unmasked). */                                                                                       \
-          { { /*src2     */ { FP64_QNAN(0), FP64_RAND_V3(1), FP64_RAND_V2(1), FP64_RAND_V2(0) } },                       \
-            { /*src1     */ { FP64_1(0),    FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V1(1) } },                       \
-            { /* =>      */ { FP64_QNAN(0), FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V1(1) } },                       \
-              /*mxcsr:in */ 0,                                                                                           \
-              /*128:out  */ X86_MXCSR_IE,                                                                                \
-              /*256:out  */ X86_MXCSR_IE,                                                                                \
-              /*xcpt?    */ true, true },                                                                                \
-    /* SNan, Normal (Unmasked). */                                                                                       \
-          { { /*src2     */ { FP64_SNAN(1), FP64_RAND_V0(1), FP64_RAND_V2(1), FP64_RAND_V2(0) } },                       \
-            { /*src1     */ { FP64_1(0),    FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V3(1) } },                       \
-            { /* =>      */ { FP64_SNAN(1), FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V3(1) } },                       \
-              /*mxcsr:in */ 0,                                                                                           \
-              /*128:out  */ X86_MXCSR_IE,                                                                                \
-              /*256:out  */ X86_MXCSR_IE,                                                                                \
-              /*xcpt?    */ true, true },                                                                                \
+    /* QNan, QNan (Masked). */                                                                         \
+    /*0 */{ { /*src2     */ { FP64_QNAN(0), FP64_RAND_V2(0), FP64_RAND_V0(1), FP64_RAND_V1(0) } },     \
+            { /*src1     */ { FP64_QNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },     \
+            { /* =>      */ { FP64_QNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },     \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                       \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                        \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                        \
+              /*xcpt?    */ false, false },                                                            \
+          { { /*src2     */ { FP64_QNAN_MAX(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(0) } }, \
+            { /*src1     */ { FP64_QNAN(0),     FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V3(1) } }, \
+            { /* =>      */ { FP64_QNAN_MAX(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V3(1) } }, \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                       \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                        \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                        \
+              /*xcpt?    */ false, false },                                                            \
+          { { /*src2     */ { FP64_QNAN_V0(0),  FP64_RAND_V0(1), FP64_RAND_V0(1), FP64_RAND_V2(0) } }, \
+            { /*src1     */ { FP64_QNAN_MAX(0), FP64_RAND_V1(0), FP64_RAND_V0(0), FP64_RAND_V2(1) } }, \
+            { /* =>      */ { FP64_QNAN_V0(0),  FP64_RAND_V1(0), FP64_RAND_V0(0), FP64_RAND_V2(1) } }, \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                       \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                        \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                        \
+              /*xcpt?    */ false, false },                                                            \
+    /* QNan, SNan (Masked). */                                                                         \
+          { { /*src2     */ { FP64_QNAN(0), FP64_RAND_V1(0), FP64_RAND_V3(1), FP64_RAND_V2(0) } },     \
+            { /*src1     */ { FP64_SNAN(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(0) } },     \
+            { /* =>      */ { FP64_QNAN(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(0) } },     \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                       \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                        \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                        \
+              /*xcpt?    */ false, false },                                                            \
+          { { /*src2     */ { FP64_QNAN_MAX(0), FP64_RAND_V2(1), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, \
+            { /*src1     */ { FP64_SNAN(0),     FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, \
+            { /* =>      */ { FP64_QNAN_MAX(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                       \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                        \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                        \
+              /*xcpt?    */ false, false },                                                            \
+          { { /*src2     */ { FP64_QNAN_V0(0),  FP64_RAND_V1(1), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, \
+            { /*src1     */ { FP64_SNAN_MAX(0), FP64_RAND_V3(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } }, \
+            { /* =>      */ { FP64_QNAN_V0(0),  FP64_RAND_V3(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } }, \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                       \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                        \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                        \
+              /*xcpt?    */ false, false },                                                            \
+    /* SNan, QNan (Masked). */                                                                         \
+          { { /*src2     */ { FP64_SNAN(0), FP64_RAND_V2(1), FP64_RAND_V3(0), FP64_RAND_V1(1) } },     \
+            { /*src1     */ { FP64_QNAN(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } },     \
+            { /* =>      */ { FP64_SNAN(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } },     \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,                                        \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,                         \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,                         \
+              /*xcpt?    */ false, false },                                                            \
+          { { /*src2     */ { FP64_SNAN(0),     FP64_RAND_V1(1), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, \
+            { /*src1     */ { FP64_QNAN_MAX(0), FP64_RAND_V2(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, \
+            { /* =>      */ { FP64_SNAN(0),     FP64_RAND_V2(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                       \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                        \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                        \
+              /*xcpt?    */ false, false },                                                            \
+          { { /*src2     */ { FP64_SNAN_V1(0), FP64_RAND_V1(1), FP64_RAND_V0(1), FP64_RAND_V2(0) } },  \
+            { /*src1     */ { FP64_QNAN_V1(0), FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } },  \
+            { /* =>      */ { FP64_SNAN_V1(0), FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } },  \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                       \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                        \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                        \
+              /*xcpt?    */ false, false },                                                            \
+    /* SNan, SNan (Masked). */                                                                         \
+          { { /*src2     */ { FP64_SNAN(0), FP64_RAND_V1(1), FP64_RAND_V0(1), FP64_RAND_V2(0) } },     \
+            { /*src1     */ { FP64_SNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },     \
+            { /* =>      */ { FP64_SNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },     \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                       \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                        \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                        \
+              /*xcpt?    */ false, false },                                                            \
+          { { /*src2     */ { FP64_SNAN(0),     FP64_RAND_V1(0), FP64_RAND_V0(1), FP64_RAND_V2(1) } }, \
+            { /*src1     */ { FP64_SNAN_MAX(0), FP64_RAND_V0(0), FP64_RAND_V3(0), FP64_RAND_V0(1) } }, \
+            { /* =>      */ { FP64_SNAN(0),     FP64_RAND_V0(0), FP64_RAND_V3(0), FP64_RAND_V0(1) } }, \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                       \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                        \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                        \
+              /*xcpt?    */ false, false },                                                            \
+          { { /*src2     */ { FP64_SNAN_V1(0), FP64_RAND_V1(1), FP64_RAND_V1(1), FP64_RAND_V2(0) } },  \
+            { /*src1     */ { FP64_SNAN_V2(0), FP64_RAND_V2(1), FP64_RAND_V3(1), FP64_RAND_V1(1) } },  \
+            { /* =>      */ { FP64_SNAN_V1(0), FP64_RAND_V2(1), FP64_RAND_V3(1), FP64_RAND_V1(1) } },  \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                       \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                        \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                        \
+              /*xcpt?    */ false, false },                                                            \
+    /* QNan, Normal (Unmasked). */                                                                     \
+          { { /*src2     */ { FP64_QNAN(0), FP64_RAND_V3(1), FP64_RAND_V2(1), FP64_RAND_V2(0) } },     \
+            { /*src1     */ { FP64_1(0),    FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V1(1) } },     \
+            { /* =>      */ { FP64_QNAN(0), FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V1(1) } },     \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                       \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                        \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                        \
+              /*xcpt?    */ false, false },                                                            \
+    /* SNan, Normal (Masked). */                                                                       \
+          { { /*src2     */ { FP64_SNAN(1), FP64_RAND_V0(1), FP64_RAND_V2(1), FP64_RAND_V2(0) } },     \
+            { /*src1     */ { FP64_1(0),    FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V3(1) } },     \
+            { /* =>      */ { FP64_SNAN(1), FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V3(1) } },     \
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                       \
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                        \
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                        \
+              /*xcpt?    */ false, false },                                                            \
+    /* QNan, QNan (Unmasked). */                                                                       \
+    /*0 */{ { /*src2     */ { FP64_QNAN(0), FP64_RAND_V2(0), FP64_RAND_V0(1), FP64_RAND_V1(0) } },     \
+            { /*src1     */ { FP64_QNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },     \
+            { /* =>      */ { FP64_QNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },     \
+              /*mxcsr:in */ 0,                                                                         \
+              /*128:out  */ X86_MXCSR_IE,                                                              \
+              /*256:out  */ X86_MXCSR_IE,                                                              \
+              /*xcpt?    */ true, true },                                                              \
+          { { /*src2     */ { FP64_QNAN_MAX(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(0) } }, \
+            { /*src1     */ { FP64_QNAN(0),     FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V3(1) } }, \
+            { /* =>      */ { FP64_QNAN_MAX(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V3(1) } }, \
+              /*mxcsr:in */ 0,                                                                         \
+              /*128:out  */ X86_MXCSR_IE,                                                              \
+              /*256:out  */ X86_MXCSR_IE,                                                              \
+              /*xcpt?    */ true, true },                                                              \
+          { { /*src2     */ { FP64_QNAN_V0(0),  FP64_RAND_V0(1), FP64_RAND_V0(1), FP64_RAND_V2(0) } }, \
+            { /*src1     */ { FP64_QNAN_MAX(0), FP64_RAND_V1(0), FP64_RAND_V0(0), FP64_RAND_V2(1) } }, \
+            { /* =>      */ { FP64_QNAN_V0(0),  FP64_RAND_V1(0), FP64_RAND_V0(0), FP64_RAND_V2(1) } }, \
+              /*mxcsr:in */ 0,                                                                         \
+              /*128:out  */ X86_MXCSR_IE,                                                              \
+              /*256:out  */ X86_MXCSR_IE,                                                              \
+              /*xcpt?    */ true, true },                                                              \
+    /* QNan, SNan (Unmasked). */                                                                       \
+          { { /*src2     */ { FP64_QNAN(0), FP64_RAND_V1(0), FP64_RAND_V3(1), FP64_RAND_V2(0) } },     \
+            { /*src1     */ { FP64_SNAN(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(0) } },     \
+            { /* =>      */ { FP64_QNAN(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(0) } },     \
+              /*mxcsr:in */ 0,                                                                         \
+              /*128:out  */ X86_MXCSR_IE,                                                              \
+              /*256:out  */ X86_MXCSR_IE,                                                              \
+              /*xcpt?    */ true, true },                                                              \
+          { { /*src2     */ { FP64_QNAN_MAX(0), FP64_RAND_V2(1), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, \
+            { /*src1     */ { FP64_SNAN(0),     FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, \
+            { /* =>      */ { FP64_QNAN_MAX(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, \
+              /*mxcsr:in */ 0,                                                                         \
+              /*128:out  */ X86_MXCSR_IE,                                                              \
+              /*256:out  */ X86_MXCSR_IE,                                                              \
+              /*xcpt?    */ true, true },                                                              \
+          { { /*src2     */ { FP64_QNAN_V0(0),  FP64_RAND_V1(1), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, \
+            { /*src1     */ { FP64_SNAN_MAX(0), FP64_RAND_V3(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } }, \
+            { /* =>      */ { FP64_QNAN_V0(0),  FP64_RAND_V3(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } }, \
+              /*mxcsr:in */ 0,                                                                         \
+              /*128:out  */ X86_MXCSR_IE,                                                              \
+              /*256:out  */ X86_MXCSR_IE,                                                              \
+              /*xcpt?    */ true, true },                                                              \
+    /* SNan, QNan (Unmasked). */                                                                       \
+          { { /*src2     */ { FP64_SNAN(0), FP64_RAND_V2(1), FP64_RAND_V3(0), FP64_RAND_V1(1) } },     \
+            { /*src1     */ { FP64_QNAN(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } },     \
+            { /* =>      */ { FP64_SNAN(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } },     \
+              /*mxcsr:in */ X86_MXCSR_FZ,                                                              \
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_IE,                                               \
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_IE,                                               \
+              /*xcpt?    */ true, true },                                                              \
+          { { /*src2     */ { FP64_SNAN(0),     FP64_RAND_V1(1), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, \
+            { /*src1     */ { FP64_QNAN_MAX(0), FP64_RAND_V2(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, \
+            { /* =>      */ { FP64_SNAN(0),     FP64_RAND_V2(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, \
+              /*mxcsr:in */ 0,                                                                         \
+              /*128:out  */ X86_MXCSR_IE,                                                              \
+              /*256:out  */ X86_MXCSR_IE,                                                              \
+              /*xcpt?    */ true, true },                                                              \
+          { { /*src2     */ { FP64_SNAN_V1(0), FP64_RAND_V1(1), FP64_RAND_V0(1), FP64_RAND_V2(0) } },  \
+            { /*src1     */ { FP64_QNAN_V1(0), FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } },  \
+            { /* =>      */ { FP64_SNAN_V1(0), FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } },  \
+              /*mxcsr:in */ 0,                                                                         \
+              /*128:out  */ X86_MXCSR_IE,                                                              \
+              /*256:out  */ X86_MXCSR_IE,                                                              \
+              /*xcpt?    */ true, true },                                                              \
+    /* SNan, SNan (Unmasked). */                                                                       \
+          { { /*src2     */ { FP64_SNAN(0), FP64_RAND_V1(1), FP64_RAND_V0(1), FP64_RAND_V2(0) } },     \
+            { /*src1     */ { FP64_SNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },     \
+            { /* =>      */ { FP64_SNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },     \
+              /*mxcsr:in */ 0,                                                                         \
+              /*128:out  */ X86_MXCSR_IE,                                                              \
+              /*256:out  */ X86_MXCSR_IE,                                                              \
+              /*xcpt?    */ true, true },                                                              \
+          { { /*src2     */ { FP64_SNAN(0),     FP64_RAND_V1(0), FP64_RAND_V0(1), FP64_RAND_V2(1) } }, \
+            { /*src1     */ { FP64_SNAN_MAX(0), FP64_RAND_V0(0), FP64_RAND_V3(0), FP64_RAND_V0(1) } }, \
+            { /* =>      */ { FP64_SNAN(0),     FP64_RAND_V0(0), FP64_RAND_V3(0), FP64_RAND_V0(1) } }, \
+              /*mxcsr:in */ 0,                                                                         \
+              /*128:out  */ X86_MXCSR_IE,                                                              \
+              /*256:out  */ X86_MXCSR_IE,                                                              \
+              /*xcpt?    */ true, true },                                                              \
+          { { /*src2     */ { FP64_SNAN_V1(0), FP64_RAND_V1(1), FP64_RAND_V1(1), FP64_RAND_V2(0) } },  \
+            { /*src1     */ { FP64_SNAN_V2(0), FP64_RAND_V2(1), FP64_RAND_V3(1), FP64_RAND_V1(1) } },  \
+            { /* =>      */ { FP64_SNAN_V1(0), FP64_RAND_V2(1), FP64_RAND_V3(1), FP64_RAND_V1(1) } },  \
+              /*mxcsr:in */ 0,                                                                         \
+              /*128:out  */ X86_MXCSR_IE,                                                              \
+              /*256:out  */ X86_MXCSR_IE,                                                              \
+              /*xcpt?    */ true, true },                                                              \
+    /* QNan, Normal (Unmasked). */                                                                     \
+          { { /*src2     */ { FP64_QNAN(0), FP64_RAND_V3(1), FP64_RAND_V2(1), FP64_RAND_V2(0) } },     \
+            { /*src1     */ { FP64_1(0),    FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V1(1) } },     \
+            { /* =>      */ { FP64_QNAN(0), FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V1(1) } },     \
+              /*mxcsr:in */ 0,                                                                         \
+              /*128:out  */ X86_MXCSR_IE,                                                              \
+              /*256:out  */ X86_MXCSR_IE,                                                              \
+              /*xcpt?    */ true, true },                                                              \
+    /* SNan, Normal (Masked). */                                                                       \
+          { { /*src2     */ { FP64_SNAN(1), FP64_RAND_V0(1), FP64_RAND_V2(1), FP64_RAND_V2(0) } },     \
+            { /*src1     */ { FP64_1(0),    FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V3(1) } },     \
+            { /* =>      */ { FP64_SNAN(1), FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V3(1) } },     \
+              /*mxcsr:in */ 0,                                                                         \
+              /*128:out  */ X86_MXCSR_IE,                                                              \
+              /*256:out  */ X86_MXCSR_IE,                                                              \
+              /*xcpt?    */ true, true },                                                              \
 
 
@@ -12191,5 +12245,5 @@
               /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
               /*xcpt?    */ false, false },
-          { { /*src2     */ { FP64_NORM_V2(0), FP64_SNAN_V(0, 1), FP64_RAND_V2(0), FP64_RAND_V3(0) } },
+          { { /*src2     */ { FP64_NORM_V2(0), FP64_SNAN(0), FP64_RAND_V2(0), FP64_RAND_V3(0) } },
             { /*src1     */ { FP64_INF(0),     FP64_RAND_V2(0),   FP64_RAND_V1(0), FP64_RAND_V2(1) } },
             { /* =>      */ { FP64_INF(0),     FP64_RAND_V2(0),   FP64_RAND_V1(0), FP64_RAND_V2(1) } },
@@ -12387,5 +12441,5 @@
               /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
               /*xcpt?    */ false, false },
-          { { /*src2     */ { FP64_DENORM_MIN(1), FP64_INF(0),     FP64_QNAN(1),    FP64_SNAN_V(1, 1) } },
+          { { /*src2     */ { FP64_DENORM_MIN(1), FP64_INF(0),     FP64_QNAN(1),    FP64_SNAN(1) } },
             { /*src1     */ { FP64_DENORM_MIN(1), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V0(1)   } },
             { /* =>      */ { FP64_DENORM_MIN(1), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V0(1)   } },
@@ -13749,5 +13803,5 @@
               /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
               /*xcpt?    */ false, false },
-          { { /*src2     */ { FP64_NORM_V2(0), FP64_SNAN_V(0, 1), FP64_RAND_V2(0), FP64_RAND_V3(0) } },
+          { { /*src2     */ { FP64_NORM_V2(0), FP64_SNAN(0), FP64_RAND_V2(0), FP64_RAND_V3(0) } },
             { /*src1     */ { FP64_INF(0),     FP64_RAND_V2(0),   FP64_RAND_V1(0), FP64_RAND_V2(1) } },
             { /* =>      */ { FP64_NORM_V2(0), FP64_RAND_V2(0),   FP64_RAND_V1(0), FP64_RAND_V2(1) } },
@@ -13945,5 +13999,5 @@
               /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
               /*xcpt?    */ false, false },
-          { { /*src2     */ { FP64_DENORM_MIN(1), FP64_INF(0),     FP64_QNAN(1),    FP64_SNAN_V(1, 1) } },
+          { { /*src2     */ { FP64_DENORM_MIN(1), FP64_INF(0),     FP64_QNAN(1),    FP64_SNAN(1) } },
             { /*src1     */ { FP64_DENORM_MIN(1), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V0(1)   } },
             { /* =>      */ { FP64_DENORM_MIN(1), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V0(1)   } },
