Changeset 106220 in vbox for trunk/src/VBox/ValidationKit/bootsectors
- Timestamp:
- Oct 4, 2024 12:36:25 PM (8 weeks ago)
- File:
-
- 1 edited
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trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32
r106216 r106220 848 848 **/ 849 849 #define FP32_TABLE_D1_SS_INVALIDS \ 850 /* QNan, QNan (Masked). */\850 /* QNan, QNan */ \ 851 851 /* 0*/{ { /*src2 */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \ 852 { /*src1 */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } }, \853 { /* => */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } }, \854 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \855 /*128:out */ X86_MXCSR_XCPT_MASK, \856 /*256:out */ X86_MXCSR_XCPT_MASK, \857 /*xcpt? */ false, false }, \858 { { /*src2 */ { FP32_QNAN_MAX(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0) } }, \859 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0), FP32_QNAN_V1(0) } }, \860 { /* => */ { FP32_QNAN(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0), FP32_QNAN_V1(0) } }, \861 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \862 /*128:out */ X86_MXCSR_XCPT_MASK, \863 /*256:out */ X86_MXCSR_XCPT_MASK, \864 /*xcpt? */ false, false }, \865 { { /*src2 */ { FP32_QNAN_V1(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0) } }, \866 { /*src1 */ { FP32_QNAN_V2(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0), FP32_QNAN_V1(0) } }, \867 { /* => */ { FP32_QNAN_V2(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0), FP32_QNAN_V1(0) } }, \868 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \869 /*128:out */ X86_MXCSR_XCPT_MASK, \870 /*256:out */ X86_MXCSR_XCPT_MASK, \871 /*xcpt? */ false, false }, \872 /* QNan, SNan (Masked). */ \873 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0) } }, \874 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V2(0), FP32_SNAN_V6(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V4(0), FP32_SNAN_V1(0) } }, \875 { /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_V2(0), FP32_SNAN_V6(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V4(0), FP32_QNAN_V1(0) } }, \876 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \877 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \878 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \879 /*xcpt? */ false, false }, \880 { { /*src2 */ { FP32_QNAN_MAX(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \881 { /*src1 */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_MAX(0), FP32_SNAN_V2(0), FP32_SNAN_V6(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V4(0) } }, \882 { /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN(0), FP32_SNAN_MAX(0), FP32_SNAN_V2(0), FP32_SNAN_V6(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V4(0) } }, \883 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \884 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \885 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \886 /*xcpt? */ false, false }, \887 { { /*src2 */ { FP32_QNAN_V1(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \888 { /*src1 */ { FP32_SNAN_V2(0), FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } }, \889 { /* => */ { FP32_QNAN_V2(0), FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } }, \890 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \891 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \892 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \893 /*xcpt? */ false, false }, \894 /* SNan, QNan (Masked). */ \895 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_V1(0), FP32_SNAN_V1(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V5(0), FP32_SNAN_V6(0) } }, \896 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } }, \897 { /* => */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } }, \898 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \899 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \900 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \901 /*xcpt? */ false, false }, \902 { { /*src2 */ { FP32_SNAN_MAX(0), FP32_SNAN_MAX(0), FP32_SNAN_V1(0), FP32_SNAN_V1(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V5(0), FP32_SNAN_V6(0) } }, \903 { /*src1 */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } }, \904 { /* => */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } }, \905 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \906 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \907 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \908 /*xcpt? */ false, false }, \909 { { /*src2 */ { FP32_SNAN_V0(0), FP32_SNAN_MAX(0), FP32_SNAN_V1(0), FP32_SNAN_V1(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V5(0), FP32_SNAN_V6(0) } }, \910 { /*src1 */ { FP32_QNAN_V6(0), FP32_QNAN(0), FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } }, \911 { /* => */ { FP32_QNAN_V6(0), FP32_QNAN(0), FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } }, \912 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \913 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \914 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \915 /*xcpt? */ false, false }, \916 /* SNan, SNan (Masked). */ \917 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V7(0), FP32_SNAN_V1(0), FP32_SNAN_V6(0), FP32_SNAN_V1(0) } }, \918 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_MAX(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } }, \919 { /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_MAX(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } }, \920 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \921 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \922 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \923 /*xcpt? */ false, false }, \924 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V7(0), FP32_SNAN_V1(0), FP32_SNAN_V6(0), FP32_SNAN_V1(0) } }, \925 { /*src1 */ { FP32_SNAN_MAX(0), FP32_SNAN_V0(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } }, \926 { /* => */ { FP32_QNAN_MAX(0), FP32_SNAN_V0(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } }, \927 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \928 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \929 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \930 /*xcpt? */ false, false }, \931 { { /*src2 */ { FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V7(0), FP32_SNAN_V1(0), FP32_SNAN_V6(0), FP32_SNAN_V1(0) } }, \932 { /*src1 */ { FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V0(0) } }, \933 { /* => */ { FP32_QNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V0(0) } }, \934 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \935 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \936 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \937 /*xcpt? */ false, false }, \938 /* QNan, Norm FP (Masked). */ \939 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_MAX(1), FP32_NORM_V0(1), FP32_QNAN_V1(0), FP32_NORM_V3(0), FP32_QNAN_V3(1), FP32_NORM_V5(0), FP32_QNAN_V5(1) } }, \940 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V0(1), FP32_NORM_V2(1), FP32_QNAN_V2(0), FP32_NORM_V4(0), FP32_QNAN_V4(1), FP32_NORM_V6(1) } }, \941 { /* => */ { FP32_QNAN(0), FP32_1(1), FP32_QNAN_V0(1), FP32_NORM_V2(1), FP32_QNAN_V2(0), FP32_NORM_V4(0), FP32_QNAN_V4(1), FP32_NORM_V6(1) } }, \942 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \943 /*128:out */ X86_MXCSR_XCPT_MASK, \944 /*256:out */ X86_MXCSR_XCPT_MASK, \945 /*xcpt? */ false, false }, \946 /* SNan, Norm FP (Masked). */ \947 { { /*src2 */ { FP32_SNAN(1), FP32_SNAN_MAX(1), FP32_NORM_V0(1), FP32_SNAN_V1(0), FP32_NORM_V3(0), FP32_SNAN_V3(1), FP32_NORM_V5(0), FP32_SNAN_V5(1) } }, \948 { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V0(1), FP32_NORM_V2(1), FP32_SNAN_V2(1), FP32_NORM_V4(0), FP32_SNAN_V4(1), FP32_NORM_V6(1) } }, \949 { /* => */ { FP32_QNAN_V(1, 1), FP32_1(0), FP32_SNAN_V0(1), FP32_NORM_V2(1), FP32_SNAN_V2(1), FP32_NORM_V4(0), FP32_SNAN_V4(1), FP32_NORM_V6(1) } }, \950 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \951 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \952 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \953 /*xcpt? */ false, false }, \954 /* QNan, QNan (Unmasked). */ \955 /*14*/{ { /*src2 */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \956 852 { /*src1 */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } }, \ 957 853 { /* => */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } }, \ 958 854 /*mxcsr:in */ 0, \ 959 855 /*128:out */ 0, \ 960 /*256:out */ 0,\856 /*256:out */ -1, \ 961 857 /*xcpt? */ false, false }, \ 962 858 { { /*src2 */ { FP32_QNAN_MAX(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0) } }, \ … … 965 861 /*mxcsr:in */ 0, \ 966 862 /*128:out */ 0, \ 967 /*256:out */ 0,\863 /*256:out */ -1, \ 968 864 /*xcpt? */ false, false }, \ 969 865 { { /*src2 */ { FP32_QNAN_V1(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0) } }, \ … … 972 868 /*mxcsr:in */ 0, \ 973 869 /*128:out */ 0, \ 974 /*256:out */ 0,\870 /*256:out */ -1, \ 975 871 /*xcpt? */ false, false }, \ 976 \ 977 /* QNan, SNan (Unmasked). */ \ 872 /* QNan, SNan */ \ 978 873 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0) } }, \ 979 874 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_V2(0), FP32_SNAN_V6(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V4(0), FP32_SNAN_V1(0) } }, \ 980 { /* => */ { FP32_QNAN_V(0, 1), FP32_ QNAN_V2(0), FP32_SNAN_V6(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V4(0), FP32_QNAN_V1(0) } }, \875 { /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_V2(0), FP32_SNAN_V6(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V4(0), FP32_QNAN_V1(0) } }, \ 981 876 /*mxcsr:in */ 0, \ 982 877 /*128:out */ X86_MXCSR_IE, \ 983 /*256:out */ X86_MXCSR_IE,\878 /*256:out */ -1, \ 984 879 /*xcpt? */ true, true }, \ 985 880 { { /*src2 */ { FP32_QNAN_MAX(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \ … … 988 883 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, \ 989 884 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, \ 990 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,\885 /*256:out */ -1, \ 991 886 /*xcpt? */ true, true }, \ 992 887 { { /*src2 */ { FP32_QNAN_V1(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \ 993 888 { /*src1 */ { FP32_SNAN_V2(0), FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } }, \ 994 { /* => */ { FP32_ SNAN_V2(0), FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } }, \889 { /* => */ { FP32_QNAN_V2(0), FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } }, \ 995 890 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, \ 996 891 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, \ 997 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,\892 /*256:out */ -1, \ 998 893 /*xcpt? */ true, true }, \ 999 /* SNan, QNan (Unmasked). */\894 /* SNan, QNan */ \ 1000 895 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_V1(0), FP32_SNAN_V1(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V5(0), FP32_SNAN_V6(0) } }, \ 1001 896 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } }, \ … … 1003 898 /*mxcsr:in */ X86_MXCSR_DAZ, \ 1004 899 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_IE, \ 1005 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_IE,\900 /*256:out */ -1, \ 1006 901 /*xcpt? */ true, true }, \ 1007 902 { { /*src2 */ { FP32_SNAN_MAX(0), FP32_SNAN_MAX(0), FP32_SNAN_V1(0), FP32_SNAN_V1(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V5(0), FP32_SNAN_V6(0) } }, \ … … 1010 905 /*mxcsr:in */ X86_MXCSR_RC_UP, \ 1011 906 /*128:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, \ 1012 /*256:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE,\907 /*256:out */ -1, \ 1013 908 /*xcpt? */ true, true }, \ 1014 909 { { /*src2 */ { FP32_SNAN_V0(0), FP32_SNAN_MAX(0), FP32_SNAN_V1(0), FP32_SNAN_V1(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V5(0), FP32_SNAN_V6(0) } }, \ … … 1017 912 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, \ 1018 913 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, \ 1019 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,\914 /*256:out */ -1, \ 1020 915 /*xcpt? */ true, true }, \ 1021 /* SNan, SNan (Unmasked). */\1022 /*24*/{ { /*src2 */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V7(0), FP32_SNAN_V1(0), FP32_SNAN_V6(0), FP32_SNAN_V1(0) } }, \916 /* SNan, SNan */ \ 917 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V7(0), FP32_SNAN_V1(0), FP32_SNAN_V6(0), FP32_SNAN_V1(0) } }, \ 1023 918 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_MAX(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } }, \ 1024 919 { /* => */ { FP32_QNAN_V(0, 1), FP32_SNAN_MAX(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } }, \ 1025 920 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, \ 1026 921 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE, \ 1027 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE,\922 /*256:out */ -1, \ 1028 923 /*xcpt? */ true, true }, \ 1029 924 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V7(0), FP32_SNAN_V1(0), FP32_SNAN_V6(0), FP32_SNAN_V1(0) } }, \ 1030 925 { /*src1 */ { FP32_SNAN_MAX(0), FP32_SNAN_V0(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } }, \ 1031 { /* => */ { FP32_ SNAN_MAX(0), FP32_SNAN_V0(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } }, \926 { /* => */ { FP32_QNAN_MAX(0), FP32_SNAN_V0(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } }, \ 1032 927 /*mxcsr:in */ X86_MXCSR_RC_ZERO, \ 1033 928 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE, \ 1034 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE,\929 /*256:out */ -1, \ 1035 930 /*xcpt? */ true, true }, \ 1036 931 { { /*src2 */ { FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V7(0), FP32_SNAN_V1(0), FP32_SNAN_V6(0), FP32_SNAN_V1(0) } }, \ … … 1039 934 /*mxcsr:in */ 0, \ 1040 935 /*128:out */ X86_MXCSR_IE, \ 1041 /*256:out */ X86_MXCSR_IE,\936 /*256:out */ -1, \ 1042 937 /*xcpt? */ true, true }, \ 1043 /* QNan, Norm FP (Unmasked). */\938 /* QNan, Norm FP */ \ 1044 939 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_MAX(1), FP32_NORM_V0(1), FP32_QNAN_V1(0), FP32_NORM_V3(0), FP32_QNAN_V3(1), FP32_NORM_V5(0), FP32_QNAN_V5(1) } }, \ 1045 940 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V0(1), FP32_NORM_V2(1), FP32_QNAN_V2(0), FP32_NORM_V4(0), FP32_QNAN_V4(1), FP32_NORM_V6(1) } }, \ … … 1047 942 /*mxcsr:in */ X86_MXCSR_FZ, \ 1048 943 /*128:out */ X86_MXCSR_FZ, \ 1049 /*256:out */ X86_MXCSR_FZ,\944 /*256:out */ -1, \ 1050 945 /*xcpt? */ false, false }, \ 1051 /* SNan, Norm FP (Unmasked). */\1052 /* 28*/{ { /*src2 */ { FP32_SNAN(1), FP32_SNAN_MAX(1), FP32_NORM_V0(1), FP32_SNAN_V1(0), FP32_NORM_V3(0), FP32_SNAN_V3(1), FP32_NORM_V5(0), FP32_SNAN_V5(1) } }, \946 /* SNan, Norm FP */ \ 947 /*13*/{ { /*src2 */ { FP32_SNAN(1), FP32_SNAN_MAX(1), FP32_NORM_V0(1), FP32_SNAN_V1(0), FP32_NORM_V3(0), FP32_SNAN_V3(1), FP32_NORM_V5(0), FP32_SNAN_V5(1) } }, \ 1053 948 { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V0(1), FP32_NORM_V2(1), FP32_SNAN_V2(1), FP32_NORM_V4(0), FP32_SNAN_V4(1), FP32_NORM_V6(1) } }, \ 1054 949 { /* => */ { FP32_QNAN_V(1, 1), FP32_1(0), FP32_SNAN_V0(1), FP32_NORM_V2(1), FP32_SNAN_V2(1), FP32_NORM_V4(0), FP32_SNAN_V4(1), FP32_NORM_V6(1) } }, \ 1055 950 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, \ 1056 951 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, \ 1057 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,\952 /*256:out */ -1, \ 1058 953 /*xcpt? */ true, true }, \ 1059 954 … … 4317 4212 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 4318 4213 /*128:out */ X86_MXCSR_XCPT_MASK, 4319 /*256:out */ X86_MXCSR_XCPT_MASK,4214 /*256:out */ -1, 4320 4215 /*xcpt? */ false, false }, 4321 4216 { { /*src2 */ { FP32_0(0), FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, … … 4324 4219 /*mxcsr:in */ 0, 4325 4220 /*128:out */ 0, 4326 /*256:out */ 0,4221 /*256:out */ -1, 4327 4222 /*xcpt? */ false, false }, 4328 4223 { { /*src2 */ { FP32_0(0), FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, … … 4331 4226 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 4332 4227 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 4333 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,4228 /*256:out */ -1, 4334 4229 /*xcpt? */ false, false }, 4335 4230 { { /*src2 */ { FP32_0(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, … … 4338 4233 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 4339 4234 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 4340 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,4235 /*256:out */ -1, 4341 4236 /*xcpt? */ false, false }, 4342 4237 { { /*src2 */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, … … 4345 4240 /*mxcsr:in */ X86_MXCSR_FZ, 4346 4241 /*128:out */ X86_MXCSR_FZ, 4347 /*256:out */ X86_MXCSR_FZ,4242 /*256:out */ -1, 4348 4243 /*xcpt? */ false, false }, 4349 4244 { { /*src2 */ { FP32_0(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, … … 4352 4247 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN, 4353 4248 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN, 4354 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN,4249 /*256:out */ -1, 4355 4250 /*xcpt? */ false, false }, 4356 4251 /* … … 4359 4254 /* 6*/{ { /*src2 */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 4360 4255 { /*src1 */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 4361 { /* => */ { FP32_ 0(0),FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },4256 { /* => */ { FP32_QNAN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 4362 4257 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM, 4363 4258 /*128:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_IE, 4364 /*256:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_IE,4259 /*256:out */ -1, 4365 4260 /*xcpt? */ true, true }, 4366 4261 { { /*src2 */ { FP32_INF(0), FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, 4367 4262 { /*src1 */ { FP32_INF(1), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, 4368 { /* => */ { FP32_ 0(0),FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },4263 { /* => */ { FP32_QNAN(1), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, 4369 4264 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO, 4370 4265 /*128:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 4371 /*256:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,4266 /*256:out */ -1, 4372 4267 /*xcpt? */ true, true }, 4373 4268 { { /*src2 */ { FP32_INF(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, … … 4376 4271 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 4377 4272 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, 4378 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,4273 /*256:out */ -1, 4379 4274 /*xcpt? */ false, false }, 4380 4275 { { /*src2 */ { FP32_INF(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, … … 4383 4278 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, 4384 4279 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, 4385 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,4280 /*256:out */ -1, 4386 4281 /*xcpt? */ false, false }, 4387 4282 { { /*src2 */ { FP32_INF(0), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } }, 4388 4283 { /*src1 */ { FP32_INF(1), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } }, 4389 { /* => */ { FP32_QNAN( 0), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },4284 { /* => */ { FP32_QNAN(1), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } }, 4390 4285 /*mxcsr:in */ X86_MXCSR_FZ, 4391 4286 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_IE, 4392 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_IE,4287 /*256:out */ -1, 4393 4288 /*xcpt? */ true, true }, 4394 4289 { { /*src2 */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V6(1) } }, … … 4397 4292 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 4398 4293 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 4399 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,4294 /*256:out */ -1, 4400 4295 /*xcpt? */ true, true }, 4401 4296 /* … … 4406 4301 { /* => */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1) } }, 4407 4302 /*mxcsr:in */ 0, 4408 /*128:out */ X86_MXCSR_OE, 4409 /*256:out */ X86_MXCSR_OE, 4303 /*128:out */ X86_MXCSR_OE | BS3_MXCSR_OM_FIXED, 4304 /*256:out */ -1, 4305 /*xcpt? */ true, true }, 4306 { { /*src2 */ { FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V6(1) } }, 4307 { /*src1 */ { FP32_NORM_MAX(1), FP32_0(1), FP32_0(1), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1) } }, 4308 { /* => */ { FP32_INF(1), FP32_0(1), FP32_0(1), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1) } }, 4309 /*mxcsr:in */ X86_MXCSR_OM, 4310 /*128:out */ X86_MXCSR_OM | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_OM_FIXED, 4311 /*256:out */ -1, 4410 4312 /*xcpt? */ true, true }, 4411 4313 { { /*src2 */ { FP32_NORM_MAX(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, 4412 4314 { /*src1 */ { FP32_NORM_MAX(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, 4413 4315 { /* => */ { FP32_INF(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, 4414 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM, 4415 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, 4416 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, 4316 /*mxcsr:in */ 0, 4317 /*128:out */ X86_MXCSR_OE | BS3_MXCSR_OM_FIXED, 4318 /*256:out */ -1, 4319 /*xcpt? */ false, false }, 4320 { { /*src2 */ { FP32_NORM_MAX(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, 4321 { /*src1 */ { FP32_NORM_MAX(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, 4322 { /* => */ { FP32_INF(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, 4323 /*mxcsr:in */ X86_MXCSR_OM, 4324 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PE | X86_MXCSR_OE | BS3_MXCSR_OM_FIXED, 4325 /*256:out */ -1, 4417 4326 /*xcpt? */ false, false }, 4418 4327 { { /*src2 */ { FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } }, … … 4421 4330 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM, 4422 4331 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_PE, 4423 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_PE,4332 /*256:out */ -1, 4424 4333 /*xcpt? */ false, false }, 4425 4334 { { /*src2 */ { FP32_NORM_MAX(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, 4426 4335 { /*src1 */ { FP32_NORM_MAX(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, 4427 4336 { /* => */ { FP32_INF(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, 4428 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM, 4429 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, 4430 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, 4337 /*mxcsr:in */ 0, 4338 /*128:out */ X86_MXCSR_OE | BS3_MXCSR_OM_FIXED, 4339 /*256:out */ -1, 4340 /*xcpt? */ false, false }, 4341 { { /*src2 */ { FP32_NORM_MAX(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, 4342 { /*src1 */ { FP32_NORM_MAX(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, 4343 { /* => */ { FP32_INF(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, 4344 /*mxcsr:in */ X86_MXCSR_OM, 4345 /*128:out */ X86_MXCSR_OM | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_OM_FIXED, 4346 /*256:out */ -1, 4431 4347 /*xcpt? */ false, false }, 4432 4348 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_V5(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V3(1), FP32_RAND_V2(1) } }, … … 4435 4351 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 4436 4352 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, 4437 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,4353 /*256:out */ -1, 4438 4354 /*xcpt? */ true, true }, 4439 4355 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, … … 4442 4358 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 4443 4359 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, 4444 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,4360 /*256:out */ -1, 4445 4361 /*xcpt? */ true, true }, 4446 4362 /* 4447 4363 * Normals. 4448 4364 */ 4449 /* 18*/{ { /*src2 */ { FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },4365 /*21*/{ { /*src2 */ { FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, 4450 4366 { /*src1 */ { FP32_V(1, 0, 0x7d)/*-0.25*/, FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V0(0), FP32_RAND_V5(1) } }, 4451 4367 { /* => */ { FP32_V(0, 0x400000, 0x7f)/* 1.50*/, FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V0(0), FP32_RAND_V5(1) } }, 4452 4368 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 4453 4369 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 4454 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,4370 /*256:out */ -1, 4455 4371 /*xcpt? */ false, false }, 4456 4372 { { /*src2 */ { FP32_NORM_MAX(0), FP32_RAND_V5(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V3(1), FP32_RAND_V2(1) } }, … … 4459 4375 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 4460 4376 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 4461 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,4377 /*256:out */ -1, 4462 4378 /*xcpt? */ false, false }, 4463 4379 { { /*src2 */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, … … 4466 4382 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 4467 4383 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 4468 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,4384 /*256:out */ -1, 4469 4385 /*xcpt? */ false, false }, 4470 4386 { { /*src2 */ { FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, … … 4473 4389 /*mxcsr:in */ 0, 4474 4390 /*128:out */ 0, 4475 /*256:out */ 0,4391 /*256:out */ -1, 4476 4392 /*xcpt? */ false, false }, 4477 4393 { { /*src2 */ { FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } }, … … 4480 4396 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 4481 4397 /*128:out */ X86_MXCSR_RC_ZERO, 4482 /*256:out */ X86_MXCSR_RC_ZERO,4398 /*256:out */ -1, 4483 4399 /*xcpt? */ false, false }, 4484 4400 { { /*src2 */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } }, … … 4487 4403 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 4488 4404 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 4489 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,4405 /*256:out */ -1, 4490 4406 /*xcpt? */ false, false }, 4491 4407 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } }, … … 4494 4410 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 4495 4411 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 4496 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,4412 /*256:out */ -1, 4497 4413 /*xcpt? */ false, false }, 4498 4414 { { /*src2 */ { FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } }, … … 4501 4417 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 4502 4418 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 4503 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,4419 /*256:out */ -1, 4504 4420 /*xcpt? */ false, false }, 4505 4421 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V0(1), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V6(1) } }, … … 4508 4424 /*mxcsr:in */ X86_MXCSR_FZ, 4509 4425 /*128:out */ X86_MXCSR_FZ, 4510 /*256:out */ X86_MXCSR_FZ,4426 /*256:out */ -1, 4511 4427 /*xcpt? */ false, false }, 4512 4428 /* 4513 4429 * Denormals. 4514 4430 */ 4515 /* 27*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(0) } },4431 /*30*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(0) } }, 4516 4432 { /*src1 */ { FP32_0(0), FP32_RAND_V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0) } }, 4517 4433 { /* => */ { FP32_0(0), FP32_RAND_V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0) } }, 4518 /*mxcsr:in */ X86_MXCSR_DE, 4519 /*128:out */ X86_MXCSR_DE, 4520 /*256:out */ X86_MXCSR_DE, 4434 /*mxcsr:in */ 0, 4435 /*128:out */ X86_MXCSR_DE | BS3_MXCSR_DM_FIXED, 4436 /*256:out */ -1, 4437 /*xcpt? */ true, true }, 4438 #ifdef TODO_X86_MXCSR_UE_IEM /** @todo THIS FAILS ON IEM: X86_MXCSR_UE not set in 128:out *AND* different output values */ 4439 /*--|31*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(0) } }, 4440 { /*src1 */ { FP32_0(0), FP32_RAND_V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0) } }, 4441 { /* => */ { FP32_0(0), FP32_RAND_V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0) } } /* result on HW (i7-10700) */, 4442 // IEM: { /* => */ { FP32_DENORM_MAX(0), FP32_RAND_V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0) } } /* result on IEM */, 4443 /*mxcsr:in */ X86_MXCSR_DM, 4444 /*128:out */ X86_MXCSR_DM | X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 4445 /*256:out */ -1, 4446 /*xcpt? */ true, true }, 4447 #endif /* TODO_X86_MXCSR_UE_IEM */ 4448 /*31|32*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(0) } }, 4449 { /*src1 */ { FP32_0(0), FP32_RAND_V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0) } }, 4450 { /* => */ { FP32_DENORM_MAX(0), FP32_RAND_V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0) } }, 4451 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_UM, 4452 /*128:out */ X86_MXCSR_DM | X86_MXCSR_UM | X86_MXCSR_DE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 4453 /*256:out */ -1, 4521 4454 /*xcpt? */ true, true }, 4522 4455 { { /*src2 */ { FP32_0(0), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V6(1) } }, 4523 4456 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1) } }, 4524 4457 { /* => */ { FP32_0(0), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1) } }, 4525 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 4526 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 4527 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 4458 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 4459 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED, 4460 /*256:out */ -1, 4461 /*xcpt? */ false, false }, 4462 { { /*src2 */ { FP32_0(0), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V6(1) } }, 4463 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1) } }, 4464 { /* => */ { FP32_0(0), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1) } }, 4465 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 4466 /*128:out */ X86_MXCSR_DM | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 4467 /*256:out */ -1, 4468 /*xcpt? */ false, false }, 4469 { { /*src2 */ { FP32_0(0), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V6(1) } }, 4470 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1) } }, 4471 { /* => */ { FP32_0(0), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1) } }, 4472 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_UM | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 4473 /*128:out */ X86_MXCSR_DM | X86_MXCSR_UM | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 4474 /*256:out */ -1, 4528 4475 /*xcpt? */ false, false }, 4529 4476 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V7(0) } }, 4530 4477 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_V3(1), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V6(1) } }, 4531 { /* => */ { FP32_ 0(0),FP32_RAND_V3(1), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V6(1) } },4478 { /* => */ { FP32_NORM_MIN(0), FP32_RAND_V3(1), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V6(1) } }, 4532 4479 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_DE, 4533 4480 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_DE, 4534 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_DE,4481 /*256:out */ -1, 4535 4482 /*xcpt? */ true, true }, 4536 4483 /** @todo More denormals etc. */ … … 4538 4485 * Invalids. 4539 4486 */ 4540 /*30*/ FP32_TABLE_D1_SS_INVALIDS4487 /*36|37*/ FP32_TABLE_D1_SS_INVALIDS 4541 4488 /** @todo Underflow; Precision; Rounding; FZ etc. */ 4542 4489 }; … … 4577 4524 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 4578 4525 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode); 4579 return bs3CpuInstr4_WorkerTestType1 (bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,4526 return bs3CpuInstr4_WorkerTestType1A(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 4580 4527 g_aXcptConfig3, RT_ELEMENTS(g_aXcptConfig3)); 4581 4528 } … … 5487 5434 /*--|30*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 5488 5435 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0) } }, 5489 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } } , /* result on HW (i7-10700) */5490 // IEM: { /* => */ { FP64_0(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_0(0) } } , /* result on IEM */5436 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } } /* result on HW (i7-10700) */, 5437 // IEM: { /* => */ { FP64_0(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_0(0) } } /* result on IEM */, 5491 5438 /*mxcsr:in */ X86_MXCSR_DM, 5492 5439 /*128:out */ X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, … … 6257 6204 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 6258 6205 /*128:out */ X86_MXCSR_XCPT_MASK, 6259 /*256:out */ X86_MXCSR_XCPT_MASK,6206 /*256:out */ -1, 6260 6207 /*xcpt? */ false, false }, 6261 6208 { { /*src2 */ { FP32_0(0), FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, … … 6264 6211 /*mxcsr:in */ 0, 6265 6212 /*128:out */ 0, 6266 /*256:out */ 0,6213 /*256:out */ -1, 6267 6214 /*xcpt? */ false, false }, 6268 6215 { { /*src2 */ { FP32_0(0), FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, … … 6271 6218 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 6272 6219 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 6273 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,6220 /*256:out */ -1, 6274 6221 /*xcpt? */ false, false }, 6275 6222 { { /*src2 */ { FP32_0(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, … … 6278 6225 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 6279 6226 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 6280 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,6227 /*256:out */ -1, 6281 6228 /*xcpt? */ false, false }, 6282 6229 { { /*src2 */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, … … 6285 6232 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 6286 6233 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 6287 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,6234 /*256:out */ -1, 6288 6235 /*xcpt? */ false, false }, 6289 6236 { { /*src2 */ { FP32_0(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, … … 6292 6239 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 6293 6240 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 6294 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,6241 /*256:out */ -1, 6295 6242 /*xcpt? */ false, false }, 6296 6243 /* … … 6302 6249 /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM, 6303 6250 /*128:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM, 6304 /*256:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,6305 /*xcpt? */ false, false }, 6306 { { /*src2 */ { FP32_INF(0), FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },6307 { /*src1 */ { FP32_INF(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },6308 { /* => */ { FP32_ INF(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },6251 /*256:out */ -1, 6252 /*xcpt? */ false, false }, 6253 { { /*src2 */ { FP32_INF(0), FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, 6254 { /*src1 */ { FP32_INF(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, 6255 { /* => */ { FP32_QNAN(1), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, 6309 6256 /*mxcsr:in */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM), 6310 6257 /*128:out */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_IE, 6311 /*256:out */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_IE,6258 /*256:out */ -1, 6312 6259 /*xcpt? */ true, true }, 6313 6260 { { /*src2 */ { FP32_INF(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, … … 6316 6263 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 6317 6264 /*128:out */ X86_MXCSR_XCPT_MASK, 6318 /*256:out */ X86_MXCSR_XCPT_MASK,6265 /*256:out */ -1, 6319 6266 /*xcpt? */ false, false }, 6320 6267 { { /*src2 */ { FP32_INF(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, … … 6323 6270 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, 6324 6271 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, 6325 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,6272 /*256:out */ -1, 6326 6273 /*xcpt? */ false, false }, 6327 6274 { { /*src2 */ { FP32_INF(0), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } }, … … 6330 6277 /*mxcsr:in */ X86_MXCSR_FZ, 6331 6278 /*128:out */ X86_MXCSR_FZ, 6332 /*256:out */ X86_MXCSR_FZ,6279 /*256:out */ -1, 6333 6280 /*xcpt? */ false, false }, 6334 6281 { { /*src2 */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V6(1) } }, … … 6337 6284 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 6338 6285 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 6339 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,6286 /*256:out */ -1, 6340 6287 /*xcpt? */ false, false }, 6341 6288 /* … … 6347 6294 /*mxcsr:in */ 0, 6348 6295 /*128:out */ 0, 6349 /*256:out */ X86_MXCSR_PE,6296 /*256:out */ -1, 6350 6297 /*xcpt? */ false, true }, 6351 6298 { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_MAX(0) } }, 6352 6299 { /*src1 */ { FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_MAX(0) } }, 6353 6300 { /* => */ { FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0) } }, 6354 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO, 6355 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, 6356 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, 6301 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 6302 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | BS3_MXCSR_OM_FIXED, 6303 /*256:out */ -1, 6304 /*xcpt? */ false, false }, 6305 { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_MAX(0) } }, 6306 { /*src1 */ { FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_MAX(0) } }, 6307 { /* => */ { FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0) } }, 6308 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_RC_ZERO, 6309 /*128:out */ X86_MXCSR_OM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_OM_FIXED, 6310 /*256:out */ -1, 6357 6311 /*xcpt? */ false, false }, 6358 6312 { { /*src2 */ { FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0) } }, 6359 6313 { /*src1 */ { FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1) } }, 6360 6314 { /* => */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1) } }, 6361 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM, 6362 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, 6363 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, 6315 /*mxcsr:in */ 0, 6316 /*128:out */ X86_MXCSR_OE | BS3_MXCSR_OM_FIXED, 6317 /*256:out */ -1, 6318 /*xcpt? */ false, false }, 6319 { { /*src2 */ { FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0) } }, 6320 { /*src1 */ { FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1) } }, 6321 { /* => */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1) } }, 6322 /*mxcsr:in */ X86_MXCSR_OM, 6323 /*128:out */ X86_MXCSR_OM | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_OM_FIXED, 6324 /*256:out */ -1, 6364 6325 /*xcpt? */ false, false }, 6365 6326 { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 6366 6327 { /*src1 */ { FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 6367 6328 { /* => */ { FP32_INF(1), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 6368 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM, 6369 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, 6370 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, 6329 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 6330 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OE | BS3_MXCSR_OM_FIXED, 6331 /*256:out */ -1, 6332 /*xcpt? */ false, false }, 6333 { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 6334 { /*src1 */ { FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 6335 { /* => */ { FP32_INF(1), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 6336 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM, 6337 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_OM_FIXED, 6338 /*256:out */ -1, 6371 6339 /*xcpt? */ false, false }, 6372 6340 { { /*src2 */ { FP32_NORM_MIN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, … … 6375 6343 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM, 6376 6344 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_PE, 6377 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,6345 /*256:out */ -1, 6378 6346 /*xcpt? */ false, false }, 6379 6347 { { /*src2 */ { FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 6380 6348 { /*src1 */ { FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 6381 6349 { /* => */ { FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 6382 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,6383 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,6384 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,6385 /*xcpt? */ false, false }, 6386 { { /*src2 */ { FP32_NORM_M IN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },6350 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 6351 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | BS3_MXCSR_OM_FIXED, 6352 /*256:out */ -1, 6353 /*xcpt? */ false, false }, 6354 { { /*src2 */ { FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 6387 6355 { /*src1 */ { FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 6388 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 6356 { /* => */ { FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 6357 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_RC_ZERO, 6358 /*128:out */ X86_MXCSR_OM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_OM_FIXED, 6359 /*256:out */ -1, 6360 /*xcpt? */ false, false }, 6361 { { /*src2 */ { FP32_NORM_MIN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 6362 { /*src1 */ { FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 6363 { /* => */ { FP32_V(1, FP32_FRAC_NORM_MAX - 1, FP32_EXP_NORM_MAX), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 6389 6364 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 6390 6365 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, 6391 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,6392 /*xcpt? */ true, true }, 6393 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },6394 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },6395 { /* => */ { FP32_ 0(0),FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },6366 /*256:out */ -1, 6367 /*xcpt? */ true, true }, 6368 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 6369 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 6370 { /* => */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 6396 6371 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 6397 6372 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, 6398 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,6399 /*xcpt? */ true, true }, 6400 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },6401 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },6402 { /* => */ { FP32_ 0(1),FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },6373 /*256:out */ -1, 6374 /*xcpt? */ true, true }, 6375 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 6376 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 6377 { /* => */ { FP32_V(1, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 6403 6378 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 6404 6379 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, 6405 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,6380 /*256:out */ -1, 6406 6381 /*xcpt? */ true, true }, 6407 6382 /* 6408 6383 * Normals. 6409 6384 */ 6410 /*2 1*/{ { /*src2 */ { FP32_V(0, 0x600000, 0x7f)/*1.75*/, FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },6385 /*25*/{ { /*src2 */ { FP32_V(0, 0x600000, 0x7f)/*1.75*/, FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, 6411 6386 { /*src1 */ { FP32_V(0, 0, 0x7d)/*0.25*/, FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V0(0), FP32_RAND_V5(1) } }, 6412 6387 { /* => */ { FP32_V(1, 0x400000, 0x7f)/*1.50*/, FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V0(0), FP32_RAND_V5(1) } }, 6413 6388 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 6414 6389 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 6415 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,6390 /*256:out */ -1, 6416 6391 /*xcpt? */ false, false }, 6417 6392 { { /*src2 */ { FP32_NORM_MAX(1), FP32_RAND_V5(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V3(1), FP32_RAND_V2(1) } }, … … 6420 6395 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, 6421 6396 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, 6422 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,6397 /*256:out */ -1, 6423 6398 /*xcpt? */ false, false }, 6424 6399 { { /*src2 */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, … … 6427 6402 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 6428 6403 /*128:out */ X86_MXCSR_XCPT_MASK, 6429 /*256:out */ X86_MXCSR_XCPT_MASK,6404 /*256:out */ -1, 6430 6405 /*xcpt? */ false, false }, 6431 6406 { { /*src2 */ { FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, … … 6434 6409 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 6435 6410 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 6436 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,6411 /*256:out */ -1, 6437 6412 /*xcpt? */ false, false }, 6438 6413 { { /*src2 */ { FP32_V(0, 0x712060, 0x92)/* 987654*/, FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } }, … … 6441 6416 /*mxcsr:in */ 0, 6442 6417 /*128:out */ 0, 6443 /*256:out */ 0,6418 /*256:out */ -1, 6444 6419 /*xcpt? */ false, false }, 6445 6420 { { /*src2 */ { FP32_1(0), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } }, … … 6448 6423 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 6449 6424 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 6450 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 6451 /*xcpt? */ false, false }, 6452 { { /*src2 */ { FP32_1(0), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } }, 6453 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } }, 6454 { /* => */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } }, 6455 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 6456 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 6457 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 6425 /*256:out */ -1, 6458 6426 /*xcpt? */ false, false }, 6459 6427 { { /*src2 */ { FP32_V(1, 0x600000, 0x7e)/* -0.875*/, FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } }, … … 6462 6430 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 6463 6431 /*128:out */ X86_MXCSR_XCPT_MASK, 6464 /*256:out */ X86_MXCSR_XCPT_MASK,6432 /*256:out */ -1, 6465 6433 /*xcpt? */ false, false }, 6466 6434 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V0(1), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V6(1) } }, … … 6469 6437 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 6470 6438 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 6471 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ,6439 /*256:out */ -1, 6472 6440 /*xcpt? */ false, false }, 6473 6441 /* 6474 6442 * Denormals. 6475 6443 */ 6476 /* 27*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(0) } },6444 /*33*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(0) } }, 6477 6445 { /*src1 */ { FP32_0(0), FP32_RAND_V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0) } }, 6478 6446 { /* => */ { FP32_0(0), FP32_RAND_V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0) } }, 6479 6447 /*mxcsr:in */ 0, 6480 /*128:out */ X86_MXCSR_DE, 6481 /*256:out */ X86_MXCSR_DE, 6448 /*128:out */ X86_MXCSR_DE | BS3_MXCSR_DM_FIXED, 6449 /*256:out */ -1, 6450 /*xcpt? */ true, true }, 6451 #ifdef TODO_X86_MXCSR_UE_IEM /** @todo THIS FAILS ON IEM: X86_MXCSR_UE not set in 128:out *AND* different output values */ 6452 /*--|34*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(0) } }, 6453 { /*src1 */ { FP32_0(0), FP32_RAND_V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0) } }, 6454 { /* => */ { FP32_0(0), FP32_RAND_V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0) } } /* result on HW (i7-10700) */, 6455 // IEM: { /* => */ { FP32_DENORM_MAX(1), FP32_RAND_V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0) } } /* result on IEM */, 6456 /*mxcsr:in */ X86_MXCSR_DM, 6457 /*128:out */ X86_MXCSR_DM | X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 6458 /*256:out */ -1, 6459 /*xcpt? */ true, true }, 6460 #endif /* TODO_X86_MXCSR_UE_IEM */ 6461 /*34|35*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(0) } }, 6462 { /*src1 */ { FP32_0(0), FP32_RAND_V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0) } }, 6463 { /* => */ { FP32_DENORM_MAX(1), FP32_RAND_V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0) } }, 6464 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_UM, 6465 /*128:out */ X86_MXCSR_DM | X86_MXCSR_UM | X86_MXCSR_DE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 6466 /*256:out */ -1, 6482 6467 /*xcpt? */ true, true }, 6483 6468 { { /*src2 */ { FP32_0(0), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V6(1) } }, … … 6486 6471 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK, 6487 6472 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK, 6488 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,6473 /*256:out */ -1, 6489 6474 /*xcpt? */ false, false }, 6490 6475 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V7(0) } }, … … 6493 6478 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, 6494 6479 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, 6495 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,6480 /*256:out */ -1, 6496 6481 /*xcpt? */ false, false }, 6497 6482 /** @todo More denormals. */ … … 6499 6484 * Invalids. 6500 6485 */ 6501 /*30*/ FP32_TABLE_D1_SS_INVALIDS6486 /*37|38*/ FP32_TABLE_D1_SS_INVALIDS 6502 6487 /** @todo Underflow; Precision; Rounding; FZ etc. */ 6503 6488 }; … … 6538 6523 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 6539 6524 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode); 6540 return bs3CpuInstr4_WorkerTestType1 (bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,6525 return bs3CpuInstr4_WorkerTestType1A(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 6541 6526 g_aXcptConfig3, RT_ELEMENTS(g_aXcptConfig3)); 6542 6527 } … … 7429 7414 /*--|24*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_DENORM_MAX(0), FP64_0(0) } }, 7430 7415 { /*src1 */ { FP64_0(0), FP64_DENORM_MAX(1), FP64_0(0), FP64_DENORM_MAX(1) } }, 7431 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } } , /* result on HW (i7-10700) */7432 // IEM: { /* => */ { FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } } , /* result on IEM */7416 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } } /* result on HW (i7-10700) */, 7417 // IEM: { /* => */ { FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } } /* result on IEM */, 7433 7418 /*mxcsr:in */ X86_MXCSR_DM, 7434 7419 /*128:out */ X86_MXCSR_DM | X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, … … 7460 7445 /*--|28*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 7461 7446 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0) } }, 7462 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } } , /* result on HW (i7-10700) */7463 // IEM: { /* => */ { FP64_0(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_0(0) } } , /* result on IEM */7447 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } } /* result on HW (i7-10700) */, 7448 // IEM: { /* => */ { FP64_0(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_0(0) } } /* result on IEM */, 7464 7449 /*mxcsr:in */ X86_MXCSR_DM, 7465 7450 /*128:out */ X86_MXCSR_DM | X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, … … 8245 8230 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 8246 8231 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 8247 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,8248 /*128:out */ X86_MXCSR_XCPT_MASK,8249 /*256:out */ X86_MXCSR_XCPT_MASK,8250 /*xcpt? */ false, false },8251 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },8252 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },8253 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },8254 8232 /*mxcsr:in */ 0, 8255 8233 /*128:out */ 0, 8256 /*256:out */ 0,8234 /*256:out */ -1, 8257 8235 /*xcpt? */ false, false }, 8258 8236 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, … … 8261 8239 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 8262 8240 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 8263 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,8241 /*256:out */ -1, 8264 8242 /*xcpt? */ false, false }, 8265 8243 { { /*src2 */ { FP32_0(0), FP32_NORM_V7(0), FP32_NORM_V6(0), FP32_0(0), FP32_0(1), FP32_NORM_V3(0), FP32_0(0), FP32_0(0) } }, … … 8268 8246 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 8269 8247 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 8270 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,8248 /*256:out */ -1, 8271 8249 /*xcpt? */ false, false }, 8272 8250 { { /*src2 */ { FP32_0(1), FP32_0(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, … … 8275 8253 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 8276 8254 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 8277 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,8255 /*256:out */ -1, 8278 8256 /*xcpt? */ false, false }, 8279 8257 { { /*src2 */ { FP32_0(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, … … 8282 8260 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 8283 8261 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 8284 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,8262 /*256:out */ -1, 8285 8263 /*xcpt? */ false, false }, 8286 8264 { { /*src2 */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, … … 8289 8267 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ, 8290 8268 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ, 8291 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,8269 /*256:out */ -1, 8292 8270 /*xcpt? */ false, false }, 8293 8271 { { /*src2 */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, … … 8296 8274 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 8297 8275 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 8298 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,8276 /*256:out */ -1, 8299 8277 /*xcpt? */ false, false }, 8300 8278 /* 8301 8279 * Infinity. 8302 8280 */ 8303 /* 8*/{ { /*src2 */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },8281 /* 7*/{ { /*src2 */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 8304 8282 { /*src1 */ { FP32_1(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 8305 8283 { /* => */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 8306 8284 /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM, 8307 8285 /*128:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM, 8308 /*256:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,8286 /*256:out */ -1, 8309 8287 /*xcpt? */ false, false }, 8310 8288 { { /*src2 */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, … … 8313 8291 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 8314 8292 /*128:out */ X86_MXCSR_XCPT_MASK, 8315 /*256:out */ X86_MXCSR_XCPT_MASK,8293 /*256:out */ -1, 8316 8294 /*xcpt? */ false, false }, 8317 8295 { { /*src2 */ { FP32_INF(0), FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, … … 8320 8298 /*mxcsr:in */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_DAZ | X86_MXCSR_FZ, 8321 8299 /*128:out */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_DAZ | X86_MXCSR_FZ, 8322 /*256:out */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_DAZ | X86_MXCSR_FZ,8300 /*256:out */ -1, 8323 8301 /*xcpt? */ false, false }, 8324 8302 { { /*src2 */ { FP32_INF(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, … … 8327 8305 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 8328 8306 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 8329 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,8307 /*256:out */ -1, 8330 8308 /*xcpt? */ false, false }, 8331 8309 { { /*src2 */ { FP32_1(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, … … 8334 8312 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, 8335 8313 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, 8336 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,8314 /*256:out */ -1, 8337 8315 /*xcpt? */ false, false }, 8338 8316 { { /*src2 */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(1) } }, … … 8341 8319 /*mxcsr:in */ X86_MXCSR_FZ, 8342 8320 /*128:out */ X86_MXCSR_FZ, 8343 /*256:out */ X86_MXCSR_FZ,8321 /*256:out */ -1, 8344 8322 /*xcpt? */ false, false }, 8345 8323 { { /*src2 */ { FP32_INF(1), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V2(0) } }, … … 8348 8326 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 8349 8327 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 8350 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,8328 /*256:out */ -1, 8351 8329 /*xcpt? */ false, false }, 8352 8330 /* 8353 8331 * Normals. 8354 8332 */ 8355 /*1 5*/{ { /*src2 */ { FP32_V(0, 0x600000, 0x7f)/*1.7500*/, FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },8333 /*14*/{ { /*src2 */ { FP32_V(0, 0x600000, 0x7f)/*1.7500*/, FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, 8356 8334 { /*src1 */ { FP32_V(0, 0, 0x7d)/*0.2500*/, FP32_RAND_V6(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V2(1) } }, 8357 8335 { /* => */ { FP32_V(0, 0x600000, 0x7d)/*0.4375*/, FP32_RAND_V6(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V2(1) } }, 8358 8336 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 8359 8337 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 8360 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,8338 /*256:out */ -1, 8361 8339 /*xcpt? */ false, false }, 8362 8340 { { /*src2 */ { FP32_V(0, 0x61e000, 0x89)/* 1807*/, FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, … … 8365 8343 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 8366 8344 /*128:out */ X86_MXCSR_XCPT_MASK, 8367 /*256:out */ X86_MXCSR_XCPT_MASK,8345 /*256:out */ -1, 8368 8346 /*xcpt? */ false, false }, 8369 8347 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, … … 8372 8350 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 8373 8351 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 8374 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,8352 /*256:out */ -1, 8375 8353 /*xcpt? */ false, false }, 8376 8354 { { /*src2 */ { FP32_V(0, 0x61e000, 0x89)/* 1807*/, FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, … … 8379 8357 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, 8380 8358 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, 8381 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,8359 /*256:out */ -1, 8382 8360 /*xcpt? */ false, false }, 8383 8361 { { /*src2 */ { FP32_V(0, 0x4a30b8, 0x8f)/* 103521.4375*/, FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, … … 8386 8364 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 8387 8365 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 8388 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,8366 /*256:out */ -1, 8389 8367 /*xcpt? */ false, false }, 8390 8368 { { /*src2 */ { FP32_V(0, 0x1a5200, 0x8c)/* 9876.5*/, FP32_RAND_V6(0), FP32_RAND_V0(1), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V5(1), FP32_RAND_V7(1) } }, … … 8393 8371 /*mxcsr:in */ 0, 8394 8372 /*128:out */ 0, 8395 /*256:out */ 0,8373 /*256:out */ -1, 8396 8374 /*xcpt? */ false, false }, 8397 8375 { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_V1(1), FP32_0(0), FP32_1(0), FP32_NORM_MIN(0), FP32_NORM_V1(0), FP32_NORM_V2(0), FP32_0(0) } }, … … 8400 8378 /*mxcsr:in */ 0, 8401 8379 /*128:out */ 0, 8402 /*256:out */ 0,8380 /*256:out */ -1, 8403 8381 /*xcpt? */ false, false }, 8404 8382 { { /*src2 */ { FP32_V(0, 0x23b6a0, 0x8e)/*41910.625000*/, FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V2(0) } }, … … 8407 8385 /*mxcsr:in */ 0, 8408 8386 /*128:out */ 0, 8409 /*256:out */ 0,8387 /*256:out */ -1, 8410 8388 /*xcpt? */ false, false }, 8411 8389 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(0), FP32_1(1), FP32_1(1), FP32_1(0), FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_1(0) } }, … … 8414 8392 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 8415 8393 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 8416 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,8394 /*256:out */ -1, 8417 8395 /*xcpt? */ false, false }, 8418 8396 /** @todo More Normals. */ … … 8420 8398 * Denormals. 8421 8399 */ 8422 /*2 4*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(1) } },8400 /*23*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(1) } }, 8423 8401 { /*src1 */ { FP32_0(0), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(1) } }, 8424 { /* => */ { FP32_0(0), FP32_ RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V5(0)} },8402 { /* => */ { FP32_0(0), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(1) } }, 8425 8403 /*mxcsr:in */ 0, 8426 8404 /*128:out */ X86_MXCSR_DE, 8427 /*256:out */ X86_MXCSR_DE,8405 /*256:out */ -1, 8428 8406 /*xcpt? */ true, true }, 8429 8407 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(1) } }, 8430 8408 { /*src1 */ { FP32_0(0), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(1) } }, 8431 { /* => */ { FP32_0(0), FP32_ RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V5(0)} },8409 { /* => */ { FP32_0(0), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(1) } }, 8432 8410 /*mxcsr:in */ 0, 8433 8411 /*128:out */ X86_MXCSR_DE, 8434 /*256:out */ X86_MXCSR_DE,8412 /*256:out */ -1, 8435 8413 /*xcpt? */ true, true }, 8436 8414 { { /*src2 */ { FP32_0(0), FP32_DENORM_MIN(0), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_1(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_1(0) } }, … … 8439 8417 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 8440 8418 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, 8441 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,8419 /*256:out */ -1, 8442 8420 /*xcpt? */ false, false }, 8443 8421 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_1(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V0(0), FP32_DENORM_MAX(0) } }, … … 8446 8424 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 8447 8425 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 8448 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,8426 /*256:out */ -1, 8449 8427 /*xcpt? */ false, false }, 8450 8428 /** @todo More Denormals. */ … … 8452 8430 * Invalids. 8453 8431 */ 8454 /*2 8*/ FP32_TABLE_D1_SS_INVALIDS8455 /** @todo Underflow, Precision; Rounding; FZ etc. */8432 /*27*/ FP32_TABLE_D1_SS_INVALIDS 8433 /** @todo Overflow, Underflow, Precision; Rounding; FZ etc. */ 8456 8434 }; 8457 8435 … … 8491 8469 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 8492 8470 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode); 8493 return bs3CpuInstr4_WorkerTestType1 (bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,8471 return bs3CpuInstr4_WorkerTestType1A(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 8494 8472 g_aXcptConfig3, RT_ELEMENTS(g_aXcptConfig3)); 8495 8473 } … … 9567 9545 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 9568 9546 { /* => */ { FP32_QNAN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 9569 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,9570 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,9571 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,9572 /*xcpt? */ false, false },9573 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },9574 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },9575 { /* => */ { FP32_QNAN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },9576 9547 /*mxcsr:in */ 0, 9577 9548 /*128:out */ X86_MXCSR_IE, 9578 /*256:out */ X86_MXCSR_IE,9549 /*256:out */ -1, 9579 9550 /*xcpt? */ true, true }, 9580 9551 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, … … 9583 9554 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 9584 9555 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 9585 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,9556 /*256:out */ -1, 9586 9557 /*xcpt? */ false, false }, 9587 9558 { { /*src2 */ { FP32_0(0), FP32_NORM_V7(0), FP32_NORM_V6(0), FP32_0(0), FP32_0(1), FP32_NORM_V3(0), FP32_0(0), FP32_0(0) } }, … … 9590 9561 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 9591 9562 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, 9592 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,9563 /*256:out */ -1, 9593 9564 /*xcpt? */ false, false }, 9594 9565 { { /*src2 */ { FP32_0(1), FP32_0(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, … … 9597 9568 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 9598 9569 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, 9599 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,9570 /*256:out */ -1, 9600 9571 /*xcpt? */ true, true }, 9601 9572 { { /*src2 */ { FP32_0(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, … … 9604 9575 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 9605 9576 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 9606 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,9577 /*256:out */ -1, 9607 9578 /*xcpt? */ true, true }, 9608 9579 { { /*src2 */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, … … 9611 9582 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ, 9612 9583 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_IE, 9613 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_IE,9584 /*256:out */ -1, 9614 9585 /*xcpt? */ false, false }, 9615 9586 { { /*src2 */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, … … 9618 9589 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 9619 9590 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_FSW_ZE, 9620 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_FSW_ZE,9591 /*256:out */ -1, 9621 9592 /*xcpt? */ false, false }, 9622 9593 /* 9623 9594 * Infinity. 9624 9595 */ 9625 /* 8*/{ { /*src2 */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },9596 /* 7*/{ { /*src2 */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 9626 9597 { /*src1 */ { FP32_1(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 9627 9598 { /* => */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 9628 9599 /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM, 9629 9600 /*128:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM, 9630 /*256:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,9601 /*256:out */ -1, 9631 9602 /*xcpt? */ false, false }, 9632 9603 { { /*src2 */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, … … 9635 9606 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 9636 9607 /*128:out */ X86_MXCSR_XCPT_MASK, 9637 /*256:out */ X86_MXCSR_XCPT_MASK,9638 /*xcpt? */ false, false }, 9639 { { /*src2 */ { FP32_INF(0), FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },9640 { /*src1 */ { FP32_INF(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },9641 { /* => */ { FP32_ INF(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },9608 /*256:out */ -1, 9609 /*xcpt? */ false, false }, 9610 { { /*src2 */ { FP32_INF(0), FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, 9611 { /*src1 */ { FP32_INF(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, 9612 { /* => */ { FP32_QNAN(1), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, 9642 9613 /*mxcsr:in */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_DAZ | X86_MXCSR_FZ, 9643 9614 /*128:out */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE, 9644 /*256:out */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE,9615 /*256:out */ -1, 9645 9616 /*xcpt? */ true, true }, 9646 9617 { { /*src2 */ { FP32_INF(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, … … 9649 9620 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 9650 9621 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 9651 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,9622 /*256:out */ -1, 9652 9623 /*xcpt? */ false, false }, 9653 9624 { { /*src2 */ { FP32_1(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, … … 9656 9627 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, 9657 9628 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, 9658 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,9629 /*256:out */ -1, 9659 9630 /*xcpt? */ false, false }, 9660 9631 { { /*src2 */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(1) } }, … … 9663 9634 /*mxcsr:in */ X86_MXCSR_FZ, 9664 9635 /*128:out */ X86_MXCSR_FZ, 9665 /*256:out */ X86_MXCSR_FZ,9636 /*256:out */ -1, 9666 9637 /*xcpt? */ false, false }, 9667 9638 { { /*src2 */ { FP32_INF(1), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V2(0) } }, … … 9670 9641 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 9671 9642 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 9672 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,9643 /*256:out */ -1, 9673 9644 /*xcpt? */ true, true }, 9674 9645 /* 9675 9646 * Normals. 9676 9647 */ 9677 /*1 5*/{ { /*src2 */ { FP32_V(0, 0x600000, 0x7f)/*1.7500*/, FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },9648 /*14*/{ { /*src2 */ { FP32_V(0, 0x600000, 0x7f)/*1.7500*/, FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, 9678 9649 { /*src1 */ { FP32_V(0, 0x600000, 0x7d)/*0.4375*/, FP32_RAND_V6(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V2(1) } }, 9679 9650 { /* => */ { FP32_V(0, 0, 0x7d)/*0.2500*/, FP32_RAND_V6(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V2(1) } }, 9680 9651 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 9681 9652 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 9682 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,9653 /*256:out */ -1, 9683 9654 /*xcpt? */ false, false }, 9684 9655 { { /*src2 */ { FP32_V(0, 0x61e000, 0x89)/* 1807*/, FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, … … 9687 9658 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 9688 9659 /*128:out */ X86_MXCSR_XCPT_MASK, 9689 /*256:out */ X86_MXCSR_XCPT_MASK,9660 /*256:out */ -1, 9690 9661 /*xcpt? */ false, false }, 9691 9662 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } }, … … 9694 9665 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 9695 9666 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 9696 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,9667 /*256:out */ -1, 9697 9668 /*xcpt? */ false, false }, 9698 9669 { { /*src2 */ { FP32_V(0, 0x61e000, 0x89)/* 1807*/, FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, … … 9701 9672 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, 9702 9673 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, 9703 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,9674 /*256:out */ -1, 9704 9675 /*xcpt? */ false, false }, 9705 9676 { { /*src2 */ { FP32_V(0, 0x4a30b8, 0x8f)/* 103521.4375*/, FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, … … 9708 9679 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 9709 9680 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 9710 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,9681 /*256:out */ -1, 9711 9682 /*xcpt? */ false, false }, 9712 9683 { { /*src2 */ { FP32_V(0, 0x1a5200, 0x8c)/* 9876.5*/, FP32_RAND_V6(0), FP32_RAND_V0(1), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V5(1), FP32_RAND_V7(1) } }, … … 9715 9686 /*mxcsr:in */ 0, 9716 9687 /*128:out */ 0, 9717 /*256:out */ 0,9688 /*256:out */ -1, 9718 9689 /*xcpt? */ false, false }, 9719 9690 { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_V1(1), FP32_0(0), FP32_1(0), FP32_NORM_MIN(0), FP32_NORM_V1(0), FP32_NORM_V2(0), FP32_0(0) } }, … … 9722 9693 /*mxcsr:in */ 0, 9723 9694 /*128:out */ 0, 9724 /*256:out */ 0,9695 /*256:out */ -1, 9725 9696 /*xcpt? */ false, false }, 9726 9697 { { /*src2 */ { FP32_V(0, 0x23b6a0, 0x8e)/*41910.625000*/, FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V2(0) } }, … … 9729 9700 /*mxcsr:in */ 0, 9730 9701 /*128:out */ 0, 9731 /*256:out */ 0,9702 /*256:out */ -1, 9732 9703 /*xcpt? */ false, false }, 9733 9704 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(0), FP32_1(1), FP32_1(1), FP32_1(0), FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_1(0) } }, … … 9736 9707 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 9737 9708 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 9738 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,9709 /*256:out */ -1, 9739 9710 /*xcpt? */ false, false }, 9740 9711 /** @todo More Normals. */ … … 9742 9713 * Denormals. 9743 9714 */ 9744 /*2 4*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(1) } },9715 /*23*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(1) } }, 9745 9716 { /*src1 */ { FP32_0(0), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(1) } }, 9746 9717 { /* => */ { FP32_0(0), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(1) } }, 9747 9718 /*mxcsr:in */ 0, 9748 9719 /*128:out */ X86_MXCSR_DE, 9749 /*256:out */ X86_MXCSR_DE,9720 /*256:out */ -1, 9750 9721 /*xcpt? */ true, true }, 9751 9722 { { /*src2 */ { FP32_0(0), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(1) } }, … … 9754 9725 /*mxcsr:in */ 0, 9755 9726 /*128:out */ X86_MXCSR_ZE, 9756 /*256:out */ X86_MXCSR_ZE, 9757 /*xcpt? */ true, true }, 9758 { { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(1) } }, 9759 { /*src1 */ { FP32_0(0), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(1) } }, 9760 { /* => */ { FP32_0(0), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(1) } }, 9761 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 9762 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, 9763 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, 9764 /*xcpt? */ false, false }, 9765 { { /*src2 */ { FP32_0(0), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(1) } }, 9766 { /*src1 */ { FP32_DENORM_MAX(0), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(1) } }, 9767 { /* => */ { FP32_INF(0), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(1) } }, 9768 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 9769 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_ZE, 9770 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_ZE, 9771 /*xcpt? */ false, false }, 9727 /*256:out */ -1, 9728 /*xcpt? */ true, true }, 9772 9729 { { /*src2 */ { FP32_0(0), FP32_DENORM_MIN(0), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_1(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_1(0) } }, 9773 9730 { /*src1 */ { FP32_DENORM_MIN(1), FP32_1(0), FP32_1(0), FP32_1(0), FP32_RAND_V2(0), FP32_1(0), FP32_1(0), FP32_DENORM_MAX(0) } }, … … 9775 9732 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 9776 9733 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_ZE, 9777 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_ZE,9734 /*256:out */ -1, 9778 9735 /*xcpt? */ false, false }, 9779 9736 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_1(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V0(0), FP32_DENORM_MAX(0) } }, … … 9782 9739 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 9783 9740 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, 9784 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,9741 /*256:out */ -1, 9785 9742 /*xcpt? */ false, false }, 9786 9743 /** @todo More Denormals. */ … … 9788 9745 * Invalids. 9789 9746 */ 9790 /* 30*/ FP32_TABLE_D1_SS_INVALIDS9791 /** @todo Underflow; Precision; Rounding, FZ etc. */9747 /*27*/ FP32_TABLE_D1_SS_INVALIDS 9748 /** @todo Overflow; Underflow; Precision; Rounding, FZ etc. */ 9792 9749 }; 9793 9750 … … 9829 9786 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 9830 9787 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode); 9831 return bs3CpuInstr4_WorkerTestType1 (bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,9788 return bs3CpuInstr4_WorkerTestType1A(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 9832 9789 g_aXcptConfig3, RT_ELEMENTS(g_aXcptConfig3)); 9833 9790 }
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