Index: trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32
===================================================================
--- trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32	(revision 106216)
+++ trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32	(revision 106220)
@@ -848,115 +848,11 @@
  **/
 #define FP32_TABLE_D1_SS_INVALIDS \
-    /* QNan, QNan (Masked). */                                                                                                                                                                                                                                                                      \
+    /* QNan, QNan */                                                                                                                                                          \
     /* 0*/{ { /*src2     */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0),  FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } },      \
-            { /*src1     */ { FP32_QNAN(0), FP32_QNAN(0),     FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } },      \
-            { /* =>      */ { FP32_QNAN(0), FP32_QNAN(0),     FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } },      \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                              \
-              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                              \
-              /*256:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                              \
-              /*xcpt?    */ false, false },                                                                                                                                   \
-          { { /*src2     */ { FP32_QNAN_MAX(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0) } },                     \
-            { /*src1     */ { FP32_QNAN(0),     FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0), FP32_QNAN_V1(0) } },                     \
-            { /* =>      */ { FP32_QNAN(0),     FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0), FP32_QNAN_V1(0) } },                     \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                              \
-              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                              \
-              /*256:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                              \
-              /*xcpt?    */ false, false },                                                                                                                                   \
-          { { /*src2     */ { FP32_QNAN_V1(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0) } },                      \
-            { /*src1     */ { FP32_QNAN_V2(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0), FP32_QNAN_V1(0) } },                      \
-            { /* =>      */ { FP32_QNAN_V2(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0), FP32_QNAN_V1(0) } },                      \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                              \
-              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                              \
-              /*256:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                              \
-              /*xcpt?    */ false, false },                                                                                                                                   \
-    /* QNan, SNan (Masked). */                                                                                                                                                \
-          { { /*src2     */ { FP32_QNAN(0),      FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0) } },                    \
-            { /*src1     */ { FP32_SNAN(0),      FP32_SNAN_V2(0), FP32_SNAN_V6(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V4(0), FP32_SNAN_V1(0) } },                    \
-            { /* =>      */ { FP32_QNAN_V(0, 1), FP32_SNAN_V2(0), FP32_SNAN_V6(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V4(0), FP32_QNAN_V1(0) } },                    \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                              \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                               \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                               \
-              /*xcpt?    */ false, false },                                                                                                                                   \
-          { { /*src2     */ { FP32_QNAN_MAX(0),  FP32_QNAN_MAX(0), FP32_QNAN_V0(0),  FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \
-            { /*src1     */ { FP32_SNAN(0),      FP32_SNAN(0),     FP32_SNAN_MAX(0), FP32_SNAN_V2(0), FP32_SNAN_V6(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V4(0) } }, \
-            { /* =>      */ { FP32_QNAN_V(0, 1), FP32_SNAN(0),     FP32_SNAN_MAX(0), FP32_SNAN_V2(0), FP32_SNAN_V6(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V4(0) } }, \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                              \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                               \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                               \
-              /*xcpt?    */ false, false },                                                                                                                                   \
-          { { /*src2     */ { FP32_QNAN_V1(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0),  FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } },   \
-            { /*src1     */ { FP32_SNAN_V2(0), FP32_QNAN(0),     FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } },   \
-            { /* =>      */ { FP32_QNAN_V2(0), FP32_QNAN(0),     FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } },   \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                              \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                               \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                               \
-              /*xcpt?    */ false, false },                                                                                                                                   \
-    /* SNan, QNan (Masked). */                                                                                                                                                \
-          { { /*src2     */ { FP32_SNAN(0), FP32_SNAN(0),     FP32_SNAN_V1(0), FP32_SNAN_V1(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V5(0), FP32_SNAN_V6(0) } },       \
-            { /*src1     */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } },       \
-            { /* =>      */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } },       \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                              \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                               \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                               \
-              /*xcpt?    */ false, false },                                                                                                                                   \
-          { { /*src2     */ { FP32_SNAN_MAX(0), FP32_SNAN_MAX(0), FP32_SNAN_V1(0), FP32_SNAN_V1(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V5(0), FP32_SNAN_V6(0) } },   \
-            { /*src1     */ { FP32_QNAN(0),     FP32_QNAN(0),     FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } },   \
-            { /* =>      */ { FP32_QNAN(0),     FP32_QNAN(0),     FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } },   \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                              \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                               \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                               \
-              /*xcpt?    */ false, false },                                                                                                                                   \
-          { { /*src2     */ { FP32_SNAN_V0(0), FP32_SNAN_MAX(0), FP32_SNAN_V1(0), FP32_SNAN_V1(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V5(0), FP32_SNAN_V6(0) } },    \
-            { /*src1     */ { FP32_QNAN_V6(0), FP32_QNAN(0),     FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } },    \
-            { /* =>      */ { FP32_QNAN_V6(0), FP32_QNAN(0),     FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } },    \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                              \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                               \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                               \
-              /*xcpt?    */ false, false },                                                                                                                                   \
-    /* SNan, SNan (Masked). */                                                                                                                                                \
-          { { /*src2     */ { FP32_SNAN(0),      FP32_SNAN(0),     FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V7(0), FP32_SNAN_V1(0), FP32_SNAN_V6(0), FP32_SNAN_V1(0) } },  \
-            { /*src1     */ { FP32_SNAN(0),      FP32_SNAN_MAX(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } },  \
-            { /* =>      */ { FP32_QNAN_V(0, 1), FP32_SNAN_MAX(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } },  \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                              \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                               \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                               \
-              /*xcpt?    */ false, false },                                                                                                                                   \
-          { { /*src2     */ { FP32_SNAN(0),     FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V7(0), FP32_SNAN_V1(0), FP32_SNAN_V6(0), FP32_SNAN_V1(0) } },    \
-            { /*src1     */ { FP32_SNAN_MAX(0), FP32_SNAN_V0(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } },    \
-            { /* =>      */ { FP32_QNAN_MAX(0), FP32_SNAN_V0(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } },    \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                              \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                               \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                               \
-              /*xcpt?    */ false, false },                                                                                                                                   \
-          { { /*src2     */ { FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V7(0), FP32_SNAN_V1(0), FP32_SNAN_V6(0), FP32_SNAN_V1(0) } },     \
-            { /*src1     */ { FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V0(0) } },     \
-            { /* =>      */ { FP32_QNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V0(0) } },     \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                              \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                               \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                               \
-              /*xcpt?    */ false, false },                                                                                                                                   \
-    /* QNan, Norm FP (Masked). */                                                                                                                                             \
-          { { /*src2     */ { FP32_QNAN(0), FP32_QNAN_MAX(1), FP32_NORM_V0(1), FP32_QNAN_V1(0), FP32_NORM_V3(0), FP32_QNAN_V3(1), FP32_NORM_V5(0), FP32_QNAN_V5(1) } },       \
-            { /*src1     */ { FP32_1(0),    FP32_1(1),        FP32_QNAN_V0(1), FP32_NORM_V2(1), FP32_QNAN_V2(0), FP32_NORM_V4(0), FP32_QNAN_V4(1), FP32_NORM_V6(1) } },       \
-            { /* =>      */ { FP32_QNAN(0), FP32_1(1),        FP32_QNAN_V0(1), FP32_NORM_V2(1), FP32_QNAN_V2(0), FP32_NORM_V4(0), FP32_QNAN_V4(1), FP32_NORM_V6(1) } },       \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                              \
-              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                              \
-              /*256:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                              \
-              /*xcpt?    */ false, false },                                                                                                                                   \
-    /* SNan, Norm FP (Masked). */                                                                                                                                             \
-          { { /*src2     */ { FP32_SNAN(1),      FP32_SNAN_MAX(1), FP32_NORM_V0(1), FP32_SNAN_V1(0), FP32_NORM_V3(0), FP32_SNAN_V3(1), FP32_NORM_V5(0), FP32_SNAN_V5(1) } },  \
-            { /*src1     */ { FP32_1(0),         FP32_1(0),        FP32_SNAN_V0(1), FP32_NORM_V2(1), FP32_SNAN_V2(1), FP32_NORM_V4(0), FP32_SNAN_V4(1), FP32_NORM_V6(1) } },  \
-            { /* =>      */ { FP32_QNAN_V(1, 1), FP32_1(0),        FP32_SNAN_V0(1), FP32_NORM_V2(1), FP32_SNAN_V2(1), FP32_NORM_V4(0), FP32_SNAN_V4(1), FP32_NORM_V6(1) } },  \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                              \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                               \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                               \
-              /*xcpt?    */ false, false },                                                                                                                                   \
-    /* QNan, QNan (Unmasked). */                                                                                                                                              \
-    /*14*/{ { /*src2     */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0),  FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } },      \
             { /*src1     */ { FP32_QNAN(0), FP32_QNAN(0),     FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } },      \
             { /* =>      */ { FP32_QNAN(0), FP32_QNAN(0),     FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } },      \
               /*mxcsr:in */ 0,                                                                                                                                                \
               /*128:out  */ 0,                                                                                                                                                \
-              /*256:out  */ 0,                                                                                                                                                \
+              /*256:out  */ -1,                                                                                                                                               \
               /*xcpt?    */ false, false },                                                                                                                                   \
           { { /*src2     */ { FP32_QNAN_MAX(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0) } },                     \
@@ -965,5 +861,5 @@
               /*mxcsr:in */ 0,                                                                                                                                                \
               /*128:out  */ 0,                                                                                                                                                \
-              /*256:out  */ 0,                                                                                                                                                \
+              /*256:out  */ -1,                                                                                                                                               \
               /*xcpt?    */ false, false },                                                                                                                                   \
           { { /*src2     */ { FP32_QNAN_V1(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0) } },                      \
@@ -972,14 +868,13 @@
               /*mxcsr:in */ 0,                                                                                                                                                \
               /*128:out  */ 0,                                                                                                                                                \
-              /*256:out  */ 0,                                                                                                                                                \
+              /*256:out  */ -1,                                                                                                                                               \
               /*xcpt?    */ false, false },                                                                                                                                   \
-                                                                                                                                                                              \
-    /* QNan, SNan (Unmasked). */                                                                                                                                              \
+    /* QNan, SNan */                                                                                                                                                          \
           { { /*src2     */ { FP32_QNAN(0),      FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0) } },                    \
             { /*src1     */ { FP32_SNAN(0),      FP32_SNAN_V2(0), FP32_SNAN_V6(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V4(0), FP32_SNAN_V1(0) } },                    \
-            { /* =>      */ { FP32_QNAN_V(0, 1), FP32_QNAN_V2(0), FP32_SNAN_V6(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V4(0), FP32_QNAN_V1(0) } },                    \
+            { /* =>      */ { FP32_QNAN_V(0, 1), FP32_SNAN_V2(0), FP32_SNAN_V6(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V4(0), FP32_QNAN_V1(0) } },                    \
               /*mxcsr:in */ 0,                                                                                                                                                \
               /*128:out  */ X86_MXCSR_IE,                                                                                                                                     \
-              /*256:out  */ X86_MXCSR_IE,                                                                                                                                     \
+              /*256:out  */ -1,                                                                                                                                               \
               /*xcpt?    */ true, true },                                                                                                                                     \
           { { /*src2     */ { FP32_QNAN_MAX(0),  FP32_QNAN_MAX(0), FP32_QNAN_V0(0),  FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \
@@ -988,14 +883,14 @@
               /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,                                                                                                 \
               /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,                                                                                  \
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,                                                                                  \
+              /*256:out  */ -1,                                                                                                                                               \
               /*xcpt?    */ true, true },                                                                                                                                     \
           { { /*src2     */ { FP32_QNAN_V1(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0),  FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } },   \
             { /*src1     */ { FP32_SNAN_V2(0), FP32_QNAN(0),     FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } },   \
-            { /* =>      */ { FP32_SNAN_V2(0), FP32_QNAN(0),     FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } },   \
+            { /* =>      */ { FP32_QNAN_V2(0), FP32_QNAN(0),     FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } },   \
               /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,                                                                                                                 \
               /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,                                                                                                  \
-              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,                                                                                                  \
+              /*256:out  */ -1,                                                                                                                                               \
               /*xcpt?    */ true, true },                                                                                                                                     \
-    /* SNan, QNan (Unmasked). */                                                                                                                                              \
+    /* SNan, QNan */                                                                                                                                                          \
           { { /*src2     */ { FP32_SNAN(0), FP32_SNAN(0),     FP32_SNAN_V1(0), FP32_SNAN_V1(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V5(0), FP32_SNAN_V6(0) } },       \
             { /*src1     */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } },       \
@@ -1003,5 +898,5 @@
               /*mxcsr:in */ X86_MXCSR_DAZ,                                                                                                                                    \
               /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_IE,                                                                                                                     \
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_IE,                                                                                                                     \
+              /*256:out  */ -1,                                                                                                                                               \
               /*xcpt?    */ true, true },                                                                                                                                     \
           { { /*src2     */ { FP32_SNAN_MAX(0), FP32_SNAN_MAX(0), FP32_SNAN_V1(0), FP32_SNAN_V1(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V5(0), FP32_SNAN_V6(0) } },   \
@@ -1010,5 +905,5 @@
               /*mxcsr:in */ X86_MXCSR_RC_UP,                                                                                                                                  \
               /*128:out  */ X86_MXCSR_RC_UP | X86_MXCSR_IE,                                                                                                                   \
-              /*256:out  */ X86_MXCSR_RC_UP | X86_MXCSR_IE,                                                                                                                   \
+              /*256:out  */ -1,                                                                                                                                               \
               /*xcpt?    */ true, true },                                                                                                                                     \
           { { /*src2     */ { FP32_SNAN_V0(0), FP32_SNAN_MAX(0), FP32_SNAN_V1(0), FP32_SNAN_V1(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V5(0), FP32_SNAN_V6(0) } },    \
@@ -1017,20 +912,20 @@
               /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,                                                                                                                 \
               /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,                                                                                                  \
-              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,                                                                                                  \
+              /*256:out  */ -1,                                                                                                                                               \
               /*xcpt?    */ true, true },                                                                                                                                     \
-    /* SNan, SNan (Unmasked). */                                                                                                                                              \
-    /*24*/{ { /*src2     */ { FP32_SNAN(0),      FP32_SNAN(0),     FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V7(0), FP32_SNAN_V1(0), FP32_SNAN_V6(0), FP32_SNAN_V1(0) } },  \
+    /* SNan, SNan */                                                                                                                                                          \
+          { { /*src2     */ { FP32_SNAN(0),      FP32_SNAN(0),     FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V7(0), FP32_SNAN_V1(0), FP32_SNAN_V6(0), FP32_SNAN_V1(0) } },  \
             { /*src1     */ { FP32_SNAN(0),      FP32_SNAN_MAX(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } },  \
             { /* =>      */ { FP32_QNAN_V(0, 1), FP32_SNAN_MAX(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } },  \
               /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ,                                                                                                                     \
               /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE,                                                                                                      \
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE,                                                                                                      \
+              /*256:out  */ -1,                                                                                                                                               \
               /*xcpt?    */ true, true },                                                                                                                                     \
           { { /*src2     */ { FP32_SNAN(0),     FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V7(0), FP32_SNAN_V1(0), FP32_SNAN_V6(0), FP32_SNAN_V1(0) } },    \
             { /*src1     */ { FP32_SNAN_MAX(0), FP32_SNAN_V0(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } },    \
-            { /* =>      */ { FP32_SNAN_MAX(0), FP32_SNAN_V0(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } },    \
+            { /* =>      */ { FP32_QNAN_MAX(0), FP32_SNAN_V0(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } },    \
               /*mxcsr:in */ X86_MXCSR_RC_ZERO,                                                                                                                                \
               /*128:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE,                                                                                                                 \
-              /*256:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE,                                                                                                                 \
+              /*256:out  */ -1,                                                                                                                                               \
               /*xcpt?    */ true, true },                                                                                                                                     \
           { { /*src2     */ { FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V7(0), FP32_SNAN_V1(0), FP32_SNAN_V6(0), FP32_SNAN_V1(0) } },     \
@@ -1039,7 +934,7 @@
               /*mxcsr:in */ 0,                                                                                                                                                \
               /*128:out  */ X86_MXCSR_IE,                                                                                                                                     \
-              /*256:out  */ X86_MXCSR_IE,                                                                                                                                     \
+              /*256:out  */ -1,                                                                                                                                               \
               /*xcpt?    */ true, true },                                                                                                                                     \
-    /* QNan, Norm FP (Unmasked). */                                                                                                                                           \
+    /* QNan, Norm FP */                                                                                                                                                       \
           { { /*src2     */ { FP32_QNAN(0), FP32_QNAN_MAX(1), FP32_NORM_V0(1), FP32_QNAN_V1(0), FP32_NORM_V3(0), FP32_QNAN_V3(1), FP32_NORM_V5(0), FP32_QNAN_V5(1) } },       \
             { /*src1     */ { FP32_1(0),    FP32_1(1),        FP32_QNAN_V0(1), FP32_NORM_V2(1), FP32_QNAN_V2(0), FP32_NORM_V4(0), FP32_QNAN_V4(1), FP32_NORM_V6(1) } },       \
@@ -1047,13 +942,13 @@
               /*mxcsr:in */ X86_MXCSR_FZ,                                                                                                                                     \
               /*128:out  */ X86_MXCSR_FZ,                                                                                                                                     \
-              /*256:out  */ X86_MXCSR_FZ,                                                                                                                                     \
+              /*256:out  */ -1,                                                                                                                                               \
               /*xcpt?    */ false, false },                                                                                                                                   \
-    /* SNan, Norm FP (Unmasked). */                                                                                                                                           \
-    /*28*/{ { /*src2     */ { FP32_SNAN(1),      FP32_SNAN_MAX(1), FP32_NORM_V0(1), FP32_SNAN_V1(0), FP32_NORM_V3(0), FP32_SNAN_V3(1), FP32_NORM_V5(0), FP32_SNAN_V5(1) } },  \
+    /* SNan, Norm FP */                                                                                                                                                       \
+    /*13*/{ { /*src2     */ { FP32_SNAN(1),      FP32_SNAN_MAX(1), FP32_NORM_V0(1), FP32_SNAN_V1(0), FP32_NORM_V3(0), FP32_SNAN_V3(1), FP32_NORM_V5(0), FP32_SNAN_V5(1) } },  \
             { /*src1     */ { FP32_1(0),         FP32_1(0),        FP32_SNAN_V0(1), FP32_NORM_V2(1), FP32_SNAN_V2(1), FP32_NORM_V4(0), FP32_SNAN_V4(1), FP32_NORM_V6(1) } },  \
             { /* =>      */ { FP32_QNAN_V(1, 1), FP32_1(0),        FP32_SNAN_V0(1), FP32_NORM_V2(1), FP32_SNAN_V2(1), FP32_NORM_V4(0), FP32_SNAN_V4(1), FP32_NORM_V6(1) } },  \
               /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,                                                                                                 \
               /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,                                                                                  \
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,                                                                                  \
+              /*256:out  */ -1,                                                                                                                                               \
               /*xcpt?    */ true, true },                                                                                                                                     \
 
@@ -4317,5 +4212,5 @@
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
               /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_0(0), FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
@@ -4324,5 +4219,5 @@
               /*mxcsr:in */ 0,
               /*128:out  */ 0,
-              /*256:out  */ 0,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_0(0), FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
@@ -4331,5 +4226,5 @@
               /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
               /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_0(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
@@ -4338,5 +4233,5 @@
               /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
               /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
@@ -4345,5 +4240,5 @@
               /*mxcsr:in */ X86_MXCSR_FZ,
               /*128:out  */ X86_MXCSR_FZ,
-              /*256:out  */ X86_MXCSR_FZ,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_0(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
@@ -4352,5 +4247,5 @@
               /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN,
               /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
     /*
@@ -4359,15 +4254,15 @@
     /* 6*/{ { /*src2     */ { FP32_INF(0),  FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
             { /*src1     */ { FP32_INF(1),  FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
-            { /* =>      */ { FP32_0(0),    FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
+            { /* =>      */ { FP32_QNAN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
               /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM,
               /*128:out  */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_IE,
+              /*256:out  */ -1,
               /*xcpt?    */ true, true },
           { { /*src2     */ { FP32_INF(0),  FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
             { /*src1     */ { FP32_INF(1),  FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
-            { /* =>      */ { FP32_0(0),    FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
+            { /* =>      */ { FP32_QNAN(1), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
               /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,
               /*128:out  */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
+              /*256:out  */ -1,
               /*xcpt?    */ true, true },
           { { /*src2     */ { FP32_INF(1),  FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
@@ -4376,5 +4271,5 @@
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
               /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_INF(0),  FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
@@ -4383,12 +4278,12 @@
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
               /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_INF(0),  FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } },
             { /*src1     */ { FP32_INF(1),  FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
-            { /* =>      */ { FP32_QNAN(0), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
+            { /* =>      */ { FP32_QNAN(1), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
               /*mxcsr:in */ X86_MXCSR_FZ,
               /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_IE,
+              /*256:out  */ -1,
               /*xcpt?    */ true, true },
           { { /*src2     */ { FP32_INF(1),  FP32_0(0), FP32_0(0), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V6(1) } },
@@ -4397,5 +4292,5 @@
               /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
               /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
+              /*256:out  */ -1,
               /*xcpt?    */ true, true },
     /*
@@ -4406,13 +4301,27 @@
             { /* =>      */ { FP32_0(0),        FP32_0(1), FP32_0(1), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1) } },
               /*mxcsr:in */ 0,
-              /*128:out  */ X86_MXCSR_OE,
-              /*256:out  */ X86_MXCSR_OE,
+              /*128:out  */ X86_MXCSR_OE | BS3_MXCSR_OM_FIXED,
+              /*256:out  */ -1,
+              /*xcpt?    */ true, true },
+          { { /*src2     */ { FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V6(1) } },
+            { /*src1     */ { FP32_NORM_MAX(1), FP32_0(1), FP32_0(1), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1) } },
+            { /* =>      */ { FP32_INF(1),      FP32_0(1), FP32_0(1), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1) } },
+              /*mxcsr:in */ X86_MXCSR_OM,
+              /*128:out  */ X86_MXCSR_OM | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_OM_FIXED,
+              /*256:out  */ -1,
               /*xcpt?    */ true, true },
           { { /*src2     */ { FP32_NORM_MAX(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
             { /*src1     */ { FP32_NORM_MAX(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
             { /* =>      */ { FP32_INF(0),      FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
-              /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM,
-              /*128:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
-              /*256:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_OE | BS3_MXCSR_OM_FIXED,
+              /*256:out  */ -1,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_NORM_MAX(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
+            { /*src1     */ { FP32_NORM_MAX(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
+            { /* =>      */ { FP32_INF(0),      FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
+              /*mxcsr:in */ X86_MXCSR_OM,
+              /*128:out  */ X86_MXCSR_OM | X86_MXCSR_PE | X86_MXCSR_OE | BS3_MXCSR_OM_FIXED,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_RAND_V0(1),  FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } },
@@ -4421,12 +4330,19 @@
               /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM,
               /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_PE,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_PE,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_NORM_MAX(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
             { /*src1     */ { FP32_NORM_MAX(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
             { /* =>      */ { FP32_INF(1),      FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
-              /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM,
-              /*128:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
-              /*256:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_OE | BS3_MXCSR_OM_FIXED,
+              /*256:out  */ -1,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_NORM_MAX(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
+            { /*src1     */ { FP32_NORM_MAX(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
+            { /* =>      */ { FP32_INF(1),      FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
+              /*mxcsr:in */ X86_MXCSR_OM,
+              /*128:out  */ X86_MXCSR_OM | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_OM_FIXED,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_NORM_SAFE_INT_MIN(0),                            FP32_RAND_V5(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V3(1), FP32_RAND_V2(1) } },
@@ -4435,5 +4351,5 @@
               /*mxcsr:in */ X86_MXCSR_RC_ZERO,
               /*128:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
-              /*256:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
+              /*256:out  */ -1,
               /*xcpt?    */ true, true },
           { { /*src2     */ { FP32_NORM_SAFE_INT_MIN(1),                            FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
@@ -4442,15 +4358,15 @@
               /*mxcsr:in */ X86_MXCSR_RC_ZERO,
               /*128:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
-              /*256:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
+              /*256:out  */ -1,
               /*xcpt?    */ true, true },
     /*
      * Normals.
      */
-    /*18*/{ { /*src2     */ { FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
+    /*21*/{ { /*src2     */ { FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
             { /*src1     */ { FP32_V(1, 0,        0x7d)/*-0.25*/, FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V0(0), FP32_RAND_V5(1) } },
             { /* =>      */ { FP32_V(0, 0x400000, 0x7f)/* 1.50*/, FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V0(0), FP32_RAND_V5(1) } },
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_NORM_MAX(0), FP32_RAND_V5(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V3(1), FP32_RAND_V2(1) } },
@@ -4459,5 +4375,5 @@
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
               /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
@@ -4466,5 +4382,5 @@
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
               /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
@@ -4473,5 +4389,5 @@
               /*mxcsr:in */ 0,
               /*128:out  */ 0,
-              /*256:out  */ 0,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } },
@@ -4480,5 +4396,5 @@
               /*mxcsr:in */ X86_MXCSR_RC_ZERO,
               /*128:out  */ X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_RC_ZERO,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } },
@@ -4487,5 +4403,5 @@
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
               /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_NORM_SAFE_INT_MAX(0),                                FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } },
@@ -4494,5 +4410,5 @@
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
               /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_V(0, 0x600000, 0x7e)/*      0.875*/, FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } },
@@ -4501,5 +4417,5 @@
               /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
               /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V0(1), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V6(1) } },
@@ -4508,29 +4424,60 @@
               /*mxcsr:in */ X86_MXCSR_FZ,
               /*128:out  */ X86_MXCSR_FZ,
-              /*256:out  */ X86_MXCSR_FZ,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
     /*
      * Denormals.
      */
-    /*27*/{ { /*src2     */ { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(0) } },
+    /*30*/{ { /*src2     */ { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(0) } },
             { /*src1     */ { FP32_0(0),          FP32_RAND_V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0) } },
             { /* =>      */ { FP32_0(0),          FP32_RAND_V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0) } },
-              /*mxcsr:in */ X86_MXCSR_DE,
-              /*128:out  */ X86_MXCSR_DE,
-              /*256:out  */ X86_MXCSR_DE,
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_DE | BS3_MXCSR_DM_FIXED,
+              /*256:out  */ -1,
+              /*xcpt?    */ true, true },
+#ifdef TODO_X86_MXCSR_UE_IEM /** @todo THIS FAILS ON IEM: X86_MXCSR_UE not set in 128:out *AND* different output values */
+ /*--|31*/{ { /*src2     */ { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(0) } },
+            { /*src1     */ { FP32_0(0),          FP32_RAND_V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0) } },
+            { /* =>      */ { FP32_0(0),          FP32_RAND_V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0) } } /* result on HW (i7-10700) */,
+    // IEM: { /* =>      */ { FP32_DENORM_MAX(0), FP32_RAND_V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0) } } /* result on IEM */,
+              /*mxcsr:in */ X86_MXCSR_DM,
+              /*128:out  */ X86_MXCSR_DM | X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED,
+              /*256:out  */ -1,
+              /*xcpt?    */ true, true },
+#endif /* TODO_X86_MXCSR_UE_IEM */
+ /*31|32*/{ { /*src2     */ { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(0) } },
+            { /*src1     */ { FP32_0(0),          FP32_RAND_V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0) } },
+            { /* =>      */ { FP32_DENORM_MAX(0), FP32_RAND_V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0) } },
+              /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_UM,
+              /*128:out  */ X86_MXCSR_DM | X86_MXCSR_UM | X86_MXCSR_DE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED,
+              /*256:out  */ -1,
               /*xcpt?    */ true, true },
           { { /*src2     */ { FP32_0(0),          FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V6(1) } },
             { /*src1     */ { FP32_DENORM_MAX(0), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1) } },
             { /* =>      */ { FP32_0(0),          FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED,
+              /*256:out  */ -1,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_0(0),          FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V6(1) } },
+            { /*src1     */ { FP32_DENORM_MAX(0), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1) } },
+            { /* =>      */ { FP32_0(0),          FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1) } },
+              /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DM | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED,
+              /*256:out  */ -1,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_0(0),          FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V6(1) } },
+            { /*src1     */ { FP32_DENORM_MAX(0), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1) } },
+            { /* =>      */ { FP32_0(0),          FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1) } },
+              /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_UM | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DM | X86_MXCSR_UM | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_DENORM_MIN(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V7(0) } },
             { /*src1     */ { FP32_DENORM_MAX(0), FP32_RAND_V3(1), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V6(1) } },
-            { /* =>      */ { FP32_0(0),          FP32_RAND_V3(1), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V6(1) } },
+            { /* =>      */ { FP32_NORM_MIN(0),   FP32_RAND_V3(1), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V6(1) } },
               /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_DE,
               /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_DE,
-              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_DE,
+              /*256:out  */ -1,
               /*xcpt?    */ true, true },
     /** @todo More denormals etc. */
@@ -4538,5 +4485,5 @@
      * Invalids.
      */
-    /*30*/ FP32_TABLE_D1_SS_INVALIDS
+ /*36|37*/ FP32_TABLE_D1_SS_INVALIDS
     /** @todo Underflow; Precision; Rounding; FZ etc. */
     };
@@ -4577,5 +4524,5 @@
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     unsigned const                         iTest       = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
-    return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+    return bs3CpuInstr4_WorkerTestType1A(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
                                         g_aXcptConfig3, RT_ELEMENTS(g_aXcptConfig3));
 }
@@ -5487,6 +5434,6 @@
  /*--|30*/{ { /*src2     */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0),          FP64_0(0) } },
             { /*src1     */ { FP64_0(0),          FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0) } },
-            { /* =>      */ { FP64_0(0),          FP64_0(0), FP64_0(0),          FP64_0(0) } }, /* result on HW (i7-10700) */
-    // IEM: { /* =>      */ { FP64_0(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_0(0) } }, /* result on IEM */
+            { /* =>      */ { FP64_0(0),          FP64_0(0), FP64_0(0),          FP64_0(0) } } /* result on HW (i7-10700) */,
+    // IEM: { /* =>      */ { FP64_0(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_0(0) } } /* result on IEM */,
               /*mxcsr:in */ X86_MXCSR_DM,
               /*128:out  */ X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED,
@@ -6257,5 +6204,5 @@
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
               /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_0(0), FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
@@ -6264,5 +6211,5 @@
               /*mxcsr:in */ 0,
               /*128:out  */ 0,
-              /*256:out  */ 0,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_0(0), FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
@@ -6271,5 +6218,5 @@
               /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
               /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_0(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
@@ -6278,5 +6225,5 @@
               /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
               /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
@@ -6285,5 +6232,5 @@
               /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_0(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
@@ -6292,5 +6239,5 @@
               /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
     /*
@@ -6302,12 +6249,12 @@
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
               /*128:out  */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
-              /*256:out  */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
-              /*xcpt?    */ false, false },
-          { { /*src2     */ { FP32_INF(0), FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
-            { /*src1     */ { FP32_INF(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
-            { /* =>      */ { FP32_INF(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
+              /*256:out  */ -1,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_INF(0),  FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
+            { /*src1     */ { FP32_INF(0),  FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
+            { /* =>      */ { FP32_QNAN(1), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
               /*mxcsr:in */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM),
               /*128:out  */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_IE,
-              /*256:out  */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_IE,
+              /*256:out  */ -1,
               /*xcpt?    */ true, true },
           { { /*src2     */ { FP32_INF(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
@@ -6316,5 +6263,5 @@
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
               /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_INF(1),  FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
@@ -6323,5 +6270,5 @@
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
               /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_INF(0), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } },
@@ -6330,5 +6277,5 @@
               /*mxcsr:in */ X86_MXCSR_FZ,
               /*128:out  */ X86_MXCSR_FZ,
-              /*256:out  */ X86_MXCSR_FZ,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V6(1) } },
@@ -6337,5 +6284,5 @@
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
               /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
     /*
@@ -6347,26 +6294,47 @@
               /*mxcsr:in */ 0,
               /*128:out  */ 0,
-              /*256:out  */ X86_MXCSR_PE,
+              /*256:out  */ -1,
               /*xcpt?    */ false, true },
           { { /*src2     */ { FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_MAX(0) } },
             { /*src1     */ { FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_MAX(0) } },
             { /* =>      */ { FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0)        } },
-              /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
-              /*256:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | BS3_MXCSR_OM_FIXED,
+              /*256:out  */ -1,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_MAX(0) } },
+            { /*src1     */ { FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_MAX(0) } },
+            { /* =>      */ { FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0)        } },
+              /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_OM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_OM_FIXED,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0) } },
             { /*src1     */ { FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1) } },
             { /* =>      */ { FP32_INF(1),      FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1)      } },
-              /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM,
-              /*128:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
-              /*256:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_OE | BS3_MXCSR_OM_FIXED,
+              /*256:out  */ -1,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0) } },
+            { /*src1     */ { FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1) } },
+            { /* =>      */ { FP32_INF(1),      FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1)      } },
+              /*mxcsr:in */ X86_MXCSR_OM,
+              /*128:out  */ X86_MXCSR_OM | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_OM_FIXED,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
             { /*src1     */ { FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
             { /* =>      */ { FP32_INF(1),      FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM,
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OE | BS3_MXCSR_OM_FIXED,
+              /*256:out  */ -1,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
+            { /*src1     */ { FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
+            { /* =>      */ { FP32_INF(1),      FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_OM_FIXED,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_NORM_MIN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
@@ -6375,43 +6343,50 @@
               /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM,
               /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_PE,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
             { /*src1     */ { FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
             { /* =>      */ { FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
-              /*xcpt?    */ false, false },
-          { { /*src2     */ { FP32_NORM_MIN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | BS3_MXCSR_OM_FIXED,
+              /*256:out  */ -1,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
             { /*src1     */ { FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
-            { /* =>      */ { FP32_0(0),       FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
+            { /* =>      */ { FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
+              /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_OM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_OM_FIXED,
+              /*256:out  */ -1,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_NORM_MIN(1),                                     FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
+            { /*src1     */ { FP32_NORM_MAX(1),                                     FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
+            { /* =>      */ { FP32_V(1, FP32_FRAC_NORM_MAX - 1, FP32_EXP_NORM_MAX), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
               /*mxcsr:in */ X86_MXCSR_RC_ZERO,
               /*128:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
-              /*256:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
-              /*xcpt?    */ true, true },
-          { { /*src2     */ { FP32_NORM_SAFE_INT_MIN(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
-            { /*src1     */ { FP32_NORM_SAFE_INT_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
-            { /* =>      */ { FP32_0(0),                 FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
+              /*256:out  */ -1,
+              /*xcpt?    */ true, true },
+          { { /*src2     */ { FP32_NORM_SAFE_INT_MIN(0),                                FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
+            { /*src1     */ { FP32_NORM_SAFE_INT_MAX(0),                                FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
+            { /* =>      */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
               /*mxcsr:in */ X86_MXCSR_RC_ZERO,
               /*128:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
-              /*256:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
-              /*xcpt?    */ true, true },
-          { { /*src2     */ { FP32_NORM_SAFE_INT_MIN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
-            { /*src1     */ { FP32_NORM_SAFE_INT_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
-            { /* =>      */ { FP32_0(1),                 FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
+              /*256:out  */ -1,
+              /*xcpt?    */ true, true },
+          { { /*src2     */ { FP32_NORM_SAFE_INT_MIN(1),                                FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
+            { /*src1     */ { FP32_NORM_SAFE_INT_MAX(1),                                FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
+            { /* =>      */ { FP32_V(1, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
               /*mxcsr:in */ X86_MXCSR_RC_ZERO,
               /*128:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
-              /*256:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
+              /*256:out  */ -1,
               /*xcpt?    */ true, true },
     /*
      * Normals.
      */
-    /*21*/{ { /*src2     */ { FP32_V(0, 0x600000, 0x7f)/*1.75*/, FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
+    /*25*/{ { /*src2     */ { FP32_V(0, 0x600000, 0x7f)/*1.75*/, FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
             { /*src1     */ { FP32_V(0, 0,        0x7d)/*0.25*/, FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V0(0), FP32_RAND_V5(1) } },
             { /* =>      */ { FP32_V(1, 0x400000, 0x7f)/*1.50*/, FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V0(0), FP32_RAND_V5(1) } },
               /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
               /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_NORM_MAX(1), FP32_RAND_V5(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V3(1), FP32_RAND_V2(1) } },
@@ -6420,5 +6395,5 @@
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
               /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
@@ -6427,5 +6402,5 @@
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
               /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
@@ -6434,5 +6409,5 @@
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
               /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_V(0, 0x712060, 0x92)/*  987654*/, FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } },
@@ -6441,5 +6416,5 @@
               /*mxcsr:in */ 0,
               /*128:out  */ 0,
-              /*256:out  */ 0,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_1(0),                                                FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } },
@@ -6448,12 +6423,5 @@
               /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
               /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*xcpt?    */ false, false },
-          { { /*src2     */ { FP32_1(0),                                                FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } },
-            { /*src1     */ { FP32_NORM_SAFE_INT_MAX(0),                                FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
-            { /* =>      */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_RAND_V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0) } },
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_V(1, 0x600000, 0x7e)/*      -0.875*/, FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1) } },
@@ -6462,5 +6430,5 @@
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
               /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V0(1), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V6(1) } },
@@ -6469,15 +6437,32 @@
               /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
               /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
     /*
      * Denormals.
      */
-    /*27*/{ { /*src2     */ { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(0) } },
+    /*33*/{ { /*src2     */ { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(0) } },
             { /*src1     */ { FP32_0(0),          FP32_RAND_V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0) } },
             { /* =>      */ { FP32_0(0),          FP32_RAND_V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0) } },
               /*mxcsr:in */ 0,
-              /*128:out  */ X86_MXCSR_DE,
-              /*256:out  */ X86_MXCSR_DE,
+              /*128:out  */ X86_MXCSR_DE | BS3_MXCSR_DM_FIXED,
+              /*256:out  */ -1,
+              /*xcpt?    */ true, true },
+#ifdef TODO_X86_MXCSR_UE_IEM /** @todo THIS FAILS ON IEM: X86_MXCSR_UE not set in 128:out *AND* different output values */
+ /*--|34*/{ { /*src2     */ { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(0) } },
+            { /*src1     */ { FP32_0(0),          FP32_RAND_V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0) } },
+            { /* =>      */ { FP32_0(0),          FP32_RAND_V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0) } } /* result on HW (i7-10700) */,
+    // IEM: { /* =>      */ { FP32_DENORM_MAX(1), FP32_RAND_V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0) } } /* result on IEM */,
+              /*mxcsr:in */ X86_MXCSR_DM,
+              /*128:out  */ X86_MXCSR_DM | X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED,
+              /*256:out  */ -1,
+              /*xcpt?    */ true, true },
+#endif /* TODO_X86_MXCSR_UE_IEM */
+ /*34|35*/{ { /*src2     */ { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(0) } },
+            { /*src1     */ { FP32_0(0),          FP32_RAND_V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0) } },
+            { /* =>      */ { FP32_DENORM_MAX(1), FP32_RAND_V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0) } },
+              /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_UM,
+              /*128:out  */ X86_MXCSR_DM | X86_MXCSR_UM | X86_MXCSR_DE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED,
+              /*256:out  */ -1,
               /*xcpt?    */ true, true },
           { { /*src2     */ { FP32_0(0),          FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V6(1) } },
@@ -6486,5 +6471,5 @@
               /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
               /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_DENORM_MIN(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V7(0) } },
@@ -6493,5 +6478,5 @@
               /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
               /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
     /** @todo More denormals. */
@@ -6499,5 +6484,5 @@
      * Invalids.
      */
-    /*30*/ FP32_TABLE_D1_SS_INVALIDS
+ /*37|38*/ FP32_TABLE_D1_SS_INVALIDS
     /** @todo Underflow; Precision; Rounding; FZ etc. */
     };
@@ -6538,5 +6523,5 @@
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     unsigned const                         iTest       = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
-    return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+    return bs3CpuInstr4_WorkerTestType1A(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
                                         g_aXcptConfig3, RT_ELEMENTS(g_aXcptConfig3));
 }
@@ -7429,6 +7414,6 @@
  /*--|24*/{ { /*src2     */ { FP64_DENORM_MAX(0), FP64_0(0),          FP64_DENORM_MAX(0), FP64_0(0)          } },
             { /*src1     */ { FP64_0(0),          FP64_DENORM_MAX(1), FP64_0(0),          FP64_DENORM_MAX(1) } },
-            { /* =>      */ { FP64_0(0),          FP64_0(0),          FP64_0(0),          FP64_0(0)          } }, /* result on HW (i7-10700) */
-    // IEM: { /* =>      */ { FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } }, /* result on IEM */
+            { /* =>      */ { FP64_0(0),          FP64_0(0),          FP64_0(0),          FP64_0(0)          } } /* result on HW (i7-10700) */,
+    // IEM: { /* =>      */ { FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } } /* result on IEM */,
               /*mxcsr:in */ X86_MXCSR_DM,
               /*128:out  */ X86_MXCSR_DM | X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED,
@@ -7460,6 +7445,6 @@
  /*--|28*/{ { /*src2     */ { FP64_DENORM_MAX(0), FP64_0(0),          FP64_0(0),          FP64_0(0) } },
             { /*src1     */ { FP64_0(0),          FP64_0(0),          FP64_DENORM_MIN(0), FP64_0(0) } },
-            { /* =>      */ { FP64_0(0),          FP64_0(0),          FP64_0(0),          FP64_0(0) } }, /* result on HW (i7-10700) */
-    // IEM: { /* =>      */ { FP64_0(0),          FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_0(0) } }, /* result on IEM */
+            { /* =>      */ { FP64_0(0),          FP64_0(0),          FP64_0(0),          FP64_0(0) } } /* result on HW (i7-10700) */,
+    // IEM: { /* =>      */ { FP64_0(0),          FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_0(0) } } /* result on IEM */,
               /*mxcsr:in */ X86_MXCSR_DM,
               /*128:out  */ X86_MXCSR_DM | X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED,
@@ -8245,14 +8230,7 @@
             { /*src1     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
             { /* =>      */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK,
-              /*xcpt?    */ false, false },
-          { { /*src2     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
-            { /*src1     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
-            { /* =>      */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
               /*mxcsr:in */ 0,
               /*128:out  */ 0,
-              /*256:out  */ 0,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
@@ -8261,5 +8239,5 @@
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
               /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_0(0), FP32_NORM_V7(0), FP32_NORM_V6(0), FP32_0(0),       FP32_0(1),       FP32_NORM_V3(0), FP32_0(0),       FP32_0(0)       } },
@@ -8268,5 +8246,5 @@
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_0(1), FP32_0(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
@@ -8275,5 +8253,5 @@
               /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
               /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_0(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
@@ -8282,5 +8260,5 @@
               /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
               /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
@@ -8289,5 +8267,5 @@
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
               /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_0(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
@@ -8296,15 +8274,15 @@
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
     /*
      * Infinity.
      */
-    /* 8*/{ { /*src2     */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
+    /* 7*/{ { /*src2     */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
             { /*src1     */ { FP32_1(1),   FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
             { /* =>      */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
               /*128:out  */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
-              /*256:out  */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
@@ -8313,5 +8291,5 @@
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
               /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_INF(0), FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
@@ -8320,5 +8298,5 @@
               /*mxcsr:in */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_DAZ | X86_MXCSR_FZ,
               /*128:out  */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_DAZ | X86_MXCSR_FZ,
-              /*256:out  */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_DAZ | X86_MXCSR_FZ,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_INF(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
@@ -8327,5 +8305,5 @@
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
               /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_1(0),   FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
@@ -8334,5 +8312,5 @@
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
               /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(1) } },
@@ -8341,5 +8319,5 @@
               /*mxcsr:in */ X86_MXCSR_FZ,
               /*128:out  */ X86_MXCSR_FZ,
-              /*256:out  */ X86_MXCSR_FZ,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_INF(1), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V2(0) } },
@@ -8348,15 +8326,15 @@
               /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
               /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
     /*
      * Normals.
      */
-    /*15*/{ { /*src2     */ { FP32_V(0, 0x600000, 0x7f)/*1.7500*/, FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
+    /*14*/{ { /*src2     */ { FP32_V(0, 0x600000, 0x7f)/*1.7500*/, FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
             { /*src1     */ { FP32_V(0, 0,        0x7d)/*0.2500*/, FP32_RAND_V6(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V2(1) } },
             { /* =>      */ { FP32_V(0, 0x600000, 0x7d)/*0.4375*/, FP32_RAND_V6(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V2(1) } },
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_V(0, 0x61e000, 0x89)/*   1807*/, FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
@@ -8365,5 +8343,5 @@
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
               /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
@@ -8372,5 +8350,5 @@
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
               /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_V(0, 0x61e000, 0x89)/*   1807*/, FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
@@ -8379,5 +8357,5 @@
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
               /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_V(0, 0x4a30b8, 0x8f)/* 103521.4375*/, FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
@@ -8386,5 +8364,5 @@
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
               /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_V(0, 0x1a5200, 0x8c)/*     9876.5*/, FP32_RAND_V6(0), FP32_RAND_V0(1), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V5(1), FP32_RAND_V7(1) } },
@@ -8393,5 +8371,5 @@
               /*mxcsr:in */ 0,
               /*128:out  */ 0,
-              /*256:out  */ 0,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_NORM_MAX(0), FP32_NORM_V1(1), FP32_0(0),       FP32_1(0),       FP32_NORM_MIN(0), FP32_NORM_V1(0), FP32_NORM_V2(0), FP32_0(0)       } },
@@ -8400,5 +8378,5 @@
               /*mxcsr:in */ 0,
               /*128:out  */ 0,
-              /*256:out  */ 0,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_V(0, 0x23b6a0, 0x8e)/*41910.625000*/, FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V2(0) } },
@@ -8407,5 +8385,5 @@
               /*mxcsr:in */ 0,
               /*128:out  */ 0,
-              /*256:out  */ 0,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(0), FP32_1(1), FP32_1(1), FP32_1(0),                                                FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_1(0) } },
@@ -8414,5 +8392,5 @@
               /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
     /** @todo More Normals. */
@@ -8420,17 +8398,17 @@
      * Denormals.
      */
-    /*24*/{ { /*src2     */ { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_1(1),       FP32_RAND_V0(1), FP32_RAND_V5(0), FP32_1(1),       FP32_RAND_V0(1), FP32_RAND_V5(1) } },
+    /*23*/{ { /*src2     */ { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_1(1),       FP32_RAND_V0(1), FP32_RAND_V5(0), FP32_1(1),       FP32_RAND_V0(1), FP32_RAND_V5(1) } },
             { /*src1     */ { FP32_0(0),          FP32_1(0),       FP32_RAND_V3(1), FP32_1(1),       FP32_1(0),       FP32_RAND_V3(1), FP32_1(1),       FP32_1(1)       } },
-            { /* =>      */ { FP32_0(0),          FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V5(0) } },
+            { /* =>      */ { FP32_0(0),          FP32_1(0),       FP32_RAND_V3(1), FP32_1(1),       FP32_1(0),       FP32_RAND_V3(1), FP32_1(1),       FP32_1(1)       } },
               /*mxcsr:in */ 0,
               /*128:out  */ X86_MXCSR_DE,
-              /*256:out  */ X86_MXCSR_DE,
+              /*256:out  */ -1,
               /*xcpt?    */ true, true },
           { { /*src2     */ { FP32_DENORM_MIN(0), FP32_RAND_V5(0), FP32_1(1),       FP32_RAND_V0(1), FP32_RAND_V5(0), FP32_1(1),       FP32_RAND_V0(1), FP32_RAND_V5(1) } },
             { /*src1     */ { FP32_0(0),          FP32_1(0),       FP32_RAND_V3(1), FP32_1(1),       FP32_1(0),       FP32_RAND_V3(1), FP32_1(1),       FP32_1(1)       } },
-            { /* =>      */ { FP32_0(0),          FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V5(0) } },
+            { /* =>      */ { FP32_0(0),          FP32_1(0),       FP32_RAND_V3(1), FP32_1(1),       FP32_1(0),       FP32_RAND_V3(1), FP32_1(1),       FP32_1(1)       } },
               /*mxcsr:in */ 0,
               /*128:out  */ X86_MXCSR_DE,
-              /*256:out  */ X86_MXCSR_DE,
+              /*256:out  */ -1,
               /*xcpt?    */ true, true },
           { { /*src2     */ { FP32_0(0),          FP32_DENORM_MIN(0), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_1(0),       FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_1(0)          } },
@@ -8439,5 +8417,5 @@
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
               /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_DENORM_MIN(0), FP32_1(0),       FP32_DENORM_MAX(0), FP32_DENORM_MAX(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V0(0),    FP32_DENORM_MAX(0) } },
@@ -8446,5 +8424,5 @@
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
               /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
     /** @todo More Denormals. */
@@ -8452,6 +8430,6 @@
      * Invalids.
      */
-    /*28*/ FP32_TABLE_D1_SS_INVALIDS
-    /** @todo Underflow, Precision; Rounding; FZ etc. */
+    /*27*/ FP32_TABLE_D1_SS_INVALIDS
+    /** @todo Overflow, Underflow, Precision; Rounding; FZ etc. */
     };
 
@@ -8491,5 +8469,5 @@
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     unsigned const                         iTest       = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
-    return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+    return bs3CpuInstr4_WorkerTestType1A(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
                                         g_aXcptConfig3, RT_ELEMENTS(g_aXcptConfig3));
 }
@@ -9567,14 +9545,7 @@
             { /*src1     */ { FP32_0(0),    FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
             { /* =>      */ { FP32_QNAN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
-              /*xcpt?    */ false, false },
-          { { /*src2     */ { FP32_0(0),    FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
-            { /*src1     */ { FP32_0(0),    FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
-            { /* =>      */ { FP32_QNAN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
               /*mxcsr:in */ 0,
               /*128:out  */ X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_IE,
+              /*256:out  */ -1,
               /*xcpt?    */ true, true },
           { { /*src2     */ { FP32_0(0),    FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
@@ -9583,5 +9554,5 @@
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
               /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_0(0),    FP32_NORM_V7(0), FP32_NORM_V6(0), FP32_0(0),       FP32_0(1),       FP32_NORM_V3(0), FP32_0(0),       FP32_0(0)       } },
@@ -9590,5 +9561,5 @@
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_0(1),    FP32_0(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
@@ -9597,5 +9568,5 @@
               /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
               /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,
+              /*256:out  */ -1,
               /*xcpt?    */ true, true },
           { { /*src2     */ { FP32_0(1),    FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
@@ -9604,5 +9575,5 @@
               /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
               /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
+              /*256:out  */ -1,
               /*xcpt?    */ true, true },
           { { /*src2     */ { FP32_0(0),    FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
@@ -9611,5 +9582,5 @@
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
               /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_IE,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_0(0),   FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
@@ -9618,15 +9589,15 @@
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_FSW_ZE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_FSW_ZE,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
     /*
      * Infinity.
      */
-    /* 8*/{ { /*src2     */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
+    /* 7*/{ { /*src2     */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
             { /*src1     */ { FP32_1(1),   FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
             { /* =>      */ { FP32_0(1),   FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
               /*128:out  */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
-              /*256:out  */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
@@ -9635,12 +9606,12 @@
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
               /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK,
-              /*xcpt?    */ false, false },
-          { { /*src2     */ { FP32_INF(0), FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
-            { /*src1     */ { FP32_INF(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
-            { /* =>      */ { FP32_INF(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
+              /*256:out  */ -1,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_INF(0),  FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
+            { /*src1     */ { FP32_INF(0),  FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
+            { /* =>      */ { FP32_QNAN(1), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0) } },
               /*mxcsr:in */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_DAZ | X86_MXCSR_FZ,
               /*128:out  */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE,
-              /*256:out  */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE,
+              /*256:out  */ -1,
               /*xcpt?    */ true, true },
           { { /*src2     */ { FP32_INF(1),  FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
@@ -9649,5 +9620,5 @@
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
               /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_1(0),   FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
@@ -9656,5 +9627,5 @@
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
               /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(1) } },
@@ -9663,5 +9634,5 @@
               /*mxcsr:in */ X86_MXCSR_FZ,
               /*128:out  */ X86_MXCSR_FZ,
-              /*256:out  */ X86_MXCSR_FZ,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_INF(1),  FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V2(0) } },
@@ -9670,15 +9641,15 @@
               /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
               /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
+              /*256:out  */ -1,
               /*xcpt?    */ true, true },
     /*
      * Normals.
      */
-    /*15*/{ { /*src2     */ { FP32_V(0, 0x600000, 0x7f)/*1.7500*/, FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
+    /*14*/{ { /*src2     */ { FP32_V(0, 0x600000, 0x7f)/*1.7500*/, FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
             { /*src1     */ { FP32_V(0, 0x600000, 0x7d)/*0.4375*/, FP32_RAND_V6(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V2(1) } },
             { /* =>      */ { FP32_V(0, 0,        0x7d)/*0.2500*/, FP32_RAND_V6(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V2(1) } },
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_V(0, 0x61e000, 0x89)/*   1807*/, FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
@@ -9687,5 +9658,5 @@
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
               /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1) } },
@@ -9694,5 +9665,5 @@
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
               /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_V(0, 0x61e000, 0x89)/*   1807*/, FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
@@ -9701,5 +9672,5 @@
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
               /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_V(0, 0x4a30b8, 0x8f)/* 103521.4375*/, FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1) } },
@@ -9708,5 +9679,5 @@
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
               /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_V(0, 0x1a5200, 0x8c)/*     9876.5*/, FP32_RAND_V6(0), FP32_RAND_V0(1), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V5(1), FP32_RAND_V7(1) } },
@@ -9715,5 +9686,5 @@
               /*mxcsr:in */ 0,
               /*128:out  */ 0,
-              /*256:out  */ 0,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_NORM_MAX(0), FP32_NORM_V1(1), FP32_0(0),       FP32_1(0),       FP32_NORM_MIN(0), FP32_NORM_V1(0), FP32_NORM_V2(0), FP32_0(0)       } },
@@ -9722,5 +9693,5 @@
               /*mxcsr:in */ 0,
               /*128:out  */ 0,
-              /*256:out  */ 0,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_V(0, 0x23b6a0, 0x8e)/*41910.625000*/, FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V2(0) } },
@@ -9729,5 +9700,5 @@
               /*mxcsr:in */ 0,
               /*128:out  */ 0,
-              /*256:out  */ 0,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(0), FP32_1(1), FP32_1(1), FP32_1(0),                                                FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_1(0) } },
@@ -9736,5 +9707,5 @@
               /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
     /** @todo More Normals. */
@@ -9742,10 +9713,10 @@
      * Denormals.
      */
-    /*24*/{ { /*src2     */ { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_1(1),       FP32_RAND_V0(1), FP32_RAND_V5(0), FP32_1(1),       FP32_RAND_V0(1), FP32_RAND_V5(1) } },
+    /*23*/{ { /*src2     */ { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_1(1),       FP32_RAND_V0(1), FP32_RAND_V5(0), FP32_1(1),       FP32_RAND_V0(1), FP32_RAND_V5(1) } },
             { /*src1     */ { FP32_0(0),          FP32_1(0),       FP32_RAND_V3(1), FP32_1(1),       FP32_1(0),       FP32_RAND_V3(1), FP32_1(1),       FP32_1(1)       } },
             { /* =>      */ { FP32_0(0),          FP32_1(0),       FP32_RAND_V3(1), FP32_1(1),       FP32_1(0),       FP32_RAND_V3(1), FP32_1(1),       FP32_1(1)       } },
               /*mxcsr:in */ 0,
               /*128:out  */ X86_MXCSR_DE,
-              /*256:out  */ X86_MXCSR_DE,
+              /*256:out  */ -1,
               /*xcpt?    */ true, true },
           { { /*src2     */ { FP32_0(0),          FP32_RAND_V5(0), FP32_1(1),       FP32_RAND_V0(1), FP32_RAND_V5(0), FP32_1(1),       FP32_RAND_V0(1), FP32_RAND_V5(1) } },
@@ -9754,20 +9725,6 @@
               /*mxcsr:in */ 0,
               /*128:out  */ X86_MXCSR_ZE,
-              /*256:out  */ X86_MXCSR_ZE,
-              /*xcpt?    */ true, true },
-          { { /*src2     */ { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_1(1),       FP32_RAND_V0(1), FP32_RAND_V5(0), FP32_1(1),       FP32_RAND_V0(1), FP32_RAND_V5(1) } },
-            { /*src1     */ { FP32_0(0),          FP32_1(0),       FP32_RAND_V3(1), FP32_1(1),       FP32_1(0),       FP32_RAND_V3(1), FP32_1(1),       FP32_1(1)       } },
-            { /* =>      */ { FP32_0(0),          FP32_1(0),       FP32_RAND_V3(1), FP32_1(1),       FP32_1(0),       FP32_RAND_V3(1), FP32_1(1),       FP32_1(1)       } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
-              /*xcpt?    */ false, false },
-          { { /*src2     */ { FP32_0(0),          FP32_RAND_V5(0), FP32_1(1),       FP32_RAND_V0(1), FP32_RAND_V5(0), FP32_1(1),       FP32_RAND_V0(1), FP32_RAND_V5(1) } },
-            { /*src1     */ { FP32_DENORM_MAX(0), FP32_1(0),       FP32_RAND_V3(1), FP32_1(1),       FP32_1(0),       FP32_RAND_V3(1), FP32_1(1),       FP32_1(1)       } },
-            { /* =>      */ { FP32_INF(0),        FP32_1(0),       FP32_RAND_V3(1), FP32_1(1),       FP32_1(0),       FP32_RAND_V3(1), FP32_1(1),       FP32_1(1)       } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_ZE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_ZE,
-              /*xcpt?    */ false, false },
+              /*256:out  */ -1,
+              /*xcpt?    */ true, true },
           { { /*src2     */ { FP32_0(0),          FP32_DENORM_MIN(0), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_1(0),       FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_1(0)          } },
             { /*src1     */ { FP32_DENORM_MIN(1), FP32_1(0),          FP32_1(0),       FP32_1(0),       FP32_RAND_V2(0), FP32_1(0),          FP32_1(0),          FP32_DENORM_MAX(0) } },
@@ -9775,5 +9732,5 @@
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
               /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_ZE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_ZE,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
           { { /*src2     */ { FP32_DENORM_MIN(0), FP32_1(0),       FP32_DENORM_MAX(0), FP32_DENORM_MAX(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V0(0),    FP32_DENORM_MAX(0) } },
@@ -9782,5 +9739,5 @@
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
               /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,
+              /*256:out  */ -1,
               /*xcpt?    */ false, false },
     /** @todo More Denormals. */
@@ -9788,6 +9745,6 @@
      * Invalids.
      */
-    /*30*/ FP32_TABLE_D1_SS_INVALIDS
-    /** @todo Underflow; Precision; Rounding, FZ etc. */
+    /*27*/ FP32_TABLE_D1_SS_INVALIDS
+    /** @todo Overflow; Underflow; Precision; Rounding, FZ etc. */
     };
 
@@ -9829,5 +9786,5 @@
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     unsigned const                         iTest       = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
-    return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+    return bs3CpuInstr4_WorkerTestType1A(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
                                         g_aXcptConfig3, RT_ELEMENTS(g_aXcptConfig3));
 }
