Changeset 106223 in vbox for trunk/src/VBox/ValidationKit/bootsectors
- Timestamp:
- Oct 7, 2024 9:54:35 AM (4 months ago)
- File:
-
- 1 edited
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- Unmodified
- Added
- Removed
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trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32
r106220 r106223 964 964 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 965 965 /*128:out */ X86_MXCSR_XCPT_MASK, \ 966 /*256:out */ X86_MXCSR_XCPT_MASK,\966 /*256:out */ -1, \ 967 967 /*xcpt? */ false, false }, \ 968 968 { { /*src2 */ { FP64_QNAN_MAX(0), FP64_QNAN_V1(1), FP64_QNAN_V2(0), FP64_INF(0) } }, \ … … 971 971 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 972 972 /*128:out */ X86_MXCSR_XCPT_MASK, \ 973 /*256:out */ X86_MXCSR_XCPT_MASK,\973 /*256:out */ -1, \ 974 974 /*xcpt? */ false, false }, \ 975 975 { { /*src2 */ { FP64_QNAN_V1(0), FP64_QNAN_V1(0), FP64_QNAN_V2(0), FP64_INF(1) } }, \ … … 978 978 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 979 979 /*128:out */ X86_MXCSR_XCPT_MASK, \ 980 /*256:out */ X86_MXCSR_XCPT_MASK,\980 /*256:out */ -1, \ 981 981 /*xcpt? */ false, false }, \ 982 982 /* QNan, SNan (Masked). */ \ … … 986 986 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 987 987 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 988 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,\988 /*256:out */ -1, \ 989 989 /*xcpt? */ false, false }, \ 990 990 { { /*src2 */ { FP64_QNAN_MAX(0), FP64_QNAN_MAX(0), FP64_QNAN_V0(0), FP64_QNAN_V1(0) } }, \ … … 993 993 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 994 994 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 995 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,\995 /*256:out */ -1, \ 996 996 /*xcpt? */ false, false }, \ 997 997 { { /*src2 */ { FP64_QNAN_V1(0), FP64_QNAN_MAX(0), FP64_QNAN_V0(0), FP64_INF(0) } }, \ … … 1000 1000 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1001 1001 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1002 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,\1002 /*256:out */ -1, \ 1003 1003 /*xcpt? */ false, false }, \ 1004 1004 /* SNan, QNan (Masked). */ \ … … 1008 1008 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1009 1009 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1010 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,\1010 /*256:out */ -1, \ 1011 1011 /*xcpt? */ false, false }, \ 1012 1012 { { /*src2 */ { FP64_SNAN_MAX(0), FP64_SNAN_MAX(1), FP64_SNAN_V1(0), FP64_SNAN_V1(0) } }, \ … … 1015 1015 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1016 1016 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1017 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,\1017 /*256:out */ -1, \ 1018 1018 /*xcpt? */ false, false }, \ 1019 1019 { { /*src2 */ { FP64_SNAN_V0(0), FP64_SNAN_MAX(0), FP64_SNAN_V1(0), FP64_SNAN_V1(0) } }, \ … … 1022 1022 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1023 1023 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1024 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,\1024 /*256:out */ -1, \ 1025 1025 /*xcpt? */ false, false }, \ 1026 1026 /* SNan, SNan (Masked). */ \ … … 1030 1030 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1031 1031 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1032 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,\1032 /*256:out */ -1, \ 1033 1033 /*xcpt? */ false, false }, \ 1034 1034 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V2(0), FP64_SNAN_V1(0), FP64_SNAN_V2(0) } }, \ … … 1037 1037 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1038 1038 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1039 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,\1039 /*256:out */ -1, \ 1040 1040 /*xcpt? */ false, false }, \ 1041 1041 { { /*src2 */ { FP64_SNAN_V1(0), FP64_SNAN_V2(0), FP64_SNAN_V1(0), FP64_SNAN_V2(0) } }, \ … … 1044 1044 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1045 1045 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1046 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,\1046 /*256:out */ -1, \ 1047 1047 /*xcpt? */ false, false }, \ 1048 1048 /* QNan, Norm FP (Masked). */ \ … … 1052 1052 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1053 1053 /*128:out */ X86_MXCSR_XCPT_MASK, \ 1054 /*256:out */ X86_MXCSR_XCPT_MASK,\1054 /*256:out */ -1, \ 1055 1055 /*xcpt? */ false, false }, \ 1056 1056 /* SNan, Norm FP (Masked). */ \ … … 1060 1060 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, \ 1061 1061 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE, \ 1062 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,\1062 /*256:out */ -1, \ 1063 1063 /*xcpt? */ false, false }, \ 1064 1064 /* QNan, QNan (Unmasked). */ \ … … 1068 1068 /*mxcsr:in */ 0, \ 1069 1069 /*128:out */ 0, \ 1070 /*256:out */ 0,\1070 /*256:out */ -1, \ 1071 1071 /*xcpt? */ false, false }, \ 1072 1072 { { /*src2 */ { FP64_QNAN_MAX(0), FP64_QNAN_V1(0), FP64_QNAN_V2(0), FP64_QNAN_V3(0) } }, \ … … 1075 1075 /*mxcsr:in */ 0, \ 1076 1076 /*128:out */ 0, \ 1077 /*256:out */ 0,\1077 /*256:out */ -1, \ 1078 1078 /*xcpt? */ false, false }, \ 1079 1079 { { /*src2 */ { FP64_QNAN_V1(0), FP64_QNAN_V1(0), FP64_QNAN_V2(0), FP64_QNAN_V3(0) } }, \ … … 1082 1082 /*mxcsr:in */ 0, \ 1083 1083 /*128:out */ 0, \ 1084 /*256:out */ 0,\1084 /*256:out */ -1, \ 1085 1085 /*xcpt? */ false, false }, \ 1086 \1087 1086 /* QNan, SNan (Unmasked). */ \ 1088 1087 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_V1(0), FP64_QNAN_V2(0), FP64_QNAN_V3(0) } }, \ 1089 1088 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V2(1), FP64_SNAN_V3(1), FP64_SNAN_V2(0) } }, \ 1090 { /* => */ { FP64_QNAN_V(0, 1), FP64_ QNAN_V2(1), FP64_SNAN_V3(1), FP64_SNAN_V2(0) } }, \1089 { /* => */ { FP64_QNAN_V(0, 1), FP64_SNAN_V2(1), FP64_SNAN_V3(1), FP64_SNAN_V2(0) } }, \ 1091 1090 /*mxcsr:in */ 0, \ 1092 1091 /*128:out */ X86_MXCSR_IE, \ 1093 /*256:out */ X86_MXCSR_IE,\1092 /*256:out */ -1, \ 1094 1093 /*xcpt? */ true, true }, \ 1095 1094 { { /*src2 */ { FP64_QNAN_MAX(0), FP64_QNAN_MAX(0), FP64_QNAN_V0(0), FP64_QNAN_V1(0) } }, \ … … 1098 1097 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, \ 1099 1098 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, \ 1100 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,\1099 /*256:out */ -1, \ 1101 1100 /*xcpt? */ true, true }, \ 1102 1101 { { /*src2 */ { FP64_QNAN_V1(0), FP64_QNAN_MAX(0), FP64_QNAN_V0(0), FP64_QNAN_V1(0) } }, \ … … 1105 1104 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, \ 1106 1105 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, \ 1107 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,\1106 /*256:out */ -1, \ 1108 1107 /*xcpt? */ true, true }, \ 1109 1108 /* SNan, QNan (Unmasked). */ \ … … 1113 1112 /*mxcsr:in */ X86_MXCSR_DAZ, \ 1114 1113 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_IE, \ 1115 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_IE,\1114 /*256:out */ -1, \ 1116 1115 /*xcpt? */ true, true }, \ 1117 1116 { { /*src2 */ { FP64_SNAN_MAX(0), FP64_SNAN_MAX(0), FP64_SNAN_V1(0), FP64_SNAN_V1(1) } }, \ … … 1120 1119 /*mxcsr:in */ X86_MXCSR_RC_UP, \ 1121 1120 /*128:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE, \ 1122 /*256:out */ X86_MXCSR_RC_UP | X86_MXCSR_IE,\1121 /*256:out */ -1, \ 1123 1122 /*xcpt? */ true, true }, \ 1124 1123 { { /*src2 */ { FP64_SNAN_V0(0), FP64_SNAN_MAX(0), FP64_SNAN_V1(0), FP64_SNAN_V1(1) } }, \ … … 1127 1126 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, \ 1128 1127 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, \ 1129 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,\1128 /*256:out */ -1, \ 1130 1129 /*xcpt? */ true, true }, \ 1131 1130 /* SNan, SNan (Unmasked). */ \ … … 1135 1134 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, \ 1136 1135 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE, \ 1137 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE,\1136 /*256:out */ -1, \ 1138 1137 /*xcpt? */ true, true }, \ 1139 1138 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V2(0), FP64_SNAN_V1(0), FP64_SNAN_V2(1) } }, \ … … 1142 1141 /*mxcsr:in */ X86_MXCSR_RC_ZERO, \ 1143 1142 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE, \ 1144 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE,\1143 /*256:out */ -1, \ 1145 1144 /*xcpt? */ true, true }, \ 1146 1145 { { /*src2 */ { FP64_SNAN_V1(0), FP64_SNAN_V2(0), FP64_SNAN_V0(1), FP64_SNAN_V2(0) } }, \ … … 1149 1148 /*mxcsr:in */ 0, \ 1150 1149 /*128:out */ X86_MXCSR_IE, \ 1151 /*256:out */ X86_MXCSR_IE,\1150 /*256:out */ -1, \ 1152 1151 /*xcpt? */ true, true }, \ 1153 1152 /* QNan, Norm FP (Unmasked). */ \ … … 1157 1156 /*mxcsr:in */ X86_MXCSR_FZ, \ 1158 1157 /*128:out */ X86_MXCSR_FZ, \ 1159 /*256:out */ X86_MXCSR_FZ,\1158 /*256:out */ -1, \ 1160 1159 /*xcpt? */ false, false }, \ 1161 1160 /* SNan, Norm FP (Unmasked). */ \ … … 1165 1164 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, \ 1166 1165 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, \ 1167 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,\1166 /*256:out */ -1, \ 1168 1167 /*xcpt? */ true, true }, \ 1169 1168 … … 4544 4543 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 4545 4544 /*128:out */ X86_MXCSR_XCPT_MASK, 4546 /*256:out */ X86_MXCSR_XCPT_MASK,4545 /*256:out */ -1, 4547 4546 /*xcpt? */ false, false }, 4548 4547 { { /*src2 */ { FP64_0(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, … … 4551 4550 /*mxcsr:in */ 0, 4552 4551 /*128:out */ 0, 4553 /*256:out */ 0,4552 /*256:out */ -1, 4554 4553 /*xcpt? */ false, false }, 4555 4554 { { /*src2 */ { FP64_0(0), FP64_RAND_V1(0), FP64_RAND_V2(0), FP64_RAND_V0(1) } }, … … 4558 4557 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 4559 4558 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 4560 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,4559 /*256:out */ -1, 4561 4560 /*xcpt? */ false, false }, 4562 4561 { { /*src2 */ { FP64_0(1), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, … … 4565 4564 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 4566 4565 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 4567 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,4566 /*256:out */ -1, 4568 4567 /*xcpt? */ false, false }, 4569 4568 { { /*src2 */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, … … 4572 4571 /*mxcsr:in */ X86_MXCSR_FZ, 4573 4572 /*128:out */ X86_MXCSR_FZ, 4574 /*256:out */ X86_MXCSR_FZ,4573 /*256:out */ -1, 4575 4574 /*xcpt? */ false, false }, 4576 4575 { { /*src2 */ { FP64_0(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, … … 4579 4578 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN, 4580 4579 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN, 4581 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN,4580 /*256:out */ -1, 4582 4581 /*xcpt? */ false, false }, 4583 4582 /* … … 4586 4585 /* 6*/{ { /*src2 */ { FP64_INF(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 4587 4586 { /*src1 */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, 4588 { /* => */ { FP64_ 0(0),FP64_0(0), FP64_0(0), FP64_0(0) } },4587 { /* => */ { FP64_QNAN(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, 4589 4588 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM, 4590 4589 /*128:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_IE, 4591 /*256:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_IE,4590 /*256:out */ -1, 4592 4591 /*xcpt? */ true, true }, 4593 4592 { { /*src2 */ { FP64_INF(0), FP64_RAND_V1(0), FP64_RAND_V2(0), FP32_RAND_V3(1) } }, 4594 4593 { /*src1 */ { FP64_INF(1), FP64_RAND_V0(0), FP64_RAND_V1(1), FP32_RAND_V1(1) } }, 4595 { /* => */ { FP64_ 0(0),FP64_RAND_V0(0), FP64_RAND_V1(1), FP32_RAND_V1(1) } },4594 { /* => */ { FP64_QNAN(1), FP64_RAND_V0(0), FP64_RAND_V1(1), FP32_RAND_V1(1) } }, 4596 4595 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO, 4597 4596 /*128:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 4598 /*256:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,4597 /*256:out */ -1, 4599 4598 /*xcpt? */ true, true }, 4600 4599 { { /*src2 */ { FP64_INF(1), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, … … 4603 4602 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 4604 4603 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, 4605 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,4604 /*256:out */ -1, 4606 4605 /*xcpt? */ false, false }, 4607 4606 { { /*src2 */ { FP64_INF(0), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, … … 4610 4609 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, 4611 4610 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, 4612 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,4611 /*256:out */ -1, 4613 4612 /*xcpt? */ false, false }, 4614 4613 { { /*src2 */ { FP64_INF(0), FP64_RAND_V0(0), FP64_RAND_V0(0), FP64_RAND_V0(1) } }, 4615 4614 { /*src1 */ { FP64_INF(1), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V1(0) } }, 4616 { /* => */ { FP64_QNAN( 0), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V1(0) } },4615 { /* => */ { FP64_QNAN(1), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V1(0) } }, 4617 4616 /*mxcsr:in */ X86_MXCSR_FZ, 4618 4617 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_IE, 4619 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_IE,4618 /*256:out */ -1, 4620 4619 /*xcpt? */ true, true }, 4621 4620 { { /*src2 */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_RAND_V1(1) } }, … … 4624 4623 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 4625 4624 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 4626 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,4625 /*256:out */ -1, 4627 4626 /*xcpt? */ true, true }, 4628 4627 /* … … 4631 4630 /*12*/{ { /*src2 */ { FP64_NORM_MAX(1), FP64_0(0), FP64_0(0), FP64_RAND_V1(1) } }, 4632 4631 { /*src1 */ { FP64_NORM_MAX(1), FP64_0(1), FP64_0(1), FP64_RAND_V1(1) } }, 4633 { /* => */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_RAND_V1(1) } }, 4634 /*mxcsr:in */ 0, 4635 /*128:out */ X86_MXCSR_OE, 4636 /*256:out */ X86_MXCSR_OE, 4632 { /* => */ { FP64_INF(1), FP64_0(1), FP64_0(1), FP64_RAND_V1(1) } }, 4633 /*mxcsr:in */ 0, 4634 /*128:out */ X86_MXCSR_OE | BS3_MXCSR_OM_FIXED, 4635 /*256:out */ -1, 4636 /*xcpt? */ true, true }, 4637 { { /*src2 */ { FP64_NORM_MAX(1), FP64_0(0), FP64_0(0), FP64_RAND_V1(1) } }, 4638 { /*src1 */ { FP64_NORM_MAX(1), FP64_0(1), FP64_0(1), FP64_RAND_V1(1) } }, 4639 { /* => */ { FP64_INF(1), FP64_0(1), FP64_0(1), FP64_RAND_V1(1) } }, 4640 /*mxcsr:in */ X86_MXCSR_OM, 4641 /*128:out */ X86_MXCSR_OM | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_OM_FIXED, 4642 /*256:out */ -1, 4637 4643 /*xcpt? */ true, true }, 4638 4644 { { /*src2 */ { FP64_NORM_MAX(0), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V0(1) } }, 4639 4645 { /*src1 */ { FP64_NORM_MAX(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, 4640 4646 { /* => */ { FP64_INF(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, 4641 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM, 4642 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, 4643 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, 4647 /*mxcsr:in */ 0, 4648 /*128:out */ X86_MXCSR_OE | BS3_MXCSR_OM_FIXED, 4649 /*256:out */ -1, 4650 /*xcpt? */ false, false }, 4651 { { /*src2 */ { FP64_NORM_MAX(0), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V0(1) } }, 4652 { /*src1 */ { FP64_NORM_MAX(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, 4653 { /* => */ { FP64_INF(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, 4654 /*mxcsr:in */ X86_MXCSR_OM, 4655 /*128:out */ X86_MXCSR_OM | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_OM_FIXED, 4656 /*256:out */ -1, 4644 4657 /*xcpt? */ false, false }, 4645 4658 { { /*src2 */ { FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V1(0), FP64_RAND_V3(1) } }, … … 4648 4661 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM, 4649 4662 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_PE, 4650 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_PE,4663 /*256:out */ -1, 4651 4664 /*xcpt? */ false, false }, 4652 4665 { { /*src2 */ { FP64_NORM_MAX(1), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V0(1) } }, 4653 4666 { /*src1 */ { FP64_NORM_MAX(1), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, 4654 4667 { /* => */ { FP64_INF(1), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, 4655 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM, 4656 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, 4657 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, 4668 /*mxcsr:in */ 0, 4669 /*128:out */ X86_MXCSR_OE | BS3_MXCSR_OM_FIXED, 4670 /*256:out */ -1, 4671 /*xcpt? */ false, false }, 4672 { { /*src2 */ { FP64_NORM_MAX(1), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V0(1) } }, 4673 { /*src1 */ { FP64_NORM_MAX(1), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, 4674 { /* => */ { FP64_INF(1), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, 4675 /*mxcsr:in */ X86_MXCSR_OM, 4676 /*128:out */ X86_MXCSR_OM | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_OM_FIXED, 4677 /*256:out */ -1, 4658 4678 /*xcpt? */ false, false }, 4659 4679 { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0), FP64_RAND_V0(1) } }, … … 4662 4682 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 4663 4683 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, 4664 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,4684 /*256:out */ -1, 4665 4685 /*xcpt? */ true, true }, 4666 4686 { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(1), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, … … 4669 4689 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 4670 4690 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, 4671 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,4691 /*256:out */ -1, 4672 4692 /*xcpt? */ true, true }, 4673 4693 /* 4674 4694 * Normals. 4675 4695 */ 4676 /*1 8*/{ { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_V1(0), FP64_0(0), FP64_SNAN(0) } },4696 /*19*/{ { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_V1(0), FP64_0(0), FP64_SNAN(0) } }, 4677 4697 { /*src1 */ { FP64_NORM_MAX(1), FP64_NORM_V1(1), FP64_0(0), FP64_SNAN(1) } }, 4678 4698 { /* => */ { FP64_0(0), FP64_NORM_V1(1), FP64_0(0), FP64_SNAN(1) } }, 4679 4699 /*mxcsr:in */ 0, 4680 4700 /*128:out */ 0, 4681 /*256:out */ 0,4701 /*256:out */ -1, 4682 4702 /*xcpt? */ false, false }, 4683 4703 { { /*src2 */ { FP64_V(0, 0, 0x409)/*1024*/, FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V0(1) } }, … … 4686 4706 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 4687 4707 /*128:out */ X86_MXCSR_XCPT_MASK, 4688 /*256:out */ X86_MXCSR_XCPT_MASK,4708 /*256:out */ -1, 4689 4709 /*xcpt? */ false, false }, 4690 4710 { { /*src2 */ { FP64_V(0, 0xb800000000000, 0x404)/*55*/, FP64_RAND_V2(1), FP64_RAND_V1(0), FP64_RAND_V0(1) } }, … … 4693 4713 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 4694 4714 /*128:out */ X86_MXCSR_XCPT_MASK, 4695 /*256:out */ X86_MXCSR_XCPT_MASK,4715 /*256:out */ -1, 4696 4716 /*xcpt? */ false, false }, 4697 4717 { { /*src2 */ { FP64_V(0, 0x26580b4800000, 0x41d)/* 1234567890*/, FP64_RAND_V0(1), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, … … 4700 4720 /*mxcsr:in */ 0, 4701 4721 /*128:out */ 0, 4702 /*256:out */ 0,4722 /*256:out */ -1, 4703 4723 /*xcpt? */ false, false }, 4704 4724 { { /*src2 */ { FP64_V(0, 0xd6f3458800000, 0x41c)/*987654321*/, FP64_RAND_V2(1), FP64_RAND_V1(0), FP64_RAND_V0(1) } }, … … 4707 4727 /*mxcsr:in */ 0, 4708 4728 /*128:out */ 0, 4709 /*256:out */ 0,4729 /*256:out */ -1, 4710 4730 /*xcpt? */ false, false }, 4711 4731 { { /*src2 */ { FP64_V(0, 0xcf0033a34f337, 0x432)/*4072598000007579.5*/, FP64_RAND_V0(1), FP64_RAND_V2(0), FP64_RAND_V0(1) } }, … … 4714 4734 /*mxcsr:in */ 0, 4715 4735 /*128:out */ 0, 4716 /*256:out */ 0,4736 /*256:out */ -1, 4717 4737 /*xcpt? */ false, false }, 4718 4738 { { /*src2 */ { FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_RAND_V1(0), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, … … 4721 4741 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 4722 4742 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 4723 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,4743 /*256:out */ -1, 4724 4744 /*xcpt? */ false, false }, 4725 4745 { { /*src2 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(0) } }, … … 4728 4748 /*mxcsr:in */ X86_MXCSR_FZ, 4729 4749 /*128:out */ X86_MXCSR_FZ, 4730 /*256:out */ X86_MXCSR_FZ,4750 /*256:out */ -1, 4731 4751 /*xcpt? */ false, false }, 4732 4752 { { /*src2 */ { FP64_1(1), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, … … 4735 4755 /*mxcsr:in */ X86_MXCSR_FZ, 4736 4756 /*128:out */ X86_MXCSR_FZ, 4737 /*256:out */ X86_MXCSR_FZ,4757 /*256:out */ -1, 4738 4758 /*xcpt? */ false, false }, 4739 4759 { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_RAND_V2(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, … … 4742 4762 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 4743 4763 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 4744 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,4764 /*256:out */ -1, 4745 4765 /*xcpt? */ false, false }, 4746 4766 { { /*src2 */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, … … 4749 4769 /*mxcsr:in */ X86_MXCSR_RC_UP, 4750 4770 /*128:out */ X86_MXCSR_RC_UP, 4751 /*256:out */ X86_MXCSR_RC_UP,4771 /*256:out */ -1, 4752 4772 /*xcpt? */ false, false }, 4753 4773 /* 4754 4774 * Denormals. 4755 4775 */ 4756 /* 29*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_SNAN(0), FP64_SNAN(0), FP64_QNAN(0) } },4776 /*32*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_SNAN(0), FP64_SNAN(0), FP64_QNAN(0) } }, 4757 4777 { /*src1 */ { FP64_0(0), FP64_SNAN(0), FP64_QNAN(1), FP64_SNAN(1) } }, 4758 4778 { /* => */ { FP64_0(0), FP64_SNAN(0), FP64_QNAN(1), FP64_SNAN(1) } }, 4759 4779 /*mxcsr:in */ 0, 4760 /*128:out */ X86_MXCSR_DE, 4761 /*256:out */ X86_MXCSR_DE, 4780 /*128:out */ X86_MXCSR_DE | BS3_MXCSR_DM_FIXED, 4781 /*256:out */ -1, 4782 /*xcpt? */ true, true }, 4783 #ifdef TODO_X86_MXCSR_UE_IEM /** @todo THIS FAILS ON IEM: X86_MXCSR_UE not set in 128:out *AND* different output values */ 4784 /*--|33*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_SNAN(0), FP64_SNAN(0), FP64_QNAN(0) } }, 4785 { /*src1 */ { FP64_0(0), FP64_SNAN(0), FP64_QNAN(1), FP64_SNAN(1) } }, 4786 { /* => */ { FP64_0(0), FP64_SNAN(0), FP64_QNAN(1), FP64_SNAN(1) } } /* result on HW (i7-10700) */, 4787 // IEM: { /* => */ { FP64_DENORM_MAX(0), FP64_SNAN(0), FP64_QNAN(1), FP64_SNAN(1) } } /* result on IEM */, 4788 /*mxcsr:in */ X86_MXCSR_DM, 4789 /*128:out */ X86_MXCSR_DM | X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 4790 /*256:out */ -1, 4791 /*xcpt? */ true, true }, 4792 #endif /* TODO_X86_MXCSR_UE_IEM */ 4793 /*33|34*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_SNAN(0), FP64_SNAN(0), FP64_QNAN(0) } }, 4794 { /*src1 */ { FP64_0(0), FP64_SNAN(0), FP64_QNAN(1), FP64_SNAN(1) } }, 4795 { /* => */ { FP64_DENORM_MAX(0), FP64_SNAN(0), FP64_QNAN(1), FP64_SNAN(1) } }, 4796 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_UM, 4797 /*128:out */ X86_MXCSR_DM | X86_MXCSR_UM | X86_MXCSR_DE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 4798 /*256:out */ -1, 4762 4799 /*xcpt? */ true, true }, 4763 4800 { { /*src2 */ { FP64_0(0), FP64_SNAN(1), FP64_INF(0), FP64_SNAN(0) } }, 4764 4801 { /*src1 */ { FP64_DENORM_MAX(0), FP64_INF(0), FP64_SNAN(1), FP64_QNAN(0) } }, 4765 4802 { /* => */ { FP64_DENORM_MAX(0), FP64_INF(0), FP64_SNAN(1), FP64_QNAN(0) } }, 4766 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 4767 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, 4768 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, 4803 /*mxcsr:in */ 0, 4804 /*128:out */ X86_MXCSR_DE | BS3_MXCSR_DM_FIXED, 4805 /*256:out */ -1, 4806 /*xcpt? */ false, false }, 4807 #ifdef TODO_X86_MXCSR_UE_IEM /** @todo THIS FAILS ON IEM: X86_MXCSR_UE not set in 128:out */ 4808 /*--|36*/{ { /*src2 */ { FP64_0(0), FP64_SNAN(1), FP64_INF(0), FP64_SNAN(0) } }, 4809 { /*src1 */ { FP64_DENORM_MAX(0), FP64_INF(0), FP64_SNAN(1), FP64_QNAN(0) } }, 4810 { /* => */ { FP64_DENORM_MAX(0), FP64_INF(0), FP64_SNAN(1), FP64_QNAN(0) } }, 4811 /*mxcsr:in */ X86_MXCSR_DM, 4812 /*128:out */ X86_MXCSR_DM | X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 4813 /*256:out */ -1, 4814 /*xcpt? */ false, false }, 4815 #endif /* TODO_X86_MXCSR_UE_IEM */ 4816 /*35|37*/{ { /*src2 */ { FP64_0(0), FP64_SNAN(1), FP64_INF(0), FP64_SNAN(0) } }, 4817 { /*src1 */ { FP64_DENORM_MAX(0), FP64_INF(0), FP64_SNAN(1), FP64_QNAN(0) } }, 4818 { /* => */ { FP64_DENORM_MAX(0), FP64_INF(0), FP64_SNAN(1), FP64_QNAN(0) } }, 4819 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_UM, 4820 /*128:out */ X86_MXCSR_DM | X86_MXCSR_UM | X86_MXCSR_DE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 4821 /*256:out */ -1, 4769 4822 /*xcpt? */ false, false }, 4770 4823 { { /*src2 */ { FP64_DENORM_MIN(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } }, … … 4773 4826 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 4774 4827 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 4775 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,4828 /*256:out */ -1, 4776 4829 /*xcpt? */ false, false }, 4777 4830 /** @todo More Denormals. */ … … 4779 4832 * Invalids. 4780 4833 */ 4781 /*32*/ FP64_TABLE_D1_SD_INVALIDS4834 /*37|39*/ FP64_TABLE_D1_SD_INVALIDS 4782 4835 /** @todo Underflow, Precision; Rounding; FZ etc. */ 4783 4836 }; … … 4818 4871 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 4819 4872 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode); 4820 return bs3CpuInstr4_WorkerTestType1 (bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,4873 return bs3CpuInstr4_WorkerTestType1A(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 4821 4874 g_aXcptConfig3, RT_ELEMENTS(g_aXcptConfig3)); 4822 4875 } … … 6543 6596 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 6544 6597 /*128:out */ X86_MXCSR_XCPT_MASK, 6545 /*256:out */ X86_MXCSR_XCPT_MASK,6598 /*256:out */ -1, 6546 6599 /*xcpt? */ false, false }, 6547 6600 { { /*src2 */ { FP64_0(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, … … 6550 6603 /*mxcsr:in */ 0, 6551 6604 /*128:out */ 0, 6552 /*256:out */ 0,6605 /*256:out */ -1, 6553 6606 /*xcpt? */ false, false }, 6554 6607 { { /*src2 */ { FP64_0(0), FP64_RAND_V1(0), FP64_RAND_V2(0), FP64_RAND_V0(1) } }, … … 6557 6610 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 6558 6611 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 6559 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,6612 /*256:out */ -1, 6560 6613 /*xcpt? */ false, false }, 6561 6614 { { /*src2 */ { FP64_0(1), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, … … 6564 6617 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 6565 6618 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 6566 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,6619 /*256:out */ -1, 6567 6620 /*xcpt? */ false, false }, 6568 6621 { { /*src2 */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, … … 6571 6624 /*mxcsr:in */ X86_MXCSR_FZ, 6572 6625 /*128:out */ X86_MXCSR_FZ, 6573 /*256:out */ X86_MXCSR_FZ,6626 /*256:out */ -1, 6574 6627 /*xcpt? */ false, false }, 6575 6628 { { /*src2 */ { FP64_0(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, … … 6578 6631 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN, 6579 6632 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN, 6580 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN,6633 /*256:out */ -1, 6581 6634 /*xcpt? */ false, false }, 6582 6635 /* 6583 6636 * Infinity. 6584 6637 */ 6585 /* 6*/{ { /*src2 */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_0(0) } },6586 { /*src1 */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_0(0) } },6587 { /* => */ { FP64_ 0(0),FP64_0(0), FP64_0(0), FP64_0(0) } },6638 /* 6*/{ { /*src2 */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, 6639 { /*src1 */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, 6640 { /* => */ { FP64_QNAN(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, 6588 6641 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM, 6589 6642 /*128:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_IE, 6590 /*256:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_IE,6591 /*xcpt? */ true, true }, 6592 { { /*src2 */ { FP64_INF(1), FP64_RAND_V1(0), FP64_RAND_V2(0), FP32_RAND_V3(1) } },6593 { /*src1 */ { FP64_INF(1), FP64_RAND_V0(0), FP64_RAND_V1(1), FP32_RAND_V1(1) } },6594 { /* => */ { FP64_ 0(0),FP64_RAND_V0(0), FP64_RAND_V1(1), FP32_RAND_V1(1) } },6643 /*256:out */ -1, 6644 /*xcpt? */ true, true }, 6645 { { /*src2 */ { FP64_INF(1), FP64_RAND_V1(0), FP64_RAND_V2(0), FP32_RAND_V3(1) } }, 6646 { /*src1 */ { FP64_INF(1), FP64_RAND_V0(0), FP64_RAND_V1(1), FP32_RAND_V1(1) } }, 6647 { /* => */ { FP64_QNAN(1), FP64_RAND_V0(0), FP64_RAND_V1(1), FP32_RAND_V1(1) } }, 6595 6648 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO, 6596 6649 /*128:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 6597 /*256:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,6650 /*256:out */ -1, 6598 6651 /*xcpt? */ true, true }, 6599 6652 { { /*src2 */ { FP64_INF(1), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, … … 6602 6655 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 6603 6656 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, 6604 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,6657 /*256:out */ -1, 6605 6658 /*xcpt? */ false, false }, 6606 6659 { { /*src2 */ { FP64_INF(1), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, … … 6609 6662 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, 6610 6663 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, 6611 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,6664 /*256:out */ -1, 6612 6665 /*xcpt? */ false, false }, 6613 6666 { { /*src2 */ { FP64_INF(1), FP64_RAND_V0(0), FP64_RAND_V0(0), FP64_RAND_V0(1) } }, 6614 6667 { /*src1 */ { FP64_INF(1), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V1(0) } }, 6615 { /* => */ { FP64_QNAN( 0), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V1(0) } },6668 { /* => */ { FP64_QNAN(1), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V1(0) } }, 6616 6669 /*mxcsr:in */ X86_MXCSR_FZ, 6617 6670 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_IE, 6618 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_IE,6671 /*256:out */ -1, 6619 6672 /*xcpt? */ true, true }, 6620 6673 { { /*src2 */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_RAND_V1(1) } }, … … 6623 6676 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 6624 6677 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 6625 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,6678 /*256:out */ -1, 6626 6679 /*xcpt? */ true, true }, 6627 6680 { { /*src2 */ { FP64_INF(0), FP64_0(0), FP64_0(0), FP64_RAND_V1(1) } }, … … 6630 6683 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 6631 6684 /*128:out */ X86_MXCSR_XCPT_MASK, 6632 /*256:out */ X86_MXCSR_XCPT_MASK,6685 /*256:out */ -1, 6633 6686 /*xcpt? */ false, false }, 6634 6687 { { /*src2 */ { FP64_INF(1), FP64_RAND_V1(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } }, … … 6637 6690 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 6638 6691 /*128:out */ X86_MXCSR_XCPT_MASK, 6639 /*256:out */ X86_MXCSR_XCPT_MASK,6692 /*256:out */ -1, 6640 6693 /*xcpt? */ false, false }, 6641 6694 /* … … 6644 6697 /*14*/{ { /*src2 */ { FP64_NORM_MIN(1), FP64_RAND_V1(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } }, 6645 6698 { /*src1 */ { FP64_NORM_MAX(0), FP64_RAND_V0(1), FP64_RAND_V2(1), FP64_RAND_V1(0) } }, 6646 { /* => */ { FP64_ 0(0),FP64_RAND_V0(1), FP64_RAND_V2(1), FP64_RAND_V1(0) } },6699 { /* => */ { FP64_NORM_MAX(0), FP64_RAND_V0(1), FP64_RAND_V2(1), FP64_RAND_V1(0) } }, 6647 6700 /*mxcsr:in */ 0, 6648 6701 /*128:out */ X86_MXCSR_PE, 6649 /*256:out */ X86_MXCSR_PE,6702 /*256:out */ -1, 6650 6703 /*xcpt? */ true, true }, 6651 6704 { { /*src2 */ { FP64_NORM_MIN(0), FP64_RAND_V0(0), FP64_RAND_V0(0), FP64_RAND_V3(1) } }, 6652 6705 { /*src1 */ { FP64_NORM_MAX(0), FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V1(1) } }, 6653 { /* => */ { FP64_ 0(0),FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V1(1) } },6706 { /* => */ { FP64_NORM_MAX(0), FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V1(1) } }, 6654 6707 /*mxcsr:in */ 0, 6655 6708 /*128:out */ X86_MXCSR_PE, 6656 /*256:out */ X86_MXCSR_PE,6709 /*256:out */ -1, 6657 6710 /*xcpt? */ true, true }, 6658 6711 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1) } }, 6659 6712 { /*src1 */ { FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0), FP64_NORM_MAX(1) } }, 6660 6713 { /* => */ { FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0), FP64_0(0) } }, 6661 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO, 6662 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, 6663 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, 6714 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 6715 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | BS3_MXCSR_OM_FIXED, 6716 /*256:out */ -1, 6717 /*xcpt? */ false, false }, 6718 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1) } }, 6719 { /*src1 */ { FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0), FP64_NORM_MAX(1) } }, 6720 { /* => */ { FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0), FP64_0(0) } }, 6721 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_RC_ZERO, 6722 /*128:out */ X86_MXCSR_OM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_OM_FIXED, 6723 /*256:out */ -1, 6664 6724 /*xcpt? */ false, false }, 6665 6725 { { /*src2 */ { FP64_NORM_MAX(0), FP64_0(0), FP64_0(0), FP64_NORM_MAX(0) } }, 6666 6726 { /*src1 */ { FP64_NORM_MAX(1), FP64_0(0), FP64_0(0), FP64_NORM_MAX(1) } }, 6667 6727 { /* => */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_INF(1) } }, 6668 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_FZ, 6669 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE, 6670 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE, 6728 /*mxcsr:in */ X86_MXCSR_FZ, 6729 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_OE | BS3_MXCSR_OM_FIXED, 6730 /*256:out */ -1, 6731 /*xcpt? */ false, false }, 6732 { { /*src2 */ { FP64_NORM_MAX(0), FP64_0(0), FP64_0(0), FP64_NORM_MAX(0) } }, 6733 { /*src1 */ { FP64_NORM_MAX(1), FP64_0(0), FP64_0(0), FP64_NORM_MAX(1) } }, 6734 { /* => */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_INF(1) } }, 6735 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_FZ, 6736 /*128:out */ X86_MXCSR_OM | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_OM_FIXED, 6737 /*256:out */ -1, 6671 6738 /*xcpt? */ false, false }, 6672 6739 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_V(1, 0, FP32_EXP_NORM_MIN + 1), FP64_NORM_MIN(1) } }, 6673 6740 { /*src1 */ { FP64_NORM_MAX(1), FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MIN(1) } }, 6674 6741 { /* => */ { FP64_INF(1), FP64_NORM_MAX(0), FP64_NORM_MIN(0), FP64_0(0) } }, 6675 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM, 6676 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, 6677 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, 6742 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 6743 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OE | BS3_MXCSR_OM_FIXED, 6744 /*256:out */ -1, 6745 /*xcpt? */ false, false }, 6746 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_V(1, 0, FP32_EXP_NORM_MIN + 1), FP64_NORM_MIN(1) } }, 6747 { /*src1 */ { FP64_NORM_MAX(1), FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MIN(1) } }, 6748 { /* => */ { FP64_INF(1), FP64_NORM_MAX(0), FP64_NORM_MIN(0), FP64_0(0) } }, 6749 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM, 6750 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_OM_FIXED, 6751 /*256:out */ -1, 6678 6752 /*xcpt? */ false, false }, 6679 6753 { { /*src2 */ { FP64_NORM_MAX(1), FP64_RAND_V0(0), FP64_RAND_V0(0), FP64_RAND_V0(0) } }, 6680 6754 { /*src1 */ { FP64_NORM_MAX(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V1(0) } }, 6681 6755 { /* => */ { FP64_NORM_MAX(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V1(0) } }, 6682 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM, 6683 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, 6684 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, 6756 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 6757 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | BS3_MXCSR_OM_FIXED, 6758 /*256:out */ -1, 6759 /*xcpt? */ false, false }, 6760 { { /*src2 */ { FP64_NORM_MAX(1), FP64_RAND_V0(0), FP64_RAND_V0(0), FP64_RAND_V0(0) } }, 6761 { /*src1 */ { FP64_NORM_MAX(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V1(0) } }, 6762 { /* => */ { FP64_NORM_MAX(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V1(0) } }, 6763 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM, 6764 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_OM_FIXED, 6765 /*256:out */ -1, 6685 6766 /*xcpt? */ false, false }, 6686 6767 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_NORM_MIN(0), FP64_NORM_MAX(0) } }, … … 6689 6770 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 6690 6771 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 6691 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, 6692 /*xcpt? */ false, false }, 6693 { { /*src2 */ { FP64_NORM_MIN(0), FP64_NORM_MIN(0), FP64_NORM_MIN(1), FP64_NORM_MIN(0) } }, 6694 { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } }, 6695 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 6696 /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM) | X86_MXCSR_RC_ZERO, 6697 /*128:out */ X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM) | X86_MXCSR_RC_ZERO | X86_MXCSR_PE, 6698 /*256:out */ X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM) | X86_MXCSR_RC_ZERO | X86_MXCSR_PE, 6699 /*xcpt? */ true, true }, 6700 { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_MAX(0), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MAX(1) } }, 6701 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_MAX(1), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MAX(1) } }, 6702 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 6772 /*256:out */ -1, 6773 /*xcpt? */ false, false }, 6774 { { /*src2 */ { FP64_NORM_MIN(0), FP64_NORM_MIN(0), FP64_NORM_MIN(1), FP64_NORM_MIN(0) } }, 6775 { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } }, 6776 { /* => */ { FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_NORM_MAX), FP64_NORM_MAX(0), FP64_0(0), FP64_0(0) } }, 6703 6777 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 6704 6778 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, 6705 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, 6779 /*256:out */ -1, 6780 /*xcpt? */ true, true }, 6781 { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_MAX(0), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MAX(1) } }, 6782 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_MAX(1), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MAX(1) } }, 6783 { /* => */ { FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_NORM_MAX(1), FP64_0(0), FP64_0(0) } }, 6784 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 6785 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, 6786 /*256:out */ -1, 6706 6787 /*xcpt? */ true, true }, 6707 6788 /* 6708 6789 * Normals. 6709 6790 */ 6710 /*2 3*/{ { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_V1(1), FP64_NORM_MAX(0), FP64_NORM_V2(0) } },6791 /*27*/{ { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_V1(1), FP64_NORM_MAX(0), FP64_NORM_V2(0) } }, 6711 6792 { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_V1(1), FP64_NORM_MAX(1), FP64_NORM_V1(0) } }, 6712 6793 { /* => */ { FP64_0(0), FP64_NORM_V1(1), FP64_NORM_MAX(1), FP64_NORM_V1(0) } }, 6713 6794 /*mxcsr:in */ 0, 6714 6795 /*128:out */ 0, 6715 /*256:out */ 0,6796 /*256:out */ -1, 6716 6797 /*xcpt? */ false, false }, 6717 6798 { { /*src2 */ { FP64_NORM_MIN(0), FP64_NORM_V2(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, … … 6720 6801 /*mxcsr:in */ 0, 6721 6802 /*128:out */ 0, 6722 /*256:out */ 0,6803 /*256:out */ -1, 6723 6804 /*xcpt? */ false, false }, 6724 6805 { { /*src2 */ { FP64_V(0, 0, 0x409)/*1024*/, FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, … … 6727 6808 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 6728 6809 /*128:out */ X86_MXCSR_XCPT_MASK, 6729 /*256:out */ X86_MXCSR_XCPT_MASK,6810 /*256:out */ -1, 6730 6811 /*xcpt? */ false, false }, 6731 6812 { { /*src2 */ { FP64_V(0, 0xc000000000000, 0x401)/* 7*/, FP64_RAND_V2(0), FP64_RAND_V2(0), FP64_RAND_V0(1) } }, … … 6734 6815 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 6735 6816 /*128:out */ X86_MXCSR_XCPT_MASK, 6736 /*256:out */ X86_MXCSR_XCPT_MASK,6817 /*256:out */ -1, 6737 6818 /*xcpt? */ false, false }, 6738 6819 { { /*src2 */ { FP64_V(0, 0x26580b4800000, 0x41d)/*1234567890*/, FP64_RAND_V3(0), FP64_RAND_V0(0), FP64_RAND_V1(1) } }, … … 6741 6822 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 6742 6823 /*128:out */ X86_MXCSR_XCPT_MASK, 6743 /*256:out */ X86_MXCSR_XCPT_MASK,6824 /*256:out */ -1, 6744 6825 /*xcpt? */ false, false }, 6745 6826 { { /*src2 */ { FP64_V(0, 0x9000000000000, 0x405)/* 100*/, FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, … … 6748 6829 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 6749 6830 /*128:out */ X86_MXCSR_XCPT_MASK, 6750 /*256:out */ X86_MXCSR_XCPT_MASK,6831 /*256:out */ -1, 6751 6832 /*xcpt? */ false, false }, 6752 6833 { { /*src2 */ { FP64_V(0, 0xd6eca42000000, 0x419)/* 123450000.5*/, FP64_RAND_V0(0), FP64_RAND_V0(1), FP64_RAND_V0(1) } }, … … 6755 6836 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 6756 6837 /*128:out */ X86_MXCSR_XCPT_MASK, 6757 /*256:out */ X86_MXCSR_XCPT_MASK,6838 /*256:out */ -1, 6758 6839 /*xcpt? */ false, false }, 6759 6840 { { /*src2 */ { FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V1(1) } }, … … 6762 6843 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 6763 6844 /*128:out */ X86_MXCSR_XCPT_MASK, 6764 /*256:out */ X86_MXCSR_XCPT_MASK,6845 /*256:out */ -1, 6765 6846 /*xcpt? */ false, false }, 6766 6847 { { /*src2 */ { FP64_1(0), FP64_RAND_V3(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } }, … … 6769 6850 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK, 6770 6851 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK, 6771 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK,6852 /*256:out */ -1, 6772 6853 /*xcpt? */ false, false }, 6773 6854 { { /*src2 */ { FP64_NORM_SAFE_INT_MAX(1), FP64_RAND_V0(0), FP64_RAND_V0(1), FP64_RAND_V0(1) } }, … … 6776 6857 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK, 6777 6858 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK, 6778 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,6859 /*256:out */ -1, 6779 6860 /*xcpt? */ false, false }, 6780 6861 { { /*src2 */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_RAND_V0(0), FP64_RAND_V0(1), FP64_RAND_V0(1) } }, … … 6783 6864 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_XCPT_MASK, 6784 6865 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_XCPT_MASK, 6785 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_XCPT_MASK,6866 /*256:out */ -1, 6786 6867 /*xcpt? */ false, false }, 6787 6868 /* 6788 6869 * Denormals. 6789 6870 */ 6790 /*3 4*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0), FP64_0(0) } },6871 /*38*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 6791 6872 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 6792 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 6793 /*mxcsr:in */ 0, 6794 /*128:out */ X86_MXCSR_DE, 6795 /*256:out */ X86_MXCSR_DE, 6873 { /* => */ { FP64_DENORM_MAX(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, 6874 /*mxcsr:in */ 0, 6875 /*128:out */ X86_MXCSR_DE | BS3_MXCSR_DM_FIXED, 6876 /*256:out */ -1, 6877 /*xcpt? */ true, true }, 6878 #ifdef TODO_X86_MXCSR_UE_IEM /** @todo THIS FAILS ON IEM: X86_MXCSR_UE not set in 128:out */ 6879 /*--|39*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 6880 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 6881 { /* => */ { FP64_DENORM_MAX(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, 6882 /*mxcsr:in */ X86_MXCSR_DM, 6883 /*128:out */ X86_MXCSR_DM | X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 6884 /*256:out */ -1, 6885 /*xcpt? */ true, true }, 6886 #endif /* TODO_X86_MXCSR_UE_IEM */ 6887 /*39|40*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 6888 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 6889 { /* => */ { FP64_DENORM_MAX(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, 6890 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_UM, 6891 /*128:out */ X86_MXCSR_DM | X86_MXCSR_UM | X86_MXCSR_DE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 6892 /*256:out */ -1, 6796 6893 /*xcpt? */ true, true }, 6797 6894 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, … … 6800 6897 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK, 6801 6898 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK, 6802 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,6899 /*256:out */ -1, 6803 6900 /*xcpt? */ false, false }, 6804 6901 { { /*src2 */ { FP64_DENORM_MIN(0), FP64_RAND_V1(0), FP64_RAND_V0(0), FP64_RAND_V0(1) } }, … … 6807 6904 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK, 6808 6905 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK, 6809 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,6906 /*256:out */ -1, 6810 6907 /*xcpt? */ false, false }, 6811 6908 /** @todo More Denormals. */ … … 6813 6910 * Invalids. 6814 6911 */ 6815 /*32*/ FP64_TABLE_D1_SD_INVALIDS6912 /*42|43*/ FP64_TABLE_D1_SD_INVALIDS 6816 6913 /** @todo Underflow; Precision; Rounding; FZ etc. */ 6817 6914 }; … … 6852 6949 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 6853 6950 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode); 6854 return bs3CpuInstr4_WorkerTestType1 (bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,6951 return bs3CpuInstr4_WorkerTestType1A(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 6855 6952 g_aXcptConfig3, RT_ELEMENTS(g_aXcptConfig3)); 6856 6953 } … … 8487 8584 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 8488 8585 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 8489 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,8490 /*128:out */ X86_MXCSR_XCPT_MASK,8491 /*256:out */ X86_MXCSR_XCPT_MASK,8492 /*xcpt? */ false, false },8493 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },8494 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },8495 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },8496 8586 /*mxcsr:in */ 0, 8497 8587 /*128:out */ 0, 8498 /*256:out */ 0,8588 /*256:out */ -1, 8499 8589 /*xcpt? */ false, false }, 8500 8590 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, … … 8503 8593 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 8504 8594 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 8505 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,8595 /*256:out */ -1, 8506 8596 /*xcpt? */ false, false }, 8507 8597 { { /*src2 */ { FP64_0(0), FP64_NORM_V3(0), FP64_NORM_V2(0), FP64_0(0) } }, … … 8510 8600 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 8511 8601 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 8512 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,8602 /*256:out */ -1, 8513 8603 /*xcpt? */ false, false }, 8514 8604 { { /*src2 */ { FP64_0(1), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V1(1) } }, … … 8517 8607 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 8518 8608 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 8519 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,8609 /*256:out */ -1, 8520 8610 /*xcpt? */ false, false }, 8521 8611 { { /*src2 */ { FP64_0(1), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, … … 8524 8614 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 8525 8615 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 8526 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,8616 /*256:out */ -1, 8527 8617 /*xcpt? */ false, false }, 8528 8618 { { /*src2 */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, … … 8531 8621 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ, 8532 8622 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ, 8533 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,8623 /*256:out */ -1, 8534 8624 /*xcpt? */ false, false }, 8535 8625 { { /*src2 */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, … … 8538 8628 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 8539 8629 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 8540 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,8630 /*256:out */ -1, 8541 8631 /*xcpt? */ false, false }, 8542 8632 /* … … 8548 8638 /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM, 8549 8639 /*128:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM, 8550 /*256:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,8640 /*256:out */ -1, 8551 8641 /*xcpt? */ false, false }, 8552 8642 { { /*src2 */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, … … 8555 8645 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 8556 8646 /*128:out */ X86_MXCSR_XCPT_MASK, 8557 /*256:out */ X86_MXCSR_XCPT_MASK,8647 /*256:out */ -1, 8558 8648 /*xcpt? */ false, false }, 8559 8649 { { /*src2 */ { FP64_INF(0), FP64_RAND_V1(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, … … 8562 8652 /*mxcsr:in */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_DAZ | X86_MXCSR_FZ, 8563 8653 /*128:out */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_DAZ | X86_MXCSR_FZ, 8564 /*256:out */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_DAZ | X86_MXCSR_FZ,8654 /*256:out */ -1, 8565 8655 /*xcpt? */ false, false }, 8566 8656 { { /*src2 */ { FP64_INF(1), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V1(1) } }, … … 8569 8659 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 8570 8660 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 8571 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,8661 /*256:out */ -1, 8572 8662 /*xcpt? */ false, false }, 8573 8663 { { /*src2 */ { FP64_1(0), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } }, … … 8576 8666 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, 8577 8667 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, 8578 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,8668 /*256:out */ -1, 8579 8669 /*xcpt? */ false, false }, 8580 8670 { { /*src2 */ { FP64_INF(0), FP64_INF(0), FP64_INF(1), FP64_INF(1) } }, … … 8583 8673 /*mxcsr:in */ X86_MXCSR_FZ, 8584 8674 /*128:out */ X86_MXCSR_FZ, 8585 /*256:out */ X86_MXCSR_FZ,8675 /*256:out */ -1, 8586 8676 /*xcpt? */ false, false }, 8587 8677 { { /*src2 */ { FP64_INF(1), FP64_QNAN(0), FP64_SNAN(0), FP64_RAND_V0(0) } }, … … 8590 8680 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 8591 8681 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 8592 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,8682 /*256:out */ -1, 8593 8683 /*xcpt? */ false, false }, 8594 8684 /* … … 8600 8690 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 8601 8691 /*128:out */ X86_MXCSR_XCPT_MASK, 8602 /*256:out */ X86_MXCSR_XCPT_MASK,8692 /*256:out */ -1, 8603 8693 /*xcpt? */ false, false }, 8604 8694 { { /*src2 */ { FP64_V(0, 0xaf00000000000, 0x406)/* 215.50*/, FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } }, … … 8607 8697 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 8608 8698 /*128:out */ X86_MXCSR_XCPT_MASK, 8609 /*256:out */ X86_MXCSR_XCPT_MASK,8699 /*256:out */ -1, 8610 8700 /*xcpt? */ false, false }, 8611 8701 { { /*src2 */ { FP64_V(1, 0x107526e749f80, 0x42b)/*-18723145413791.50*/, FP64_RAND_V3(0), FP64_RAND_V1(0), FP64_RAND_V1(1) } }, … … 8614 8704 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 8615 8705 /*128:out */ X86_MXCSR_XCPT_MASK, 8616 /*256:out */ X86_MXCSR_XCPT_MASK,8706 /*256:out */ -1, 8617 8707 /*xcpt? */ false, false }, 8618 8708 { { /*src2 */ { FP64_V(0, 0x6fee0e4bd0000, 0x420)/* 12345678999.62500*/, FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, … … 8621 8711 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 8622 8712 /*128:out */ X86_MXCSR_XCPT_MASK, 8623 /*256:out */ X86_MXCSR_XCPT_MASK,8713 /*256:out */ -1, 8624 8714 /*xcpt? */ false, false }, 8625 8715 { { /*src2 */ { FP64_NORM_MAX(1), FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } }, … … 8628 8718 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 8629 8719 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 8630 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,8720 /*256:out */ -1, 8631 8721 /*xcpt? */ false, false }, 8632 8722 { { /*src2 */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_RAND_V2(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, … … 8635 8725 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 8636 8726 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 8637 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,8727 /*256:out */ -1, 8638 8728 /*xcpt? */ false, false }, 8639 8729 { { /*src2 */ { FP64_V(1, 0x68b83b1ed4000, 0x41e)/*-3025935759.4140625*/, FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, … … 8642 8732 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 8643 8733 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 8644 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,8734 /*256:out */ -1, 8645 8735 /*xcpt? */ false, false }, 8646 8736 { { /*src2 */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, … … 8649 8739 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 8650 8740 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 8651 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,8741 /*256:out */ -1, 8652 8742 /*xcpt? */ false, false }, 8653 8743 { { /*src2 */ { FP64_1(0), FP64_0(0), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_MAX(1) } }, … … 8656 8746 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 8657 8747 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 8658 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,8748 /*256:out */ -1, 8659 8749 /*xcpt? */ false, false }, 8660 8750 { { /*src2 */ { FP64_NORM_V0(0), FP64_NORM_V1(1), FP64_NORM_V2(0), FP64_NORM_V3(1) } }, … … 8663 8753 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 8664 8754 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 8665 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,8755 /*256:out */ -1, 8666 8756 /*xcpt? */ false, false }, 8667 8757 /* … … 8673 8763 /*mxcsr:in */ 0, 8674 8764 /*128:out */ X86_MXCSR_DE, 8675 /*256:out */ X86_MXCSR_DE,8765 /*256:out */ -1, 8676 8766 /*xcpt? */ true, true }, 8677 8767 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, … … 8680 8770 /*mxcsr:in */ X86_MXCSR_FZ, 8681 8771 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_DE, 8682 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_DE,8772 /*256:out */ -1, 8683 8773 /*xcpt? */ true, true }, 8684 8774 { { /*src2 */ { FP64_DENORM_MAX(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, … … 8687 8777 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 8688 8778 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 8689 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ,8779 /*256:out */ -1, 8690 8780 /*xcpt? */ false, false }, 8691 8781 { { /*src2 */ { FP64_DENORM_MAX(0), FP64_RAND_V2(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, … … 8694 8784 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ, 8695 8785 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ, 8696 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ,8786 /*256:out */ -1, 8697 8787 /*xcpt? */ false, false }, 8698 8788 { { /*src2 */ { FP64_DENORM_MIN(1), FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, … … 8701 8791 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 8702 8792 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 8703 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,8793 /*256:out */ -1, 8704 8794 /*xcpt? */ false, false }, 8705 8795 { { /*src2 */ { FP64_1(1), FP64_RAND_V3(0), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, 8706 8796 { /*src1 */ { FP64_DENORM_MIN(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, 8707 8797 { /* => */ { FP64_0(1), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, 8708 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 8709 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_DE | X86_MXCSR_UE | X86_MXCSR_PE, 8710 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_DE | X86_MXCSR_UE | X86_MXCSR_PE, 8798 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 8799 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_DE | X86_MXCSR_UE | X86_MXCSR_PE | BS3_MXCSR_DM_FIXED, 8800 /*256:out */ -1, 8801 /*xcpt? */ false, false }, 8802 { { /*src2 */ { FP64_1(1), FP64_RAND_V3(0), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, 8803 { /*src1 */ { FP64_DENORM_MIN(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, 8804 { /* => */ { FP64_0(1), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, 8805 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 8806 /*128:out */ X86_MXCSR_DM | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 8807 /*256:out */ -1, 8808 /*xcpt? */ false, false }, 8809 { { /*src2 */ { FP64_1(1), FP64_RAND_V3(0), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, 8810 { /*src1 */ { FP64_DENORM_MIN(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, 8811 { /* => */ { FP64_0(1), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, 8812 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_UM | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 8813 /*128:out */ X86_MXCSR_DM | X86_MXCSR_UM | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_DE | X86_MXCSR_UE | X86_MXCSR_PE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 8814 /*256:out */ -1, 8711 8815 /*xcpt? */ false, false }, 8712 8816 { { /*src2 */ { FP64_DENORM_MAX(0), FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V1(0) } }, … … 8714 8818 { /* => */ { FP64_0(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V0(0) } }, 8715 8819 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 8716 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_DE, 8717 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_DE, 8820 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_DE | BS3_MXCSR_DM_FIXED, 8821 /*256:out */ -1, 8822 /*xcpt? */ true, true }, 8823 #ifdef TODO_X86_MXCSR_PE_IEM /** @todo THIS FAILS ON IEM: X86_MXCSR_PE not set in 128:out */ 8824 /*--|34*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V1(0) } }, 8825 { /*src1 */ { FP64_DENORM_MAX(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V0(0) } }, 8826 { /* => */ { FP64_0(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V0(0) } }, 8827 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 8828 /*128:out */ X86_MXCSR_DM | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 8829 /*256:out */ -1, 8830 /*xcpt? */ true, true }, 8831 #endif /* TODO_X86_MXCSR_PE_IEM */ 8832 /*34|35*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V1(0) } }, 8833 { /*src1 */ { FP64_DENORM_MAX(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V0(0) } }, 8834 { /* => */ { FP64_0(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V0(0) } }, 8835 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_UM | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 8836 /*128:out */ X86_MXCSR_DM | X86_MXCSR_UM | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 8837 /*256:out */ -1, 8718 8838 /*xcpt? */ true, true }, 8719 8839 { { /*src2 */ { FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } }, … … 8721 8841 { /* => */ { FP64_0(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(1), FP64_DENORM_MIN(1) } }, 8722 8842 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 8723 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_DE, 8724 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_DE, 8843 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_DE | BS3_MXCSR_DM_FIXED, 8844 /*256:out */ -1, 8845 /*xcpt? */ true, true }, 8846 { { /*src2 */ { FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } }, 8847 { /*src1 */ { FP64_DENORM_MIN(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(1), FP64_DENORM_MIN(1) } }, 8848 { /* => */ { FP64_0(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(1), FP64_DENORM_MIN(1) } }, 8849 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 8850 /*128:out */ X86_MXCSR_DM | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 8851 /*256:out */ -1, 8852 /*xcpt? */ true, true }, 8853 { { /*src2 */ { FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } }, 8854 { /*src1 */ { FP64_DENORM_MIN(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(1), FP64_DENORM_MIN(1) } }, 8855 { /* => */ { FP64_0(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(1), FP64_DENORM_MIN(1) } }, 8856 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_UM | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 8857 /*128:out */ X86_MXCSR_DM | X86_MXCSR_UM | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 8858 /*256:out */ -1, 8725 8859 /*xcpt? */ true, true }, 8726 8860 /* 8727 8861 * Invalids. 8728 8862 */ 8729 /*33*/ FP64_TABLE_D1_SD_INVALIDS8863 /*38|39*/ FP64_TABLE_D1_SD_INVALIDS 8730 8864 /** @todo Underflow, Precision; Rounding; FZ etc. */ 8731 8865 }; … … 8766 8900 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 8767 8901 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode); 8768 return bs3CpuInstr4_WorkerTestType1 (bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,8902 return bs3CpuInstr4_WorkerTestType1A(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 8769 8903 g_aXcptConfig3, RT_ELEMENTS(g_aXcptConfig3)); 8770 8904 } … … 9801 9935 * Zero. 9802 9936 */ 9803 /* 0*/{ { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },9804 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },9937 /* 0*/{ { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 9938 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 9805 9939 { /* => */ { FP64_QNAN(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, 9806 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,9807 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,9808 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,9809 /*xcpt? */ false, false },9810 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },9811 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },9812 { /* => */ { FP64_QNAN(1), FP64_0(0), FP64_0(0), FP64_0(0) } },9813 9940 /*mxcsr:in */ 0, 9814 9941 /*128:out */ X86_MXCSR_IE, 9815 /*256:out */ X86_MXCSR_IE,9816 /*xcpt? */ true, true }, 9817 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },9818 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },9942 /*256:out */ -1, 9943 /*xcpt? */ true, true }, 9944 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 9945 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 9819 9946 { /* => */ { FP64_QNAN(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, 9820 9947 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 9821 9948 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 9822 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,9823 /*xcpt? */ false, false }, 9824 { { /*src2 */ { FP64_0(0), FP64_NORM_V3(0), FP64_NORM_V2(0), FP64_0(0) } },9825 { /*src1 */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_NORM_V1(0) } },9949 /*256:out */ -1, 9950 /*xcpt? */ false, false }, 9951 { { /*src2 */ { FP64_0(0), FP64_NORM_V3(0), FP64_NORM_V2(0), FP64_0(0) } }, 9952 { /*src1 */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_NORM_V1(0) } }, 9826 9953 { /* => */ { FP64_QNAN(1), FP64_0(1), FP64_0(1), FP64_NORM_V1(0) } }, 9827 9954 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 9828 9955 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, 9829 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,9830 /*xcpt? */ false, false }, 9831 { { /*src2 */ { FP64_0(1), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V1(1) } },9832 { /*src1 */ { FP64_0(1), FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V2(0) } },9956 /*256:out */ -1, 9957 /*xcpt? */ false, false }, 9958 { { /*src2 */ { FP64_0(1), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V1(1) } }, 9959 { /*src1 */ { FP64_0(1), FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V2(0) } }, 9833 9960 { /* => */ { FP64_QNAN(1), FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V2(0) } }, 9834 9961 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 9835 9962 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, 9836 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,9837 /*xcpt? */ true, true }, 9838 { { /*src2 */ { FP64_0(1), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } },9839 { /*src1 */ { FP64_0(0), FP64_RAND_V2(1), FP64_RAND_V3(0), FP64_RAND_V0(0) } },9963 /*256:out */ -1, 9964 /*xcpt? */ true, true }, 9965 { { /*src2 */ { FP64_0(1), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, 9966 { /*src1 */ { FP64_0(0), FP64_RAND_V2(1), FP64_RAND_V3(0), FP64_RAND_V0(0) } }, 9840 9967 { /* => */ { FP64_QNAN(1), FP64_RAND_V2(1), FP64_RAND_V3(0), FP64_RAND_V0(0) } }, 9841 9968 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 9842 9969 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 9843 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,9844 /*xcpt? */ true, true }, 9845 { { /*src2 */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } },9846 { /*src1 */ { FP64_0(1), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V0(0) } },9970 /*256:out */ -1, 9971 /*xcpt? */ true, true }, 9972 { { /*src2 */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, 9973 { /*src1 */ { FP64_0(1), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V0(0) } }, 9847 9974 { /* => */ { FP64_QNAN(1), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V0(0) } }, 9848 9975 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ, 9849 9976 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_IE, 9850 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_IE,9851 /*xcpt? */ false, false }, 9852 { { /*src2 */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } },9853 { /*src1 */ { FP64_1(0), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V0(0) } },9977 /*256:out */ -1, 9978 /*xcpt? */ false, false }, 9979 { { /*src2 */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, 9980 { /*src1 */ { FP64_1(0), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V0(0) } }, 9854 9981 { /* => */ { FP64_INF(0), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V0(0) } }, 9855 9982 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 9856 9983 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_FSW_ZE, 9857 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_FSW_ZE,9984 /*256:out */ -1, 9858 9985 /*xcpt? */ false, false }, 9859 9986 /* 9860 9987 * Infinity. 9861 9988 */ 9862 /* 8*/{ { /*src2 */ { FP64_INF(0), FP64_0(0), FP64_0(0), FP64_0(0) } },9989 /* 7*/{ { /*src2 */ { FP64_INF(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 9863 9990 { /*src1 */ { FP64_1(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, 9864 9991 { /* => */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, 9865 9992 /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM, 9866 9993 /*128:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM, 9867 /*256:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,9994 /*256:out */ -1, 9868 9995 /*xcpt? */ false, false }, 9869 9996 { { /*src2 */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, … … 9872 9999 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 9873 10000 /*128:out */ X86_MXCSR_XCPT_MASK, 9874 /*256:out */ X86_MXCSR_XCPT_MASK,9875 /*xcpt? */ false, false }, 9876 { { /*src2 */ { FP64_INF(0), FP64_RAND_V1(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },9877 { /*src1 */ { FP64_INF(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } },9878 { /* => */ { FP64_ INF(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } },10001 /*256:out */ -1, 10002 /*xcpt? */ false, false }, 10003 { { /*src2 */ { FP64_INF(0), FP64_RAND_V1(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, 10004 { /*src1 */ { FP64_INF(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } }, 10005 { /* => */ { FP64_QNAN(1), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } }, 9879 10006 /*mxcsr:in */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_DAZ | X86_MXCSR_FZ, 9880 10007 /*128:out */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE, 9881 /*256:out */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE,9882 /*xcpt? */ true, true }, 9883 { { /*src2 */ { FP64_INF(1), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V1(1) } },9884 { /*src1 */ { FP64_INF(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V0(0) } },10008 /*256:out */ -1, 10009 /*xcpt? */ true, true }, 10010 { { /*src2 */ { FP64_INF(1), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V1(1) } }, 10011 { /*src1 */ { FP64_INF(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V0(0) } }, 9885 10012 { /* => */ { FP64_QNAN(1), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V0(0) } }, 9886 10013 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 9887 10014 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 9888 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,10015 /*256:out */ -1, 9889 10016 /*xcpt? */ false, false }, 9890 10017 { { /*src2 */ { FP64_1(0), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } }, … … 9893 10020 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, 9894 10021 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, 9895 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,10022 /*256:out */ -1, 9896 10023 /*xcpt? */ false, false }, 9897 10024 { { /*src2 */ { FP64_INF(0), FP64_INF(0), FP64_INF(1), FP64_INF(1) } }, … … 9900 10027 /*mxcsr:in */ X86_MXCSR_FZ, 9901 10028 /*128:out */ X86_MXCSR_FZ, 9902 /*256:out */ X86_MXCSR_FZ,9903 /*xcpt? */ false, false }, 9904 { { /*src2 */ { FP64_INF(1), FP64_QNAN(0), FP64_SNAN(0), FP64_RAND_V0(0) } },9905 { /*src1 */ { FP64_INF(0), FP64_QNAN(0), FP64_SNAN(0), FP64_RAND_V0(0) } },10029 /*256:out */ -1, 10030 /*xcpt? */ false, false }, 10031 { { /*src2 */ { FP64_INF(1), FP64_QNAN(0), FP64_SNAN(0), FP64_RAND_V0(0) } }, 10032 { /*src1 */ { FP64_INF(0), FP64_QNAN(0), FP64_SNAN(0), FP64_RAND_V0(0) } }, 9906 10033 { /* => */ { FP64_QNAN(1), FP64_QNAN(0), FP64_SNAN(0), FP64_RAND_V0(0) } }, 9907 10034 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 9908 10035 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 9909 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,10036 /*256:out */ -1, 9910 10037 /*xcpt? */ true, true }, 9911 10038 /* 9912 10039 * Normals. 9913 10040 */ 9914 /*1 5*/{ { /*src2 */ { FP64_V(0, 0xe66f500000000, 0x40d)/*31131.828125*/, FP64_RAND_V1(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },10041 /*14*/{ { /*src2 */ { FP64_V(0, 0xe66f500000000, 0x40d)/*31131.828125*/, FP64_RAND_V1(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, 9915 10042 { /*src1 */ { FP64_V(0, 0xe66f500000000, 0x40d)/*31131.828125*/, FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } }, 9916 10043 { /* => */ { FP64_1(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } }, 9917 10044 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 9918 10045 /*128:out */ X86_MXCSR_XCPT_MASK, 9919 /*256:out */ X86_MXCSR_XCPT_MASK,10046 /*256:out */ -1, 9920 10047 /*xcpt? */ false, false }, 9921 10048 { { /*src2 */ { FP64_V(0, 0xaf00000000000, 0x406)/* 215.50*/, FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } }, … … 9924 10051 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 9925 10052 /*128:out */ X86_MXCSR_XCPT_MASK, 9926 /*256:out */ X86_MXCSR_XCPT_MASK,10053 /*256:out */ -1, 9927 10054 /*xcpt? */ false, false }, 9928 10055 { { /*src2 */ { FP64_V(1, 0x107526e749f80, 0x42b)/*-18723145413791.50*/, FP64_RAND_V3(0), FP64_RAND_V1(0), FP64_RAND_V1(1) } }, … … 9931 10058 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 9932 10059 /*128:out */ X86_MXCSR_XCPT_MASK, 9933 /*256:out */ X86_MXCSR_XCPT_MASK,10060 /*256:out */ -1, 9934 10061 /*xcpt? */ false, false }, 9935 10062 { { /*src2 */ { FP64_V(0, 0x6fee0e4bd0000, 0x420)/* 12345678999.62500*/, FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, … … 9938 10065 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 9939 10066 /*128:out */ X86_MXCSR_XCPT_MASK, 9940 /*256:out */ X86_MXCSR_XCPT_MASK,10067 /*256:out */ -1, 9941 10068 /*xcpt? */ false, false }, 9942 10069 { { /*src2 */ { FP64_NORM_MAX(1), FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } }, … … 9945 10072 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 9946 10073 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 9947 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,10074 /*256:out */ -1, 9948 10075 /*xcpt? */ false, false }, 9949 10076 { { /*src2 */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_RAND_V2(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, … … 9952 10079 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 9953 10080 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 9954 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,10081 /*256:out */ -1, 9955 10082 /*xcpt? */ false, false }, 9956 10083 { { /*src2 */ { FP64_V(1, 0x68b83b1ed4000, 0x41e)/*-3025935759.4140625*/, FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, … … 9959 10086 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 9960 10087 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 9961 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,10088 /*256:out */ -1, 9962 10089 /*xcpt? */ false, false }, 9963 10090 { { /*src2 */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, … … 9966 10093 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 9967 10094 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 9968 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,10095 /*256:out */ -1, 9969 10096 /*xcpt? */ false, false }, 9970 10097 { { /*src2 */ { FP64_1(0), FP64_0(0), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_MAX(1) } }, … … 9973 10100 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 9974 10101 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 9975 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,10102 /*256:out */ -1, 9976 10103 /*xcpt? */ false, false }, 9977 10104 { { /*src2 */ { FP64_NORM_V0(0), FP64_NORM_V1(1), FP64_NORM_V2(0), FP64_NORM_V3(1) } }, … … 9980 10107 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 9981 10108 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 9982 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,10109 /*256:out */ -1, 9983 10110 /*xcpt? */ false, false }, 9984 10111 /* 9985 10112 * Denormals. 9986 10113 */ 9987 /*2 5*/{ { /* UNMASKED: 0 / DENORM_MAX = 0 &&_DE */9988 /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), 9989 { /*src1 */ { FP64_0(0), FP64_DENORM_MIN(0), 9990 { /* => */ { FP64_0(0), FP64_DENORM_MIN(0), 10114 /*24*/{ { /* 0 / DENORM_MAX = 0 &_DE */ 10115 /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0) } }, 10116 { /*src1 */ { FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0), FP64_DENORM_MAX(0) } }, 10117 { /* => */ { FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0), FP64_DENORM_MAX(0) } }, 9991 10118 /*mxcsr:in */ 0, 9992 10119 /*128:out */ X86_MXCSR_DE, 9993 /*256:out */ X86_MXCSR_DE, 9994 /*xcpt? */ true, true }, 9995 { { /* MASKED: 0 / DENORM_MAX = 0 &_DE */ 9996 /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0) } }, 9997 { /*src1 */ { FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0), FP64_DENORM_MAX(0) } }, 9998 { /* => */ { FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0), FP64_DENORM_MAX(0) } }, 9999 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 10000 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, 10001 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, 10002 /*xcpt? */ false, false }, 10003 { { /* UNMASKED: DENORM_MAX / -0 = -INF &&_ZE */ 10004 /*src2 */ { FP64_0(1), FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0) } }, 10005 { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_0(0), FP64_DENORM_MAX(0) } }, 10006 { /* => */ { FP64_INF(1), FP64_DENORM_MIN(0), FP64_0(0), FP64_DENORM_MAX(0) } }, 10120 /*256:out */ -1, 10121 /*xcpt? */ true, true }, 10122 { { /* DENORM_MAX / -0 = -INF &_ZE */ 10123 /*src2 */ { FP64_0(1), FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0) } }, 10124 { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_0(0), FP64_DENORM_MAX(0) } }, 10125 { /* => */ { FP64_INF(1), FP64_DENORM_MIN(0), FP64_0(0), FP64_DENORM_MAX(0) } }, 10007 10126 /*mxcsr:in */ 0, 10008 10127 /*128:out */ X86_MXCSR_ZE, 10009 /*256:out */ X86_MXCSR_ZE,10010 /*xcpt? */ true, true }, 10011 { { /* MASKED: -DENORM_MAX / -0 = INF &_ZE */10012 /*src2 */ { FP64_0(1), FP64_0(0), 10013 { /*src1 */ { FP64_DENORM_MAX(1), FP64_DENORM_MIN(0), 10014 { /* => */ { FP64_INF(0), FP64_DENORM_MIN(0), 10128 /*256:out */ -1, 10129 /*xcpt? */ true, true }, 10130 { { /* DENORM_MAX / -0 = INF &_ZE */ 10131 /*src2 */ { FP64_0(1), FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0) } }, 10132 { /*src1 */ { FP64_DENORM_MAX(1), FP64_DENORM_MIN(0), FP64_0(0), FP64_DENORM_MAX(0) } }, 10133 { /* => */ { FP64_INF(0), FP64_DENORM_MIN(0), FP64_0(0), FP64_DENORM_MAX(0) } }, 10015 10134 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 10016 10135 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_ZE, 10017 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_ZE,10018 /*xcpt? */ false, false }, 10019 { { /* MASKED:-DENORM_MAX / DENORM_MIN = (-huge) &_DE */10020 /*src2 */ { FP64_DENORM_MIN(0), FP64_0(0),FP64_RAND_V2(0), FP64_RAND_V1(1) } },10021 { /*src1 */ { FP64_DENORM_MAX(1), FP64_DENORM_MIN(0),FP64_RAND_V1(1), FP64_RAND_V3(0) } },10022 { /* => */ { FP64_V(1, 0xffffffffffffe, 0x432)/*-4503599627370495.0*/, FP64_DENORM_MIN(0), 10136 /*256:out */ -1, 10137 /*xcpt? */ false, false }, 10138 { { /* -DENORM_MAX / DENORM_MIN = (-huge) &_DE */ 10139 /*src2 */ { FP64_DENORM_MIN(0), FP64_0(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 10140 { /*src1 */ { FP64_DENORM_MAX(1), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 10141 { /* => */ { FP64_V(1, 0xffffffffffffe, 0x432)/*-4503599627370495.0*/, FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 10023 10142 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, 10024 10143 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP | X86_MXCSR_DE, 10025 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP | X86_MXCSR_DE,10026 /*xcpt? */ false, false }, 10027 { { /* UNMASKED: -DENORM_MAX / -DENORM_MIN = (huge) &&_DE */10028 /*src2 */ { FP64_DENORM_MIN(1), FP64_0(0),FP64_RAND_V2(0), FP64_RAND_V1(1) } },10029 { /*src1 */ { FP64_DENORM_MAX(1), FP64_DENORM_MIN(0),FP64_RAND_V1(1), FP64_RAND_V3(0) } },10030 { /* => */ { FP64_V(0, 0xffffffffffffe, 0x432)/*4503599627370495.0*/, FP64_DENORM_MIN(0), 10144 /*256:out */ -1, 10145 /*xcpt? */ false, false }, 10146 { { /* -DENORM_MAX / -DENORM_MIN = (huge) &_DE */ 10147 /*src2 */ { FP64_DENORM_MIN(1), FP64_0(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 10148 { /*src1 */ { FP64_DENORM_MAX(1), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 10149 { /* => */ { FP64_V(0, 0xffffffffffffe, 0x432)/*4503599627370495.0*/, FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 10031 10150 /*mxcsr:in */ X86_MXCSR_RC_UP, 10032 10151 /*128:out */ X86_MXCSR_RC_UP | X86_MXCSR_DE, 10033 /*256:out */ X86_MXCSR_RC_UP | X86_MXCSR_DE,10034 /*xcpt? */ true, true }, 10035 { { /* MASKED: -DENORM_MIN / DENORM_MAX = (-tiny) &_DE,_PE */10036 /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0),FP64_RAND_V2(0), FP64_RAND_V1(1) } },10037 { /*src1 */ { FP64_DENORM_MIN(1), FP64_DENORM_MIN(0),FP64_RAND_V1(1), FP64_RAND_V3(0) } },10038 { /* => */ { FP64_V(1, 0x0000000000001, 0x3cb)/*-22204460492503135739e-35*/, FP64_DENORM_MIN(0), 10152 /*256:out */ -1, 10153 /*xcpt? */ true, true }, 10154 { { /* -DENORM_MIN / DENORM_MAX = (-tiny) &_DE &_PE */ 10155 /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 10156 { /*src1 */ { FP64_DENORM_MIN(1), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 10157 { /* => */ { FP64_V(1, 0x0000000000001, 0x3cb)/*-22204460492503135739e-35*/, FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 10039 10158 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 10040 10159 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_PE, 10041 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_PE,10042 /*xcpt? */ false, false }, 10043 { { /* MASKED:-0 / DENORM_MIN = -0 &_DE */10044 /*src2 */ { FP64_DENORM_MIN(0), FP64_0(0), 10045 { /*src1 */ { FP64_0(1), FP64_DENORM_MIN(0),FP64_RAND_V1(1), FP64_RAND_V3(0) } },10046 { /* => */ { FP64_0(1), FP64_DENORM_MIN(0),FP64_RAND_V1(1), FP64_RAND_V3(0) } },10160 /*256:out */ -1, 10161 /*xcpt? */ false, false }, 10162 { { /* -0 / DENORM_MIN = -0 &_DE */ 10163 /*src2 */ { FP64_DENORM_MIN(0), FP64_0(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 10164 { /*src1 */ { FP64_0(1), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 10165 { /* => */ { FP64_0(1), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 10047 10166 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 10048 10167 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, 10049 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,10050 /*xcpt? */ false, false }, 10051 { { /* MASKED:-0.25 / DENORM_MAX = (-HUGE) &_DE &_PE */10052 /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0),FP64_RAND_V2(0), FP64_RAND_V1(1) } },10053 { /*src1 */ { FP64_V(1, 0, 0x3fd)/*0.25*/, FP64_DENORM_MIN(0),FP64_RAND_V1(1), FP64_RAND_V3(0) } },10054 { /* => */ { FP64_V(1, 1, 0x7fb)/*1.1XYZe307*/, FP64_DENORM_MIN(0), 10168 /*256:out */ -1, 10169 /*xcpt? */ false, false }, 10170 { { /* -0.25 / DENORM_MAX = (-HUGE) &_DE &_PE */ 10171 /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 10172 { /*src1 */ { FP64_V(1, 0, 0x3fd)/*0.25*/, FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 10173 { /* => */ { FP64_V(1, 1, 0x7fb)/*1.1XYZe307*/, FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 10055 10174 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 10056 10175 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_PE, 10057 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_PE, 10058 /*xcpt? */ false, false }, 10059 { { /* MASKED: 42.0 / DENORM_MIN = INF &_DE &_PE &_OE */ 10060 /*src2 */ { FP64_DENORM_MIN(0), FP64_0(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 10061 { /*src1 */ { FP64_V(0, 0x5000000000000, 0x404)/*42.0*/, FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 10062 { /* => */ { FP64_INF(0), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 10063 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 10064 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_OE, 10065 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_OE, 10066 /*xcpt? */ false, false }, 10067 { { /* ~OMASKED: 42.0 / DENORM_MIN = INF &_DE &&_OE */ 10068 /*src2 */ { FP64_DENORM_MIN(0), FP64_0(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 10069 { /*src1 */ { FP64_V(0, 0x5000000000000, 0x404)/*42.0*/, FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 10070 { /* => */ { FP64_INF(0), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 10071 /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_OM, 10072 /*128:out */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_OM) | X86_MXCSR_DE | X86_MXCSR_OE, 10073 /*256:out */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_OM) | X86_MXCSR_DE | X86_MXCSR_OE, 10074 /*xcpt? */ true, true }, 10075 { { /* DAZ+MASK: 42.0 / DENORM_MIN = INF &_ZE */ 10076 /*src2 */ { FP64_DENORM_MIN(0), FP64_0(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 10077 { /*src1 */ { FP64_V(0, 0x5000000000000, 0x404)/*42.0*/, FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 10078 { /* => */ { FP64_INF(0), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 10176 /*256:out */ -1, 10177 /*xcpt? */ false, false }, 10178 { { /* 42.0 / DENORM_MIN = INF &_DE &_PE(if OM) &_OE */ 10179 /*src2 */ { FP64_DENORM_MIN(0), FP64_0(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 10180 { /*src1 */ { FP64_V(0, 0x5000000000000, 0x404)/*42.0*/, FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 10181 { /* => */ { FP64_INF(0), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 10182 /*mxcsr:in */ X86_MXCSR_OM, 10183 /*128:out */ X86_MXCSR_OM | X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_OE | BS3_MXCSR_OM_FIXED, 10184 /*256:out */ -1, 10185 /*xcpt? */ false, false }, 10186 { { /* 42.0 / DENORM_MIN = INF &_DE &_PE(if !DM) &_OE */ 10187 /*src2 */ { FP64_DENORM_MIN(0), FP64_0(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 10188 { /*src1 */ { FP64_V(0, 0x5000000000000, 0x404)/*42.0*/, FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 10189 { /* => */ { FP64_INF(0), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 10190 /*mxcsr:in */ 0, 10191 /*128:out */ X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_OE | BS3_MXCSR_DM_FIXED, 10192 /*256:out */ -1, 10193 /*xcpt? */ false, false }, 10194 { { /* 42.0 / DENORM_MIN = INF &_DE &!_PE(if !OM && DM) &_OE */ 10195 /*src2 */ { FP64_DENORM_MIN(0), FP64_0(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 10196 { /*src1 */ { FP64_V(0, 0x5000000000000, 0x404)/*42.0*/, FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 10197 { /* => */ { FP64_INF(0), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 10198 /*mxcsr:in */ X86_MXCSR_DM, 10199 /*128:out */ X86_MXCSR_DM | X86_MXCSR_DE | X86_MXCSR_OE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_OM_FIXED, 10200 /*256:out */ -1, 10201 /*xcpt? */ false, false }, 10202 { { /* ~DMASKED: 42.0 / DENORM_MIN = INF &_DE &_OE &!_PE(if !DM)*/ 10203 /*src2 */ { FP64_DENORM_MIN(0), FP64_0(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 10204 { /*src1 */ { FP64_V(0, 0x5000000000000, 0x404)/*42.0*/, FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 10205 { /* => */ { FP64_INF(0), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 10206 /*mxcsr:in */ 0, 10207 /*128:out */ X86_MXCSR_DE | X86_MXCSR_OE | BS3_MXCSR_DM_FIXED, 10208 /*256:out */ -1, 10209 /*xcpt? */ true, true }, 10210 { { /* ~OMASKED: 42.0 / DENORM_MIN = INF &_DE &_OE &!_PE(if !OM)*/ 10211 /*src2 */ { FP64_DENORM_MIN(0), FP64_0(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 10212 { /*src1 */ { FP64_V(0, 0x5000000000000, 0x404)/*42.0*/, FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 10213 { /* => */ { FP64_INF(0), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 10214 /*mxcsr:in */ 0, 10215 /*128:out */ X86_MXCSR_DE | X86_MXCSR_OE | BS3_MXCSR_OM_FIXED, 10216 /*256:out */ -1, 10217 /*xcpt? */ true, true }, 10218 { { /* DOMASKED: 42.0 / DENORM_MIN = INF &_DE &_OE &_PE(if DM && OM) */ 10219 /*src2 */ { FP64_DENORM_MIN(0), FP64_0(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 10220 { /*src1 */ { FP64_V(0, 0x5000000000000, 0x404)/*42.0*/, FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 10221 { /* => */ { FP64_INF(0), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 10222 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_OM, 10223 /*128:out */ X86_MXCSR_DM | X86_MXCSR_OM | X86_MXCSR_DE | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_OM_FIXED, 10224 /*256:out */ -1, 10225 /*xcpt? */ true, true }, 10226 { { /* DAZ: 42.0 / DENORM_MIN = INF &_ZE */ 10227 /*src2 */ { FP64_DENORM_MIN(0), FP64_0(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 10228 { /*src1 */ { FP64_V(0, 0x5000000000000, 0x404)/*42.0*/, FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 10229 { /* => */ { FP64_INF(0), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 10079 10230 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ, 10080 10231 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_ZE | X86_MXCSR_DAZ, 10081 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_ZE | X86_MXCSR_DAZ, 10082 /*xcpt? */ false, false }, 10083 { { /* MASKED: DENORM_MAX / -42.0 = -5e-310 &_DE &_PE &_UE */ 10084 /*src2 */ { FP64_V(1, 0x5000000000000, 0x404)/*-42.0*/, FP64_0(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 10085 { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 10086 { /* => */ { FP64_V(1, 0x618618618618, 0)/*-5.29XYZe-310*/, FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 10087 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 10088 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_UE, 10089 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_UE, 10232 /*256:out */ -1, 10233 /*xcpt? */ false, false }, 10234 { { /* DENORM_MAX / -42.0 = -5e-310 &_DE &_PE(if UM) &_UE */ 10235 /*src2 */ { FP64_V(1, 0x5000000000000, 0x404)/*-42.0*/, FP64_0(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 10236 { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 10237 { /* => */ { FP64_V(1, 0x618618618618, 0)/*-5.29XYZe-310*/, FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 10238 /*mxcsr:in */ X86_MXCSR_UM, 10239 /*128:out */ X86_MXCSR_UM | X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_UE | BS3_MXCSR_UM_FIXED, 10240 /*256:out */ -1, 10241 /*xcpt? */ false, false }, 10242 { { /* DENORM_MAX / -42.0 = -5e-310 &_DE &_PE(if !DM) &_UE */ 10243 /*src2 */ { FP64_V(1, 0x5000000000000, 0x404)/*-42.0*/, FP64_0(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 10244 { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 10245 { /* => */ { FP64_V(1, 0x618618618618, 0)/*-5.29XYZe-310*/, FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 10246 /*mxcsr:in */ 0, 10247 /*128:out */ X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED, 10248 /*256:out */ -1, 10090 10249 /*xcpt? */ false, false }, 10091 10250 #ifdef TODO_X86_MXCSR_PE /** @todo THIS FAILS ON IEM: X86_MXCSR_PE not set in 128:out */ 10092 { { /* ~UMASKED: DENORM_MAX / 42.0 = 5e-310 &_DE &_PE &&_UE */10093 /*src2 */ { FP64_V( 0, 0x5000000000000, 0x404)/*-42.0*/, FP64_0(0),FP64_RAND_V2(0), FP64_RAND_V1(1) } },10094 { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0),FP64_RAND_V1(1), FP64_RAND_V3(0) } },10095 { /* => */ { FP64_V( 0, 0x618618618618, 0)/*-5.29XYZe-310*/, FP64_DENORM_MIN(0),FP64_RAND_V1(1), FP64_RAND_V3(0) } },10096 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK & ~X86_MXCSR_UM,10097 /*128:out */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_UM) | X86_MXCSR_PE | X86_MXCSR_DE | X86_MXCSR_UE, // | BS3_MXCSR_PE_FUZZY /* IEM: when converted to Worker1A */10098 /*256:out */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_UM) | X86_MXCSR_PE | X86_MXCSR_DE | X86_MXCSR_UE,10099 /*xcpt? */ true, true },10251 /*--|41*/{ { /* DENORM_MAX / -42.0 = -5e-310 &_DE &!_PE(if DM && !UM) &_UE */ 10252 /*src2 */ { FP64_V(1, 0x5000000000000, 0x404)/*-42.0*/, FP64_0(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 10253 { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 10254 { /* => */ { FP64_V(1, 0x618618618618, 0)/*-5.29XYZe-310*/, FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 10255 /*mxcsr:in */ X86_MXCSR_DM, 10256 /*128:out */ X86_MXCSR_DM | X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 10257 /*256:out */ -1, 10258 /*xcpt? */ false, false }, 10100 10259 #endif /* TODO_X86_MXCSR_PE */ 10101 { { /* DAZ+MASK: DENORM_MAX / -42.0 = -0 &- */ 10102 /*src2 */ { FP64_V(1, 0x5000000000000, 0x404)/*-42.0*/, FP64_0(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 10103 { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 10104 { /* => */ { FP64_0(1), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 10260 /*41|42*/{ { /* UMASKED: DENORM_MAX / 42.0 = 5e-310 &_DE &_PE(if UM) &_UE */ 10261 /*src2 */ { FP64_V(0, 0x5000000000000, 0x404)/*-42.0*/, FP64_0(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 10262 { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 10263 { /* => */ { FP64_V(0, 0x618618618618, 0)/*-5.29XYZe-310*/, FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 10264 /*mxcsr:in */ X86_MXCSR_UM, 10265 /*128:out */ X86_MXCSR_UM | X86_MXCSR_PE | X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_UM_FIXED, 10266 /*256:out */ -1, 10267 /*xcpt? */ true, true }, 10268 { { /* ~DMASKED: DENORM_MAX / 42.0 = 5e-310 &_DE &_PE(if !DM) &_UE */ 10269 /*src2 */ { FP64_V(0, 0x5000000000000, 0x404)/*-42.0*/, FP64_0(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 10270 { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 10271 { /* => */ { FP64_V(0, 0x618618618618, 0)/*-5.29XYZe-310*/, FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 10272 /*mxcsr:in */ 0, 10273 /*128:out */ X86_MXCSR_PE | X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED, 10274 /*256:out */ -1, 10275 /*xcpt? */ true, true }, 10276 #ifdef TODO_X86_MXCSR_PE /** @todo THIS FAILS ON IEM: X86_MXCSR_PE not set in 128:out */ 10277 /*--|44*/{ { /* D~UMASKED: DENORM_MAX / 42.0 = 5e-310 &_DE &!_PE(if DM && !UM) &_UE */ 10278 /*src2 */ { FP64_V(0, 0x5000000000000, 0x404)/*-42.0*/, FP64_0(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 10279 { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 10280 { /* => */ { FP64_V(0, 0x618618618618, 0)/*-5.29XYZe-310*/, FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 10281 /*mxcsr:in */ X86_MXCSR_DM, 10282 /*128:out */ X86_MXCSR_DM | X86_MXCSR_PE | X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 10283 /*256:out */ -1, 10284 /*xcpt? */ true, true }, 10285 #endif /* TODO_X86_MXCSR_PE */ 10286 /*43|45*/{ { /* DAZ: DENORM_MAX / -42.0 = -0 &- */ 10287 /*src2 */ { FP64_V(1, 0x5000000000000, 0x404)/*-42.0*/, FP64_0(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 10288 { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 10289 { /* => */ { FP64_0(1), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 10105 10290 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ, 10106 10291 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ, 10107 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,10108 /*xcpt? */ false, false }, 10109 { { /* DAZ+FZ +M:DENORM_MAX / -42.0 = -0 &- */10110 /*src2 */ { FP64_V(1, 0x5000000000000, 0x404)/*-42.0*/, FP64_0(0), 10111 { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0),FP64_RAND_V1(1), FP64_RAND_V3(0) } },10112 { /* => */ { FP64_0(1), FP64_DENORM_MIN(0),FP64_RAND_V1(1), FP64_RAND_V3(0) } },10292 /*256:out */ -1, 10293 /*xcpt? */ false, false }, 10294 { { /* DAZ+FZ: DENORM_MAX / -42.0 = -0 &- */ 10295 /*src2 */ { FP64_V(1, 0x5000000000000, 0x404)/*-42.0*/, FP64_0(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 10296 { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 10297 { /* => */ { FP64_0(1), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 10113 10298 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ, 10114 10299 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ, 10115 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ,10300 /*256:out */ -1, 10116 10301 /*xcpt? */ false, false }, 10117 10302 /** @todo how to usefully test FZ, RC_{NEAREST,UP,DOWN,ZERO} ? */ 10118 10119 10303 /* 10120 10304 * Invalids. 10121 10305 */ 10122 /*40*/ FP64_TABLE_D1_SD_INVALIDS10306 /*45|47*/ FP64_TABLE_D1_SD_INVALIDS 10123 10307 /** @todo Underflow, Precision; Rounding; FZ etc. */ 10124 10308 }; … … 10159 10343 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 10160 10344 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode); 10161 return bs3CpuInstr4_WorkerTestType1 (bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,10345 return bs3CpuInstr4_WorkerTestType1A(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 10162 10346 g_aXcptConfig3, RT_ELEMENTS(g_aXcptConfig3)); 10163 10347 }
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