- Timestamp:
- Oct 8, 2024 8:32:50 AM (7 weeks ago)
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trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32
r106228 r106229 247 247 #define FP32_RAND_V7(a_Sign) RTFLOAT32U_INIT_C(a_Sign, 0x05432f, 0xd7) 248 248 249 /* 250 * Zeroes and a set of seven random single-precision floating-point values primarily 251 * intended to be used for for unused arguments in scalar instructions. 252 */ 253 #define FP32_0_x7(a_Sign) FP32_0(a_Sign), FP32_0(a_Sign), FP32_0(a_Sign), \ 254 FP32_0(a_Sign), FP32_0(a_Sign), FP32_0(a_Sign), \ 255 FP32_0(a_Sign) 256 #define FP32_RAND_x7_V0 FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(0), \ 257 FP32_RAND_V3(0), FP32_NORM_V1(1), FP32_RAND_V5(1), \ 258 FP32_RAND_V6(0) 259 #define FP32_RAND_x7_V1 FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), \ 260 FP32_RAND_V4(1), FP32_QNAN(0), FP32_RAND_V2(1), \ 261 FP32_NORM_V0(1) 262 #define FP32_RAND_x7_V2 FP32_RAND_V1(0), FP32_RAND_V7(1), FP32_RAND_V6(1), \ 263 FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), \ 264 FP32_INF(0) 265 #define FP32_RAND_x7_V3 FP32_RAND_V6(1), FP32_QNAN(0), FP32_RAND_V2(1), \ 266 FP32_1(1), FP32_RAND_V1(0), FP32_INF(1), \ 267 FP32_RAND_V5(0) 268 #define FP32_RAND_x7_V4 FP32_RAND_V4(1), FP32_RAND_V6(0), FP32_RAND_V0(0), \ 269 FP32_RAND_V2(1), FP32_RAND_V1(0), FP32_1(1), \ 270 FP32_SNAN_MAX(1) 271 #define FP32_RAND_x7_V5 FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_QNAN_MAX(1), \ 272 FP32_QNAN_MAX(1), FP32_RAND_V1(0), FP32_RAND_V2(0), \ 273 FP32_RAND_V6(0) 274 #define FP32_RAND_x7_V6 FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V6(1), \ 275 FP32_RAND_V2(0), FP32_QNAN(1), FP32_QNAN_V(1, 0), \ 276 FP32_SNAN(1) 277 #define FP32_RAND_x7_V7 FP32_RAND_V7(0), FP32_RAND_V1(1), FP32_RAND_V2(0), \ 278 FP32_RAND_V6(1), FP32_QNAN_V(0, 1), FP32_RAND_V2(1), \ 279 FP32_NORM_SAFE_INT_MAX(1) 249 280 /* 250 281 * Double-precision (64 bits) floating-point defines. … … 4291 4322 * Zero. 4292 4323 */ 4293 /* 0*/{ { /*src2 */ { FP32_0(0), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },4294 { /*src1 */ { FP32_0(0), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },4295 { /* => */ { FP32_0(0), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },4296 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 4297 /*128:out */ X86_MXCSR_XCPT_MASK, 4298 /*256:out */ -1, 4299 /*xcpt? */ false, false }, 4300 { { /*src2 */ { FP32_0(0), FP32_RAND_ V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1)} },4301 { /*src1 */ { FP32_0(0), FP32_RAND_ V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0)} },4302 { /* => */ { FP32_0(0), FP32_RAND_ V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0)} },4324 /* 0*/{ { /*src2 */ { FP32_0(0), FP32_0_x7(0) } }, 4325 { /*src1 */ { FP32_0(0), FP32_0_x7(0) } }, 4326 { /* => */ { FP32_0(0), FP32_0_x7(0) } }, 4327 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 4328 /*128:out */ X86_MXCSR_XCPT_MASK, 4329 /*256:out */ -1, 4330 /*xcpt? */ false, false }, 4331 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V7 } }, 4332 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V0 } }, 4333 { /* => */ { FP32_0(0), FP32_RAND_x7_V0 } }, 4303 4334 /*mxcsr:in */ 0, 4304 4335 /*128:out */ 0, 4305 4336 /*256:out */ -1, 4306 4337 /*xcpt? */ false, false }, 4307 { { /*src2 */ { FP32_0(0), FP32_RAND_ V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1)} },4308 { /*src1 */ { FP32_0(0), FP32_RAND_ V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0)} },4309 { /* => */ { FP32_0(0), FP32_RAND_ V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0)} },4338 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V1 } }, 4339 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V2 } }, 4340 { /* => */ { FP32_0(0), FP32_RAND_x7_V2 } }, 4310 4341 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 4311 4342 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 4312 4343 /*256:out */ -1, 4313 4344 /*xcpt? */ false, false }, 4314 { { /*src2 */ { FP32_0(1), FP32_RAND_ V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1)} },4315 { /*src1 */ { FP32_0(1), FP32_RAND_ V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1)} },4316 { /* => */ { FP32_0(1), FP32_RAND_ V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1)} },4345 { { /*src2 */ { FP32_0(1), FP32_RAND_x7_V3 } }, 4346 { /*src1 */ { FP32_0(1), FP32_RAND_x7_V4 } }, 4347 { /* => */ { FP32_0(1), FP32_RAND_x7_V4 } }, 4317 4348 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 4318 4349 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 4319 4350 /*256:out */ -1, 4320 4351 /*xcpt? */ false, false }, 4321 { { /*src2 */ { FP32_0(0), FP32_RAND_ V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1)} },4322 { /*src1 */ { FP32_0(0), FP32_RAND_ V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1)} },4323 { /* => */ { FP32_0(0), FP32_RAND_ V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1)} },4352 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V5 } }, 4353 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V6 } }, 4354 { /* => */ { FP32_0(0), FP32_RAND_x7_V6 } }, 4324 4355 /*mxcsr:in */ X86_MXCSR_FZ, 4325 4356 /*128:out */ X86_MXCSR_FZ, 4326 4357 /*256:out */ -1, 4327 4358 /*xcpt? */ false, false }, 4328 { { /*src2 */ { FP32_0(0), FP32_RAND_ V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1)} },4329 { /*src1 */ { FP32_0(0), FP32_RAND_ V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0)} },4330 { /* => */ { FP32_0(0), FP32_RAND_ V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0)} },4359 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V3 } }, 4360 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V5 } }, 4361 { /* => */ { FP32_0(0), FP32_RAND_x7_V5 } }, 4331 4362 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN, 4332 4363 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN, … … 4336 4367 * Infinity. 4337 4368 */ 4338 /* 6*/{ { /*src2 */ { FP32_INF(0), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },4339 { /*src1 */ { FP32_INF(1), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },4340 { /* => */ { FP32_QNAN(1), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },4369 /* 6*/{ { /*src2 */ { FP32_INF(0), FP32_0_x7(0) } }, 4370 { /*src1 */ { FP32_INF(1), FP32_0_x7(0) } }, 4371 { /* => */ { FP32_QNAN(1), FP32_0_x7(0) } }, 4341 4372 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM, 4342 4373 /*128:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_IE, 4343 4374 /*256:out */ -1, 4344 4375 /*xcpt? */ true, true }, 4345 { { /*src2 */ { FP32_INF(0), FP32_RAND_ V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1)} },4346 { /*src1 */ { FP32_INF(1), FP32_RAND_ V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0)} },4347 { /* => */ { FP32_QNAN(1), FP32_RAND_ V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0)} },4376 { { /*src2 */ { FP32_INF(0), FP32_RAND_x7_V1 } }, 4377 { /*src1 */ { FP32_INF(1), FP32_RAND_x7_V2 } }, 4378 { /* => */ { FP32_QNAN(1), FP32_RAND_x7_V2 } }, 4348 4379 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO, 4349 4380 /*128:out */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 4350 4381 /*256:out */ -1, 4351 4382 /*xcpt? */ true, true }, 4352 { { /*src2 */ { FP32_INF(1), FP32_RAND_ V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1)} },4353 { /*src1 */ { FP32_INF(0), FP32_RAND_ V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0)} },4354 { /* => */ { FP32_QNAN(1), FP32_RAND_ V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0)} },4383 { { /*src2 */ { FP32_INF(1), FP32_RAND_x7_V4 } }, 4384 { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V5 } }, 4385 { /* => */ { FP32_QNAN(1), FP32_RAND_x7_V5 } }, 4355 4386 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 4356 4387 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, 4357 4388 /*256:out */ -1, 4358 4389 /*xcpt? */ false, false }, 4359 { { /*src2 */ { FP32_INF(0), FP32_RAND_ V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1)} },4360 { /*src1 */ { FP32_INF(1), FP32_RAND_ V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1)} },4361 { /* => */ { FP32_QNAN(1), FP32_RAND_ V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1)} },4390 { { /*src2 */ { FP32_INF(0), FP32_RAND_x7_V6 } }, 4391 { /*src1 */ { FP32_INF(1), FP32_RAND_x7_V3 } }, 4392 { /* => */ { FP32_QNAN(1), FP32_RAND_x7_V3 } }, 4362 4393 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, 4363 4394 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, 4364 4395 /*256:out */ -1, 4365 4396 /*xcpt? */ false, false }, 4366 { { /*src2 */ { FP32_INF(0), FP32_RAND_ V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1)} },4367 { /*src1 */ { FP32_INF(1), FP32_RAND_ V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0)} },4368 { /* => */ { FP32_QNAN(1), FP32_RAND_ V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0)} },4397 { { /*src2 */ { FP32_INF(0), FP32_RAND_x7_V5 } }, 4398 { /*src1 */ { FP32_INF(1), FP32_RAND_x7_V5 } }, 4399 { /* => */ { FP32_QNAN(1), FP32_RAND_x7_V5 } }, 4369 4400 /*mxcsr:in */ X86_MXCSR_FZ, 4370 4401 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_IE, 4371 4402 /*256:out */ -1, 4372 4403 /*xcpt? */ true, true }, 4373 { { /*src2 */ { FP32_INF(1), FP32_ 0(0), FP32_0(0), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V6(1)} },4374 { /*src1 */ { FP32_INF(0), FP32_ 0(1), FP32_0(1), FP32_RAND_V3(1), FP32_RAND_V1(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1)} },4375 { /* => */ { FP32_QNAN(1), FP32_ 0(1), FP32_0(1), FP32_RAND_V3(1), FP32_RAND_V1(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1)} },4404 { { /*src2 */ { FP32_INF(1), FP32_RAND_x7_V1 } }, 4405 { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V3 } }, 4406 { /* => */ { FP32_QNAN(1), FP32_RAND_x7_V3 } }, 4376 4407 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 4377 4408 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, … … 4381 4412 * Overflow, Precision. 4382 4413 */ 4383 /*12*/{ { /*src2 */ { FP32_NORM_MAX(1), FP32_ 0(0), FP32_0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V6(1)} },4384 { /*src1 */ { FP32_NORM_MAX(1), FP32_ 0(1), FP32_0(1), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1)} },4385 { /* => */ { FP32_0(0), FP32_ 0(1), FP32_0(1), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1)} },4414 /*12*/{ { /*src2 */ { FP32_NORM_MAX(1), FP32_RAND_x7_V3 } }, 4415 { /*src1 */ { FP32_NORM_MAX(1), FP32_RAND_x7_V2 } }, 4416 { /* => */ { FP32_0(0), FP32_RAND_x7_V2 } }, 4386 4417 /*mxcsr:in */ 0, 4387 4418 /*128:out */ X86_MXCSR_OE | BS3_MXCSR_OM_FIXED, 4388 4419 /*256:out */ -1, 4389 4420 /*xcpt? */ true, true }, 4390 { { /*src2 */ { FP32_NORM_MAX(1), FP32_ 0(0), FP32_0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V6(1)} },4391 { /*src1 */ { FP32_NORM_MAX(1), FP32_ 0(1), FP32_0(1), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1)} },4392 { /* => */ { FP32_INF(1), FP32_ 0(1), FP32_0(1), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1)} },4421 { { /*src2 */ { FP32_NORM_MAX(1), FP32_RAND_x7_V4 } }, 4422 { /*src1 */ { FP32_NORM_MAX(1), FP32_RAND_x7_V5 } }, 4423 { /* => */ { FP32_INF(1), FP32_RAND_x7_V5 } }, 4393 4424 /*mxcsr:in */ X86_MXCSR_OM, 4394 4425 /*128:out */ X86_MXCSR_OM | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_OM_FIXED, 4395 4426 /*256:out */ -1, 4396 4427 /*xcpt? */ true, true }, 4397 { { /*src2 */ { FP32_NORM_MAX(0), FP32_RAND_ V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1)} },4398 { /*src1 */ { FP32_NORM_MAX(0), FP32_RAND_ V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0)} },4399 { /* => */ { FP32_INF(0), FP32_RAND_ V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0)} },4428 { { /*src2 */ { FP32_NORM_MAX(0), FP32_RAND_x7_V7 } }, 4429 { /*src1 */ { FP32_NORM_MAX(0), FP32_RAND_x7_V0 } }, 4430 { /* => */ { FP32_INF(0), FP32_RAND_x7_V0 } }, 4400 4431 /*mxcsr:in */ 0, 4401 4432 /*128:out */ X86_MXCSR_OE | BS3_MXCSR_OM_FIXED, 4402 4433 /*256:out */ -1, 4403 4434 /*xcpt? */ false, false }, 4404 { { /*src2 */ { FP32_NORM_MAX(0), FP32_RAND_ V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1)} },4405 { /*src1 */ { FP32_NORM_MAX(0), FP32_RAND_ V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0)} },4406 { /* => */ { FP32_INF(0), FP32_RAND_ V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0)} },4435 { { /*src2 */ { FP32_NORM_MAX(0), FP32_RAND_x7_V3 } }, 4436 { /*src1 */ { FP32_NORM_MAX(0), FP32_RAND_x7_V1 } }, 4437 { /* => */ { FP32_INF(0), FP32_RAND_x7_V1 } }, 4407 4438 /*mxcsr:in */ X86_MXCSR_OM, 4408 4439 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PE | X86_MXCSR_OE | BS3_MXCSR_OM_FIXED, 4409 4440 /*256:out */ -1, 4410 4441 /*xcpt? */ false, false }, 4411 { { /*src2 */ { FP32_RAND_V0(1), FP32_RAND_ V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1)} },4412 { /*src1 */ { FP32_NORM_MAX(1), FP32_RAND_ V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0)} },4413 { /* => */ { FP32_NORM_MAX(1), FP32_RAND_ V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0)} },4442 { { /*src2 */ { FP32_RAND_V0(1), FP32_RAND_x7_V4 } }, 4443 { /*src1 */ { FP32_NORM_MAX(1), FP32_RAND_x7_V1 } }, 4444 { /* => */ { FP32_NORM_MAX(1), FP32_RAND_x7_V1 } }, 4414 4445 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM, 4415 4446 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_PE, 4416 4447 /*256:out */ -1, 4417 4448 /*xcpt? */ false, false }, 4418 { { /*src2 */ { FP32_NORM_MAX(1), FP32_RAND_ V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1)} },4419 { /*src1 */ { FP32_NORM_MAX(1), FP32_RAND_ V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0)} },4420 { /* => */ { FP32_INF(1), FP32_RAND_ V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0)} },4449 { { /*src2 */ { FP32_NORM_MAX(1), FP32_RAND_x7_V5 } }, 4450 { /*src1 */ { FP32_NORM_MAX(1), FP32_RAND_x7_V1 } }, 4451 { /* => */ { FP32_INF(1), FP32_RAND_x7_V1 } }, 4421 4452 /*mxcsr:in */ 0, 4422 4453 /*128:out */ X86_MXCSR_OE | BS3_MXCSR_OM_FIXED, 4423 4454 /*256:out */ -1, 4424 4455 /*xcpt? */ false, false }, 4425 { { /*src2 */ { FP32_NORM_MAX(1), FP32_RAND_ V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1)} },4426 { /*src1 */ { FP32_NORM_MAX(1), FP32_RAND_ V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0)} },4427 { /* => */ { FP32_INF(1), FP32_RAND_ V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0)} },4456 { { /*src2 */ { FP32_NORM_MAX(1), FP32_RAND_x7_V5 } }, 4457 { /*src1 */ { FP32_NORM_MAX(1), FP32_RAND_x7_V2 } }, 4458 { /* => */ { FP32_INF(1), FP32_RAND_x7_V2 } }, 4428 4459 /*mxcsr:in */ X86_MXCSR_OM, 4429 4460 /*128:out */ X86_MXCSR_OM | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_OM_FIXED, 4430 4461 /*256:out */ -1, 4431 4462 /*xcpt? */ false, false }, 4432 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_ V5(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V3(1), FP32_RAND_V2(1)} },4433 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_ V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0)} },4434 { /* => */ { FP32_V(0, FP32_FRAC_NORM_MAX, FP32_EXP_SAFE_INT_MAX), FP32_RAND_ V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0)} },4463 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_x7_V3 } }, 4464 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V0 } }, 4465 { /* => */ { FP32_V(0, FP32_FRAC_NORM_MAX, FP32_EXP_SAFE_INT_MAX), FP32_RAND_x7_V0 } }, 4435 4466 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 4436 4467 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, 4437 4468 /*256:out */ -1, 4438 4469 /*xcpt? */ true, true }, 4439 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(1), FP32_RAND_ V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1)} },4440 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(1), FP32_RAND_ V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V0(0), FP32_RAND_V5(1)} },4441 { /* => */ { FP32_V(1, FP32_FRAC_NORM_MAX, FP32_EXP_SAFE_INT_MAX), FP32_RAND_ V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V0(0), FP32_RAND_V5(1)} },4470 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(1), FP32_RAND_x7_V6 } }, 4471 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(1), FP32_RAND_x7_V4 } }, 4472 { /* => */ { FP32_V(1, FP32_FRAC_NORM_MAX, FP32_EXP_SAFE_INT_MAX), FP32_RAND_x7_V4 } }, 4442 4473 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 4443 4474 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, … … 4447 4478 * Normals. 4448 4479 */ 4449 /*21*/{ { /*src2 */ { FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_RAND_ V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1)} },4450 { /*src1 */ { FP32_V(1, 0, 0x7d)/*-0.25*/, FP32_RAND_ V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V0(0), FP32_RAND_V5(1)} },4451 { /* => */ { FP32_V(0, 0x400000, 0x7f)/* 1.50*/, FP32_RAND_ V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V0(0), FP32_RAND_V5(1)} },4480 /*21*/{ { /*src2 */ { FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_RAND_x7_V4 } }, 4481 { /*src1 */ { FP32_V(1, 0, 0x7d)/*-0.25*/, FP32_RAND_x7_V2 } }, 4482 { /* => */ { FP32_V(0, 0x400000, 0x7f)/* 1.50*/, FP32_RAND_x7_V2 } }, 4452 4483 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 4453 4484 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 4454 4485 /*256:out */ -1, 4455 4486 /*xcpt? */ false, false }, 4456 { { /*src2 */ { FP32_NORM_MAX(0), FP32_RAND_ V5(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V3(1), FP32_RAND_V2(1)} },4457 { /*src1 */ { FP32_NORM_MAX(1), FP32_RAND_ V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0)} },4458 { /* => */ { FP32_0(0), FP32_RAND_ V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0)} },4487 { { /*src2 */ { FP32_NORM_MAX(0), FP32_RAND_x7_V3 } }, 4488 { /*src1 */ { FP32_NORM_MAX(1), FP32_RAND_x7_V3 } }, 4489 { /* => */ { FP32_0(0), FP32_RAND_x7_V3 } }, 4459 4490 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 4460 4491 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 4461 4492 /*256:out */ -1, 4462 4493 /*xcpt? */ false, false }, 4463 { { /*src2 */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_RAND_ V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1)} },4464 { /*src1 */ { FP32_V(0, 0x1ea980, 0x8f)/* 81235*/, FP32_RAND_ V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0)} },4465 { /* => */ { FP32_V(0, 0x669050, 0x93)/*1888778*/, FP32_RAND_ V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0)} },4494 { { /*src2 */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_RAND_x7_V2 } }, 4495 { /*src1 */ { FP32_V(0, 0x1ea980, 0x8f)/* 81235*/, FP32_RAND_x7_V1 } }, 4496 { /* => */ { FP32_V(0, 0x669050, 0x93)/*1888778*/, FP32_RAND_x7_V1 } }, 4466 4497 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 4467 4498 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 4468 4499 /*256:out */ -1, 4469 4500 /*xcpt? */ false, false }, 4470 { { /*src2 */ { FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_RAND_ V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1)} },4471 { /*src1 */ { FP32_V(0, 0x7c9000, 0x88)/* 1010.25*/, FP32_RAND_ V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0)} },4472 { /* => */ { FP32_V(0, 0x253468, 0x93)/*1353357.00*/, FP32_RAND_ V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0)} },4501 { { /*src2 */ { FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_RAND_x7_V1 } }, 4502 { /*src1 */ { FP32_V(0, 0x7c9000, 0x88)/* 1010.25*/, FP32_RAND_x7_V3 } }, 4503 { /* => */ { FP32_V(0, 0x253468, 0x93)/*1353357.00*/, FP32_RAND_x7_V3 } }, 4473 4504 /*mxcsr:in */ 0, 4474 4505 /*128:out */ 0, 4475 4506 /*256:out */ -1, 4476 4507 /*xcpt? */ false, false }, 4477 { { /*src2 */ { FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_RAND_ V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1)} },4478 { /*src1 */ { FP32_V(1, 0x712060, 0x92)/*- 987654*/, FP32_RAND_ V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0)} },4479 { /* => */ { FP32_V(0, 0x6cb99c, 0x97)/*31028024*/, FP32_RAND_ V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0)} },4508 { { /*src2 */ { FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_RAND_x7_V3 } }, 4509 { /*src1 */ { FP32_V(1, 0x712060, 0x92)/*- 987654*/, FP32_RAND_x7_V5 } }, 4510 { /* => */ { FP32_V(0, 0x6cb99c, 0x97)/*31028024*/, FP32_RAND_x7_V5 } }, 4480 4511 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 4481 4512 /*128:out */ X86_MXCSR_RC_ZERO, 4482 4513 /*256:out */ -1, 4483 4514 /*xcpt? */ false, false }, 4484 { { /*src2 */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_RAND_ V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1)} },4485 { /*src1 */ { FP32_1(0), FP32_RAND_ V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0)} },4486 { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_ V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0)} },4515 { { /*src2 */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_RAND_x7_V5 } }, 4516 { /*src1 */ { FP32_1(0), FP32_RAND_x7_V2 } }, 4517 { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V2 } }, 4487 4518 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 4488 4519 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 4489 4520 /*256:out */ -1, 4490 4521 /*xcpt? */ false, false }, 4491 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_ V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1)} },4492 { /*src1 */ { FP32_1(1), FP32_RAND_ V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0)} },4493 { /* => */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_RAND_ V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0)} },4522 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V4 } }, 4523 { /*src1 */ { FP32_1(1), FP32_RAND_x7_V3 } }, 4524 { /* => */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_RAND_x7_V3 } }, 4494 4525 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 4495 4526 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 4496 4527 /*256:out */ -1, 4497 4528 /*xcpt? */ false, false }, 4498 { { /*src2 */ { FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_RAND_ V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1)} },4499 { /*src1 */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_RAND_ V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0)} },4500 { /* => */ { FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/, FP32_RAND_ V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0)} },4529 { { /*src2 */ { FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_RAND_x7_V1 } }, 4530 { /*src1 */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_RAND_x7_V1 } }, 4531 { /* => */ { FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/, FP32_RAND_x7_V1 } }, 4501 4532 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 4502 4533 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 4503 4534 /*256:out */ -1, 4504 4535 /*xcpt? */ false, false }, 4505 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_ V3(0), FP32_RAND_V4(0), FP32_RAND_V0(1), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V6(1)} },4506 { /*src1 */ { FP32_NORM_SAFE_INT_MIN(1), FP32_RAND_ V3(1), FP32_RAND_V1(0), FP32_RAND_V0(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1)} },4507 { /* => */ { FP32_0(0), FP32_RAND_ V3(1), FP32_RAND_V1(0), FP32_RAND_V0(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1)} },4536 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_x7_V2 } }, 4537 { /*src1 */ { FP32_NORM_SAFE_INT_MIN(1), FP32_RAND_x7_V3 } }, 4538 { /* => */ { FP32_0(0), FP32_RAND_x7_V3 } }, 4508 4539 /*mxcsr:in */ X86_MXCSR_FZ, 4509 4540 /*128:out */ X86_MXCSR_FZ, … … 4513 4544 * Denormals. 4514 4545 */ 4515 /*30*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_ V5(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(0)} },4516 { /*src1 */ { FP32_0(0), FP32_RAND_ V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0)} },4517 { /* => */ { FP32_0(0), FP32_RAND_ V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0)} },4546 /*30*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V7 } }, 4547 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V6 } }, 4548 { /* => */ { FP32_0(0), FP32_RAND_x7_V6 } }, 4518 4549 /*mxcsr:in */ 0, 4519 4550 /*128:out */ X86_MXCSR_DE | BS3_MXCSR_DM_FIXED, … … 4521 4552 /*xcpt? */ true, true }, 4522 4553 #ifdef TODO_X86_MXCSR_UE_IEM /** @todo THIS FAILS ON IEM: X86_MXCSR_UE not set in 128:out *AND* different output values */ 4523 /*--|31*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_ V5(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(0)} },4524 { /*src1 */ { FP32_0(0), FP32_RAND_ V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0)} },4525 { /* => */ { FP32_0(0), FP32_RAND_ V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0) } } /* result on HW (i7-10700) */,4554 /*--|31*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V5 } }, 4555 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V4 } }, 4556 { /* => */ { FP32_0(0), FP32_RAND_x7_V4 } }, 4526 4557 // IEM: { /* => */ { FP32_DENORM_MAX(0), FP32_RAND_V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0) } } /* result on IEM */, 4527 4558 /*mxcsr:in */ X86_MXCSR_DM, … … 4530 4561 /*xcpt? */ true, true }, 4531 4562 #endif /* TODO_X86_MXCSR_UE_IEM */ 4532 /*31|32*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_ V5(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(0)} },4533 { /*src1 */ { FP32_0(0), FP32_RAND_ V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0)} },4534 { /* => */ { FP32_DENORM_MAX(0), FP32_RAND_ V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0)} },4563 /*31|32*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V1 } }, 4564 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V2 } }, 4565 { /* => */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V2 } }, 4535 4566 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_UM, 4536 4567 /*128:out */ X86_MXCSR_DM | X86_MXCSR_UM | X86_MXCSR_DE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 4537 4568 /*256:out */ -1, 4538 4569 /*xcpt? */ true, true }, 4539 { { /*src2 */ { FP32_0(0), FP32_RAND_ V1(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V6(1)} },4540 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_ V1(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1)} },4541 { /* => */ { FP32_0(0), FP32_RAND_ V1(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1)} },4570 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V6 } }, 4571 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V5 } }, 4572 { /* => */ { FP32_0(0), FP32_RAND_x7_V5 } }, 4542 4573 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 4543 4574 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED, 4544 4575 /*256:out */ -1, 4545 4576 /*xcpt? */ false, false }, 4546 { { /*src2 */ { FP32_0(0), FP32_RAND_ V1(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V6(1)} },4547 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_ V1(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1)} },4548 { /* => */ { FP32_0(0), FP32_RAND_ V1(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1)} },4577 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V1 } }, 4578 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V2 } }, 4579 { /* => */ { FP32_0(0), FP32_RAND_x7_V2 } }, 4549 4580 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 4550 4581 /*128:out */ X86_MXCSR_DM | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 4551 4582 /*256:out */ -1, 4552 4583 /*xcpt? */ false, false }, 4553 { { /*src2 */ { FP32_0(0), FP32_RAND_ V1(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V6(1)} },4554 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_ V1(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1)} },4555 { /* => */ { FP32_0(0), FP32_RAND_ V1(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1)} },4584 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V4 } }, 4585 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V3 } }, 4586 { /* => */ { FP32_0(0), FP32_RAND_x7_V3 } }, 4556 4587 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_UM | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 4557 4588 /*128:out */ X86_MXCSR_DM | X86_MXCSR_UM | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 4558 4589 /*256:out */ -1, 4559 4590 /*xcpt? */ false, false }, 4560 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_RAND_ V3(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V7(0)} },4561 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_ V3(1), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V6(1)} },4562 { /* => */ { FP32_NORM_MIN(0), FP32_RAND_ V3(1), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V6(1)} },4591 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_RAND_x7_V5 } }, 4592 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V1 } }, 4593 { /* => */ { FP32_NORM_MIN(0), FP32_RAND_x7_V1 } }, 4563 4594 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_DE, 4564 4595 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_DE, … … 6439 6470 * Zero. 6440 6471 */ 6441 /* 0*/{ { /*src2 */ { FP32_0(0), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },6442 { /*src1 */ { FP32_0(0), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },6443 { /* => */ { FP32_0(0), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },6444 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 6445 /*128:out */ X86_MXCSR_XCPT_MASK, 6446 /*256:out */ -1, 6447 /*xcpt? */ false, false }, 6448 { { /*src2 */ { FP32_0(0), FP32_RAND_ V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1)} },6449 { /*src1 */ { FP32_0(0), FP32_RAND_ V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0)} },6450 { /* => */ { FP32_0(0), FP32_RAND_ V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0)} },6472 /* 0*/{ { /*src2 */ { FP32_0(0), FP32_0_x7(0) } }, 6473 { /*src1 */ { FP32_0(0), FP32_0_x7(0) } }, 6474 { /* => */ { FP32_0(0), FP32_0_x7(0) } }, 6475 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 6476 /*128:out */ X86_MXCSR_XCPT_MASK, 6477 /*256:out */ -1, 6478 /*xcpt? */ false, false }, 6479 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V0 } }, 6480 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V1 } }, 6481 { /* => */ { FP32_0(0), FP32_RAND_x7_V1 } }, 6451 6482 /*mxcsr:in */ 0, 6452 6483 /*128:out */ 0, 6453 6484 /*256:out */ -1, 6454 6485 /*xcpt? */ false, false }, 6455 { { /*src2 */ { FP32_0(0), FP32_RAND_ V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1)} },6456 { /*src1 */ { FP32_0(0), FP32_RAND_ V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0)} },6457 { /* => */ { FP32_0(0), FP32_RAND_ V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0)} },6486 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V1 } }, 6487 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V2 } }, 6488 { /* => */ { FP32_0(0), FP32_RAND_x7_V2 } }, 6458 6489 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 6459 6490 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 6460 6491 /*256:out */ -1, 6461 6492 /*xcpt? */ false, false }, 6462 { { /*src2 */ { FP32_0(1), FP32_RAND_ V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1)} },6463 { /*src1 */ { FP32_0(1), FP32_RAND_ V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1)} },6464 { /* => */ { FP32_0(0), FP32_RAND_ V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1)} },6493 { { /*src2 */ { FP32_0(1), FP32_RAND_x7_V3 } }, 6494 { /*src1 */ { FP32_0(1), FP32_RAND_x7_V4 } }, 6495 { /* => */ { FP32_0(0), FP32_RAND_x7_V4 } }, 6465 6496 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 6466 6497 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 6467 6498 /*256:out */ -1, 6468 6499 /*xcpt? */ false, false }, 6469 { { /*src2 */ { FP32_0(0), FP32_RAND_ V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1)} },6470 { /*src1 */ { FP32_0(0), FP32_RAND_ V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1)} },6471 { /* => */ { FP32_0(1), FP32_RAND_ V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1)} },6500 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V6 } }, 6501 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V7 } }, 6502 { /* => */ { FP32_0(1), FP32_RAND_x7_V7 } }, 6472 6503 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 6473 6504 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 6474 6505 /*256:out */ -1, 6475 6506 /*xcpt? */ false, false }, 6476 { { /*src2 */ { FP32_0(0), FP32_RAND_ V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1)} },6477 { /*src1 */ { FP32_0(0), FP32_RAND_ V0(1), FP32_RAND_V1(0), FP32_RAND_V3(1), FP32_RAND_V5(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1)} },6478 { /* => */ { FP32_0(1), FP32_RAND_ V0(1), FP32_RAND_V1(0), FP32_RAND_V3(1), FP32_RAND_V5(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1)} },6507 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V0 } }, 6508 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V3 } }, 6509 { /* => */ { FP32_0(1), FP32_RAND_x7_V3 } }, 6479 6510 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 6480 6511 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, … … 6484 6515 * Infinity. 6485 6516 */ 6486 /* 6*/{ { /*src2 */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },6487 { /*src1 */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },6488 { /* => */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },6517 /* 6*/{ { /*src2 */ { FP32_INF(0), FP32_0_x7(0) } }, 6518 { /*src1 */ { FP32_INF(1), FP32_0_x7(0) } }, 6519 { /* => */ { FP32_INF(1), FP32_0_x7(0) } }, 6489 6520 /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM, 6490 6521 /*128:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM, 6491 6522 /*256:out */ -1, 6492 6523 /*xcpt? */ false, false }, 6493 { { /*src2 */ { FP32_INF(0), FP32_RAND_ V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1)} },6494 { /*src1 */ { FP32_INF(0), FP32_RAND_ V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0)} },6495 { /* => */ { FP32_QNAN(1), FP32_RAND_ V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0)} },6524 { { /*src2 */ { FP32_INF(0), FP32_RAND_x7_V6 } }, 6525 { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V7 } }, 6526 { /* => */ { FP32_QNAN(1), FP32_RAND_x7_V7 } }, 6496 6527 /*mxcsr:in */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM), 6497 6528 /*128:out */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_IE, 6498 6529 /*256:out */ -1, 6499 6530 /*xcpt? */ true, true }, 6500 { { /*src2 */ { FP32_INF(1), FP32_RAND_ V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1)} },6501 { /*src1 */ { FP32_INF(0), FP32_RAND_ V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0)} },6502 { /* => */ { FP32_INF(0), FP32_RAND_ V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0)} },6503 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 6504 /*128:out */ X86_MXCSR_XCPT_MASK, 6505 /*256:out */ -1, 6506 /*xcpt? */ false, false }, 6507 { { /*src2 */ { FP32_INF(1), FP32_RAND_ V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1)} },6508 { /*src1 */ { FP32_INF(1), FP32_RAND_ V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1)} },6509 { /* => */ { FP32_QNAN(1), FP32_RAND_ V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1)} },6531 { { /*src2 */ { FP32_INF(1), FP32_RAND_x7_V0 } }, 6532 { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V1 } }, 6533 { /* => */ { FP32_INF(0), FP32_RAND_x7_V1 } }, 6534 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 6535 /*128:out */ X86_MXCSR_XCPT_MASK, 6536 /*256:out */ -1, 6537 /*xcpt? */ false, false }, 6538 { { /*src2 */ { FP32_INF(1), FP32_RAND_x7_V4 } }, 6539 { /*src1 */ { FP32_INF(1), FP32_RAND_x7_V3 } }, 6540 { /* => */ { FP32_QNAN(1), FP32_RAND_x7_V3 } }, 6510 6541 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, 6511 6542 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE, 6512 6543 /*256:out */ -1, 6513 6544 /*xcpt? */ false, false }, 6514 { { /*src2 */ { FP32_INF(0), FP32_RAND_ V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1)} },6515 { /*src1 */ { FP32_INF(1), FP32_RAND_ V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0)} },6516 { /* => */ { FP32_INF(1), FP32_RAND_ V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0)} },6545 { { /*src2 */ { FP32_INF(0), FP32_RAND_x7_V5 } }, 6546 { /*src1 */ { FP32_INF(1), FP32_RAND_x7_V1 } }, 6547 { /* => */ { FP32_INF(1), FP32_RAND_x7_V1 } }, 6517 6548 /*mxcsr:in */ X86_MXCSR_FZ, 6518 6549 /*128:out */ X86_MXCSR_FZ, 6519 6550 /*256:out */ -1, 6520 6551 /*xcpt? */ false, false }, 6521 { { /*src2 */ { FP32_INF(1), FP32_ 0(0), FP32_0(0), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V6(1)} },6522 { /*src1 */ { FP32_INF(0), FP32_ 0(1), FP32_0(1), FP32_RAND_V3(1), FP32_RAND_V1(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1)} },6523 { /* => */ { FP32_INF(0), FP32_ 0(1), FP32_0(1), FP32_RAND_V3(1), FP32_RAND_V1(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1)} },6552 { { /*src2 */ { FP32_INF(1), FP32_RAND_x7_V1 } }, 6553 { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V2 } }, 6554 { /* => */ { FP32_INF(0), FP32_RAND_x7_V2 } }, 6524 6555 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 6525 6556 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, … … 6529 6560 * Overflow, Precision. 6530 6561 */ 6531 /*12*/{ { /*src2 */ { FP32_0(0), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_NORM_MIN(1), FP32_0(0), FP32_NORM_MIN(1), FP32_NORM_MIN(0) } },6532 { /*src1 */ { FP32_0(0), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0) } },6533 { /* => */ { FP32_0(0), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0)} },6562 /*12*/{ { /*src2 */ { FP32_0(0), FP32_0_x7(0) } }, 6563 { /*src1 */ { FP32_0(0), FP32_0_x7(0) } }, 6564 { /* => */ { FP32_0(0), FP32_0_x7(0) } }, 6534 6565 /*mxcsr:in */ 0, 6535 6566 /*128:out */ 0, 6536 6567 /*256:out */ -1, 6537 6568 /*xcpt? */ false, true }, 6538 { { /*src2 */ { FP32_NORM_MAX(0), FP32_ NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_MAX(0)} },6539 { /*src1 */ { FP32_NORM_MAX(1), FP32_ NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_MAX(0)} },6540 { /* => */ { FP32_NORM_MAX(1), FP32_ NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0)} },6569 { { /*src2 */ { FP32_NORM_MAX(0), FP32_RAND_x7_V2 } }, 6570 { /*src1 */ { FP32_NORM_MAX(1), FP32_RAND_x7_V3 } }, 6571 { /* => */ { FP32_NORM_MAX(1), FP32_RAND_x7_V3 } }, 6541 6572 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 6542 6573 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | BS3_MXCSR_OM_FIXED, 6543 6574 /*256:out */ -1, 6544 6575 /*xcpt? */ false, false }, 6545 { { /*src2 */ { FP32_NORM_MAX(0), FP32_ NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_MAX(0)} },6546 { /*src1 */ { FP32_NORM_MAX(1), FP32_ NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_MAX(0)} },6547 { /* => */ { FP32_NORM_MAX(1), FP32_ NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0)} },6576 { { /*src2 */ { FP32_NORM_MAX(0), FP32_RAND_x7_V5 } }, 6577 { /*src1 */ { FP32_NORM_MAX(1), FP32_RAND_x7_V4 } }, 6578 { /* => */ { FP32_NORM_MAX(1), FP32_RAND_x7_V4 } }, 6548 6579 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_RC_ZERO, 6549 6580 /*128:out */ X86_MXCSR_OM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_OM_FIXED, 6550 6581 /*256:out */ -1, 6551 6582 /*xcpt? */ false, false }, 6552 { { /*src2 */ { FP32_NORM_MAX(0), FP32_ 0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0)} },6553 { /*src1 */ { FP32_NORM_MAX(1), FP32_ 0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1)} },6554 { /* => */ { FP32_INF(1), FP32_ 0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1)} },6583 { { /*src2 */ { FP32_NORM_MAX(0), FP32_RAND_x7_V3 } }, 6584 { /*src1 */ { FP32_NORM_MAX(1), FP32_RAND_x7_V3 } }, 6585 { /* => */ { FP32_INF(1), FP32_RAND_x7_V3 } }, 6555 6586 /*mxcsr:in */ 0, 6556 6587 /*128:out */ X86_MXCSR_OE | BS3_MXCSR_OM_FIXED, 6557 6588 /*256:out */ -1, 6558 6589 /*xcpt? */ false, false }, 6559 { { /*src2 */ { FP32_NORM_MAX(0), FP32_ 0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0)} },6560 { /*src1 */ { FP32_NORM_MAX(1), FP32_ 0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1)} },6561 { /* => */ { FP32_INF(1), FP32_ 0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1)} },6590 { { /*src2 */ { FP32_NORM_MAX(0), FP32_RAND_x7_V4 } }, 6591 { /*src1 */ { FP32_NORM_MAX(1), FP32_RAND_x7_V6 } }, 6592 { /* => */ { FP32_INF(1), FP32_RAND_x7_V6 } }, 6562 6593 /*mxcsr:in */ X86_MXCSR_OM, 6563 6594 /*128:out */ X86_MXCSR_OM | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_OM_FIXED, 6564 6595 /*256:out */ -1, 6565 6596 /*xcpt? */ false, false }, 6566 { { /*src2 */ { FP32_NORM_MAX(0), FP32_ NORM_MIN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0)} },6567 { /*src1 */ { FP32_NORM_MAX(1), FP32_ NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0)} },6568 { /* => */ { FP32_INF(1), FP32_ NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0)} },6597 { { /*src2 */ { FP32_NORM_MAX(0), FP32_RAND_x7_V7 } }, 6598 { /*src1 */ { FP32_NORM_MAX(1), FP32_RAND_x7_V2 } }, 6599 { /* => */ { FP32_INF(1), FP32_RAND_x7_V2 } }, 6569 6600 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 6570 6601 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OE | BS3_MXCSR_OM_FIXED, 6571 6602 /*256:out */ -1, 6572 6603 /*xcpt? */ false, false }, 6573 { { /*src2 */ { FP32_NORM_MAX(0), FP32_ NORM_MIN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0)} },6574 { /*src1 */ { FP32_NORM_MAX(1), FP32_ NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0)} },6575 { /* => */ { FP32_INF(1), FP32_ NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0)} },6604 { { /*src2 */ { FP32_NORM_MAX(0), FP32_RAND_x7_V2 } }, 6605 { /*src1 */ { FP32_NORM_MAX(1), FP32_RAND_x7_V3 } }, 6606 { /* => */ { FP32_INF(1), FP32_RAND_x7_V3 } }, 6576 6607 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM, 6577 6608 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_OM_FIXED, 6578 6609 /*256:out */ -1, 6579 6610 /*xcpt? */ false, false }, 6580 { { /*src2 */ { FP32_NORM_MIN(1), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },6581 { /*src1 */ { FP32_NORM_MAX(0), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },6582 { /* => */ { FP32_NORM_MAX(0), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },6611 { { /*src2 */ { FP32_NORM_MIN(1), FP32_0_x7(0) } }, 6612 { /*src1 */ { FP32_NORM_MAX(0), FP32_0_x7(0) } }, 6613 { /* => */ { FP32_NORM_MAX(0), FP32_0_x7(0) } }, 6583 6614 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM, 6584 6615 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_PE, 6585 6616 /*256:out */ -1, 6586 6617 /*xcpt? */ false, false }, 6587 { { /*src2 */ { FP32_NORM_MAX(0), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },6588 { /*src1 */ { FP32_NORM_MAX(1), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },6589 { /* => */ { FP32_NORM_MAX(1), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },6618 { { /*src2 */ { FP32_NORM_MAX(0), FP32_0_x7(0) } }, 6619 { /*src1 */ { FP32_NORM_MAX(1), FP32_0_x7(0) } }, 6620 { /* => */ { FP32_NORM_MAX(1), FP32_0_x7(0) } }, 6590 6621 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 6591 6622 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | BS3_MXCSR_OM_FIXED, 6592 6623 /*256:out */ -1, 6593 6624 /*xcpt? */ false, false }, 6594 { { /*src2 */ { FP32_NORM_MAX(0), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },6595 { /*src1 */ { FP32_NORM_MAX(1), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },6596 { /* => */ { FP32_NORM_MAX(1), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },6625 { { /*src2 */ { FP32_NORM_MAX(0), FP32_0_x7(0) } }, 6626 { /*src1 */ { FP32_NORM_MAX(1), FP32_0_x7(0) } }, 6627 { /* => */ { FP32_NORM_MAX(1), FP32_0_x7(0) } }, 6597 6628 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_RC_ZERO, 6598 6629 /*128:out */ X86_MXCSR_OM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_OM_FIXED, 6599 6630 /*256:out */ -1, 6600 6631 /*xcpt? */ false, false }, 6601 { { /*src2 */ { FP32_NORM_MIN(1), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },6602 { /*src1 */ { FP32_NORM_MAX(1), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },6603 { /* => */ { FP32_V(1, FP32_FRAC_NORM_MAX - 1, FP32_EXP_NORM_MAX), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },6632 { { /*src2 */ { FP32_NORM_MIN(1), FP32_0_x7(0) } }, 6633 { /*src1 */ { FP32_NORM_MAX(1), FP32_0_x7(0) } }, 6634 { /* => */ { FP32_V(1, FP32_FRAC_NORM_MAX - 1, FP32_EXP_NORM_MAX), FP32_0_x7(0) } }, 6604 6635 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 6605 6636 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, 6606 6637 /*256:out */ -1, 6607 6638 /*xcpt? */ true, true }, 6608 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },6609 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },6610 { /* => */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },6639 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_0_x7(0) } }, 6640 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_0_x7(0) } }, 6641 { /* => */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_0_x7(0) } }, 6611 6642 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 6612 6643 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, 6613 6644 /*256:out */ -1, 6614 6645 /*xcpt? */ true, true }, 6615 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(1), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },6616 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(1), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },6617 { /* => */ { FP32_V(1, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },6646 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(1), FP32_0_x7(0) } }, 6647 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(1), FP32_0_x7(0) } }, 6648 { /* => */ { FP32_V(1, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_0_x7(0) } }, 6618 6649 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 6619 6650 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, … … 6623 6654 * Normals. 6624 6655 */ 6625 /*25*/{ { /*src2 */ { FP32_V(0, 0x600000, 0x7f)/*1.75*/, FP32_RAND_ V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1)} },6626 { /*src1 */ { FP32_V(0, 0, 0x7d)/*0.25*/, FP32_RAND_ V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V0(0), FP32_RAND_V5(1)} },6627 { /* => */ { FP32_V(1, 0x400000, 0x7f)/*1.50*/, FP32_RAND_ V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V0(0), FP32_RAND_V5(1)} },6656 /*25*/{ { /*src2 */ { FP32_V(0, 0x600000, 0x7f)/*1.75*/, FP32_RAND_x7_V1 } }, 6657 { /*src1 */ { FP32_V(0, 0, 0x7d)/*0.25*/, FP32_RAND_x7_V2 } }, 6658 { /* => */ { FP32_V(1, 0x400000, 0x7f)/*1.50*/, FP32_RAND_x7_V2 } }, 6628 6659 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 6629 6660 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 6630 6661 /*256:out */ -1, 6631 6662 /*xcpt? */ false, false }, 6632 { { /*src2 */ { FP32_NORM_MAX(1), FP32_RAND_ V5(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V3(1), FP32_RAND_V2(1)} },6633 { /*src1 */ { FP32_NORM_MAX(1), FP32_RAND_ V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0)} },6634 { /* => */ { FP32_0(0), FP32_RAND_ V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0)} },6663 { { /*src2 */ { FP32_NORM_MAX(1), FP32_RAND_x7_V3 } }, 6664 { /*src1 */ { FP32_NORM_MAX(1), FP32_RAND_x7_V4 } }, 6665 { /* => */ { FP32_0(0), FP32_RAND_x7_V4 } }, 6635 6666 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, 6636 6667 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, 6637 6668 /*256:out */ -1, 6638 6669 /*xcpt? */ false, false }, 6639 { { /*src2 */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_RAND_ V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1)} },6640 { /*src1 */ { FP32_V(0, 0x669050, 0x93)/*1888778*/, FP32_RAND_ V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0)} },6641 { /* => */ { FP32_V(0, 0x1ea980, 0x8f)/* 81235*/, FP32_RAND_ V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0)} },6642 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 6643 /*128:out */ X86_MXCSR_XCPT_MASK, 6644 /*256:out */ -1, 6645 /*xcpt? */ false, false }, 6646 { { /*src2 */ { FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_RAND_ V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1)} },6647 { /*src1 */ { FP32_V(0, 0x253468, 0x93)/*1353357.00*/, FP32_RAND_ V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0)} },6648 { /* => */ { FP32_V(0, 0x7c9000, 0x88)/* 1010.25*/, FP32_RAND_ V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0)} },6670 { { /*src2 */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_RAND_x7_V5 } }, 6671 { /*src1 */ { FP32_V(0, 0x669050, 0x93)/*1888778*/, FP32_RAND_x7_V6 } }, 6672 { /* => */ { FP32_V(0, 0x1ea980, 0x8f)/* 81235*/, FP32_RAND_x7_V6 } }, 6673 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 6674 /*128:out */ X86_MXCSR_XCPT_MASK, 6675 /*256:out */ -1, 6676 /*xcpt? */ false, false }, 6677 { { /*src2 */ { FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_RAND_x7_V7 } }, 6678 { /*src1 */ { FP32_V(0, 0x253468, 0x93)/*1353357.00*/, FP32_RAND_x7_V0 } }, 6679 { /* => */ { FP32_V(0, 0x7c9000, 0x88)/* 1010.25*/, FP32_RAND_x7_V0 } }, 6649 6680 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 6650 6681 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 6651 6682 /*256:out */ -1, 6652 6683 /*xcpt? */ false, false }, 6653 { { /*src2 */ { FP32_V(0, 0x712060, 0x92)/* 987654*/, FP32_RAND_ V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1)} },6654 { /*src1 */ { FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_RAND_ V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0)} },6655 { /* => */ { FP32_V(0, 0x6cb99c, 0x97)/*31028024*/, FP32_RAND_ V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0)} },6684 { { /*src2 */ { FP32_V(0, 0x712060, 0x92)/* 987654*/, FP32_RAND_x7_V0 } }, 6685 { /*src1 */ { FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_RAND_x7_V1 } }, 6686 { /* => */ { FP32_V(0, 0x6cb99c, 0x97)/*31028024*/, FP32_RAND_x7_V1 } }, 6656 6687 /*mxcsr:in */ 0, 6657 6688 /*128:out */ 0, 6658 6689 /*256:out */ -1, 6659 6690 /*xcpt? */ false, false }, 6660 { { /*src2 */ { FP32_1(0), FP32_RAND_ V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1)} },6661 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_ V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0)} },6662 { /* => */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_RAND_ V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0)} },6691 { { /*src2 */ { FP32_1(0), FP32_RAND_x7_V4 } }, 6692 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V4 } }, 6693 { /* => */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_RAND_x7_V4 } }, 6663 6694 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 6664 6695 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 6665 6696 /*256:out */ -1, 6666 6697 /*xcpt? */ false, false }, 6667 { { /*src2 */ { FP32_V(1, 0x600000, 0x7e)/* -0.875*/, FP32_RAND_ V1(0), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(0), FP32_RAND_V6(1), FP32_RAND_V3(1)} },6668 { /*src1 */ { FP32_V(0, 0x769b50, 0x92)/* 1010101.000*/, FP32_RAND_ V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0)} },6669 { /* => */ { FP32_V(0, 0x769b5e, 0x92)/* 1010101.875*/, FP32_RAND_ V2(0), FP32_RAND_V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V2(0)} },6670 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 6671 /*128:out */ X86_MXCSR_XCPT_MASK, 6672 /*256:out */ -1, 6673 /*xcpt? */ false, false }, 6674 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_ V3(0), FP32_RAND_V4(0), FP32_RAND_V0(1), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V6(1)} },6675 { /*src1 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_ V3(1), FP32_RAND_V1(0), FP32_RAND_V0(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1)} },6676 { /* => */ { FP32_0(0), FP32_RAND_ V3(1), FP32_RAND_V1(0), FP32_RAND_V0(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1)} },6698 { { /*src2 */ { FP32_V(1, 0x600000, 0x7e)/* -0.875*/, FP32_RAND_x7_V5 } }, 6699 { /*src1 */ { FP32_V(0, 0x769b50, 0x92)/* 1010101.000*/, FP32_RAND_x7_V6 } }, 6700 { /* => */ { FP32_V(0, 0x769b5e, 0x92)/* 1010101.875*/, FP32_RAND_x7_V6 } }, 6701 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 6702 /*128:out */ X86_MXCSR_XCPT_MASK, 6703 /*256:out */ -1, 6704 /*xcpt? */ false, false }, 6705 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_x7_V1 } }, 6706 { /*src1 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_x7_V3 } }, 6707 { /* => */ { FP32_0(0), FP32_RAND_x7_V3 } }, 6677 6708 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 6678 6709 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ, … … 6682 6713 * Denormals. 6683 6714 */ 6684 /*33*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_ V5(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(0)} },6685 { /*src1 */ { FP32_0(0), FP32_RAND_ V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0)} },6686 { /* => */ { FP32_0(0), FP32_RAND_ V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0)} },6715 /*33*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V1 } }, 6716 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V2 } }, 6717 { /* => */ { FP32_0(0), FP32_RAND_x7_V2 } }, 6687 6718 /*mxcsr:in */ 0, 6688 6719 /*128:out */ X86_MXCSR_DE | BS3_MXCSR_DM_FIXED, … … 6690 6721 /*xcpt? */ true, true }, 6691 6722 #ifdef TODO_X86_MXCSR_UE_IEM /** @todo THIS FAILS ON IEM: X86_MXCSR_UE not set in 128:out *AND* different output values */ 6692 /*--|34*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_ V5(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(0)} },6693 { /*src1 */ { FP32_0(0), FP32_RAND_ V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0)} },6694 { /* => */ { FP32_0(0), FP32_RAND_ V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0) } }/* result on HW (i7-10700) */,6695 // IEM: { /* => */ { FP32_DENORM_MAX(1), FP32_RAND_ V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0) } }/* result on IEM */,6723 /*--|34*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V2 } }, 6724 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V3 } }, 6725 { /* => */ { FP32_0(0), FP32_RAND_x7_V3 } }/* result on HW (i7-10700) */, 6726 // IEM: { /* => */ { FP32_DENORM_MAX(1), FP32_RAND_x7_V3 } }/* result on IEM */, 6696 6727 /*mxcsr:in */ X86_MXCSR_DM, 6697 6728 /*128:out */ X86_MXCSR_DM | X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, … … 6699 6730 /*xcpt? */ true, true }, 6700 6731 #endif /* TODO_X86_MXCSR_UE_IEM */ 6701 /*34|35*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_ V5(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V4(0)} },6702 { /*src1 */ { FP32_0(0), FP32_RAND_ V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0)} },6703 { /* => */ { FP32_DENORM_MAX(1), FP32_RAND_ V5(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V0(0)} },6732 /*34|35*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V5 } }, 6733 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V7 } }, 6734 { /* => */ { FP32_DENORM_MAX(1), FP32_RAND_x7_V7 } }, 6704 6735 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_UM, 6705 6736 /*128:out */ X86_MXCSR_DM | X86_MXCSR_UM | X86_MXCSR_DE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 6706 6737 /*256:out */ -1, 6707 6738 /*xcpt? */ true, true }, 6708 { { /*src2 */ { FP32_0(0), FP32_RAND_ V1(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V6(1)} },6709 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_ V1(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1)} },6710 { /* => */ { FP32_0(0), FP32_RAND_ V1(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V7(1)} },6739 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V2 } }, 6740 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V3 } }, 6741 { /* => */ { FP32_0(0), FP32_RAND_x7_V3 } }, 6711 6742 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK, 6712 6743 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK, 6713 6744 /*256:out */ -1, 6714 6745 /*xcpt? */ false, false }, 6715 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_RAND_ V3(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V7(0)} },6716 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_ V3(1), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V6(1)} },6717 { /* => */ { FP32_0(0), FP32_RAND_ V3(1), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V6(1)} },6746 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_RAND_x7_V6 } }, 6747 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V6 } }, 6748 { /* => */ { FP32_0(0), FP32_RAND_x7_V6 } }, 6718 6749 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, 6719 6750 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, … … 8594 8625 * Zero. 8595 8626 */ 8596 /* 0*/{ { /*src2 */ { FP32_0(0), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },8597 { /*src1 */ { FP32_0(0), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },8598 { /* => */ { FP32_0(0), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },8627 /* 0*/{ { /*src2 */ { FP32_0(0), FP32_0_x7(0) } }, 8628 { /*src1 */ { FP32_0(0), FP32_0_x7(0) } }, 8629 { /* => */ { FP32_0(0), FP32_0_x7(0) } }, 8599 8630 /*mxcsr:in */ 0, 8600 8631 /*128:out */ 0, 8601 8632 /*256:out */ -1, 8602 8633 /*xcpt? */ false, false }, 8603 { { /*src2 */ { FP32_0(0), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },8604 { /*src1 */ { FP32_0(0), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },8605 { /* => */ { FP32_0(0), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },8634 { { /*src2 */ { FP32_0(0), FP32_0_x7(0) } }, 8635 { /*src1 */ { FP32_0(0), FP32_0_x7(0) } }, 8636 { /* => */ { FP32_0(0), FP32_0_x7(0) } }, 8606 8637 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 8607 8638 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 8608 8639 /*256:out */ -1, 8609 8640 /*xcpt? */ false, false }, 8610 { { /*src2 */ { FP32_0(0), FP32_ NORM_V7(0), FP32_NORM_V6(0), FP32_0(0), FP32_0(1), FP32_NORM_V3(0), FP32_0(0), FP32_0(0)} },8611 { /*src1 */ { FP32_0(0), FP32_ 0(1), FP32_0(1), FP32_NORM_V2(0), FP32_NORM_V3(1), FP32_0(0), FP32_NORM_V6(0), FP32_NORM_V2(0)} },8612 { /* => */ { FP32_0(0), FP32_ 0(1), FP32_0(1), FP32_NORM_V2(0), FP32_NORM_V3(0), FP32_0(0), FP32_NORM_V6(0), FP32_NORM_V2(0)} },8641 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V1 } }, 8642 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V2 } }, 8643 { /* => */ { FP32_0(0), FP32_RAND_x7_V2 } }, 8613 8644 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 8614 8645 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 8615 8646 /*256:out */ -1, 8616 8647 /*xcpt? */ false, false }, 8617 { { /*src2 */ { FP32_0(1), FP32_ 0(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1)} },8618 { /*src1 */ { FP32_0(1), FP32_ 0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0)} },8619 { /* => */ { FP32_0(0), FP32_ 0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0)} },8648 { { /*src2 */ { FP32_0(1), FP32_RAND_x7_V4 } }, 8649 { /*src1 */ { FP32_0(1), FP32_RAND_x7_V5 } }, 8650 { /* => */ { FP32_0(0), FP32_RAND_x7_V5 } }, 8620 8651 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 8621 8652 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 8622 8653 /*256:out */ -1, 8623 8654 /*xcpt? */ false, false }, 8624 { { /*src2 */ { FP32_0(1), FP32_RAND_ V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1)} },8625 { /*src1 */ { FP32_0(0), FP32_RAND_ V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1)} },8626 { /* => */ { FP32_0(1), FP32_RAND_ V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1)} },8655 { { /*src2 */ { FP32_0(1), FP32_RAND_x7_V6 } }, 8656 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V7 } }, 8657 { /* => */ { FP32_0(1), FP32_RAND_x7_V7 } }, 8627 8658 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 8628 8659 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 8629 8660 /*256:out */ -1, 8630 8661 /*xcpt? */ false, false }, 8631 { { /*src2 */ { FP32_0(0), FP32_RAND_ V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1)} },8632 { /*src1 */ { FP32_0(1), FP32_RAND_ V6(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V3(1)} },8633 { /* => */ { FP32_0(1), FP32_RAND_ V6(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V3(1)} },8662 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V3 } }, 8663 { /*src1 */ { FP32_0(1), FP32_RAND_x7_V1 } }, 8664 { /* => */ { FP32_0(1), FP32_RAND_x7_V1 } }, 8634 8665 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ, 8635 8666 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ, 8636 8667 /*256:out */ -1, 8637 8668 /*xcpt? */ false, false }, 8638 { { /*src2 */ { FP32_0(0), FP32_RAND_ V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1)} },8639 { /*src1 */ { FP32_1(0), FP32_RAND_ V6(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V3(1)} },8640 { /* => */ { FP32_0(0), FP32_RAND_ V6(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V3(1)} },8669 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V5 } }, 8670 { /*src1 */ { FP32_1(0), FP32_RAND_x7_V2 } }, 8671 { /* => */ { FP32_0(0), FP32_RAND_x7_V2 } }, 8641 8672 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 8642 8673 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, … … 8646 8677 * Infinity. 8647 8678 */ 8648 /* 7*/{ { /*src2 */ { FP32_INF(0), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },8649 { /*src1 */ { FP32_1(1), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },8650 { /* => */ { FP32_INF(1), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },8679 /* 7*/{ { /*src2 */ { FP32_INF(0), FP32_0_x7(0) } }, 8680 { /*src1 */ { FP32_1(1), FP32_0_x7(0) } }, 8681 { /* => */ { FP32_INF(1), FP32_0_x7(0) } }, 8651 8682 /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM, 8652 8683 /*128:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM, 8653 8684 /*256:out */ -1, 8654 8685 /*xcpt? */ false, false }, 8655 { { /*src2 */ { FP32_INF(1), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },8656 { /*src1 */ { FP32_1(1), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },8657 { /* => */ { FP32_INF(0), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },8658 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 8659 /*128:out */ X86_MXCSR_XCPT_MASK, 8660 /*256:out */ -1, 8661 /*xcpt? */ false, false }, 8662 { { /*src2 */ { FP32_INF(0), FP32_RAND_ V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1)} },8663 { /*src1 */ { FP32_INF(0), FP32_RAND_ V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0)} },8664 { /* => */ { FP32_INF(0), FP32_RAND_ V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0)} },8686 { { /*src2 */ { FP32_INF(1), FP32_0_x7(0) } }, 8687 { /*src1 */ { FP32_1(1), FP32_0_x7(0) } }, 8688 { /* => */ { FP32_INF(0), FP32_0_x7(0) } }, 8689 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 8690 /*128:out */ X86_MXCSR_XCPT_MASK, 8691 /*256:out */ -1, 8692 /*xcpt? */ false, false }, 8693 { { /*src2 */ { FP32_INF(0), FP32_RAND_x7_V7 } }, 8694 { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V0 } }, 8695 { /* => */ { FP32_INF(0), FP32_RAND_x7_V0 } }, 8665 8696 /*mxcsr:in */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_DAZ | X86_MXCSR_FZ, 8666 8697 /*128:out */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_DAZ | X86_MXCSR_FZ, 8667 8698 /*256:out */ -1, 8668 8699 /*xcpt? */ false, false }, 8669 { { /*src2 */ { FP32_INF(1), FP32_RAND_ V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1)} },8670 { /*src1 */ { FP32_INF(0), FP32_RAND_ V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0)} },8671 { /* => */ { FP32_INF(1), FP32_RAND_ V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0)} },8700 { { /*src2 */ { FP32_INF(1), FP32_RAND_x7_V7 } }, 8701 { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V1 } }, 8702 { /* => */ { FP32_INF(1), FP32_RAND_x7_V1 } }, 8672 8703 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 8673 8704 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 8674 8705 /*256:out */ -1, 8675 8706 /*xcpt? */ false, false }, 8676 { { /*src2 */ { FP32_1(0), FP32_RAND_ V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1)} },8677 { /*src1 */ { FP32_INF(0), FP32_RAND_ V6(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V2(1)} },8678 { /* => */ { FP32_INF(0), FP32_RAND_ V6(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V2(1)} },8707 { { /*src2 */ { FP32_1(0), FP32_RAND_x7_V3 } }, 8708 { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V2 } }, 8709 { /* => */ { FP32_INF(0), FP32_RAND_x7_V2 } }, 8679 8710 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, 8680 8711 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, 8681 8712 /*256:out */ -1, 8682 8713 /*xcpt? */ false, false }, 8683 { { /*src2 */ { FP32_INF(0), FP32_ INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(1)} },8684 { /*src1 */ { FP32_1(1), FP32_ INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(0)} },8685 { /* => */ { FP32_INF(1), FP32_ INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1)} },8714 { { /*src2 */ { FP32_INF(0), FP32_RAND_x7_V0 } }, 8715 { /*src1 */ { FP32_1(1), FP32_RAND_x7_V0 } }, 8716 { /* => */ { FP32_INF(1), FP32_RAND_x7_V0 } }, 8686 8717 /*mxcsr:in */ X86_MXCSR_FZ, 8687 8718 /*128:out */ X86_MXCSR_FZ, 8688 8719 /*256:out */ -1, 8689 8720 /*xcpt? */ false, false }, 8690 { { /*src2 */ { FP32_INF(1), FP32_ QNAN(0), FP32_SNAN(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V2(0)} },8691 { /*src1 */ { FP32_INF(0), FP32_ QNAN(0), FP32_SNAN(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V2(0)} },8692 { /* => */ { FP32_INF(1), FP32_ QNAN(0), FP32_SNAN(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V2(0)} },8721 { { /*src2 */ { FP32_INF(1), FP32_RAND_x7_V2 } }, 8722 { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V3 } }, 8723 { /* => */ { FP32_INF(1), FP32_RAND_x7_V3 } }, 8693 8724 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 8694 8725 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, … … 8698 8729 * Normals. 8699 8730 */ 8700 /*14*/{ { /*src2 */ { FP32_V(0, 0x600000, 0x7f)/*1.7500*/, FP32_RAND_ V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1)} },8701 { /*src1 */ { FP32_V(0, 0, 0x7d)/*0.2500*/, FP32_RAND_ V6(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V2(1)} },8702 { /* => */ { FP32_V(0, 0x600000, 0x7d)/*0.4375*/, FP32_RAND_ V6(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V2(1)} },8731 /*14*/{ { /*src2 */ { FP32_V(0, 0x600000, 0x7f)/*1.7500*/, FP32_RAND_x7_V3 } }, 8732 { /*src1 */ { FP32_V(0, 0, 0x7d)/*0.2500*/, FP32_RAND_x7_V4 } }, 8733 { /* => */ { FP32_V(0, 0x600000, 0x7d)/*0.4375*/, FP32_RAND_x7_V4 } }, 8703 8734 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 8704 8735 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 8705 8736 /*256:out */ -1, 8706 8737 /*xcpt? */ false, false }, 8707 { { /*src2 */ { FP32_V(0, 0x61e000, 0x89)/* 1807*/, FP32_RAND_ V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1)} },8708 { /*src1 */ { FP32_V(0, 0x504000, 0x8a)/* 3332*/, FP32_RAND_ V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0)} },8709 { /* => */ { FP32_V(0, 0x37be78, 0x95)/*6020924*/, FP32_RAND_ V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0)} },8710 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 8711 /*128:out */ X86_MXCSR_XCPT_MASK, 8712 /*256:out */ -1, 8713 /*xcpt? */ false, false }, 8714 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_ V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1)} },8715 { /*src1 */ { FP32_1(0), FP32_RAND_ V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0)} },8716 { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_ V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0)} },8738 { { /*src2 */ { FP32_V(0, 0x61e000, 0x89)/* 1807*/, FP32_RAND_x7_V4 } }, 8739 { /*src1 */ { FP32_V(0, 0x504000, 0x8a)/* 3332*/, FP32_RAND_x7_V5 } }, 8740 { /* => */ { FP32_V(0, 0x37be78, 0x95)/*6020924*/, FP32_RAND_x7_V5 } }, 8741 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 8742 /*128:out */ X86_MXCSR_XCPT_MASK, 8743 /*256:out */ -1, 8744 /*xcpt? */ false, false }, 8745 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V6 } }, 8746 { /*src1 */ { FP32_1(0), FP32_RAND_x7_V6 } }, 8747 { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V6 } }, 8717 8748 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 8718 8749 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 8719 8750 /*256:out */ -1, 8720 8751 /*xcpt? */ false, false }, 8721 { { /*src2 */ { FP32_V(0, 0x61e000, 0x89)/* 1807*/, FP32_RAND_ V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1)} },8722 { /*src1 */ { FP32_V(0, 0x504000, 0x8a)/* 3332*/, FP32_RAND_ V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1)} },8723 { /* => */ { FP32_V(0, 0x37be78, 0x95)/*6020924*/, FP32_RAND_ V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1)} },8752 { { /*src2 */ { FP32_V(0, 0x61e000, 0x89)/* 1807*/, FP32_RAND_x7_V6 } }, 8753 { /*src1 */ { FP32_V(0, 0x504000, 0x8a)/* 3332*/, FP32_RAND_x7_V2 } }, 8754 { /* => */ { FP32_V(0, 0x37be78, 0x95)/*6020924*/, FP32_RAND_x7_V2 } }, 8724 8755 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, 8725 8756 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, 8726 8757 /*256:out */ -1, 8727 8758 /*xcpt? */ false, false }, 8728 { { /*src2 */ { FP32_V(0, 0x4a30b8, 0x8f)/* 103521.4375*/, FP32_RAND_ V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1)} },8729 { /*src1 */ { FP32_V(0, 0x600000, 0x82)/* 14.0000*/, FP32_RAND_ V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V2(1)} },8730 { /* => */ { FP32_V(0, 0x30eaa1, 0x93)/*1449300.1250*/, FP32_RAND_ V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V2(1)} },8759 { { /*src2 */ { FP32_V(0, 0x4a30b8, 0x8f)/* 103521.4375*/, FP32_RAND_x7_V7 } }, 8760 { /*src1 */ { FP32_V(0, 0x600000, 0x82)/* 14.0000*/, FP32_RAND_x7_V2 } }, 8761 { /* => */ { FP32_V(0, 0x30eaa1, 0x93)/*1449300.1250*/, FP32_RAND_x7_V2 } }, 8731 8762 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 8732 8763 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 8733 8764 /*256:out */ -1, 8734 8765 /*xcpt? */ false, false }, 8735 { { /*src2 */ { FP32_V(0, 0x1a5200, 0x8c)/* 9876.5*/, FP32_RAND_ V6(0), FP32_RAND_V0(1), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V5(1), FP32_RAND_V7(1)} },8736 { /*src1 */ { FP32_V(1, 0x1a4000, 0x89)/* -1234.0*/, FP32_RAND_ V6(0), FP32_RAND_V0(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V6(0), FP32_RAND_V1(1)} },8737 { /* => */ { FP32_V(1, 0x39f7d1, 0x96)/*-12187601.0*/, FP32_RAND_ V6(0), FP32_RAND_V0(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V1(1)} },8766 { { /*src2 */ { FP32_V(0, 0x1a5200, 0x8c)/* 9876.5*/, FP32_RAND_x7_V3 } }, 8767 { /*src1 */ { FP32_V(1, 0x1a4000, 0x89)/* -1234.0*/, FP32_RAND_x7_V5 } }, 8768 { /* => */ { FP32_V(1, 0x39f7d1, 0x96)/*-12187601.0*/, FP32_RAND_x7_V5 } }, 8738 8769 /*mxcsr:in */ 0, 8739 8770 /*128:out */ 0, 8740 8771 /*256:out */ -1, 8741 8772 /*xcpt? */ false, false }, 8742 { { /*src2 */ { FP32_NORM_MAX(0), FP32_ NORM_V1(1), FP32_0(0), FP32_1(0), FP32_NORM_MIN(0), FP32_NORM_V1(0), FP32_NORM_V2(0), FP32_0(0)} },8743 { /*src1 */ { FP32_1(1), FP32_ 1(0), FP32_NORM_V1(1), FP32_NORM_V3(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_NORM_V3(0)} },8744 { /* => */ { FP32_NORM_MAX(1), FP32_ 1(0), FP32_NORM_V1(1), FP32_NORM_V3(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_NORM_V3(0)} },8773 { { /*src2 */ { FP32_NORM_MAX(0), FP32_RAND_x7_V5 } }, 8774 { /*src1 */ { FP32_1(1), FP32_RAND_x7_V4 } }, 8775 { /* => */ { FP32_NORM_MAX(1), FP32_RAND_x7_V4 } }, 8745 8776 /*mxcsr:in */ 0, 8746 8777 /*128:out */ 0, 8747 8778 /*256:out */ -1, 8748 8779 /*xcpt? */ false, false }, 8749 { { /*src2 */ { FP32_V(0, 0x23b6a0, 0x8e)/*41910.625000*/, FP32_ QNAN(0), FP32_SNAN(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V2(0)} },8750 { /*src1 */ { FP32_V(0, 0, 0x7c)/* 0.125000*/, FP32_ QNAN(0), FP32_SNAN(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V2(0)} },8751 { /* => */ { FP32_V(0, 0x23b6a0, 0x8b)/* 5238.828125*/, FP32_ QNAN(0), FP32_SNAN(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V2(0)} },8780 { { /*src2 */ { FP32_V(0, 0x23b6a0, 0x8e)/*41910.625000*/, FP32_RAND_x7_V6 } }, 8781 { /*src1 */ { FP32_V(0, 0, 0x7c)/* 0.125000*/, FP32_RAND_x7_V5 } }, 8782 { /* => */ { FP32_V(0, 0x23b6a0, 0x8b)/* 5238.828125*/, FP32_RAND_x7_V5 } }, 8752 8783 /*mxcsr:in */ 0, 8753 8784 /*128:out */ 0, 8754 8785 /*256:out */ -1, 8755 8786 /*xcpt? */ false, false }, 8756 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_ NORM_SAFE_INT_MAX(0), FP32_1(1), FP32_1(1), FP32_1(0), FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_1(0)} },8757 { /*src1 */ { FP32_1(0), FP32_ 1(1), FP32_1(0), FP32_1(0), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_1(1), FP32_1(0), FP32_1(0)} },8758 { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_ 1(1), FP32_1(0), FP32_1(0), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_1(1), FP32_1(0), FP32_1(0)} },8787 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V4 } }, 8788 { /*src1 */ { FP32_1(0), FP32_RAND_x7_V1 } }, 8789 { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V1 } }, 8759 8790 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 8760 8791 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, … … 8765 8796 * Denormals. 8766 8797 */ 8767 /*23*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_ V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(1)} },8768 { /*src1 */ { FP32_0(0), FP32_ 1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(1)} },8769 { /* => */ { FP32_0(0), FP32_ 1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(1)} },8798 /*23*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V5 } }, 8799 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V2 } }, 8800 { /* => */ { FP32_0(0), FP32_RAND_x7_V2 } }, 8770 8801 /*mxcsr:in */ 0, 8771 8802 /*128:out */ X86_MXCSR_DE, 8772 8803 /*256:out */ -1, 8773 8804 /*xcpt? */ true, true }, 8774 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_RAND_ V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(1)} },8775 { /*src1 */ { FP32_0(0), FP32_ 1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(1)} },8776 { /* => */ { FP32_0(0), FP32_ 1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(1)} },8805 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_RAND_x7_V6 } }, 8806 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V3 } }, 8807 { /* => */ { FP32_0(0), FP32_RAND_x7_V3 } }, 8777 8808 /*mxcsr:in */ 0, 8778 8809 /*128:out */ X86_MXCSR_DE, 8779 8810 /*256:out */ -1, 8780 8811 /*xcpt? */ true, true }, 8781 { { /*src2 */ { FP32_0(0), FP32_ DENORM_MIN(0), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_1(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_1(0)} },8782 { /*src1 */ { FP32_DENORM_MIN(1), FP32_ 1(0), FP32_1(0), FP32_1(0), FP32_RAND_V2(0), FP32_1(0), FP32_1(0), FP32_DENORM_MAX(0)} },8783 { /* => */ { FP32_0(1), FP32_ 1(0), FP32_1(0), FP32_1(0), FP32_RAND_V2(0), FP32_1(0), FP32_1(0), FP32_DENORM_MAX(0)} },8812 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V5 } }, 8813 { /*src1 */ { FP32_DENORM_MIN(1), FP32_RAND_x7_V2 } }, 8814 { /* => */ { FP32_0(1), FP32_RAND_x7_V2 } }, 8784 8815 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 8785 8816 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, 8786 8817 /*256:out */ -1, 8787 8818 /*xcpt? */ false, false }, 8788 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_ 1(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V0(0), FP32_DENORM_MAX(0)} },8789 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_ V4(0), FP32_DENORM_MIN(1), FP32_DENORM_MIN(0), FP32_1(0), FP32_1(0), FP32_DENORM_MIN(0), FP32_RAND_V4(0)} },8790 { /* => */ { FP32_0(0), FP32_RAND_ V4(0), FP32_DENORM_MIN(1), FP32_DENORM_MIN(0), FP32_1(0), FP32_1(0), FP32_DENORM_MIN(0), FP32_RAND_V4(0)} },8819 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_RAND_x7_V3 } }, 8820 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V3 } }, 8821 { /* => */ { FP32_0(0), FP32_RAND_x7_V3 } }, 8791 8822 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 8792 8823 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, … … 9966 9997 * Zero. 9967 9998 */ 9968 /* 0*/{ { /*src2 */ { FP32_0(0), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },9969 { /*src1 */ { FP32_0(0), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },9970 { /* => */ { FP32_QNAN(1), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },9999 /* 0*/{ { /*src2 */ { FP32_0(0), FP32_0_x7(0) } }, 10000 { /*src1 */ { FP32_0(0), FP32_0_x7(0) } }, 10001 { /* => */ { FP32_QNAN(1), FP32_0_x7(0) } }, 9971 10002 /*mxcsr:in */ 0, 9972 10003 /*128:out */ X86_MXCSR_IE, 9973 10004 /*256:out */ -1, 9974 10005 /*xcpt? */ true, true }, 9975 { { /*src2 */ { FP32_0(0), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },9976 { /*src1 */ { FP32_0(0), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },9977 { /* => */ { FP32_QNAN(1), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },10006 { { /*src2 */ { FP32_0(0), FP32_0_x7(0) } }, 10007 { /*src1 */ { FP32_0(0), FP32_0_x7(0) } }, 10008 { /* => */ { FP32_QNAN(1), FP32_0_x7(0) } }, 9978 10009 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 9979 10010 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 9980 10011 /*256:out */ -1, 9981 10012 /*xcpt? */ false, false }, 9982 { { /*src2 */ { FP32_0(0), FP32_ NORM_V7(0), FP32_NORM_V6(0), FP32_0(0), FP32_0(1), FP32_NORM_V3(0), FP32_0(0), FP32_0(0)} },9983 { /*src1 */ { FP32_0(0), FP32_ 0(1), FP32_0(1), FP32_NORM_V2(0), FP32_NORM_V3(1), FP32_0(0), FP32_NORM_V6(0), FP32_NORM_V2(0)} },9984 { /* => */ { FP32_QNAN(1), FP32_ 0(1), FP32_0(1), FP32_NORM_V2(0), FP32_NORM_V3(0), FP32_0(0), FP32_NORM_V6(0), FP32_NORM_V2(0)} },10013 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V1 } }, 10014 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V2 } }, 10015 { /* => */ { FP32_QNAN(1), FP32_RAND_x7_V2 } }, 9985 10016 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 9986 10017 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, 9987 10018 /*256:out */ -1, 9988 10019 /*xcpt? */ false, false }, 9989 { { /*src2 */ { FP32_0(1), FP32_ 0(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1)} },9990 { /*src1 */ { FP32_0(1), FP32_ 0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0)} },9991 { /* => */ { FP32_QNAN(1), FP32_ 0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0)} },10020 { { /*src2 */ { FP32_0(1), FP32_RAND_x7_V2 } }, 10021 { /*src1 */ { FP32_0(1), FP32_RAND_x7_V3 } }, 10022 { /* => */ { FP32_QNAN(1), FP32_RAND_x7_V3 } }, 9992 10023 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 9993 10024 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, 9994 10025 /*256:out */ -1, 9995 10026 /*xcpt? */ true, true }, 9996 { { /*src2 */ { FP32_0(1), FP32_RAND_ V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1)} },9997 { /*src1 */ { FP32_0(0), FP32_RAND_ V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1)} },9998 { /* => */ { FP32_QNAN(1), FP32_RAND_ V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1)} },10027 { { /*src2 */ { FP32_0(1), FP32_RAND_x7_V3 } }, 10028 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V4 } }, 10029 { /* => */ { FP32_QNAN(1), FP32_RAND_x7_V4 } }, 9999 10030 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 10000 10031 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 10001 10032 /*256:out */ -1, 10002 10033 /*xcpt? */ true, true }, 10003 { { /*src2 */ { FP32_0(0), FP32_RAND_ V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1)} },10004 { /*src1 */ { FP32_0(1), FP32_RAND_ V6(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V3(1)} },10005 { /* => */ { FP32_QNAN(1), FP32_RAND_ V6(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V3(1)} },10034 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V4 } }, 10035 { /*src1 */ { FP32_0(1), FP32_RAND_x7_V5 } }, 10036 { /* => */ { FP32_QNAN(1), FP32_RAND_x7_V5 } }, 10006 10037 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ, 10007 10038 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_IE, 10008 10039 /*256:out */ -1, 10009 10040 /*xcpt? */ false, false }, 10010 { { /*src2 */ { FP32_0(0), FP32_RAND_ V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1)} },10011 { /*src1 */ { FP32_1(0), FP32_RAND_ V6(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V3(1)} },10012 { /* => */ { FP32_INF(0), FP32_RAND_ V6(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V3(1)} },10041 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V5 } }, 10042 { /*src1 */ { FP32_1(0), FP32_RAND_x7_V6 } }, 10043 { /* => */ { FP32_INF(0), FP32_RAND_x7_V6 } }, 10013 10044 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 10014 10045 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_FSW_ZE, … … 10018 10049 * Infinity. 10019 10050 */ 10020 /* 7*/{ { /*src2 */ { FP32_INF(0), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },10021 { /*src1 */ { FP32_1(1), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },10022 { /* => */ { FP32_0(1), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },10051 /* 7*/{ { /*src2 */ { FP32_INF(0), FP32_0_x7(0) } }, 10052 { /*src1 */ { FP32_1(1), FP32_0_x7(0) } }, 10053 { /* => */ { FP32_0(1), FP32_0_x7(0) } }, 10023 10054 /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM, 10024 10055 /*128:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM, 10025 10056 /*256:out */ -1, 10026 10057 /*xcpt? */ false, false }, 10027 { { /*src2 */ { FP32_INF(1), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },10028 { /*src1 */ { FP32_1(1), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },10029 { /* => */ { FP32_0(0), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },10030 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 10031 /*128:out */ X86_MXCSR_XCPT_MASK, 10032 /*256:out */ -1, 10033 /*xcpt? */ false, false }, 10034 { { /*src2 */ { FP32_INF(0), FP32_RAND_ V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1)} },10035 { /*src1 */ { FP32_INF(0), FP32_RAND_ V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0)} },10036 { /* => */ { FP32_QNAN(1), FP32_RAND_ V0(0), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0)} },10058 { { /*src2 */ { FP32_INF(1), FP32_0_x7(0) } }, 10059 { /*src1 */ { FP32_1(1), FP32_0_x7(0) } }, 10060 { /* => */ { FP32_0(0), FP32_0_x7(0) } }, 10061 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 10062 /*128:out */ X86_MXCSR_XCPT_MASK, 10063 /*256:out */ -1, 10064 /*xcpt? */ false, false }, 10065 { { /*src2 */ { FP32_INF(0), FP32_RAND_x7_V7 } }, 10066 { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V0 } }, 10067 { /* => */ { FP32_QNAN(1), FP32_RAND_x7_V0 } }, 10037 10068 /*mxcsr:in */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_DAZ | X86_MXCSR_FZ, 10038 10069 /*128:out */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE, 10039 10070 /*256:out */ -1, 10040 10071 /*xcpt? */ true, true }, 10041 { { /*src2 */ { FP32_INF(1), FP32_RAND_ V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1)} },10042 { /*src1 */ { FP32_INF(0), FP32_RAND_ V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0)} },10043 { /* => */ { FP32_QNAN(1), FP32_RAND_ V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0)} },10072 { { /*src2 */ { FP32_INF(1), FP32_RAND_x7_V7 } }, 10073 { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V1 } }, 10074 { /* => */ { FP32_QNAN(1), FP32_RAND_x7_V1 } }, 10044 10075 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 10045 10076 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 10046 10077 /*256:out */ -1, 10047 10078 /*xcpt? */ false, false }, 10048 { { /*src2 */ { FP32_1(0), FP32_RAND_ V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1)} },10049 { /*src1 */ { FP32_INF(0), FP32_RAND_ V6(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V2(1)} },10050 { /* => */ { FP32_INF(0), FP32_RAND_ V6(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V2(1)} },10079 { { /*src2 */ { FP32_1(0), FP32_RAND_x7_V7 } }, 10080 { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V6 } }, 10081 { /* => */ { FP32_INF(0), FP32_RAND_x7_V6 } }, 10051 10082 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, 10052 10083 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, 10053 10084 /*256:out */ -1, 10054 10085 /*xcpt? */ false, false }, 10055 { { /*src2 */ { FP32_INF(0), FP32_ INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(1)} },10056 { /*src1 */ { FP32_1(1), FP32_ INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(0)} },10057 { /* => */ { FP32_0(1), FP32_ INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1)} },10086 { { /*src2 */ { FP32_INF(0), FP32_RAND_x7_V5 } }, 10087 { /*src1 */ { FP32_1(1), FP32_RAND_x7_V5 } }, 10088 { /* => */ { FP32_0(1), FP32_RAND_x7_V5 } }, 10058 10089 /*mxcsr:in */ X86_MXCSR_FZ, 10059 10090 /*128:out */ X86_MXCSR_FZ, 10060 10091 /*256:out */ -1, 10061 10092 /*xcpt? */ false, false }, 10062 { { /*src2 */ { FP32_INF(1), FP32_ QNAN(0), FP32_SNAN(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V2(0)} },10063 { /*src1 */ { FP32_INF(0), FP32_ QNAN(0), FP32_SNAN(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V2(0)} },10064 { /* => */ { FP32_QNAN(1), FP32_ QNAN(0), FP32_SNAN(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V2(0)} },10093 { { /*src2 */ { FP32_INF(1), FP32_RAND_x7_V4 } }, 10094 { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V3 } }, 10095 { /* => */ { FP32_QNAN(1), FP32_RAND_x7_V3 } }, 10065 10096 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 10066 10097 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, … … 10070 10101 * Normals. 10071 10102 */ 10072 /*14*/{ { /*src2 */ { FP32_V(0, 0x600000, 0x7f)/*1.7500*/, FP32_RAND_ V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1)} },10073 { /*src1 */ { FP32_V(0, 0x600000, 0x7d)/*0.4375*/, FP32_RAND_ V6(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V2(1)} },10074 { /* => */ { FP32_V(0, 0, 0x7d)/*0.2500*/, FP32_RAND_ V6(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V2(1)} },10103 /*14*/{ { /*src2 */ { FP32_V(0, 0x600000, 0x7f)/*1.7500*/, FP32_RAND_x7_V0 } }, 10104 { /*src1 */ { FP32_V(0, 0x600000, 0x7d)/*0.4375*/, FP32_RAND_x7_V6 } }, 10105 { /* => */ { FP32_V(0, 0, 0x7d)/*0.2500*/, FP32_RAND_x7_V6 } }, 10075 10106 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 10076 10107 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 10077 10108 /*256:out */ -1, 10078 10109 /*xcpt? */ false, false }, 10079 { { /*src2 */ { FP32_V(0, 0x61e000, 0x89)/* 1807*/, FP32_RAND_ V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1)} },10080 { /*src1 */ { FP32_V(0, 0x37be78, 0x95)/*6020924*/, FP32_RAND_ V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0)} },10081 { /* => */ { FP32_V(0, 0x504000, 0x8a)/* 3332*/, FP32_RAND_ V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0)} },10082 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 10083 /*128:out */ X86_MXCSR_XCPT_MASK, 10084 /*256:out */ -1, 10085 /*xcpt? */ false, false }, 10086 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_ V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V1(1)} },10087 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_ V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0)} },10088 { /* => */ { FP32_1(0), FP32_RAND_ V1(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0)} },10110 { { /*src2 */ { FP32_V(0, 0x61e000, 0x89)/* 1807*/, FP32_RAND_x7_V6 } }, 10111 { /*src1 */ { FP32_V(0, 0x37be78, 0x95)/*6020924*/, FP32_RAND_x7_V1 } }, 10112 { /* => */ { FP32_V(0, 0x504000, 0x8a)/* 3332*/, FP32_RAND_x7_V1 } }, 10113 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 10114 /*128:out */ X86_MXCSR_XCPT_MASK, 10115 /*256:out */ -1, 10116 /*xcpt? */ false, false }, 10117 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V4 } }, 10118 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V2 } }, 10119 { /* => */ { FP32_1(0), FP32_RAND_x7_V2 } }, 10089 10120 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 10090 10121 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 10091 10122 /*256:out */ -1, 10092 10123 /*xcpt? */ false, false }, 10093 { { /*src2 */ { FP32_V(0, 0x61e000, 0x89)/* 1807*/, FP32_RAND_ V0(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1)} },10094 { /*src1 */ { FP32_V(0, 0x37be78, 0x95)/*6020924*/, FP32_RAND_ V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1)} },10095 { /* => */ { FP32_V(0, 0x504000, 0x8a)/* 3332*/, FP32_RAND_ V7(1), FP32_RAND_V6(0), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(1)} },10124 { { /*src2 */ { FP32_V(0, 0x61e000, 0x89)/* 1807*/, FP32_RAND_x7_V0 } }, 10125 { /*src1 */ { FP32_V(0, 0x37be78, 0x95)/*6020924*/, FP32_RAND_x7_V7 } }, 10126 { /* => */ { FP32_V(0, 0x504000, 0x8a)/* 3332*/, FP32_RAND_x7_V7 } }, 10096 10127 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, 10097 10128 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, 10098 10129 /*256:out */ -1, 10099 10130 /*xcpt? */ false, false }, 10100 { { /*src2 */ { FP32_V(0, 0x4a30b8, 0x8f)/* 103521.4375*/, FP32_RAND_ V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1)} },10101 { /*src1 */ { FP32_V(0, 0x30eaa1, 0x93)/*1449300.1250*/, FP32_RAND_ V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V2(1)} },10102 { /* => */ { FP32_V(0, 0x600000, 0x82)/* 14.0000*/, FP32_RAND_ V3(0), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V2(1)} },10131 { { /*src2 */ { FP32_V(0, 0x4a30b8, 0x8f)/* 103521.4375*/, FP32_RAND_x7_V1 } }, 10132 { /*src1 */ { FP32_V(0, 0x30eaa1, 0x93)/*1449300.1250*/, FP32_RAND_x7_V3 } }, 10133 { /* => */ { FP32_V(0, 0x600000, 0x82)/* 14.0000*/, FP32_RAND_x7_V3 } }, 10103 10134 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 10104 10135 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 10105 10136 /*256:out */ -1, 10106 10137 /*xcpt? */ false, false }, 10107 { { /*src2 */ { FP32_V(0, 0x1a5200, 0x8c)/* 9876.5*/, FP32_RAND_ V6(0), FP32_RAND_V0(1), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V5(1), FP32_RAND_V7(1)} },10108 { /*src1 */ { FP32_V(1, 0x39f7d1, 0x96)/*-12187601.0*/, FP32_RAND_ V6(0), FP32_RAND_V0(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V1(1)} },10109 { /* => */ { FP32_V(1, 0x1a4000, 0x89)/* -1234.0*/, FP32_RAND_ V6(0), FP32_RAND_V0(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V6(0), FP32_RAND_V1(1)} },10138 { { /*src2 */ { FP32_V(0, 0x1a5200, 0x8c)/* 9876.5*/, FP32_RAND_x7_V6 } }, 10139 { /*src1 */ { FP32_V(1, 0x39f7d1, 0x96)/*-12187601.0*/, FP32_RAND_x7_V6 } }, 10140 { /* => */ { FP32_V(1, 0x1a4000, 0x89)/* -1234.0*/, FP32_RAND_x7_V6 } }, 10110 10141 /*mxcsr:in */ 0, 10111 10142 /*128:out */ 0, 10112 10143 /*256:out */ -1, 10113 10144 /*xcpt? */ false, false }, 10114 { { /*src2 */ { FP32_NORM_MAX(0), FP32_ NORM_V1(1), FP32_0(0), FP32_1(0), FP32_NORM_MIN(0), FP32_NORM_V1(0), FP32_NORM_V2(0), FP32_0(0)} },10115 { /*src1 */ { FP32_NORM_MAX(1), FP32_ 1(0), FP32_NORM_V1(1), FP32_NORM_V3(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_NORM_V3(0)} },10116 { /* => */ { FP32_1(1), FP32_ 1(0), FP32_NORM_V1(1), FP32_NORM_V3(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_NORM_V3(0)} },10145 { { /*src2 */ { FP32_NORM_MAX(0), FP32_RAND_x7_V2 } }, 10146 { /*src1 */ { FP32_NORM_MAX(1), FP32_RAND_x7_V1 } }, 10147 { /* => */ { FP32_1(1), FP32_RAND_x7_V1 } }, 10117 10148 /*mxcsr:in */ 0, 10118 10149 /*128:out */ 0, 10119 10150 /*256:out */ -1, 10120 10151 /*xcpt? */ false, false }, 10121 { { /*src2 */ { FP32_V(0, 0x23b6a0, 0x8e)/*41910.625000*/, FP32_ QNAN(0), FP32_SNAN(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V2(0)} },10122 { /*src1 */ { FP32_V(0, 0x23b6a0, 0x8b)/* 5238.828125*/, FP32_ QNAN(0), FP32_SNAN(0), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V2(0)} },10123 { /* => */ { FP32_V(0, 0, 0x7c)/* 0.125000*/, FP32_ QNAN(0), FP32_SNAN(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V2(0)} },10152 { { /*src2 */ { FP32_V(0, 0x23b6a0, 0x8e)/*41910.625000*/, FP32_RAND_x7_V3 } }, 10153 { /*src1 */ { FP32_V(0, 0x23b6a0, 0x8b)/* 5238.828125*/, FP32_RAND_x7_V2 } }, 10154 { /* => */ { FP32_V(0, 0, 0x7c)/* 0.125000*/, FP32_RAND_x7_V2 } }, 10124 10155 /*mxcsr:in */ 0, 10125 10156 /*128:out */ 0, 10126 10157 /*256:out */ -1, 10127 10158 /*xcpt? */ false, false }, 10128 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_ NORM_SAFE_INT_MAX(0), FP32_1(1), FP32_1(1), FP32_1(0), FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_1(0)} },10129 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_ 1(1), FP32_1(0), FP32_1(0), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_1(1), FP32_1(0), FP32_1(0)} },10130 { /* => */ { FP32_1(0), FP32_ 1(1), FP32_1(0), FP32_1(0), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_1(1), FP32_1(0), FP32_1(0)} },10159 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V5 } }, 10160 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V4 } }, 10161 { /* => */ { FP32_1(0), FP32_RAND_x7_V4 } }, 10131 10162 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 10132 10163 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, … … 10137 10168 * Denormals. 10138 10169 */ 10139 /*23*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_ V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(1)} },10140 { /*src1 */ { FP32_0(0), FP32_ 1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(1)} },10141 { /* => */ { FP32_0(0), FP32_ 1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(1)} },10170 /*23*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V5 } }, 10171 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V2 } }, 10172 { /* => */ { FP32_0(0), FP32_RAND_x7_V2 } }, 10142 10173 /*mxcsr:in */ 0, 10143 10174 /*128:out */ X86_MXCSR_DE, 10144 10175 /*256:out */ -1, 10145 10176 /*xcpt? */ true, true }, 10146 { { /*src2 */ { FP32_0(0), FP32_RAND_ V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(1)} },10147 { /*src1 */ { FP32_DENORM_MAX(0), FP32_ 1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(1)} },10148 { /* => */ { FP32_INF(0), FP32_ 1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(1)} },10177 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V2 } }, 10178 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V1 } }, 10179 { /* => */ { FP32_INF(0), FP32_RAND_x7_V1 } }, 10149 10180 /*mxcsr:in */ 0, 10150 10181 /*128:out */ X86_MXCSR_ZE, 10151 10182 /*256:out */ -1, 10152 10183 /*xcpt? */ true, true }, 10153 { { /*src2 */ { FP32_0(0), FP32_ DENORM_MIN(0), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_1(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_1(0)} },10154 { /*src1 */ { FP32_DENORM_MIN(1), FP32_ 1(0), FP32_1(0), FP32_1(0), FP32_RAND_V2(0), FP32_1(0), FP32_1(0), FP32_DENORM_MAX(0)} },10155 { /* => */ { FP32_INF(1), FP32_ 1(0), FP32_1(0), FP32_1(0), FP32_RAND_V2(0), FP32_1(0), FP32_1(0), FP32_DENORM_MAX(0)} },10184 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V3 } }, 10185 { /*src1 */ { FP32_DENORM_MIN(1), FP32_RAND_x7_V2 } }, 10186 { /* => */ { FP32_INF(1), FP32_RAND_x7_V2 } }, 10156 10187 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 10157 10188 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_ZE, 10158 10189 /*256:out */ -1, 10159 10190 /*xcpt? */ false, false }, 10160 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_ 1(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V0(0), FP32_DENORM_MAX(0)} },10161 { /*src1 */ { FP32_0(0), FP32_RAND_ V4(0), FP32_DENORM_MIN(1), FP32_DENORM_MIN(0), FP32_1(0), FP32_1(0), FP32_DENORM_MIN(0), FP32_RAND_V4(0)} },10162 { /* => */ { FP32_QNAN(1), FP32_RAND_V4(0), FP32_DENORM_MIN(1), FP32_DENORM_MIN(0), FP32_1(0), FP32_1(0), FP32_DENORM_MIN(0), FP32_RAND_V4(0)} },10191 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_RAND_x7_V1 } }, 10192 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V4 } }, 10193 { /* => */ { FP32_QNAN(1), FP32_RAND_x7_V4 } }, 10163 10194 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 10164 10195 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, … … 12215 12246 * Zero. 12216 12247 */ 12217 /* 0*/{ { /*src2 */ { FP32_0(0), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },12218 { /*src1 */ { FP32_0(0), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },12219 { /* => */ { FP32_0(0), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },12248 /* 0*/{ { /*src2 */ { FP32_0(0), FP32_0_x7(0) } }, 12249 { /*src1 */ { FP32_0(0), FP32_0_x7(0) } }, 12250 { /* => */ { FP32_0(0), FP32_0_x7(0) } }, 12220 12251 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 12221 12252 /*128:out */ X86_MXCSR_XCPT_MASK, 12222 12253 /*256:out */ X86_MXCSR_XCPT_MASK, 12223 12254 /*xcpt? */ false, false }, 12224 { { /*src2 */ { FP32_0(0), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },12225 { /*src1 */ { FP32_0(0), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },12226 { /* => */ { FP32_0(0), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },12255 { { /*src2 */ { FP32_0(0), FP32_0_x7(0) } }, 12256 { /*src1 */ { FP32_0(0), FP32_0_x7(0) } }, 12257 { /* => */ { FP32_0(0), FP32_0_x7(0) } }, 12227 12258 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 12228 12259 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 12229 12260 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 12230 12261 /*xcpt? */ false, false }, 12231 { { /*src2 */ { FP32_0(0), FP32_ INF(0), FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN(1), FP32_QNAN(1), FP32_INF(1), FP32_RAND_V7(0)} },12232 { /*src1 */ { FP32_0(0), FP32_ INF(1), FP32_QNAN(0), FP32_SNAN(1), FP32_QNAN_V(0, 1), FP32_QNAN_V(1, 1), FP32_SNAN(1), FP32_SNAN(0)} },12233 { /* => */ { FP32_0(0), FP32_ INF(1), FP32_QNAN(0), FP32_SNAN(1), FP32_QNAN_V(0, 1), FP32_QNAN_V(1, 1), FP32_SNAN(1), FP32_SNAN(0)} },12262 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V1 } }, 12263 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V2 } }, 12264 { /* => */ { FP32_0(0), FP32_RAND_x7_V2 } }, 12234 12265 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 12235 12266 /*128:out */ X86_MXCSR_XCPT_MASK, 12236 12267 /*256:out */ X86_MXCSR_XCPT_MASK, 12237 12268 /*xcpt? */ false, false }, 12238 { { /*src2 */ { FP32_0(0), FP32_RAND_ V0(0), FP32_RAND_V0(0), FP32_RAND_V0(0), FP32_RAND_V0(0), FP32_RAND_V0(0), FP32_RAND_V0(0), FP32_RAND_V0(0)} },12239 { /*src1 */ { FP32_0(0), FP32_RAND_ V6(0), FP32_RAND_V5(0), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(0), FP32_RAND_V0(0)} },12240 { /* => */ { FP32_0(0), FP32_RAND_ V6(0), FP32_RAND_V5(0), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(0), FP32_RAND_V0(0)} },12269 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V2 } }, 12270 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V3 } }, 12271 { /* => */ { FP32_0(0), FP32_RAND_x7_V3 } }, 12241 12272 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 12242 12273 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 12243 12274 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 12244 12275 /*xcpt? */ false, false }, 12245 { { /*src2 */ { FP32_0(0), FP32_RAND_ V6(0), FP32_RAND_V5(0), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(0), FP32_RAND_V0(0)} },12246 { /*src1 */ { FP32_0(0), FP32_RAND_ V0(1), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(1)} },12247 { /* => */ { FP32_0(0), FP32_RAND_ V0(1), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(1)} },12276 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V3 } }, 12277 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V4 } }, 12278 { /* => */ { FP32_0(0), FP32_RAND_x7_V4 } }, 12248 12279 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 12249 12280 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 12250 12281 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 12251 12282 /*xcpt? */ false, false }, 12252 { { /*src2 */ { FP32_0(0), FP32_RAND_ V0(0), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V7(0), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V6(0)} },12253 { /*src1 */ { FP32_0(1), FP32_RAND_ V6(0), FP32_RAND_V5(0), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(0), FP32_RAND_V0(0)} },12254 { /* => */ { FP32_0(0), FP32_RAND_ V6(0), FP32_RAND_V5(0), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(0), FP32_RAND_V0(0)} },12283 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V4 } }, 12284 { /*src1 */ { FP32_0(1), FP32_RAND_x7_V5 } }, 12285 { /* => */ { FP32_0(0), FP32_RAND_x7_V5 } }, 12255 12286 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 12256 12287 /*128:out */ X86_MXCSR_XCPT_MASK, 12257 12288 /*256:out */ X86_MXCSR_XCPT_MASK, 12258 12289 /*xcpt? */ false, false }, 12259 { { /*src2 */ { FP32_0(0), FP32_RAND_ V0(1), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V7(0), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V6(0)} },12260 { /*src1 */ { FP32_0(1), FP32_RAND_ V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(0), FP32_RAND_V2(1), FP32_RAND_V1(0), FP32_RAND_V3(1)} },12261 { /* => */ { FP32_0(0), FP32_RAND_ V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(0), FP32_RAND_V2(1), FP32_RAND_V1(0), FP32_RAND_V3(1)} },12290 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V5 } }, 12291 { /*src1 */ { FP32_0(1), FP32_RAND_x7_V6 } }, 12292 { /* => */ { FP32_0(0), FP32_RAND_x7_V6 } }, 12262 12293 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 12263 12294 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 12264 12295 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 12265 12296 /*xcpt? */ false, false }, 12266 { { /*src2 */ { FP32_0(1), FP32_RAND_ V6(1), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V1(1), FP32_RAND_V0(1)} },12267 { /*src1 */ { FP32_0(0), FP32_RAND_ V0(0), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0)} },12268 { /* => */ { FP32_0(1), FP32_RAND_ V0(0), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0)} },12297 { { /*src2 */ { FP32_0(1), FP32_RAND_x7_V6 } }, 12298 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V5 } }, 12299 { /* => */ { FP32_0(1), FP32_RAND_x7_V5 } }, 12269 12300 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 12270 12301 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 12271 12302 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 12272 12303 /*xcpt? */ false, false }, 12273 { { /*src2 */ { FP32_0(1), FP32_RAND_ V5(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V0(0)} },12274 { /*src1 */ { FP32_0(0), FP32_RAND_ V0(1), FP32_RAND_V1(1), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V5(1), FP32_RAND_V2(1)} },12275 { /* => */ { FP32_0(1), FP32_RAND_ V0(1), FP32_RAND_V1(1), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V5(1), FP32_RAND_V2(1)} },12304 { { /*src2 */ { FP32_0(1), FP32_RAND_x7_V7 } }, 12305 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V2 } }, 12306 { /* => */ { FP32_0(1), FP32_RAND_x7_V2 } }, 12276 12307 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 12277 12308 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 12278 12309 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 12279 12310 /*xcpt? */ false, false }, 12280 { { /*src2 */ { FP32_0(1), FP32_RAND_ V6(1), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V1(1), FP32_RAND_V0(1)} },12281 { /*src1 */ { FP32_0(1), FP32_RAND_ V0(1), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V7(0), FP32_RAND_V3(0), FP32_RAND_V6(1), FP32_RAND_V4(1)} },12282 { /* => */ { FP32_0(1), FP32_RAND_ V0(1), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V7(0), FP32_RAND_V3(0), FP32_RAND_V6(1), FP32_RAND_V4(1)} },12311 { { /*src2 */ { FP32_0(1), FP32_RAND_x7_V1 } }, 12312 { /*src1 */ { FP32_0(1), FP32_RAND_x7_V7 } }, 12313 { /* => */ { FP32_0(1), FP32_RAND_x7_V7 } }, 12283 12314 /*mxcsr:in */ 0, 12284 12315 /*128:out */ 0, 12285 12316 /*256:out */ 0, 12286 12317 /*xcpt? */ false, false }, 12287 { { /*src2 */ { FP32_0(1), FP32_RAND_ V6(1), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V1(1), FP32_RAND_V0(1)} },12288 { /*src1 */ { FP32_0(1), FP32_RAND_ V1(0), FP32_RAND_V5(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V3(0), FP32_RAND_V1(0), FP32_RAND_V6(1)} },12289 { /* => */ { FP32_0(1), FP32_RAND_ V1(0), FP32_RAND_V5(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V3(0), FP32_RAND_V1(0), FP32_RAND_V6(1)} },12318 { { /*src2 */ { FP32_0(1), FP32_RAND_x7_V1 } }, 12319 { /*src1 */ { FP32_0(1), FP32_RAND_x7_V5 } }, 12320 { /* => */ { FP32_0(1), FP32_RAND_x7_V5 } }, 12290 12321 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 12291 12322 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP, … … 12295 12326 * Infinity. 12296 12327 */ 12297 /*11*/{ { /*src2 */ { FP32_INF(0), FP32_RAND_ V6(1), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V1(1), FP32_RAND_V0(1)} },12298 { /*src1 */ { FP32_0(0), FP32_RAND_ V1(0), FP32_RAND_V5(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V3(0), FP32_RAND_V1(0), FP32_RAND_V6(1)} },12299 { /* => */ { FP32_INF(0), FP32_RAND_ V1(0), FP32_RAND_V5(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V3(0), FP32_RAND_V1(0), FP32_RAND_V6(1)} },12328 /*11*/{ { /*src2 */ { FP32_INF(0), FP32_RAND_x7_V6 } }, 12329 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V1 } }, 12330 { /* => */ { FP32_INF(0), FP32_RAND_x7_V1 } }, 12300 12331 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 12301 12332 /*128:out */ X86_MXCSR_XCPT_MASK, 12302 12333 /*256:out */ X86_MXCSR_XCPT_MASK, 12303 12334 /*xcpt? */ false, false }, 12304 { { /*src2 */ { FP32_0(0), FP32_RAND_ V5(1), FP32_RAND_V5(1), FP32_RAND_V6(1), FP32_RAND_V3(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V0(1)} },12305 { /*src1 */ { FP32_INF(0), FP32_RAND_ V3(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V5(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V7(1)} },12306 { /* => */ { FP32_INF(0), FP32_RAND_ V3(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V5(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V7(1)} },12335 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V5 } }, 12336 { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V3 } }, 12337 { /* => */ { FP32_INF(0), FP32_RAND_x7_V3 } }, 12307 12338 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, 12308 12339 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, 12309 12340 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, 12310 12341 /*xcpt? */ false, false }, 12311 { { /*src2 */ { FP32_INF(0), FP32_ INF(1), FP32_SNAN(1), FP32_QNAN(1), FP32_RAND_V3(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V0(1)} },12312 { /*src1 */ { FP32_0(0), FP32_RAND_ V3(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_QNAN(0), FP32_RAND_V2(0), FP32_RAND_V4(1), FP32_RAND_V7(0)} },12313 { /* => */ { FP32_INF(0), FP32_RAND_ V3(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_QNAN(0), FP32_RAND_V2(0), FP32_RAND_V4(1), FP32_RAND_V7(0)} },12342 { { /*src2 */ { FP32_INF(0), FP32_RAND_x7_V0 } }, 12343 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V3 } }, 12344 { /* => */ { FP32_INF(0), FP32_RAND_x7_V3 } }, 12314 12345 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 12315 12346 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 12316 12347 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 12317 12348 /*xcpt? */ false, false }, 12318 { { /*src2 */ { FP32_0(0), FP32_RAND_ V2(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V7(0), FP32_RAND_V1(0)} },12319 { /*src1 */ { FP32_INF(1), FP32_RAND_ V0(0), FP32_RAND_V1(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0), FP32_RAND_V2(1), FP32_RAND_V2(1)} },12320 { /* => */ { FP32_0(0), FP32_RAND_ V0(0), FP32_RAND_V1(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0), FP32_RAND_V2(1), FP32_RAND_V2(1)} },12349 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V2 } }, 12350 { /*src1 */ { FP32_INF(1), FP32_RAND_x7_V0 } }, 12351 { /* => */ { FP32_0(0), FP32_RAND_x7_V0 } }, 12321 12352 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 12322 12353 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 12323 12354 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 12324 12355 /*xcpt? */ false, false }, 12325 { { /*src2 */ { FP32_INF(0), FP32_RAND_ V3(1), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(1)} },12326 { /*src1 */ { FP32_INF(0), FP32_RAND_ V1(0), FP32_RAND_V2(1), FP32_RAND_V5(1), FP32_RAND_V6(0), FP32_SNAN(0), FP32_SNAN(1), FP32_RAND_V2(1)} },12327 { /* => */ { FP32_INF(0), FP32_RAND_ V1(0), FP32_RAND_V2(1), FP32_RAND_V5(1), FP32_RAND_V6(0), FP32_SNAN(0), FP32_SNAN(1), FP32_RAND_V2(1)} },12356 { { /*src2 */ { FP32_INF(0), FP32_RAND_x7_V3 } }, 12357 { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V1 } }, 12358 { /* => */ { FP32_INF(0), FP32_RAND_x7_V1 } }, 12328 12359 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 12329 12360 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 12330 12361 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 12331 12362 /*xcpt? */ false, false }, 12332 { { /*src2 */ { FP32_INF(0), FP32_RAND_ V2(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(1)} },12333 { /*src1 */ { FP32_INF(0), FP32_RAND_ V0(1), FP32_RAND_V0(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_SNAN(1), FP32_QNAN_V(1, 1), FP32_RAND_V3(1)} },12334 { /* => */ { FP32_INF(0), FP32_RAND_ V0(1), FP32_RAND_V0(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_SNAN(1), FP32_QNAN_V(1, 1), FP32_RAND_V3(1)} },12363 { { /*src2 */ { FP32_INF(0), FP32_RAND_x7_V2 } }, 12364 { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V0 } }, 12365 { /* => */ { FP32_INF(0), FP32_RAND_x7_V0 } }, 12335 12366 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 12336 12367 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 12337 12368 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 12338 12369 /*xcpt? */ false, false }, 12339 { { /*src2 */ { FP32_INF(1), FP32_RAND_ V3(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V7(1), FP32_RAND_V0(0)} },12340 { /*src1 */ { FP32_INF(1), FP32_ QNAN_V(1, 1), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_QNAN_V(1, 0), FP32_RAND_V1(0)} },12341 { /* => */ { FP32_INF(1), FP32_ QNAN_V(1, 1), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_QNAN_V(1, 0), FP32_RAND_V1(0)} },12370 { { /*src2 */ { FP32_INF(1), FP32_RAND_x7_V1 } }, 12371 { /*src1 */ { FP32_INF(1), FP32_RAND_x7_V2 } }, 12372 { /* => */ { FP32_INF(1), FP32_RAND_x7_V2 } }, 12342 12373 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 12343 12374 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 12344 12375 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 12345 12376 /*xcpt? */ false, false }, 12346 { { /*src2 */ { FP32_INF(1), FP32_RAND_ V2(1), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V1(1), FP32_RAND_V0(1)} },12347 { /*src1 */ { FP32_INF(1), FP32_RAND_ V0(0), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V2(0), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V5(1)} },12348 { /* => */ { FP32_INF(1), FP32_RAND_ V0(0), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V2(0), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V5(1)} },12377 { { /*src2 */ { FP32_INF(1), FP32_RAND_x7_V3 } }, 12378 { /*src1 */ { FP32_INF(1), FP32_RAND_x7_V3 } }, 12379 { /* => */ { FP32_INF(1), FP32_RAND_x7_V3 } }, 12349 12380 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 12350 12381 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 12351 12382 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 12352 12383 /*xcpt? */ false, false }, 12353 { { /*src2 */ { FP32_INF(1), FP32_RAND_ V1(1), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V1(0), FP32_RAND_V1(1)} },12354 { /*src1 */ { FP32_INF(0), FP32_RAND_ V1(0), FP32_RAND_V2(1), FP32_RAND_V5(1), FP32_RAND_V6(0), FP32_RAND_V7(0), FP32_RAND_V2(0), FP32_RAND_V3(1)} },12355 { /* => */ { FP32_INF(0), FP32_RAND_ V1(0), FP32_RAND_V2(1), FP32_RAND_V5(1), FP32_RAND_V6(0), FP32_RAND_V7(0), FP32_RAND_V2(0), FP32_RAND_V3(1)} },12384 { { /*src2 */ { FP32_INF(1), FP32_RAND_x7_V1 } }, 12385 { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V1 } }, 12386 { /* => */ { FP32_INF(0), FP32_RAND_x7_V1 } }, 12356 12387 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, 12357 12388 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, 12358 12389 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, 12359 12390 /*xcpt? */ false, false }, 12360 { { /*src2 */ { FP32_INF(1), FP32_RAND_ V0(1), FP32_RAND_V2(1), FP32_RAND_V4(1), FP32_RAND_V2(1), FP32_RAND_V5(1), FP32_RAND_V2(1), FP32_RAND_V1(1)} },12361 { /*src1 */ { FP32_INF(0), FP32_RAND_ V0(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V6(1), FP32_RAND_V7(0), FP32_RAND_V4(1)} },12362 { /* => */ { FP32_INF(0), FP32_RAND_ V0(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V6(1), FP32_RAND_V7(0), FP32_RAND_V4(1)} },12391 { { /*src2 */ { FP32_INF(1), FP32_RAND_x7_V0 } }, 12392 { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V1 } }, 12393 { /* => */ { FP32_INF(0), FP32_RAND_x7_V1 } }, 12363 12394 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 12364 12395 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 12365 12396 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 12366 12397 /*xcpt? */ false, false }, 12367 { { /*src2 */ { FP32_INF(0), FP32_RAND_ V2(1), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V6(1), FP32_RAND_V1(1), FP32_RAND_V7(1), FP32_RAND_V2(0)} },12368 { /*src1 */ { FP32_INF(1), FP32_RAND_ V2(0), FP32_RAND_V3(0), FP32_RAND_V1(1), FP32_RAND_V0(1), FP32_RAND_V5(1), FP32_RAND_V7(0), FP32_RAND_V1(0)} },12369 { /* => */ { FP32_INF(0), FP32_RAND_ V2(0), FP32_RAND_V3(0), FP32_RAND_V1(1), FP32_RAND_V0(1), FP32_RAND_V5(1), FP32_RAND_V7(0), FP32_RAND_V1(0)} },12398 { { /*src2 */ { FP32_INF(0), FP32_RAND_x7_V3 } }, 12399 { /*src1 */ { FP32_INF(1), FP32_RAND_x7_V2 } }, 12400 { /* => */ { FP32_INF(0), FP32_RAND_x7_V2 } }, 12370 12401 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 12371 12402 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 12372 12403 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 12373 12404 /*xcpt? */ false, false }, 12374 { { /*src2 */ { FP32_INF(0), FP32_RAND_ V0(1), FP32_RAND_V2(1), FP32_RAND_V4(1), FP32_RAND_V2(1), FP32_RAND_V5(1), FP32_RAND_V2(1), FP32_RAND_V1(1)} },12375 { /*src1 */ { FP32_INF(1), FP32_RAND_ V0(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V6(1), FP32_RAND_V7(0), FP32_RAND_V4(1)} },12376 { /* => */ { FP32_INF(0), FP32_RAND_ V0(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V6(1), FP32_RAND_V7(0), FP32_RAND_V4(1)} },12405 { { /*src2 */ { FP32_INF(0), FP32_RAND_x7_V0 } }, 12406 { /*src1 */ { FP32_INF(1), FP32_RAND_x7_V3 } }, 12407 { /* => */ { FP32_INF(0), FP32_RAND_x7_V3 } }, 12377 12408 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, 12378 12409 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, 12379 12410 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, 12380 12411 /*xcpt? */ false, false }, 12381 { { /*src2 */ { FP32_INF(0), FP32_RAND_ V0(0), FP32_RAND_V2(1), FP32_RAND_V4(1), FP32_RAND_V2(1), FP32_RAND_V5(1), FP32_RAND_V2(1), FP32_RAND_V1(0)} },12382 { /*src1 */ { FP32_NORM_V0(0), FP32_RAND_ V1(1), FP32_RAND_V3(1), FP32_RAND_V5(1), FP32_RAND_V7(0), FP32_RAND_V6(1), FP32_RAND_V2(1), FP32_RAND_V4(0)} },12383 { /* => */ { FP32_INF(0), FP32_RAND_ V1(1), FP32_RAND_V3(1), FP32_RAND_V5(1), FP32_RAND_V7(0), FP32_RAND_V6(1), FP32_RAND_V2(1), FP32_RAND_V4(0)} },12412 { { /*src2 */ { FP32_INF(0), FP32_RAND_x7_V4 } }, 12413 { /*src1 */ { FP32_NORM_V0(0), FP32_RAND_x7_V5 } }, 12414 { /* => */ { FP32_INF(0), FP32_RAND_x7_V5 } }, 12384 12415 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 12385 12416 /*128:out */ X86_MXCSR_XCPT_MASK, 12386 12417 /*256:out */ X86_MXCSR_XCPT_MASK, 12387 12418 /*xcpt? */ false, false }, 12388 { { /*src2 */ { FP32_INF(0), FP32_ INF(0), FP32_SNAN(1), FP32_INF(1), FP32_RAND_V3(1), FP32_RAND_V6(1), FP32_RAND_V3(1), FP32_RAND_V4(0)} },12389 { /*src1 */ { FP32_NORM_V3(0), FP32_ INF(1), FP32_QNAN(1), FP32_SNAN(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V2(1), FP32_RAND_V1(1)} },12390 { /* => */ { FP32_INF(0), FP32_ INF(1), FP32_QNAN(1), FP32_SNAN(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V2(1), FP32_RAND_V1(1)} },12419 { { /*src2 */ { FP32_INF(0), FP32_RAND_x7_V6 } }, 12420 { /*src1 */ { FP32_NORM_V3(0), FP32_RAND_x7_V5 } }, 12421 { /* => */ { FP32_INF(0), FP32_RAND_x7_V5 } }, 12391 12422 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 12392 12423 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 12393 12424 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 12394 12425 /*xcpt? */ false, false }, 12395 { { /*src2 */ { FP32_NORM_V7(0), FP32_RAND_ V6(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_INF(1), FP32_SNAN(0), FP32_INF(0), FP32_RAND_V2(0)} },12396 { /*src1 */ { FP32_INF(1), FP32_RAND_ V2(1), FP32_RAND_V2(1), FP32_RAND_V1(1), FP32_INF(1), FP32_QNAN(1), FP32_SNAN(1), FP32_RAND_V3(0)} },12397 { /* => */ { FP32_NORM_V7(0), FP32_RAND_ V2(1), FP32_RAND_V2(1), FP32_RAND_V1(1), FP32_INF(1), FP32_QNAN(1), FP32_SNAN(1), FP32_RAND_V3(0)} },12426 { { /*src2 */ { FP32_NORM_V7(0), FP32_RAND_x7_V7 } }, 12427 { /*src1 */ { FP32_INF(1), FP32_RAND_x7_V1 } }, 12428 { /* => */ { FP32_NORM_V7(0), FP32_RAND_x7_V1 } }, 12398 12429 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 12399 12430 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 12400 12431 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 12401 12432 /*xcpt? */ false, false }, 12402 { { /*src2 */ { FP32_NORM_V7(0), FP32_RAND_ V6(0), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_QNAN(1), FP32_SNAN(0), FP32_INF(1), FP32_RAND_V2(1)} },12403 { /*src1 */ { FP32_INF(0), FP32_RAND_ V7(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_QNAN(1), FP32_QNAN(1), FP32_SNAN(0), FP32_RAND_V3(1)} },12404 { /* => */ { FP32_INF(0), FP32_RAND_ V7(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_QNAN(1), FP32_QNAN(1), FP32_SNAN(0), FP32_RAND_V3(1)} },12433 { { /*src2 */ { FP32_NORM_V7(0), FP32_RAND_x7_V4 } }, 12434 { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V2 } }, 12435 { /* => */ { FP32_INF(0), FP32_RAND_x7_V2 } }, 12405 12436 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 12406 12437 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, … … 12410 12441 * Normals. 12411 12442 */ 12412 /*27*/{ { /*src2 */ { FP32_NORM_MAX(0), FP32_RAND_ V2(1), FP32_RAND_V0(1), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V1(1)} },12413 { /*src1 */ { FP32_NORM_MAX(0), FP32_RAND_ V3(1), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V6(0), FP32_RAND_V7(0), FP32_RAND_V3(1), FP32_RAND_V1(1)} },12414 { /* => */ { FP32_NORM_MAX(0), FP32_RAND_ V3(1), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V6(0), FP32_RAND_V7(0), FP32_RAND_V3(1), FP32_RAND_V1(1)} },12443 /*27*/{ { /*src2 */ { FP32_NORM_MAX(0), FP32_RAND_x7_V2 } }, 12444 { /*src1 */ { FP32_NORM_MAX(0), FP32_RAND_x7_V3 } }, 12445 { /* => */ { FP32_NORM_MAX(0), FP32_RAND_x7_V3 } }, 12415 12446 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 12416 12447 /*128:out */ X86_MXCSR_XCPT_MASK, 12417 12448 /*256:out */ X86_MXCSR_XCPT_MASK, 12418 12449 /*xcpt? */ false, false }, 12419 { { /*src2 */ { FP32_NORM_MIN(0), FP32_RAND_ V3(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V7(0), FP32_RAND_V1(1)} },12420 { /*src1 */ { FP32_NORM_MIN(0), FP32_RAND_ V2(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V2(0), FP32_RAND_V1(1), FP32_RAND_V0(1), FP32_RAND_V7(0)} },12421 { /* => */ { FP32_NORM_MIN(0), FP32_RAND_ V2(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V2(0), FP32_RAND_V1(1), FP32_RAND_V0(1), FP32_RAND_V7(0)} },12450 { { /*src2 */ { FP32_NORM_MIN(0), FP32_RAND_x7_V3 } }, 12451 { /*src1 */ { FP32_NORM_MIN(0), FP32_RAND_x7_V2 } }, 12452 { /* => */ { FP32_NORM_MIN(0), FP32_RAND_x7_V2 } }, 12422 12453 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 12423 12454 /*128:out */ X86_MXCSR_XCPT_MASK, 12424 12455 /*256:out */ X86_MXCSR_XCPT_MASK, 12425 12456 /*xcpt? */ false, false }, 12426 { { /*src2 */ { FP32_NORM_MIN(0), FP32_RAND_ V3(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V2(0), FP32_RAND_V1(1), FP32_RAND_V7(0), FP32_RAND_V2(1)} },12427 { /*src1 */ { FP32_NORM_MAX(0), FP32_RAND_ V1(0), FP32_RAND_V6(0), FP32_RAND_V4(0), FP32_RAND_V4(0), FP32_RAND_V3(1), FP32_RAND_V6(0), FP32_RAND_V4(1)} },12428 { /* => */ { FP32_NORM_MAX(0), FP32_RAND_ V1(0), FP32_RAND_V6(0), FP32_RAND_V4(0), FP32_RAND_V4(0), FP32_RAND_V3(1), FP32_RAND_V6(0), FP32_RAND_V4(1)} },12457 { { /*src2 */ { FP32_NORM_MIN(0), FP32_RAND_x7_V3 } }, 12458 { /*src1 */ { FP32_NORM_MAX(0), FP32_RAND_x7_V1 } }, 12459 { /* => */ { FP32_NORM_MAX(0), FP32_RAND_x7_V1 } }, 12429 12460 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 12430 12461 /*128:out */ X86_MXCSR_XCPT_MASK, 12431 12462 /*256:out */ X86_MXCSR_XCPT_MASK, 12432 12463 /*xcpt? */ false, false }, 12433 { { /*src2 */ { FP32_NORM_MAX(0), FP32_RAND_ V2(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V7(0), FP32_RAND_V1(0)} },12434 { /*src1 */ { FP32_NORM_MAX(0), FP32_RAND_ V0(0), FP32_RAND_V1(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0), FP32_RAND_V2(1), FP32_RAND_V2(1)} },12435 { /* => */ { FP32_NORM_MAX(0), FP32_RAND_ V0(0), FP32_RAND_V1(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0), FP32_RAND_V2(1), FP32_RAND_V2(1)} },12464 { { /*src2 */ { FP32_NORM_MAX(0), FP32_RAND_x7_V2 } }, 12465 { /*src1 */ { FP32_NORM_MAX(0), FP32_RAND_x7_V0 } }, 12466 { /* => */ { FP32_NORM_MAX(0), FP32_RAND_x7_V0 } }, 12436 12467 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 12437 12468 /*128:out */ X86_MXCSR_XCPT_MASK, 12438 12469 /*256:out */ X86_MXCSR_XCPT_MASK, 12439 12470 /*xcpt? */ false, false }, 12440 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_ V2(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V7(0), FP32_RAND_V1(1)} },12441 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_ V1(0), FP32_RAND_V4(0), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V0(0), FP32_RAND_V1(1)} },12442 { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_ V1(0), FP32_RAND_V4(0), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V0(0), FP32_RAND_V1(1)} },12471 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_x7_V2 } }, 12472 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V1 } }, 12473 { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V1 } }, 12443 12474 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 12444 12475 /*128:out */ X86_MXCSR_XCPT_MASK, 12445 12476 /*256:out */ X86_MXCSR_XCPT_MASK, 12446 12477 /*xcpt? */ false, false }, 12447 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_ V6(0), FP32_RAND_V5(0), FP32_RAND_V6(1), FP32_RAND_V4(0), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V1(1)} },12448 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_ V1(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V5(0), FP32_RAND_V6(0), FP32_RAND_V7(0), FP32_RAND_V2(1)} },12449 { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_ V1(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V5(0), FP32_RAND_V6(0), FP32_RAND_V7(0), FP32_RAND_V2(1)} },12478 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V6 } }, 12479 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V1 } }, 12480 { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V1 } }, 12450 12481 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 12451 12482 /*128:out */ X86_MXCSR_XCPT_MASK, 12452 12483 /*256:out */ X86_MXCSR_XCPT_MASK, 12453 12484 /*xcpt? */ false, false }, 12454 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_ INF(0), FP32_QNAN(1), FP32_QNAN(0), FP32_SNAN(1), FP32_SNAN(1), FP32_SNAN(0), FP32_QNAN(1)} },12455 { /*src1 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_ V1(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_QNAN(0), FP32_RAND_V2(0), FP32_RAND_V4(1), FP32_RAND_V7(0)} },12456 { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_ V1(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_QNAN(0), FP32_RAND_V2(0), FP32_RAND_V4(1), FP32_RAND_V7(0)} },12485 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V0 } }, 12486 { /*src1 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_x7_V1 } }, 12487 { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V1 } }, 12457 12488 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 12458 12489 /*128:out */ X86_MXCSR_XCPT_MASK, 12459 12490 /*256:out */ X86_MXCSR_XCPT_MASK, 12460 12491 /*xcpt? */ false, false }, 12461 { { /*src2 */ { FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_RAND_ V1(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(1), FP32_RAND_V7(1)} },12462 { /*src1 */ { FP32_V(1, 0, 0x7d)/*-0.25*/, FP32_RAND_ V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1), FP32_RAND_V7(1)} },12463 { /* => */ { FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_RAND_ V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1), FP32_RAND_V7(1)} },12492 { { /*src2 */ { FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_RAND_x7_V1 } }, 12493 { /*src1 */ { FP32_V(1, 0, 0x7d)/*-0.25*/, FP32_RAND_x7_V2 } }, 12494 { /* => */ { FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_RAND_x7_V2 } }, 12464 12495 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 12465 12496 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 12466 12497 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 12467 12498 /*xcpt? */ false, false }, 12468 { { /*src2 */ { FP32_V(0, 0, 0x7d)/*0.25*/, FP32_RAND_ V2(1), FP32_RAND_V5(0), FP32_RAND_V6(1), FP32_RAND_V4(0), FP32_RAND_V3(1), FP32_RAND_V7(0), FP32_RAND_V1(1)} },12469 { /*src1 */ { FP32_V(0, 0, 0x7e)/*0.50*/, FP32_RAND_ V0(0), FP32_RAND_V5(0), FP32_RAND_V7(0), FP32_RAND_V2(1), FP32_SNAN(1), FP32_SNAN(0), FP32_RAND_V3(0)} },12470 { /* => */ { FP32_V(0, 0, 0x7e)/*0.50*/, FP32_RAND_ V0(0), FP32_RAND_V5(0), FP32_RAND_V7(0), FP32_RAND_V2(1), FP32_SNAN(1), FP32_SNAN(0), FP32_RAND_V3(0)} },12499 { { /*src2 */ { FP32_V(0, 0, 0x7d)/*0.25*/, FP32_RAND_x7_V3 } }, 12500 { /*src1 */ { FP32_V(0, 0, 0x7e)/*0.50*/, FP32_RAND_x7_V1 } }, 12501 { /* => */ { FP32_V(0, 0, 0x7e)/*0.50*/, FP32_RAND_x7_V1 } }, 12471 12502 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 12472 12503 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 12473 12504 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 12474 12505 /*xcpt? */ false, false }, 12475 { { /*src2 */ { FP32_NORM_MAX(0), FP32_RAND_ V0(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(1), FP32_RAND_V7(1)} },12476 { /*src1 */ { FP32_NORM_V1(0), FP32_RAND_ V0(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(0), FP32_RAND_V6(0), FP32_RAND_V7(0)} },12477 { /* => */ { FP32_NORM_MAX(0), FP32_RAND_ V0(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(0), FP32_RAND_V6(0), FP32_RAND_V7(0)} },12506 { { /*src2 */ { FP32_NORM_MAX(0), FP32_RAND_x7_V1 } }, 12507 { /*src1 */ { FP32_NORM_V1(0), FP32_RAND_x7_V0 } }, 12508 { /* => */ { FP32_NORM_MAX(0), FP32_RAND_x7_V0 } }, 12478 12509 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 12479 12510 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 12480 12511 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 12481 12512 /*xcpt? */ false, false }, 12482 { { /*src2 */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_RAND_ V3(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V4(0), FP32_RAND_V7(0), FP32_RAND_V6(0)} },12483 { /*src1 */ { FP32_V(0, 0x1ea980, 0x8f)/* 81235*/, FP32_RAND_ V0(0), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V3(1)} },12484 { /* => */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_RAND_ V0(0), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V3(1)} },12513 { { /*src2 */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_RAND_x7_V3 } }, 12514 { /*src1 */ { FP32_V(0, 0x1ea980, 0x8f)/* 81235*/, FP32_RAND_x7_V1 } }, 12515 { /* => */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_RAND_x7_V1 } }, 12485 12516 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 12486 12517 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 12487 12518 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 12488 12519 /*xcpt? */ false, false }, 12489 { { /*src2 */ { FP32_V(1, 0x2514d6, 0x93)/*-1352346.75*/, FP32_RAND_ V2(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V7(0), FP32_RAND_V1(0)} },12490 { /*src1 */ { FP32_V(0, 0x7c9000, 0x88)/* 1010.25*/, FP32_RAND_ V0(0), FP32_RAND_V1(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0), FP32_RAND_V2(1), FP32_RAND_V2(1)} },12491 { /* => */ { FP32_V(0, 0x7c9000, 0x88)/* 1010.25*/, FP32_RAND_ V0(0), FP32_RAND_V1(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0), FP32_RAND_V2(1), FP32_RAND_V2(1)} },12520 { { /*src2 */ { FP32_V(1, 0x2514d6, 0x93)/*-1352346.75*/, FP32_RAND_x7_V2 } }, 12521 { /*src1 */ { FP32_V(0, 0x7c9000, 0x88)/* 1010.25*/, FP32_RAND_x7_V0 } }, 12522 { /* => */ { FP32_V(0, 0x7c9000, 0x88)/* 1010.25*/, FP32_RAND_x7_V0 } }, 12492 12523 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 12493 12524 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 12494 12525 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 12495 12526 /*xcpt? */ false, false }, 12496 { { /*src2 */ { FP32_V(1, 0x2514d6, 0x93)/*-1352346.75*/, FP32_RAND_ V2(1), FP32_RAND_V3(1), FP32_RAND_V6(1), FP32_RAND_V3(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V0(1)} },12497 { /*src1 */ { FP32_V(0, 0x253468, 0x93)/* 1353357.00*/, FP32_RAND_ V3(0), FP32_RAND_V1(0), FP32_RAND_V0(1), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V4(1)} },12498 { /* => */ { FP32_V(0, 0x253468, 0x93)/* 1353357.00*/, FP32_RAND_ V3(0), FP32_RAND_V1(0), FP32_RAND_V0(1), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V4(1)} },12527 { { /*src2 */ { FP32_V(1, 0x2514d6, 0x93)/*-1352346.75*/, FP32_RAND_x7_V4 } }, 12528 { /*src1 */ { FP32_V(0, 0x253468, 0x93)/* 1353357.00*/, FP32_RAND_x7_V4 } }, 12529 { /* => */ { FP32_V(0, 0x253468, 0x93)/* 1353357.00*/, FP32_RAND_x7_V4 } }, 12499 12530 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 12500 12531 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 12501 12532 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 12502 12533 /*xcpt? */ false, false }, 12503 { { /*src2 */ { FP32_V(1, 0x40e6b6, 0x8c)/*-12345.678*/, FP32_RAND_ V3(1), FP32_RAND_V5(1), FP32_RAND_V6(1), FP32_RAND_V3(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V0(1)} },12504 { /*src1 */ { FP32_V(1, 0x40e6b7, 0x8c)/*-12345.679*/, FP32_RAND_ V1(1), FP32_RAND_V0(0), FP32_RAND_V0(1), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V4(0), FP32_RAND_V4(1)} },12505 { /* => */ { FP32_V(1, 0x40e6b6, 0x8c)/*-12345.678*/, FP32_RAND_ V1(1), FP32_RAND_V0(0), FP32_RAND_V0(1), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V4(0), FP32_RAND_V4(1)} },12534 { { /*src2 */ { FP32_V(1, 0x40e6b6, 0x8c)/*-12345.678*/, FP32_RAND_x7_V3 } }, 12535 { /*src1 */ { FP32_V(1, 0x40e6b7, 0x8c)/*-12345.679*/, FP32_RAND_x7_V1 } }, 12536 { /* => */ { FP32_V(1, 0x40e6b6, 0x8c)/*-12345.678*/, FP32_RAND_x7_V1 } }, 12506 12537 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 12507 12538 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 12508 12539 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 12509 12540 /*xcpt? */ false, false }, 12510 { { /*src2 */ { FP32_V(0, 0x620b2e, 0x92)/*925874.9*/, FP32_RAND_ V5(1), FP32_RAND_V5(1), FP32_RAND_V6(1), FP32_RAND_V3(1), FP32_RAND_V3(1), FP32_RAND_V3(1), FP32_RAND_V1(1)} },12511 { /*src1 */ { FP32_V(0, 0x620b2d, 0x92)/*925874.8*/, FP32_RAND_ V3(0), FP32_RAND_V6(1), FP32_RAND_V0(1), FP32_RAND_V6(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V2(1)} },12512 { /* => */ { FP32_V(0, 0x620b2e, 0x92)/*925874.9*/, FP32_RAND_ V3(0), FP32_RAND_V6(1), FP32_RAND_V0(1), FP32_RAND_V6(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V2(1)} },12541 { { /*src2 */ { FP32_V(0, 0x620b2e, 0x92)/*925874.9*/, FP32_RAND_x7_V2 } }, 12542 { /*src1 */ { FP32_V(0, 0x620b2d, 0x92)/*925874.8*/, FP32_RAND_x7_V4 } }, 12543 { /* => */ { FP32_V(0, 0x620b2e, 0x92)/*925874.9*/, FP32_RAND_x7_V4 } }, 12513 12544 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 12514 12545 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 12515 12546 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 12516 12547 /*xcpt? */ false, false }, 12517 { { /*src2 */ { FP32_V(0, 0x490fda, 0x80)/*3.1415926*/, FP32_RAND_ V6(1), FP32_RAND_V2(1), FP32_RAND_V4(1), FP32_RAND_V2(1), FP32_RAND_V5(1), FP32_RAND_V2(1), FP32_RAND_V1(1)} },12518 { /*src1 */ { FP32_V(0, 0x490fdb, 0x80)/*3.1415927*/, FP32_RAND_ V6(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V3(0), FP32_RAND_V7(0), FP32_RAND_V1(0), FP32_RAND_V1(1)} },12519 { /* => */ { FP32_V(0, 0x490fdb, 0x80)/*3.1415927*/, FP32_RAND_ V6(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V3(0), FP32_RAND_V7(0), FP32_RAND_V1(0), FP32_RAND_V1(1)} },12548 { { /*src2 */ { FP32_V(0, 0x490fda, 0x80)/*3.1415926*/, FP32_RAND_x7_V3 } }, 12549 { /*src1 */ { FP32_V(0, 0x490fdb, 0x80)/*3.1415927*/, FP32_RAND_x7_V1 } }, 12550 { /* => */ { FP32_V(0, 0x490fdb, 0x80)/*3.1415927*/, FP32_RAND_x7_V1 } }, 12520 12551 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 12521 12552 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 12522 12553 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 12523 12554 /*xcpt? */ false, false }, 12524 { { /*src2 */ { FP32_V(1, 0x40e6b6, 0x8c)/*-12345.678*/, FP32_ INF(1), FP32_SNAN(1), FP32_INF(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V6(1)} },12525 { /*src1 */ { FP32_V(1, 0x40e6b7, 0x8c)/*-12345.679*/, FP32_ INF(1), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V7(1)} },12526 { /* => */ { FP32_V(1, 0x40e6b6, 0x8c)/*-12345.678*/, FP32_ INF(1), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V7(1)} },12555 { { /*src2 */ { FP32_V(1, 0x40e6b6, 0x8c)/*-12345.678*/, FP32_RAND_x7_V0 } }, 12556 { /*src1 */ { FP32_V(1, 0x40e6b7, 0x8c)/*-12345.679*/, FP32_RAND_x7_V0 } }, 12557 { /* => */ { FP32_V(1, 0x40e6b6, 0x8c)/*-12345.678*/, FP32_RAND_x7_V0 } }, 12527 12558 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 12528 12559 /*128:out */ X86_MXCSR_XCPT_MASK, 12529 12560 /*256:out */ X86_MXCSR_XCPT_MASK, 12530 12561 /*xcpt? */ false, false }, 12531 { { /*src2 */ { FP32_V(0, 0x5dd520, 0x8e)/* 56789.125*/, FP32_RAND_ V6(0), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_QNAN(0), FP32_SNAN(1), FP32_INF(0), FP32_RAND_V3(1)} },12532 { /*src1 */ { FP32_V(1, 0x5dd521, 0x8e)/*-56789.127*/, FP32_RAND_ V7(0), FP32_RAND_V7(0), FP32_RAND_V5(1), FP32_QNAN(0), FP32_QNAN(0), FP32_SNAN(1), FP32_RAND_V2(0)} },12533 { /* => */ { FP32_V(0, 0x5dd520, 0x8e)/* 56789.125*/, FP32_RAND_ V7(0), FP32_RAND_V7(0), FP32_RAND_V5(1), FP32_QNAN(0), FP32_QNAN(0), FP32_SNAN(1), FP32_RAND_V2(0)} },12562 { { /*src2 */ { FP32_V(0, 0x5dd520, 0x8e)/* 56789.125*/, FP32_RAND_x7_V6 } }, 12563 { /*src1 */ { FP32_V(1, 0x5dd521, 0x8e)/*-56789.127*/, FP32_RAND_x7_V4 } }, 12564 { /* => */ { FP32_V(0, 0x5dd520, 0x8e)/* 56789.125*/, FP32_RAND_x7_V4 } }, 12534 12565 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 12535 12566 /*128:out */ X86_MXCSR_XCPT_MASK, 12536 12567 /*256:out */ X86_MXCSR_XCPT_MASK, 12537 12568 /*xcpt? */ false, false }, 12538 { { /*src2 */ { FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_RAND_ V4(0), FP32_RAND_V5(0), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V0(1), FP32_RAND_V2(1), FP32_RAND_V1(1)} },12539 { /*src1 */ { FP32_V(1, 0, 0x7d)/*-0.250*/, FP32_RAND_ V2(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V7(1), FP32_RAND_V5(1), FP32_RAND_V6(0), FP32_RAND_V7(1)} },12540 { /* => */ { FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_RAND_ V2(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V7(1), FP32_RAND_V5(1), FP32_RAND_V6(0), FP32_RAND_V7(1)} },12569 { { /*src2 */ { FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_RAND_x7_V7 } }, 12570 { /*src1 */ { FP32_V(1, 0, 0x7d)/*-0.250*/, FP32_RAND_x7_V1 } }, 12571 { /* => */ { FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_RAND_x7_V1 } }, 12541 12572 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, 12542 12573 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, … … 12547 12578 * Denormals. 12548 12579 */ 12549 /*46*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_ V2(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V2(0), FP32_RAND_V1(1), FP32_RAND_V7(0), FP32_RAND_V2(1)} },12550 { /*src1 */ { FP32_0(0), FP32_RAND_ V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V5(0), FP32_RAND_V6(1), FP32_RAND_V7(0), FP32_RAND_V1(1)} },12551 { /* => */ { FP32_DENORM_MAX(0), FP32_RAND_ V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V5(0), FP32_RAND_V6(1), FP32_RAND_V7(0), FP32_RAND_V1(1)} },12580 /*46*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V2 } }, 12581 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V3 } }, 12582 { /* => */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V3 } }, 12552 12583 /*mxcsr:in */ 0, 12553 12584 /*128:out */ X86_MXCSR_DE, 12554 12585 /*256:out */ X86_MXCSR_DE, 12555 12586 /*xcpt? */ true, true }, 12556 { { /*src2 */ { FP32_0(0), FP32_ SNAN(0), FP32_QNAN(1), FP32_QNAN(0), FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN(0), FP32_QNAN(1)} },12557 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_ V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_QNAN(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V2(0)} },12558 { /* => */ { FP32_DENORM_MAX(0), FP32_RAND_ V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_QNAN(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V2(0)} },12587 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V5 } }, 12588 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V1 } }, 12589 { /* => */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V1 } }, 12559 12590 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 12560 12591 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, 12561 12592 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, 12562 12593 /*xcpt? */ false, false }, 12563 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_ INF(1), FP32_SNAN(0), FP32_INF(1), FP32_RAND_V2(1), FP32_RAND_V5(1), FP32_RAND_V2(1), FP32_RAND_V0(1)} },12564 { /*src1 */ { FP32_DENORM_MAX(0), FP32_ INF(0), FP32_QNAN(1), FP32_SNAN(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V3(0)} },12565 { /* => */ { FP32_0(0), FP32_ INF(0), FP32_QNAN(1), FP32_SNAN(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V3(0)} },12594 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_RAND_x7_V4 } }, 12595 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V3 } }, 12596 { /* => */ { FP32_0(0), FP32_RAND_x7_V3 } }, 12566 12597 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 12567 12598 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 12568 12599 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 12569 12600 /*xcpt? */ false, false }, 12570 { { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_ V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V2(0), FP32_RAND_V1(1), FP32_RAND_V7(0), FP32_RAND_V0(0)} },12571 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_ V3(0), FP32_RAND_V5(0), FP32_RAND_V6(1), FP32_RAND_V7(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V4(1)} },12572 { /* => */ { FP32_DENORM_MAX(0), FP32_RAND_ V3(0), FP32_RAND_V5(0), FP32_RAND_V6(1), FP32_RAND_V7(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V4(1)} },12601 { { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V7 } }, 12602 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V4 } }, 12603 { /* => */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V4 } }, 12573 12604 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 12574 12605 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, 12575 12606 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, 12576 12607 /*xcpt? */ false, false }, 12577 { { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_ V1(1), FP32_RAND_V2(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1)} },12578 { /*src1 */ { FP32_DENORM_MAX(1), FP32_RAND_ V7(0), FP32_RAND_V6(0), FP32_RAND_V7(0), FP32_RAND_V5(0), FP32_RAND_V3(1), FP32_RAND_V3(1), FP32_RAND_V2(1)} },12579 { /* => */ { FP32_DENORM_MAX(0), FP32_RAND_ V7(0), FP32_RAND_V6(0), FP32_RAND_V7(0), FP32_RAND_V5(0), FP32_RAND_V3(1), FP32_RAND_V3(1), FP32_RAND_V2(1)} },12608 { { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V6 } }, 12609 { /*src1 */ { FP32_DENORM_MAX(1), FP32_RAND_x7_V4 } }, 12610 { /* => */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V4 } }, 12580 12611 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 12581 12612 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, 12582 12613 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, 12583 12614 /*xcpt? */ false, false }, 12584 { { /*src2 */ { FP32_DENORM_MAX(1), FP32_RAND_ V3(1), FP32_RAND_V7(0), FP32_RAND_V6(1), FP32_RAND_V2(0), FP32_RAND_V1(0), FP32_RAND_V7(1), FP32_RAND_V2(1)} },12585 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_ V2(1), FP32_RAND_V3(1), FP32_RAND_V5(1), FP32_RAND_V6(1), FP32_RAND_V7(1), FP32_RAND_V2(1), FP32_RAND_V1(1)} },12586 { /* => */ { FP32_DENORM_MAX(0), FP32_RAND_ V2(1), FP32_RAND_V3(1), FP32_RAND_V5(1), FP32_RAND_V6(1), FP32_RAND_V7(1), FP32_RAND_V2(1), FP32_RAND_V1(1)} },12615 { { /*src2 */ { FP32_DENORM_MAX(1), FP32_RAND_x7_V3 } }, 12616 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V2 } }, 12617 { /* => */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V2 } }, 12587 12618 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 12588 12619 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, 12589 12620 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, 12590 12621 /*xcpt? */ false, false }, 12591 { { /*src2 */ { FP32_DENORM_MIN(1), FP32_RAND_ V7(1), FP32_RAND_V6(1), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V1(1)} },12592 { /*src1 */ { FP32_DENORM_MIN(0), FP32_RAND_ V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(0), FP32_RAND_V6(1)} },12593 { /* => */ { FP32_DENORM_MIN(0), FP32_RAND_ V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(0), FP32_RAND_V6(1)} },12622 { { /*src2 */ { FP32_DENORM_MIN(1), FP32_RAND_x7_V7 } }, 12623 { /*src1 */ { FP32_DENORM_MIN(0), FP32_RAND_x7_V2 } }, 12624 { /* => */ { FP32_DENORM_MIN(0), FP32_RAND_x7_V2 } }, 12594 12625 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 12595 12626 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, 12596 12627 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, 12597 12628 /*xcpt? */ false, false }, 12598 { { /*src2 */ { FP32_DENORM_MIN(1), FP32_ INF(0), FP32_QNAN(1), FP32_QNAN(0), FP32_SNAN(1), FP32_SNAN(1), FP32_SNAN(0), FP32_QNAN(1)} },12599 { /*src1 */ { FP32_DENORM_MIN(1), FP32_RAND_ V1(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_QNAN(0), FP32_RAND_V2(0), FP32_RAND_V4(1), FP32_RAND_V7(0)} },12600 { /* => */ { FP32_DENORM_MIN(1), FP32_RAND_ V1(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_QNAN(0), FP32_RAND_V2(0), FP32_RAND_V4(1), FP32_RAND_V7(0)} },12629 { { /*src2 */ { FP32_DENORM_MIN(1), FP32_RAND_x7_V5 } }, 12630 { /*src1 */ { FP32_DENORM_MIN(1), FP32_RAND_x7_V1 } }, 12631 { /* => */ { FP32_DENORM_MIN(1), FP32_RAND_x7_V1 } }, 12601 12632 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 12602 12633 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, 12603 12634 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, 12604 12635 /*xcpt? */ false, false }, 12605 { { /*src2 */ { FP32_DENORM_MIN(1), FP32_ INF(0), FP32_QNAN(1), FP32_QNAN(0), FP32_SNAN(1), FP32_SNAN(1), FP32_SNAN(0), FP32_QNAN(1)} },12606 { /*src1 */ { FP32_DENORM_MIN(1), FP32_RAND_ V1(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_QNAN(0), FP32_RAND_V2(0), FP32_RAND_V4(1), FP32_RAND_V7(0)} },12607 { /* => */ { FP32_0(1), FP32_RAND_ V1(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_QNAN(0), FP32_RAND_V2(0), FP32_RAND_V4(1), FP32_RAND_V7(0)} },12636 { { /*src2 */ { FP32_DENORM_MIN(1), FP32_RAND_x7_V2 } }, 12637 { /*src1 */ { FP32_DENORM_MIN(1), FP32_RAND_x7_V3 } }, 12638 { /* => */ { FP32_0(1), FP32_RAND_x7_V3 } }, 12608 12639 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ, 12609 12640 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ, 12610 12641 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ, 12611 12642 /*xcpt? */ false, false }, 12612 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_RAND_ V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(0), FP32_RAND_V6(1)} },12613 { /*src1 */ { FP32_0(0), FP32_RAND_ V0(0), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(1)} },12614 { /* => */ { FP32_DENORM_MIN(0), FP32_RAND_ V0(0), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(1)} },12643 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_RAND_x7_V0 } }, 12644 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V0 } }, 12645 { /* => */ { FP32_DENORM_MIN(0), FP32_RAND_x7_V0 } }, 12615 12646 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 12616 12647 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, … … 13773 13804 * Zero. 13774 13805 */ 13775 /* 0*/{ { /*src2 */ { FP32_0(0), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },13776 { /*src1 */ { FP32_0(0), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },13777 { /* => */ { FP32_0(0), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },13806 /* 0*/{ { /*src2 */ { FP32_0(0), FP32_0_x7(0) } }, 13807 { /*src1 */ { FP32_0(0), FP32_0_x7(0) } }, 13808 { /* => */ { FP32_0(0), FP32_0_x7(0) } }, 13778 13809 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 13779 13810 /*128:out */ X86_MXCSR_XCPT_MASK, 13780 13811 /*256:out */ X86_MXCSR_XCPT_MASK, 13781 13812 /*xcpt? */ false, false }, 13782 { { /*src2 */ { FP32_0(0), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },13783 { /*src1 */ { FP32_0(0), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },13784 { /* => */ { FP32_0(0), FP32_0 (0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },13813 { { /*src2 */ { FP32_0(0), FP32_0_x7(0) } }, 13814 { /*src1 */ { FP32_0(0), FP32_0_x7(0) } }, 13815 { /* => */ { FP32_0(0), FP32_0_x7(0) } }, 13785 13816 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 13786 13817 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 13787 13818 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 13788 13819 /*xcpt? */ false, false }, 13789 { { /*src2 */ { FP32_0(0), FP32_ INF(0), FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN(1), FP32_QNAN(1), FP32_INF(1), FP32_RAND_V7(0)} },13790 { /*src1 */ { FP32_0(0), FP32_ INF(1), FP32_QNAN(0), FP32_SNAN(1), FP32_QNAN_V(0, 1), FP32_QNAN_V(1, 1), FP32_SNAN(1), FP32_SNAN(0)} },13791 { /* => */ { FP32_0(0), FP32_ INF(1), FP32_QNAN(0), FP32_SNAN(1), FP32_QNAN_V(0, 1), FP32_QNAN_V(1, 1), FP32_SNAN(1), FP32_SNAN(0)} },13820 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V1 } }, 13821 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V1 } }, 13822 { /* => */ { FP32_0(0), FP32_RAND_x7_V1 } }, 13792 13823 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 13793 13824 /*128:out */ X86_MXCSR_XCPT_MASK, 13794 13825 /*256:out */ X86_MXCSR_XCPT_MASK, 13795 13826 /*xcpt? */ false, false }, 13796 { { /*src2 */ { FP32_0(0), FP32_RAND_ V0(0), FP32_RAND_V0(0), FP32_RAND_V0(0), FP32_RAND_V0(0), FP32_RAND_V0(0), FP32_RAND_V0(0), FP32_RAND_V0(0)} },13797 { /*src1 */ { FP32_0(0), FP32_RAND_ V6(0), FP32_RAND_V5(0), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(0), FP32_RAND_V0(0)} },13798 { /* => */ { FP32_0(0), FP32_RAND_ V6(0), FP32_RAND_V5(0), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(0), FP32_RAND_V0(0)} },13827 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V0 } }, 13828 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V6 } }, 13829 { /* => */ { FP32_0(0), FP32_RAND_x7_V6 } }, 13799 13830 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 13800 13831 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 13801 13832 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 13802 13833 /*xcpt? */ false, false }, 13803 { { /*src2 */ { FP32_0(0), FP32_RAND_ V6(0), FP32_RAND_V5(0), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(0), FP32_RAND_V0(0)} },13804 { /*src1 */ { FP32_0(0), FP32_RAND_ V0(1), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(1)} },13805 { /* => */ { FP32_0(0), FP32_RAND_ V0(1), FP32_RAND_V1(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(1)} },13834 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V6 } }, 13835 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V0 } }, 13836 { /* => */ { FP32_0(0), FP32_RAND_x7_V0 } }, 13806 13837 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 13807 13838 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 13808 13839 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 13809 13840 /*xcpt? */ false, false }, 13810 { { /*src2 */ { FP32_0(0), FP32_RAND_ V0(0), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V7(0), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V6(0)} },13811 { /*src1 */ { FP32_0(1), FP32_RAND_ V6(0), FP32_RAND_V5(0), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(0), FP32_RAND_V0(0)} },13812 { /* => */ { FP32_0(0), FP32_RAND_ V6(0), FP32_RAND_V5(0), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V1(0), FP32_RAND_V0(0)} },13841 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V0 } }, 13842 { /*src1 */ { FP32_0(1), FP32_RAND_x7_V6 } }, 13843 { /* => */ { FP32_0(0), FP32_RAND_x7_V6 } }, 13813 13844 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 13814 13845 /*128:out */ X86_MXCSR_XCPT_MASK, 13815 13846 /*256:out */ X86_MXCSR_XCPT_MASK, 13816 13847 /*xcpt? */ false, false }, 13817 { { /*src2 */ { FP32_0(0), FP32_RAND_ V0(1), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V7(0), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V6(0)} },13818 { /*src1 */ { FP32_0(1), FP32_RAND_ V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(0), FP32_RAND_V2(1), FP32_RAND_V1(0), FP32_RAND_V3(1)} },13819 { /* => */ { FP32_0(0), FP32_RAND_ V6(1), FP32_RAND_V5(0), FP32_RAND_V4(1), FP32_RAND_V7(0), FP32_RAND_V2(1), FP32_RAND_V1(0), FP32_RAND_V3(1)} },13848 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V2 } }, 13849 { /*src1 */ { FP32_0(1), FP32_RAND_x7_V3 } }, 13850 { /* => */ { FP32_0(0), FP32_RAND_x7_V3 } }, 13820 13851 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 13821 13852 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 13822 13853 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 13823 13854 /*xcpt? */ false, false }, 13824 { { /*src2 */ { FP32_0(1), FP32_RAND_ V6(1), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V1(1), FP32_RAND_V0(1)} },13825 { /*src1 */ { FP32_0(0), FP32_RAND_ V0(0), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0)} },13826 { /* => */ { FP32_0(1), FP32_RAND_ V0(0), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V7(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0)} },13855 { { /*src2 */ { FP32_0(1), FP32_RAND_x7_V6 } }, 13856 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V0 } }, 13857 { /* => */ { FP32_0(1), FP32_RAND_x7_V0 } }, 13827 13858 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 13828 13859 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 13829 13860 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 13830 13861 /*xcpt? */ false, false }, 13831 { { /*src2 */ { FP32_0(1), FP32_RAND_ V5(1), FP32_RAND_V3(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V0(0)} },13832 { /*src1 */ { FP32_0(0), FP32_RAND_ V0(1), FP32_RAND_V1(1), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V5(1), FP32_RAND_V2(1)} },13833 { /* => */ { FP32_0(1), FP32_RAND_ V0(1), FP32_RAND_V1(1), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V5(1), FP32_RAND_V2(1)} },13862 { { /*src2 */ { FP32_0(1), FP32_RAND_x7_V5 } }, 13863 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V0 } }, 13864 { /* => */ { FP32_0(1), FP32_RAND_x7_V0 } }, 13834 13865 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 13835 13866 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 13836 13867 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 13837 13868 /*xcpt? */ false, false }, 13838 { { /*src2 */ { FP32_0(1), FP32_RAND_ V6(1), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V1(1), FP32_RAND_V0(1)} },13839 { /*src1 */ { FP32_0(1), FP32_RAND_ V0(1), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V7(0), FP32_RAND_V3(0), FP32_RAND_V6(1), FP32_RAND_V4(1)} },13840 { /* => */ { FP32_0(1), FP32_RAND_ V0(1), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V7(0), FP32_RAND_V3(0), FP32_RAND_V6(1), FP32_RAND_V4(1)} },13869 { { /*src2 */ { FP32_0(1), FP32_RAND_x7_V6 } }, 13870 { /*src1 */ { FP32_0(1), FP32_RAND_x7_V3 } }, 13871 { /* => */ { FP32_0(1), FP32_RAND_x7_V3 } }, 13841 13872 /*mxcsr:in */ 0, 13842 13873 /*128:out */ 0, 13843 13874 /*256:out */ 0, 13844 13875 /*xcpt? */ false, false }, 13845 { { /*src2 */ { FP32_0(1), FP32_RAND_ V6(1), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V1(1), FP32_RAND_V0(1)} },13846 { /*src1 */ { FP32_0(1), FP32_RAND_ V1(0), FP32_RAND_V5(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V3(0), FP32_RAND_V1(0), FP32_RAND_V6(1)} },13847 { /* => */ { FP32_0(1), FP32_RAND_ V1(0), FP32_RAND_V5(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V3(0), FP32_RAND_V1(0), FP32_RAND_V6(1)} },13876 { { /*src2 */ { FP32_0(1), FP32_RAND_x7_V4 } }, 13877 { /*src1 */ { FP32_0(1), FP32_RAND_x7_V7 } }, 13878 { /* => */ { FP32_0(1), FP32_RAND_x7_V7 } }, 13848 13879 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 13849 13880 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP, … … 13853 13884 * Infinity. 13854 13885 */ 13855 /*11*/{ { /*src2 */ { FP32_INF(0), FP32_RAND_ V6(1), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V1(1), FP32_RAND_V0(1)} },13856 { /*src1 */ { FP32_0(0), FP32_RAND_ V1(0), FP32_RAND_V5(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V3(0), FP32_RAND_V1(0), FP32_RAND_V6(1)} },13857 { /* => */ { FP32_0(0), FP32_RAND_ V1(0), FP32_RAND_V5(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V3(0), FP32_RAND_V1(0), FP32_RAND_V6(1)} },13886 /*11*/{ { /*src2 */ { FP32_INF(0), FP32_RAND_x7_V2 } }, 13887 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V7 } }, 13888 { /* => */ { FP32_0(0), FP32_RAND_x7_V7 } }, 13858 13889 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 13859 13890 /*128:out */ X86_MXCSR_XCPT_MASK, 13860 13891 /*256:out */ X86_MXCSR_XCPT_MASK, 13861 13892 /*xcpt? */ false, false }, 13862 { { /*src2 */ { FP32_0(0), FP32_RAND_ V5(1), FP32_RAND_V5(1), FP32_RAND_V6(1), FP32_RAND_V3(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V0(1)} },13863 { /*src1 */ { FP32_INF(0), FP32_RAND_ V3(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V5(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V7(1)} },13864 { /* => */ { FP32_0(0), FP32_RAND_ V3(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V5(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V7(1)} },13893 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V2 } }, 13894 { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V6 } }, 13895 { /* => */ { FP32_0(0), FP32_RAND_x7_V6 } }, 13865 13896 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, 13866 13897 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, 13867 13898 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, 13868 13899 /*xcpt? */ false, false }, 13869 { { /*src2 */ { FP32_INF(0), FP32_ INF(1), FP32_SNAN(1), FP32_QNAN(1), FP32_RAND_V3(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V0(1)} },13870 { /*src1 */ { FP32_0(0), FP32_RAND_ V3(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_QNAN(0), FP32_RAND_V2(0), FP32_RAND_V4(1), FP32_RAND_V7(0)} },13871 { /* => */ { FP32_0(0), FP32_RAND_ V3(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_QNAN(0), FP32_RAND_V2(0), FP32_RAND_V4(1), FP32_RAND_V7(0)} },13900 { { /*src2 */ { FP32_INF(0), FP32_RAND_x7_V2 } }, 13901 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V4 } }, 13902 { /* => */ { FP32_0(0), FP32_RAND_x7_V4 } }, 13872 13903 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 13873 13904 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 13874 13905 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 13875 13906 /*xcpt? */ false, false }, 13876 { { /*src2 */ { FP32_0(0), FP32_RAND_ V2(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V7(0), FP32_RAND_V1(0)} },13877 { /*src1 */ { FP32_INF(1), FP32_RAND_ V0(0), FP32_RAND_V1(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0), FP32_RAND_V2(1), FP32_RAND_V2(1)} },13878 { /* => */ { FP32_INF(1), FP32_RAND_ V0(0), FP32_RAND_V1(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0), FP32_RAND_V2(1), FP32_RAND_V2(1)} },13907 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V2 } }, 13908 { /*src1 */ { FP32_INF(1), FP32_RAND_x7_V0 } }, 13909 { /* => */ { FP32_INF(1), FP32_RAND_x7_V0 } }, 13879 13910 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 13880 13911 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 13881 13912 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 13882 13913 /*xcpt? */ false, false }, 13883 { { /*src2 */ { FP32_INF(0), FP32_RAND_ V3(1), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(1)} },13884 { /*src1 */ { FP32_INF(0), FP32_RAND_ V1(0), FP32_RAND_V2(1), FP32_RAND_V5(1), FP32_RAND_V6(0), FP32_SNAN(0), FP32_SNAN(1), FP32_RAND_V2(1)} },13885 { /* => */ { FP32_INF(0), FP32_RAND_ V1(0), FP32_RAND_V2(1), FP32_RAND_V5(1), FP32_RAND_V6(0), FP32_SNAN(0), FP32_SNAN(1), FP32_RAND_V2(1)} },13914 { { /*src2 */ { FP32_INF(0), FP32_RAND_x7_V3 } }, 13915 { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V7 } }, 13916 { /* => */ { FP32_INF(0), FP32_RAND_x7_V7 } }, 13886 13917 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 13887 13918 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 13888 13919 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 13889 13920 /*xcpt? */ false, false }, 13890 { { /*src2 */ { FP32_INF(0), FP32_RAND_ V2(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V7(1), FP32_RAND_V0(1)} },13891 { /*src1 */ { FP32_INF(0), FP32_RAND_ V0(1), FP32_RAND_V0(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_SNAN(1), FP32_QNAN_V(1, 1), FP32_RAND_V3(1)} },13892 { /* => */ { FP32_INF(0), FP32_RAND_ V0(1), FP32_RAND_V0(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_SNAN(1), FP32_QNAN_V(1, 1), FP32_RAND_V3(1)} },13921 { { /*src2 */ { FP32_INF(0), FP32_RAND_x7_V3 } }, 13922 { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V6 } }, 13923 { /* => */ { FP32_INF(0), FP32_RAND_x7_V6 } }, 13893 13924 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 13894 13925 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 13895 13926 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 13896 13927 /*xcpt? */ false, false }, 13897 { { /*src2 */ { FP32_INF(1), FP32_RAND_ V3(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V7(1), FP32_RAND_V0(0)} },13898 { /*src1 */ { FP32_INF(1), FP32_ QNAN_V(1, 1), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_QNAN_V(1, 0), FP32_RAND_V1(0)} },13899 { /* => */ { FP32_INF(1), FP32_ QNAN_V(1, 1), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_QNAN_V(1, 0), FP32_RAND_V1(0)} },13928 { { /*src2 */ { FP32_INF(1), FP32_RAND_x7_V3 } }, 13929 { /*src1 */ { FP32_INF(1), FP32_RAND_x7_V5 } }, 13930 { /* => */ { FP32_INF(1), FP32_RAND_x7_V5 } }, 13900 13931 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 13901 13932 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 13902 13933 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 13903 13934 /*xcpt? */ false, false }, 13904 { { /*src2 */ { FP32_INF(1), FP32_RAND_ V2(1), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V1(1), FP32_RAND_V0(1)} },13905 { /*src1 */ { FP32_INF(1), FP32_RAND_ V0(0), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V2(0), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V5(1)} },13906 { /* => */ { FP32_INF(1), FP32_RAND_ V0(0), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V2(0), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V5(1)} },13935 { { /*src2 */ { FP32_INF(1), FP32_RAND_x7_V3 } }, 13936 { /*src1 */ { FP32_INF(1), FP32_RAND_x7_V0 } }, 13937 { /* => */ { FP32_INF(1), FP32_RAND_x7_V0 } }, 13907 13938 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 13908 13939 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 13909 13940 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 13910 13941 /*xcpt? */ false, false }, 13911 { { /*src2 */ { FP32_INF(1), FP32_RAND_ V1(1), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V1(0), FP32_RAND_V1(1)} },13912 { /*src1 */ { FP32_INF(0), FP32_RAND_ V1(0), FP32_RAND_V2(1), FP32_RAND_V5(1), FP32_RAND_V6(0), FP32_RAND_V7(0), FP32_RAND_V2(0), FP32_RAND_V3(1)} },13913 { /* => */ { FP32_INF(1), FP32_RAND_ V1(0), FP32_RAND_V2(1), FP32_RAND_V5(1), FP32_RAND_V6(0), FP32_RAND_V7(0), FP32_RAND_V2(0), FP32_RAND_V3(1)} },13942 { { /*src2 */ { FP32_INF(1), FP32_RAND_x7_V3 } }, 13943 { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V1 } }, 13944 { /* => */ { FP32_INF(1), FP32_RAND_x7_V1 } }, 13914 13945 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, 13915 13946 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, 13916 13947 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, 13917 13948 /*xcpt? */ false, false }, 13918 { { /*src2 */ { FP32_INF(1), FP32_RAND_ V0(1), FP32_RAND_V2(1), FP32_RAND_V4(1), FP32_RAND_V2(1), FP32_RAND_V5(1), FP32_RAND_V2(1), FP32_RAND_V1(1)} },13919 { /*src1 */ { FP32_INF(0), FP32_RAND_ V0(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V6(1), FP32_RAND_V7(0), FP32_RAND_V4(1)} },13920 { /* => */ { FP32_INF(1), FP32_RAND_ V0(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V6(1), FP32_RAND_V7(0), FP32_RAND_V4(1)} },13949 { { /*src2 */ { FP32_INF(1), FP32_RAND_x7_V1 } }, 13950 { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V1 } }, 13951 { /* => */ { FP32_INF(1), FP32_RAND_x7_V1 } }, 13921 13952 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 13922 13953 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 13923 13954 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 13924 13955 /*xcpt? */ false, false }, 13925 { { /*src2 */ { FP32_INF(0), FP32_RAND_ V2(1), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V6(1), FP32_RAND_V1(1), FP32_RAND_V7(1), FP32_RAND_V2(0)} },13926 { /*src1 */ { FP32_INF(1), FP32_RAND_ V2(0), FP32_RAND_V3(0), FP32_RAND_V1(1), FP32_RAND_V0(1), FP32_RAND_V5(1), FP32_RAND_V7(0), FP32_RAND_V1(0)} },13927 { /* => */ { FP32_INF(1), FP32_RAND_ V2(0), FP32_RAND_V3(0), FP32_RAND_V1(1), FP32_RAND_V0(1), FP32_RAND_V5(1), FP32_RAND_V7(0), FP32_RAND_V1(0)} },13956 { { /*src2 */ { FP32_INF(0), FP32_RAND_x7_V0 } }, 13957 { /*src1 */ { FP32_INF(1), FP32_RAND_x7_V1 } }, 13958 { /* => */ { FP32_INF(1), FP32_RAND_x7_V1 } }, 13928 13959 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 13929 13960 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 13930 13961 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 13931 13962 /*xcpt? */ false, false }, 13932 { { /*src2 */ { FP32_INF(0), FP32_RAND_ V0(1), FP32_RAND_V2(1), FP32_RAND_V4(1), FP32_RAND_V2(1), FP32_RAND_V5(1), FP32_RAND_V2(1), FP32_RAND_V1(1)} },13933 { /*src1 */ { FP32_INF(1), FP32_RAND_ V0(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V6(1), FP32_RAND_V7(0), FP32_RAND_V4(1)} },13934 { /* => */ { FP32_INF(1), FP32_RAND_ V0(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V6(1), FP32_RAND_V7(0), FP32_RAND_V4(1)} },13963 { { /*src2 */ { FP32_INF(0), FP32_RAND_x7_V1 } }, 13964 { /*src1 */ { FP32_INF(1), FP32_RAND_x7_V5 } }, 13965 { /* => */ { FP32_INF(1), FP32_RAND_x7_V5 } }, 13935 13966 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, 13936 13967 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, 13937 13968 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ, 13938 13969 /*xcpt? */ false, false }, 13939 { { /*src2 */ { FP32_INF(0), FP32_RAND_ V0(0), FP32_RAND_V2(1), FP32_RAND_V4(1), FP32_RAND_V2(1), FP32_RAND_V5(1), FP32_RAND_V2(1), FP32_RAND_V1(0)} },13940 { /*src1 */ { FP32_NORM_V0(0), FP32_RAND_ V1(1), FP32_RAND_V3(1), FP32_RAND_V5(1), FP32_RAND_V7(0), FP32_RAND_V6(1), FP32_RAND_V2(1), FP32_RAND_V4(0)} },13941 { /* => */ { FP32_NORM_V0(0), FP32_RAND_ V1(1), FP32_RAND_V3(1), FP32_RAND_V5(1), FP32_RAND_V7(0), FP32_RAND_V6(1), FP32_RAND_V2(1), FP32_RAND_V4(0)} },13970 { { /*src2 */ { FP32_INF(0), FP32_RAND_x7_V0 } }, 13971 { /*src1 */ { FP32_NORM_V0(0), FP32_RAND_x7_V4 } }, 13972 { /* => */ { FP32_NORM_V0(0), FP32_RAND_x7_V4 } }, 13942 13973 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 13943 13974 /*128:out */ X86_MXCSR_XCPT_MASK, 13944 13975 /*256:out */ X86_MXCSR_XCPT_MASK, 13945 13976 /*xcpt? */ false, false }, 13946 { { /*src2 */ { FP32_INF(0), FP32_ INF(0), FP32_SNAN(1), FP32_INF(1), FP32_RAND_V3(1), FP32_RAND_V6(1), FP32_RAND_V3(1), FP32_RAND_V4(0)} },13947 { /*src1 */ { FP32_NORM_V3(0), FP32_ INF(1), FP32_QNAN(1), FP32_SNAN(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V2(1), FP32_RAND_V1(1)} },13948 { /* => */ { FP32_NORM_V3(0), FP32_ INF(1), FP32_QNAN(1), FP32_SNAN(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V2(1), FP32_RAND_V1(1)} },13977 { { /*src2 */ { FP32_INF(0), FP32_RAND_x7_V0 } }, 13978 { /*src1 */ { FP32_NORM_V3(0), FP32_RAND_x7_V3 } }, 13979 { /* => */ { FP32_NORM_V3(0), FP32_RAND_x7_V3 } }, 13949 13980 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 13950 13981 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 13951 13982 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 13952 13983 /*xcpt? */ false, false }, 13953 { { /*src2 */ { FP32_NORM_V7(0), FP32_RAND_ V6(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_INF(1), FP32_SNAN(0), FP32_INF(0), FP32_RAND_V2(0)} },13954 { /*src1 */ { FP32_INF(1), FP32_RAND_ V2(1), FP32_RAND_V2(1), FP32_RAND_V1(1), FP32_INF(1), FP32_QNAN(1), FP32_SNAN(1), FP32_RAND_V3(0)} },13955 { /* => */ { FP32_INF(1), FP32_RAND_ V2(1), FP32_RAND_V2(1), FP32_RAND_V1(1), FP32_INF(1), FP32_QNAN(1), FP32_SNAN(1), FP32_RAND_V3(0)} },13984 { { /*src2 */ { FP32_NORM_V7(0), FP32_RAND_x7_V2 } }, 13985 { /*src1 */ { FP32_INF(1), FP32_RAND_x7_V3 } }, 13986 { /* => */ { FP32_INF(1), FP32_RAND_x7_V3 } }, 13956 13987 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 13957 13988 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 13958 13989 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 13959 13990 /*xcpt? */ false, false }, 13960 { { /*src2 */ { FP32_NORM_V7(0), FP32_RAND_ V6(0), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_QNAN(1), FP32_SNAN(0), FP32_INF(1), FP32_RAND_V2(1)} },13961 { /*src1 */ { FP32_INF(0), FP32_RAND_ V7(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_QNAN(1), FP32_QNAN(1), FP32_SNAN(0), FP32_RAND_V3(1)} },13962 { /* => */ { FP32_NORM_V7(0), FP32_RAND_ V7(0), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_QNAN(1), FP32_QNAN(1), FP32_SNAN(0), FP32_RAND_V3(1)} },13991 { { /*src2 */ { FP32_NORM_V7(0), FP32_RAND_x7_V5 } }, 13992 { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V5 } }, 13993 { /* => */ { FP32_NORM_V7(0), FP32_RAND_x7_V5 } }, 13963 13994 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 13964 13995 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, … … 13968 13999 * Normals. 13969 14000 */ 13970 /*27*/{ { /*src2 */ { FP32_NORM_MAX(0), FP32_RAND_ V2(1), FP32_RAND_V0(1), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V1(1)} },13971 { /*src1 */ { FP32_NORM_MAX(0), FP32_RAND_ V3(1), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V6(0), FP32_RAND_V7(0), FP32_RAND_V3(1), FP32_RAND_V1(1)} },13972 { /* => */ { FP32_NORM_MAX(0), FP32_RAND_ V3(1), FP32_RAND_V2(0), FP32_RAND_V5(1), FP32_RAND_V6(0), FP32_RAND_V7(0), FP32_RAND_V3(1), FP32_RAND_V1(1)} },14001 /*27*/{ { /*src2 */ { FP32_NORM_MAX(0), FP32_RAND_x7_V2 } }, 14002 { /*src1 */ { FP32_NORM_MAX(0), FP32_RAND_x7_V1 } }, 14003 { /* => */ { FP32_NORM_MAX(0), FP32_RAND_x7_V1 } }, 13973 14004 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 13974 14005 /*128:out */ X86_MXCSR_XCPT_MASK, 13975 14006 /*256:out */ X86_MXCSR_XCPT_MASK, 13976 14007 /*xcpt? */ false, false }, 13977 { { /*src2 */ { FP32_NORM_MIN(0), FP32_RAND_ V3(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V7(0), FP32_RAND_V1(1)} },13978 { /*src1 */ { FP32_NORM_MIN(0), FP32_RAND_ V2(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V2(0), FP32_RAND_V1(1), FP32_RAND_V0(1), FP32_RAND_V7(0)} },13979 { /* => */ { FP32_NORM_MIN(0), FP32_RAND_ V2(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V2(0), FP32_RAND_V1(1), FP32_RAND_V0(1), FP32_RAND_V7(0)} },14008 { { /*src2 */ { FP32_NORM_MIN(0), FP32_RAND_x7_V3 } }, 14009 { /*src1 */ { FP32_NORM_MIN(0), FP32_RAND_x7_V2 } }, 14010 { /* => */ { FP32_NORM_MIN(0), FP32_RAND_x7_V2 } }, 13980 14011 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 13981 14012 /*128:out */ X86_MXCSR_XCPT_MASK, 13982 14013 /*256:out */ X86_MXCSR_XCPT_MASK, 13983 14014 /*xcpt? */ false, false }, 13984 { { /*src2 */ { FP32_NORM_MIN(0), FP32_RAND_ V3(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V2(0), FP32_RAND_V1(1), FP32_RAND_V7(0), FP32_RAND_V2(1)} },13985 { /*src1 */ { FP32_NORM_MAX(0), FP32_RAND_ V1(0), FP32_RAND_V6(0), FP32_RAND_V4(0), FP32_RAND_V4(0), FP32_RAND_V3(1), FP32_RAND_V6(0), FP32_RAND_V4(1)} },13986 { /* => */ { FP32_NORM_MIN(0), FP32_RAND_ V1(0), FP32_RAND_V6(0), FP32_RAND_V4(0), FP32_RAND_V4(0), FP32_RAND_V3(1), FP32_RAND_V6(0), FP32_RAND_V4(1)} },14015 { { /*src2 */ { FP32_NORM_MIN(0), FP32_RAND_x7_V3 } }, 14016 { /*src1 */ { FP32_NORM_MAX(0), FP32_RAND_x7_V1 } }, 14017 { /* => */ { FP32_NORM_MIN(0), FP32_RAND_x7_V1 } }, 13987 14018 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 13988 14019 /*128:out */ X86_MXCSR_XCPT_MASK, 13989 14020 /*256:out */ X86_MXCSR_XCPT_MASK, 13990 14021 /*xcpt? */ false, false }, 13991 { { /*src2 */ { FP32_NORM_MAX(0), FP32_RAND_ V2(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V7(0), FP32_RAND_V1(0)} },13992 { /*src1 */ { FP32_NORM_MAX(0), FP32_RAND_ V0(0), FP32_RAND_V1(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0), FP32_RAND_V2(1), FP32_RAND_V2(1)} },13993 { /* => */ { FP32_NORM_MAX(0), FP32_RAND_ V0(0), FP32_RAND_V1(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0), FP32_RAND_V2(1), FP32_RAND_V2(1)} },14022 { { /*src2 */ { FP32_NORM_MAX(0), FP32_RAND_x7_V2 } }, 14023 { /*src1 */ { FP32_NORM_MAX(0), FP32_RAND_x7_V0 } }, 14024 { /* => */ { FP32_NORM_MAX(0), FP32_RAND_x7_V0 } }, 13994 14025 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 13995 14026 /*128:out */ X86_MXCSR_XCPT_MASK, 13996 14027 /*256:out */ X86_MXCSR_XCPT_MASK, 13997 14028 /*xcpt? */ false, false }, 13998 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_ V2(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V7(0), FP32_RAND_V1(1)} },13999 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_ V1(0), FP32_RAND_V4(0), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V0(0), FP32_RAND_V1(1)} },14000 { /* => */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_ V1(0), FP32_RAND_V4(0), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V0(1), FP32_RAND_V0(0), FP32_RAND_V1(1)} },14029 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_x7_V2 } }, 14030 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V5 } }, 14031 { /* => */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_x7_V5 } }, 14001 14032 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 14002 14033 /*128:out */ X86_MXCSR_XCPT_MASK, 14003 14034 /*256:out */ X86_MXCSR_XCPT_MASK, 14004 14035 /*xcpt? */ false, false }, 14005 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_ V6(0), FP32_RAND_V5(0), FP32_RAND_V6(1), FP32_RAND_V4(0), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V1(1)} },14006 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_ V1(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V5(0), FP32_RAND_V6(0), FP32_RAND_V7(0), FP32_RAND_V2(1)} },14007 { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_ V1(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V5(0), FP32_RAND_V6(0), FP32_RAND_V7(0), FP32_RAND_V2(1)} },14036 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V6 } }, 14037 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V1 } }, 14038 { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V1 } }, 14008 14039 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 14009 14040 /*128:out */ X86_MXCSR_XCPT_MASK, 14010 14041 /*256:out */ X86_MXCSR_XCPT_MASK, 14011 14042 /*xcpt? */ false, false }, 14012 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_ INF(0), FP32_QNAN(1), FP32_QNAN(0), FP32_SNAN(1), FP32_SNAN(1), FP32_SNAN(0), FP32_QNAN(1)} },14013 { /*src1 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_ V1(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_QNAN(0), FP32_RAND_V2(0), FP32_RAND_V4(1), FP32_RAND_V7(0)} },14014 { /* => */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_ V1(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_QNAN(0), FP32_RAND_V2(0), FP32_RAND_V4(1), FP32_RAND_V7(0)} },14043 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V6 } }, 14044 { /*src1 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_x7_V3 } }, 14045 { /* => */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_x7_V3 } }, 14015 14046 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 14016 14047 /*128:out */ X86_MXCSR_XCPT_MASK, 14017 14048 /*256:out */ X86_MXCSR_XCPT_MASK, 14018 14049 /*xcpt? */ false, false }, 14019 { { /*src2 */ { FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_RAND_ V1(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(1), FP32_RAND_V7(1)} },14020 { /*src1 */ { FP32_V(1, 0, 0x7d)/*-0.25*/, FP32_RAND_ V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1), FP32_RAND_V7(1)} },14021 { /* => */ { FP32_V(1, 0, 0x7d)/*-0.25*/, FP32_RAND_ V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(1), FP32_RAND_V7(1)} },14050 { { /*src2 */ { FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_RAND_x7_V1 } }, 14051 { /*src1 */ { FP32_V(1, 0, 0x7d)/*-0.25*/, FP32_RAND_x7_V1 } }, 14052 { /* => */ { FP32_V(1, 0, 0x7d)/*-0.25*/, FP32_RAND_x7_V1 } }, 14022 14053 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 14023 14054 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 14024 14055 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 14025 14056 /*xcpt? */ false, false }, 14026 { { /*src2 */ { FP32_V(0, 0, 0x7d)/*0.25*/, FP32_RAND_ V2(1), FP32_RAND_V5(0), FP32_RAND_V6(1), FP32_RAND_V4(0), FP32_RAND_V3(1), FP32_RAND_V7(0), FP32_RAND_V1(1)} },14027 { /*src1 */ { FP32_V(0, 0, 0x7e)/*0.50*/, FP32_RAND_ V0(0), FP32_RAND_V5(0), FP32_RAND_V7(0), FP32_RAND_V2(1), FP32_SNAN(1), FP32_SNAN(0), FP32_RAND_V3(0)} },14028 { /* => */ { FP32_V(0, 0, 0x7d)/*0.25*/, FP32_RAND_ V0(0), FP32_RAND_V5(0), FP32_RAND_V7(0), FP32_RAND_V2(1), FP32_SNAN(1), FP32_SNAN(0), FP32_RAND_V3(0)} },14057 { { /*src2 */ { FP32_V(0, 0, 0x7d)/*0.25*/, FP32_RAND_x7_V2 } }, 14058 { /*src1 */ { FP32_V(0, 0, 0x7e)/*0.50*/, FP32_RAND_x7_V1 } }, 14059 { /* => */ { FP32_V(0, 0, 0x7d)/*0.25*/, FP32_RAND_x7_V1 } }, 14029 14060 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 14030 14061 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 14031 14062 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 14032 14063 /*xcpt? */ false, false }, 14033 { { /*src2 */ { FP32_NORM_MAX(0), FP32_RAND_ V0(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(1), FP32_RAND_V7(1)} },14034 { /*src1 */ { FP32_NORM_V1(0), FP32_RAND_ V0(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(0), FP32_RAND_V6(0), FP32_RAND_V7(0)} },14035 { /* => */ { FP32_NORM_V1(0), FP32_RAND_ V0(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(0), FP32_RAND_V6(0), FP32_RAND_V7(0)} },14064 { { /*src2 */ { FP32_NORM_MAX(0), FP32_RAND_x7_V0 } }, 14065 { /*src1 */ { FP32_NORM_V1(0), FP32_RAND_x7_V0 } }, 14066 { /* => */ { FP32_NORM_V1(0), FP32_RAND_x7_V0 } }, 14036 14067 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 14037 14068 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 14038 14069 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN, 14039 14070 /*xcpt? */ false, false }, 14040 { { /*src2 */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_RAND_ V3(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V4(0), FP32_RAND_V7(0), FP32_RAND_V6(0)} },14041 { /*src1 */ { FP32_V(0, 0x1ea980, 0x8f)/* 81235*/, FP32_RAND_ V0(0), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V3(1)} },14042 { /* => */ { FP32_V(0, 0x1ea980, 0x8f)/* 81235*/, FP32_RAND_ V0(0), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V3(1)} },14071 { { /*src2 */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_RAND_x7_V3 } }, 14072 { /*src1 */ { FP32_V(0, 0x1ea980, 0x8f)/* 81235*/, FP32_RAND_x7_V0 } }, 14073 { /* => */ { FP32_V(0, 0x1ea980, 0x8f)/* 81235*/, FP32_RAND_x7_V0 } }, 14043 14074 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 14044 14075 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 14045 14076 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 14046 14077 /*xcpt? */ false, false }, 14047 { { /*src2 */ { FP32_V(1, 0x2514d6, 0x93)/*-1352346.75*/, FP32_RAND_ V2(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V7(0), FP32_RAND_V1(0)} },14048 { /*src1 */ { FP32_V(0, 0x7c9000, 0x88)/* 1010.25*/, FP32_RAND_ V0(0), FP32_RAND_V1(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0), FP32_RAND_V2(1), FP32_RAND_V2(1)} },14049 { /* => */ { FP32_V(1, 0x2514d6, 0x93)/*-1352346.75*/, FP32_RAND_ V0(0), FP32_RAND_V1(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(0), FP32_RAND_V2(1), FP32_RAND_V2(1)} },14078 { { /*src2 */ { FP32_V(1, 0x2514d6, 0x93)/*-1352346.75*/, FP32_RAND_x7_V2 } }, 14079 { /*src1 */ { FP32_V(0, 0x7c9000, 0x88)/* 1010.25*/, FP32_RAND_x7_V0 } }, 14080 { /* => */ { FP32_V(1, 0x2514d6, 0x93)/*-1352346.75*/, FP32_RAND_x7_V0 } }, 14050 14081 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 14051 14082 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 14052 14083 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 14053 14084 /*xcpt? */ false, false }, 14054 { { /*src2 */ { FP32_V(1, 0x2514d6, 0x93)/*-1352346.75*/, FP32_RAND_ V2(1), FP32_RAND_V3(1), FP32_RAND_V6(1), FP32_RAND_V3(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V0(1)} },14055 { /*src1 */ { FP32_V(0, 0x253468, 0x93)/* 1353357.00*/, FP32_RAND_ V3(0), FP32_RAND_V1(0), FP32_RAND_V0(1), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V4(1)} },14056 { /* => */ { FP32_V(1, 0x2514d6, 0x93)/*-1352346.75*/, FP32_RAND_ V3(0), FP32_RAND_V1(0), FP32_RAND_V0(1), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V4(1)} },14085 { { /*src2 */ { FP32_V(1, 0x2514d6, 0x93)/*-1352346.75*/, FP32_RAND_x7_V2 } }, 14086 { /*src1 */ { FP32_V(0, 0x253468, 0x93)/* 1353357.00*/, FP32_RAND_x7_V3 } }, 14087 { /* => */ { FP32_V(1, 0x2514d6, 0x93)/*-1352346.75*/, FP32_RAND_x7_V3 } }, 14057 14088 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 14058 14089 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 14059 14090 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 14060 14091 /*xcpt? */ false, false }, 14061 { { /*src2 */ { FP32_V(1, 0x40e6b6, 0x8c)/*-12345.678*/, FP32_RAND_ V3(1), FP32_RAND_V5(1), FP32_RAND_V6(1), FP32_RAND_V3(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V0(1)} },14062 { /*src1 */ { FP32_V(1, 0x40e6b7, 0x8c)/*-12345.679*/, FP32_RAND_ V1(1), FP32_RAND_V0(0), FP32_RAND_V0(1), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V4(0), FP32_RAND_V4(1)} },14063 { /* => */ { FP32_V(1, 0x40e6b7, 0x8c)/*-12345.679*/, FP32_RAND_ V1(1), FP32_RAND_V0(0), FP32_RAND_V0(1), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V4(0), FP32_RAND_V4(1)} },14092 { { /*src2 */ { FP32_V(1, 0x40e6b6, 0x8c)/*-12345.678*/, FP32_RAND_x7_V4 } }, 14093 { /*src1 */ { FP32_V(1, 0x40e6b7, 0x8c)/*-12345.679*/, FP32_RAND_x7_V6 } }, 14094 { /* => */ { FP32_V(1, 0x40e6b7, 0x8c)/*-12345.679*/, FP32_RAND_x7_V6 } }, 14064 14095 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 14065 14096 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 14066 14097 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 14067 14098 /*xcpt? */ false, false }, 14068 { { /*src2 */ { FP32_V(0, 0x620b2e, 0x92)/*925874.9*/, FP32_RAND_ V5(1), FP32_RAND_V5(1), FP32_RAND_V6(1), FP32_RAND_V3(1), FP32_RAND_V3(1), FP32_RAND_V3(1), FP32_RAND_V1(1)} },14069 { /*src1 */ { FP32_V(0, 0x620b2d, 0x92)/*925874.8*/, FP32_RAND_ V3(0), FP32_RAND_V6(1), FP32_RAND_V0(1), FP32_RAND_V6(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V2(1)} },14070 { /* => */ { FP32_V(0, 0x620b2d, 0x92)/*925874.8*/, FP32_RAND_ V3(0), FP32_RAND_V6(1), FP32_RAND_V0(1), FP32_RAND_V6(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V2(1)} },14099 { { /*src2 */ { FP32_V(0, 0x620b2e, 0x92)/*925874.9*/, FP32_RAND_x7_V5 } }, 14100 { /*src1 */ { FP32_V(0, 0x620b2d, 0x92)/*925874.8*/, FP32_RAND_x7_V0 } }, 14101 { /* => */ { FP32_V(0, 0x620b2d, 0x92)/*925874.8*/, FP32_RAND_x7_V0 } }, 14071 14102 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 14072 14103 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 14073 14104 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 14074 14105 /*xcpt? */ false, false }, 14075 { { /*src2 */ { FP32_V(0, 0x490fda, 0x80)/*3.1415926*/, FP32_RAND_ V6(1), FP32_RAND_V2(1), FP32_RAND_V4(1), FP32_RAND_V2(1), FP32_RAND_V5(1), FP32_RAND_V2(1), FP32_RAND_V1(1)} },14076 { /*src1 */ { FP32_V(0, 0x490fdb, 0x80)/*3.1415927*/, FP32_RAND_ V6(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V3(0), FP32_RAND_V7(0), FP32_RAND_V1(0), FP32_RAND_V1(1)} },14077 { /* => */ { FP32_V(0, 0x490fda, 0x80)/*3.1415926*/, FP32_RAND_ V6(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V3(0), FP32_RAND_V7(0), FP32_RAND_V1(0), FP32_RAND_V1(1)} },14106 { { /*src2 */ { FP32_V(0, 0x490fda, 0x80)/*3.1415926*/, FP32_RAND_x7_V6 } }, 14107 { /*src1 */ { FP32_V(0, 0x490fdb, 0x80)/*3.1415927*/, FP32_RAND_x7_V0 } }, 14108 { /* => */ { FP32_V(0, 0x490fda, 0x80)/*3.1415926*/, FP32_RAND_x7_V0 } }, 14078 14109 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 14079 14110 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 14080 14111 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, 14081 14112 /*xcpt? */ false, false }, 14082 { { /*src2 */ { FP32_V(1, 0x40e6b6, 0x8c)/*-12345.678*/, FP32_ INF(1), FP32_SNAN(1), FP32_INF(1), FP32_RAND_V2(1), FP32_RAND_V7(1), FP32_RAND_V3(1), FP32_RAND_V6(1)} },14083 { /*src1 */ { FP32_V(1, 0x40e6b7, 0x8c)/*-12345.679*/, FP32_ INF(1), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V7(1)} },14084 { /* => */ { FP32_V(1, 0x40e6b7, 0x8c)/*-12345.679*/, FP32_ INF(1), FP32_QNAN(0), FP32_SNAN(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V7(1)} },14113 { { /*src2 */ { FP32_V(1, 0x40e6b6, 0x8c)/*-12345.678*/, FP32_RAND_x7_V5 } }, 14114 { /*src1 */ { FP32_V(1, 0x40e6b7, 0x8c)/*-12345.679*/, FP32_RAND_x7_V0 } }, 14115 { /* => */ { FP32_V(1, 0x40e6b7, 0x8c)/*-12345.679*/, FP32_RAND_x7_V0 } }, 14085 14116 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 14086 14117 /*128:out */ X86_MXCSR_XCPT_MASK, 14087 14118 /*256:out */ X86_MXCSR_XCPT_MASK, 14088 14119 /*xcpt? */ false, false }, 14089 { { /*src2 */ { FP32_V(0, 0x5dd520, 0x8e)/* 56789.125*/, FP32_RAND_ V6(0), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_QNAN(0), FP32_SNAN(1), FP32_INF(0), FP32_RAND_V3(1)} },14090 { /*src1 */ { FP32_V(1, 0x5dd521, 0x8e)/*-56789.127*/, FP32_RAND_ V7(0), FP32_RAND_V7(0), FP32_RAND_V5(1), FP32_QNAN(0), FP32_QNAN(0), FP32_SNAN(1), FP32_RAND_V2(0)} },14091 { /* => */ { FP32_V(1, 0x5dd521, 0x8e)/*-56789.127*/, FP32_RAND_ V7(0), FP32_RAND_V7(0), FP32_RAND_V5(1), FP32_QNAN(0), FP32_QNAN(0), FP32_SNAN(1), FP32_RAND_V2(0)} },14120 { { /*src2 */ { FP32_V(0, 0x5dd520, 0x8e)/* 56789.125*/, FP32_RAND_x7_V4 } }, 14121 { /*src1 */ { FP32_V(1, 0x5dd521, 0x8e)/*-56789.127*/, FP32_RAND_x7_V0 } }, 14122 { /* => */ { FP32_V(1, 0x5dd521, 0x8e)/*-56789.127*/, FP32_RAND_x7_V0 } }, 14092 14123 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 14093 14124 /*128:out */ X86_MXCSR_XCPT_MASK, 14094 14125 /*256:out */ X86_MXCSR_XCPT_MASK, 14095 14126 /*xcpt? */ false, false }, 14096 { { /*src2 */ { FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_RAND_ V4(0), FP32_RAND_V5(0), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V0(1), FP32_RAND_V2(1), FP32_RAND_V1(1)} },14097 { /*src1 */ { FP32_V(1, 0, 0x7d)/*-0.250*/, FP32_RAND_ V2(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V7(1), FP32_RAND_V5(1), FP32_RAND_V6(0), FP32_RAND_V7(1)} },14098 { /* => */ { FP32_V(1, 0, 0x7d)/*-0.250*/, FP32_RAND_ V2(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V7(1), FP32_RAND_V5(1), FP32_RAND_V6(0), FP32_RAND_V7(1)} },14127 { { /*src2 */ { FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_RAND_x7_V3 } }, 14128 { /*src1 */ { FP32_V(1, 0, 0x7d)/*-0.250*/, FP32_RAND_x7_V6 } }, 14129 { /* => */ { FP32_V(1, 0, 0x7d)/*-0.250*/, FP32_RAND_x7_V6 } }, 14099 14130 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, 14100 14131 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP, … … 14105 14136 * Denormals. 14106 14137 */ 14107 /*46*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_ V2(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V2(0), FP32_RAND_V1(1), FP32_RAND_V7(0), FP32_RAND_V2(1)} },14108 { /*src1 */ { FP32_0(0), FP32_RAND_ V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V5(0), FP32_RAND_V6(1), FP32_RAND_V7(0), FP32_RAND_V1(1)} },14109 { /* => */ { FP32_0(0), FP32_RAND_ V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V5(0), FP32_RAND_V6(1), FP32_RAND_V7(0), FP32_RAND_V1(1)} },14138 /*46*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V2 } }, 14139 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V3 } }, 14140 { /* => */ { FP32_0(0), FP32_RAND_x7_V3 } }, 14110 14141 /*mxcsr:in */ 0, 14111 14142 /*128:out */ X86_MXCSR_DE, 14112 14143 /*256:out */ X86_MXCSR_DE, 14113 14144 /*xcpt? */ true, true }, 14114 { { /*src2 */ { FP32_0(0), FP32_ SNAN(0), FP32_QNAN(1), FP32_QNAN(0), FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN(0), FP32_QNAN(1)} },14115 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_ V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_QNAN(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V2(0)} },14116 { /* => */ { FP32_0(0), FP32_RAND_ V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_QNAN(1), FP32_RAND_V6(0), FP32_RAND_V3(1), FP32_RAND_V2(0)} },14145 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V2 } }, 14146 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V4 } }, 14147 { /* => */ { FP32_0(0), FP32_RAND_x7_V4 } }, 14117 14148 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 14118 14149 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, 14119 14150 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, 14120 14151 /*xcpt? */ false, false }, 14121 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_ INF(1), FP32_SNAN(0), FP32_INF(1), FP32_RAND_V2(1), FP32_RAND_V5(1), FP32_RAND_V2(1), FP32_RAND_V0(1)} },14122 { /*src1 */ { FP32_DENORM_MAX(0), FP32_ INF(0), FP32_QNAN(1), FP32_SNAN(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V3(0)} },14123 { /* => */ { FP32_0(0), FP32_ INF(0), FP32_QNAN(1), FP32_SNAN(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V2(1), FP32_RAND_V3(0)} },14152 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_RAND_x7_V6 } }, 14153 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V3 } }, 14154 { /* => */ { FP32_0(0), FP32_RAND_x7_V3 } }, 14124 14155 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 14125 14156 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 14126 14157 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 14127 14158 /*xcpt? */ false, false }, 14128 { { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_ V2(1), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V2(0), FP32_RAND_V1(1), FP32_RAND_V7(0), FP32_RAND_V0(0)} },14129 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_ V3(0), FP32_RAND_V5(0), FP32_RAND_V6(1), FP32_RAND_V7(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V4(1)} },14130 { /* => */ { FP32_DENORM_MAX(0), FP32_RAND_ V3(0), FP32_RAND_V5(0), FP32_RAND_V6(1), FP32_RAND_V7(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V4(1)} },14159 { { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V5 } }, 14160 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V4 } }, 14161 { /* => */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V4 } }, 14131 14162 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 14132 14163 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, 14133 14164 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, 14134 14165 /*xcpt? */ false, false }, 14135 { { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_ V1(1), FP32_RAND_V2(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1)} },14136 { /*src1 */ { FP32_DENORM_MAX(1), FP32_RAND_ V7(0), FP32_RAND_V6(0), FP32_RAND_V7(0), FP32_RAND_V5(0), FP32_RAND_V3(1), FP32_RAND_V3(1), FP32_RAND_V2(1)} },14137 { /* => */ { FP32_DENORM_MAX(1), FP32_RAND_ V7(0), FP32_RAND_V6(0), FP32_RAND_V7(0), FP32_RAND_V5(0), FP32_RAND_V3(1), FP32_RAND_V3(1), FP32_RAND_V2(1)} },14166 { { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V1 } }, 14167 { /*src1 */ { FP32_DENORM_MAX(1), FP32_RAND_x7_V3 } }, 14168 { /* => */ { FP32_DENORM_MAX(1), FP32_RAND_x7_V3 } }, 14138 14169 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 14139 14170 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, 14140 14171 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, 14141 14172 /*xcpt? */ false, false }, 14142 { { /*src2 */ { FP32_DENORM_MAX(1), FP32_RAND_ V3(1), FP32_RAND_V7(0), FP32_RAND_V6(1), FP32_RAND_V2(0), FP32_RAND_V1(0), FP32_RAND_V7(1), FP32_RAND_V2(1)} },14143 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_ V2(1), FP32_RAND_V3(1), FP32_RAND_V5(1), FP32_RAND_V6(1), FP32_RAND_V7(1), FP32_RAND_V2(1), FP32_RAND_V1(1)} },14144 { /* => */ { FP32_DENORM_MAX(1), FP32_RAND_ V2(1), FP32_RAND_V3(1), FP32_RAND_V5(1), FP32_RAND_V6(1), FP32_RAND_V7(1), FP32_RAND_V2(1), FP32_RAND_V1(1)} },14173 { { /*src2 */ { FP32_DENORM_MAX(1), FP32_RAND_x7_V3 } }, 14174 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V0 } }, 14175 { /* => */ { FP32_DENORM_MAX(1), FP32_RAND_x7_V0 } }, 14145 14176 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 14146 14177 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, 14147 14178 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, 14148 14179 /*xcpt? */ false, false }, 14149 { { /*src2 */ { FP32_DENORM_MIN(1), FP32_RAND_ V7(1), FP32_RAND_V6(1), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(1), FP32_RAND_V1(1)} },14150 { /*src1 */ { FP32_DENORM_MIN(0), FP32_RAND_ V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(0), FP32_RAND_V6(1)} },14151 { /* => */ { FP32_DENORM_MIN(1), FP32_RAND_ V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(0), FP32_RAND_V6(1)} },14180 { { /*src2 */ { FP32_DENORM_MIN(1), FP32_RAND_x7_V7 } }, 14181 { /*src1 */ { FP32_DENORM_MIN(0), FP32_RAND_x7_V0 } }, 14182 { /* => */ { FP32_DENORM_MIN(1), FP32_RAND_x7_V0 } }, 14152 14183 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 14153 14184 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, 14154 14185 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, 14155 14186 /*xcpt? */ false, false }, 14156 { { /*src2 */ { FP32_DENORM_MIN(1), FP32_ INF(0), FP32_QNAN(1), FP32_QNAN(0), FP32_SNAN(1), FP32_SNAN(1), FP32_SNAN(0), FP32_QNAN(1)} },14157 { /*src1 */ { FP32_DENORM_MIN(1), FP32_RAND_ V1(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_QNAN(0), FP32_RAND_V2(0), FP32_RAND_V4(1), FP32_RAND_V7(0)} },14158 { /* => */ { FP32_DENORM_MIN(1), FP32_RAND_ V1(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_QNAN(0), FP32_RAND_V2(0), FP32_RAND_V4(1), FP32_RAND_V7(0)} },14187 { { /*src2 */ { FP32_DENORM_MIN(1), FP32_RAND_x7_V6 } }, 14188 { /*src1 */ { FP32_DENORM_MIN(1), FP32_RAND_x7_V3 } }, 14189 { /* => */ { FP32_DENORM_MIN(1), FP32_RAND_x7_V3 } }, 14159 14190 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 14160 14191 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, 14161 14192 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE, 14162 14193 /*xcpt? */ false, false }, 14163 { { /*src2 */ { FP32_DENORM_MIN(1), FP32_ INF(0), FP32_QNAN(1), FP32_QNAN(0), FP32_SNAN(1), FP32_SNAN(1), FP32_SNAN(0), FP32_QNAN(1)} },14164 { /*src1 */ { FP32_DENORM_MIN(1), FP32_RAND_ V1(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_QNAN(0), FP32_RAND_V2(0), FP32_RAND_V4(1), FP32_RAND_V7(0)} },14165 { /* => */ { FP32_0(1), FP32_RAND_ V1(0), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_QNAN(0), FP32_RAND_V2(0), FP32_RAND_V4(1), FP32_RAND_V7(0)} },14194 { { /*src2 */ { FP32_DENORM_MIN(1), FP32_RAND_x7_V6 } }, 14195 { /*src1 */ { FP32_DENORM_MIN(1), FP32_RAND_x7_V1 } }, 14196 { /* => */ { FP32_0(1), FP32_RAND_x7_V1 } }, 14166 14197 /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ, 14167 14198 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ, 14168 14199 /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ, 14169 14200 /*xcpt? */ false, false }, 14170 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_RAND_ V0(1), FP32_RAND_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(0), FP32_RAND_V6(1)} },14171 { /*src1 */ { FP32_0(0), FP32_RAND_ V0(0), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(1)} },14172 { /* => */ { FP32_0(0), FP32_RAND_ V0(0), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(1)} },14201 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_RAND_x7_V6 } }, 14202 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V2 } }, 14203 { /* => */ { FP32_0(0), FP32_RAND_x7_V2 } }, 14173 14204 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, 14174 14205 /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
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