Index: trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32
===================================================================
--- trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32	(revision 106230)
+++ trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32	(revision 106231)
@@ -2666,382 +2666,18 @@
 
 /**
- * Worker for bs3CpuInstr4_WorkerTestType1.
- */
-static uint16_t bs3CpuInstr4_WorkerTestType1_Inner(uint8_t bMode, PBS3CPUINSTR4_TEST1_CTX_T pTestCtx,
-                                                   PCBS3CPUINSTRX_CONFIG_SAVED_T pSavedCfg)
-{
-    BS3CPUINSTR4_TEST1_T const BS3_FAR        *pTest   = pTestCtx->pTest;
-    BS3CPUINSTR4_TEST1_VALUES_T const BS3_FAR *pValues = &pTestCtx->pTest->paValues[pTestCtx->iVal];
-    PBS3TRAPFRAME    pTrapFrame          = pTestCtx->pTrapFrame;
-    PBS3REGCTX       pCtx                = pTestCtx->pCtx;
-    PBS3EXTCTX       pExtCtx             = pTestCtx->pExtCtx;
-    PBS3EXTCTX       pExtCtxOut          = pTestCtx->pExtCtxOut;
-    uint8_t BS3_FAR *puMemOp             = pTestCtx->puMemOp;
-    uint8_t BS3_FAR *puMemOpAlias        = pTestCtx->puMemOpAlias;
-    uint8_t          cbMemOp             = pTestCtx->cbMemOp;
-    uint8_t const    cbOperand           = pTestCtx->cbOperand;
-    uint8_t const    cbInstr             = ((uint8_t const BS3_FAR *)(uintptr_t)pTestCtx->pTest->pfnWorker)[-1];
-    uint8_t          bXcptExpect         = pTestCtx->bXcptExpect;
-    uint8_t const    bFpXcpt             = pTestCtx->pConfig->fCr4OsXmmExcpt ? X86_XCPT_XF : X86_XCPT_UD;
-    bool const       fSseInstr           = bs3CpuInstr4IsSse(pTest->enmType);
-    uint32_t         uMxCsr;
-    X86YMMREG        MemOpExpect;
-    uint16_t         cErrors;
-    uint32_t         uExpectedMxCsr;
-    bool             fFpXcptExpected;
-
-    /*
-     * An exception may be raised based on the test value (128 vs 256 bits).
-     * In addition, we allow setting the exception flags (and mask) prior to
-     * executing the instruction, so we cannot use the exception flags to figure
-     * out if an exception will be raised. Hence, the input values provide us
-     * explicitly whether an exception is expected for 128 and 256-bit variants.
-     */
-    if (pTestCtx->cbOperand > 16)
-    {
-        uExpectedMxCsr  = pValues->u256ExpectedMxCsr;
-        fFpXcptExpected = pValues->f256FpXcptExpected;
-    }
-    else
-    {
-        uExpectedMxCsr  = pValues->u128ExpectedMxCsr;
-        fFpXcptExpected = pValues->f128FpXcptExpected;
-    }
-
-    /*
-     * Set up the context and some expectations.
-     */
-    /* Destination. */
-    Bs3MemZero(&MemOpExpect, sizeof(MemOpExpect));
-    if (pTest->iRegDst == UINT8_MAX)
-    {
-        BS3_ASSERT(pTest->enmRm >= RM_MEM);
-        Bs3MemSet(puMemOpAlias, 0xcc, cbMemOp);
-        if (bXcptExpect == X86_XCPT_DB)
-            MemOpExpect.ymm = pValues->uDstOut.ymm;
-        else
-            Bs3MemSet(&MemOpExpect, 0xcc, sizeof(MemOpExpect));
-    }
-
-    /* Source #1 (/ destination for SSE). */
-    if (pTest->iRegSrc1 == UINT8_MAX)
-    {
-        BS3_ASSERT(pTest->enmRm >= RM_MEM);
-        Bs3MemCpy(puMemOpAlias, &pValues->uSrc1, cbMemOp);
-        if (pTest->iRegDst == UINT8_MAX)
-            BS3_ASSERT(fSseInstr);
-        else
-            MemOpExpect.ymm = pValues->uSrc1.ymm;
-    }
-    else if (fSseInstr)
-        Bs3ExtCtxSetXmm(pExtCtx, pTest->iRegSrc1, &pValues->uSrc1.ymm.DQWords.dqw0);
-    else
-        Bs3ExtCtxSetYmm(pExtCtx, pTest->iRegSrc1, &pValues->uSrc1.ymm, 32);
-
-    /* Source #2. */
-    if (pTest->iRegSrc2 == UINT8_MAX)
-    {
-        BS3_ASSERT(pTest->enmRm >= RM_MEM);
-        BS3_ASSERT(pTest->iRegDst != UINT8_MAX && pTest->iRegSrc1 != UINT8_MAX);
-        Bs3MemCpy(puMemOpAlias, &pValues->uSrc2, cbMemOp);
-        MemOpExpect.ymm = pValues->uSrc2.ymm;
-    }
-    else if (fSseInstr)
-        Bs3ExtCtxSetXmm(pExtCtx, pTest->iRegSrc2, &pValues->uSrc2.ymm.DQWords.dqw0);
-    else
-        Bs3ExtCtxSetYmm(pExtCtx, pTest->iRegSrc2, &pValues->uSrc2.ymm, 32);
-
-    /* Memory pointer. */
-    if (pTest->enmRm >= RM_MEM)
-    {
-        BS3_ASSERT(   pTest->iRegDst  == UINT8_MAX
-                   || pTest->iRegSrc1 == UINT8_MAX
-                   || pTest->iRegSrc2 == UINT8_MAX);
-        Bs3RegCtxSetGrpSegFromCurPtr(pCtx, &pCtx->rbx, &pCtx->fs, puMemOp);
-    }
-
-    /* Setup MXCSR for the current test. */
-    uMxCsr = (pSavedCfg->uMxCsr & X86_MXCSR_MM) | pValues->uMxCsr;
-    BS3_ASSERT(!(uMxCsr & X86_MXCSR_MM));
-    BS3_ASSERT(!(uMxCsr & X86_MXCSR_DAZ) || g_fMxCsrDazSupported);
-    Bs3ExtCtxSetMxCsr(pExtCtx, uMxCsr);
-
-    /*
-     * Prepare globals and execute.
-     */
-    g_uBs3TrapEipHint = pCtx->rip.u32;
-    if (    bXcptExpect == X86_XCPT_DB
-        && !fFpXcptExpected)
-        g_uBs3TrapEipHint += cbInstr + 1;
-    Bs3TrapSetJmpAndRestoreWithExtCtxAndRm(pCtx, pExtCtx, pTrapFrame, pExtCtxOut);
-
-    /*
-     * Check the result.
-     *
-     * If a floating-point exception is expected, the destination is not updated by the instruction.
-     * In the case of SSE instructions, updating the destination here will work because it is the same
-     * as the source, but for AVX++ it won't because the destination is different and would contain 0s.
-     */
-    cErrors = Bs3TestSubErrorCount();
-    if (   bXcptExpect == X86_XCPT_DB
-        && !fFpXcptExpected
-        && pTest->iRegDst != UINT8_MAX)
-    {
-        if (fSseInstr)
-            Bs3ExtCtxSetXmm(pExtCtx, pTest->iRegDst, &pValues->uDstOut.ymm.DQWords.dqw0);
-        else
-            Bs3ExtCtxSetYmm(pExtCtx, pTest->iRegDst, &pValues->uDstOut.ymm, cbOperand);
-    }
-#if defined(DEBUG_aeichner) /** @todo Necessary kludge on a i7-1068NG7. */
-    if (   pExtCtx->enmMethod == BS3EXTCTXMETHOD_XSAVE
-        && pExtCtx->Ctx.x.Hdr.bmXState == 0x7
-        && pExtCtxOut->Ctx.x.Hdr.bmXState == 0x3)
-        pExtCtxOut->Ctx.x.Hdr.bmXState = 0x7;
-#endif
-    if (bXcptExpect == X86_XCPT_DB)
-        Bs3ExtCtxSetMxCsr(pExtCtx, uExpectedMxCsr | (pSavedCfg->uMxCsr & X86_MXCSR_MM));
-    Bs3TestCheckExtCtx(pExtCtxOut, pExtCtx, 0 /*fFlags*/, pTestCtx->pszMode, pTestCtx->idTestStep);
-
-    if (bXcptExpect == X86_XCPT_DB)
-    {
-        uint32_t const uGotMxCsr = Bs3ExtCtxGetMxCsr(pExtCtxOut) & ~X86_MXCSR_MM;
-
-        /* Check if the SIMD FP exception flags and mask (or lack of) are as expected. */
-        if (uGotMxCsr != uExpectedMxCsr)
-        {
-            char szExpectFlags[FP_XCPT_FLAGS_NAMES_MAXLEN];
-            char szExpectMasks[FP_XCPT_MASKS_NAMES_MAXLEN];
-            char szExpectOthers[FP_XCPT_OTHERS_NAMES_MAXLEN];
-            char szGotFlags[FP_XCPT_FLAGS_NAMES_MAXLEN];
-            char szGotMasks[FP_XCPT_MASKS_NAMES_MAXLEN];
-            char szGotOthers[FP_XCPT_OTHERS_NAMES_MAXLEN];
-            bs3CpuInstr4GetXcptFlags(&szExpectFlags[0],   sizeof(szExpectFlags),  uExpectedMxCsr);
-            bs3CpuInstr4GetXcptMasks(&szExpectMasks[0],   sizeof(szExpectMasks),  uExpectedMxCsr);
-            bs3CpuInstr4GetXcptOthers(&szExpectOthers[0], sizeof(szExpectOthers), uExpectedMxCsr);
-            bs3CpuInstr4GetXcptFlags(&szGotFlags[0],   sizeof(szGotFlags),  uGotMxCsr);
-            bs3CpuInstr4GetXcptMasks(&szGotMasks[0],   sizeof(szGotMasks),  uGotMxCsr);
-            bs3CpuInstr4GetXcptOthers(&szGotOthers[0], sizeof(szGotOthers), uGotMxCsr);
-            Bs3TestFailedF("Expected MXCSR %#RX32 (%s%s%s ) got MXCSR %#RX32 (%s%s%s )", uExpectedMxCsr,
-                           szExpectFlags, szExpectMasks, szExpectOthers, uGotMxCsr, szGotFlags, szGotMasks, szGotOthers);
-        }
-
-        /* Check if the SIMD FP exception (or lack of) is as expected. */
-        if (fFpXcptExpected)
-        {
-            if (pTrapFrame->bXcpt == bFpXcpt)
-            { /* likely */ }
-            else
-                Bs3TestFailedF("Expected floating-point xcpt %s, got %s", bs3CpuInstr4XcptName(bFpXcpt),
-                               bs3CpuInstr4XcptName(pTrapFrame->bXcpt));
-        }
-        else if (pTrapFrame->bXcpt == X86_XCPT_DB)
-        { /* likely */ }
-        else
-            Bs3TestFailedF("Expected no xcpt, got %s", bs3CpuInstr4XcptName(pTrapFrame->bXcpt));
-    }
-    /* Check if non-FP exception is as expected. */
-    else if (pTrapFrame->bXcpt != bXcptExpect)
-        Bs3TestFailedF("Expected xcpt %s, got %s", bs3CpuInstr4XcptName(bXcptExpect), bs3CpuInstr4XcptName(pTrapFrame->bXcpt));
-
-    /* Kludge! Looks like EFLAGS.AC is cleared when raising #GP in real mode on the 10980XE. WEIRD! */
-    if (bMode == BS3_MODE_RM && (pCtx->rflags.u32 & X86_EFL_AC))
-    {
-        if (pTrapFrame->Ctx.rflags.u32 & X86_EFL_AC)
-            Bs3TestFailedF("Expected EFLAGS.AC to be cleared (bXcpt=%d)", pTrapFrame->bXcpt);
-        pTrapFrame->Ctx.rflags.u32 |= X86_EFL_AC;
-    }
-    if (bXcptExpect == X86_XCPT_PF)
-        pCtx->cr2.u = (uintptr_t)puMemOp;
-    Bs3TestCheckRegCtxEx(&pTrapFrame->Ctx, pCtx, bXcptExpect == X86_XCPT_DB && !fFpXcptExpected ? cbInstr + 1 : 0, 0 /*cbSpAdjust*/,
-                         (bXcptExpect == X86_XCPT_DB && !fFpXcptExpected) || BS3_MODE_IS_16BIT_SYS(bMode) ? 0 : X86_EFL_RF,
-                         pTestCtx->pszMode, pTestCtx->idTestStep);
-    pCtx->cr2.u = 0;
-
-    if (   pTest->enmRm >= RM_MEM
-        && Bs3MemCmp(puMemOpAlias, &MemOpExpect, cbMemOp) != 0)
-        Bs3TestFailedF("Expected uMemOp %.*Rhxs, got %.*Rhxs", cbMemOp, &MemOpExpect, cbMemOp, puMemOpAlias);
-
-    return cErrors;
-}
-
-
-/**
- * Test type #1 worker.
- */
-static uint8_t bs3CpuInstr4_WorkerTestType1(uint8_t bMode, BS3CPUINSTR4_TEST1_T const BS3_FAR *paTests, unsigned cTests,
-                                            PCBS3CPUINSTR4_CONFIG_T paConfigs, unsigned cConfigs)
-{
-    BS3REGCTX                   Ctx;
-    BS3TRAPFRAME                TrapFrame;
-    const char BS3_FAR * const  pszMode = Bs3GetModeName(bMode);
-    uint8_t                     bRing   = BS3_MODE_IS_V86(bMode) ? 3 : 0;
-    uint8_t BS3_FAR            *pbBuf   = g_pbBuf;
-    uint32_t                    cbBuf   = g_cbBuf;
-    PBS3EXTCTX                  pExtCtxOut;
-    PBS3EXTCTX                  pExtCtx = bs3CpuInstrXAllocExtCtxs(&pExtCtxOut);
-    if (pExtCtx)
-    { /* likely */ }
-    else
-        return 0;
-    if (pExtCtx->enmMethod != BS3EXTCTXMETHOD_ANCIENT)
-    { /* likely */ }
-    else
-    {
-        Bs3TestPrintf("Skipped due to ancient FPU state format\n");
-        return 0;
-    }
-
-    /* Ensure the structures are allocated before we sample the stack pointer. */
-    Bs3MemSet(&Ctx, 0, sizeof(Ctx));
-    Bs3MemSet(&TrapFrame, 0, sizeof(TrapFrame));
-
-    /*
-     * Create test context.
-     */
-    pbBuf = bs3CpuInstrXBufSetup(pbBuf, &cbBuf, bMode);
-    Bs3RegCtxSaveForMode(&Ctx, bMode, 1024);
-    bs3CpuInstr4SetupSseAndAvx(&Ctx, pExtCtx);
-
-    /*
-     * Run the tests in all rings since alignment issues may behave
-     * differently in ring-3 compared to ring-0.
-     */
-    for (;;)
-    {
-        unsigned fPf = 0;
-        do
-        {
-            unsigned iCfg;
-            for (iCfg = 0; iCfg < cConfigs; iCfg++)
-            {
-                unsigned                    iTest;
-                BS3CPUINSTRX_CONFIG_SAVED_T SavedCfg;
-                if (!bs3CpuInstr4ConfigReconfigure(&SavedCfg, &Ctx, pExtCtx, &paConfigs[iCfg], bMode))
-                    continue; /* unsupported config */
-
-                /*
-                 * Iterate the tests.
-                 */
-                for (iTest = 0; iTest < cTests; iTest++)
-                {
-                    BS3CPUINSTR4_TEST1_T const BS3_FAR *pTest = &paTests[iTest];
-                    unsigned const    cValues       = pTest->cValues;
-                    bool const        fSseInstr     = bs3CpuInstr4IsSse(pTest->enmType);
-                    bool const        fAvxInstr     = bs3CpuInstr4IsAvx(pTest->enmType);
-                    uint8_t const     cbOperand     = bs3CpuInstr4GetOperandSize(pTest->enmType);
-                    uint8_t const     cbMemOp       = bs3CpuInstrXMemOpSize(cbOperand, pTest->enmRm);
-                    uint8_t const     cbAlign       = cbMemOp;
-                    uint8_t BS3_FAR  *puMemOp       = bs3CpuInstrXBufForOperand(pbBuf, cbBuf, cbMemOp, cbAlign, &paConfigs[iCfg], fPf);
-                    uint8_t          *puMemOpAlias  = &g_pbBufAlias[(uintptr_t)puMemOp - (uintptr_t)pbBuf];
-                    uint8_t           bXcptExpect   = !g_afTypeSupports[pTest->enmType] ? X86_XCPT_UD
-                                                    : fSseInstr ? paConfigs[iCfg].bXcptSse
-                                                    : BS3_MODE_IS_RM_OR_V86(bMode) ? X86_XCPT_UD : paConfigs[iCfg].bXcptAvx;
-                    uint16_t         idTestStep     = bRing * 10000 + iCfg * 100 + iTest * 10;
-                    unsigned         cRecompRuns    = 0;
-                    unsigned const   cMaxRecompRuns = g_cBs3ThresholdNativeRecompiler + cValues;
-                    unsigned         iVal;
-
-                    /* If testing unaligned memory accesses (or #PF), skip register-only tests.  This
-                       allows setting bXcptSse and bXcptAvx to reflect the misaligned exceptions. */
-                    if (   (pTest->enmRm == RM_REG || pTest->enmRm == RM_MEM8)
-                        && (!paConfigs[iCfg].fAligned || paConfigs[iCfg].fAlignCheck || fPf))
-                        continue;
-
-                    /* #AC is only raised in ring-3. */
-                    if (bXcptExpect == X86_XCPT_AC)
-                    {
-                        if (bRing != 3)
-                            bXcptExpect = X86_XCPT_DB;
-                        else if (fAvxInstr)
-                            bXcptExpect = pTest->bAvxMisalignXcpt; /* they generally don't raise #AC */
-                    }
-
-                    if (fPf && bXcptExpect == X86_XCPT_DB)
-                        bXcptExpect = X86_XCPT_PF;
-
-                    Bs3RegCtxSetRipCsFromCurPtr(&Ctx, pTest->pfnWorker);
-
-                    /*
-                     * Iterate the test values and do the actual testing.
-                     */
-                    while (cRecompRuns < cMaxRecompRuns)
-                    {
-                        for (iVal = 0; iVal < cValues; iVal++, idTestStep++, cRecompRuns++)
-                        {
-                            uint16_t                 cErrors;
-                            BS3CPUINSTR4_TEST1_CTX_T TestCtx;
-
-                            if (BS3_SKIPIT(bRing, iCfg, iTest, iVal, 0))
-                                continue;
-
-                            /*
-                             * If the hardware does not support DAZ bit skip test values that set it.
-                             */
-                            if (   !g_fMxCsrDazSupported
-                                && (pTest->paValues[iVal].uMxCsr & X86_MXCSR_DAZ))
-                                continue;
-
-                            /*
-                             * Setup the test instruction context and pass it to the worker.
-                             * A few of these can be figured out by the worker but initializing
-                             * it outside the inner most loop is more optimal.
-                             */
-                            TestCtx.pConfig      = &paConfigs[iCfg];
-                            TestCtx.pTest        = pTest;
-                            TestCtx.iVal         = iVal;
-                            TestCtx.pszMode      = pszMode;
-                            TestCtx.pTrapFrame   = &TrapFrame;
-                            TestCtx.pCtx         = &Ctx;
-                            TestCtx.pExtCtx      = pExtCtx;
-                            TestCtx.pExtCtxOut   = pExtCtxOut;
-                            TestCtx.puMemOp      = (uint8_t *)puMemOp;
-                            TestCtx.puMemOpAlias = puMemOpAlias;
-                            TestCtx.cbMemOp      = cbMemOp;
-                            TestCtx.cbOperand    = cbOperand;
-                            TestCtx.bXcptExpect  = bXcptExpect;
-                            TestCtx.idTestStep   = idTestStep;
-                            cErrors = bs3CpuInstr4_WorkerTestType1_Inner(bMode, &TestCtx, &SavedCfg);
-                            if (cErrors != Bs3TestSubErrorCount())
-                            {
-                                if (paConfigs[iCfg].fAligned)
-                                    Bs3TestFailedF("%s: ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%u %s, %s %u-bit)",
-                                                   Bs3GetModeName(bMode), bRing, iCfg, iTest, iVal,
-                                                   bXcptExpect, bs3CpuInstr4XcptName(bXcptExpect), fSseInstr ? "SSE" : "AVX", cbOperand * 8);
-                                else
-                                    Bs3TestFailedF("%s: ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%u %s, puMemOp=%p, EFLAGS=%#RX32, %s %u-bit)",
-                                                   Bs3GetModeName(bMode), bRing, iCfg, iTest, iVal,
-                                                   bXcptExpect, bs3CpuInstr4XcptName(bXcptExpect), puMemOp,
-                                                   TrapFrame.Ctx.rflags.u32, fSseInstr ? "SSE" : "AVX", cbOperand * 8);
-                                Bs3TestPrintf("\n");
-                            }
-                        }
-                    }
-                }
-                bs3CpuInstrXConfigRestore(&SavedCfg, &Ctx, pExtCtx);
-            }
-        } while (fPf++ == 0 && BS3_MODE_IS_PAGED(bMode));
-
-        /*
-         * Next ring.
-         */
-        bRing++;
-        if (bRing > 3 || bMode == BS3_MODE_RM)
-            break;
-        Bs3RegCtxConvertToRingX(&Ctx, bRing);
-    }
-
-    /*
-     * Cleanup.
-     */
-    bs3CpuInstrXBufCleanup(pbBuf, cbBuf, bMode);
-    bs3CpuInstrXFreeExtCtxs(pExtCtx, pExtCtxOut);
-    return 0;
-}
-
-
-/**
- * Constants used in the 'Worker 1A' test value definitions.  These are
- * extra bits which can be set in the ':out' fields of a test value.
- * They are described below in the corresponding code.
+ * Constants used in test value definitions.  These are extra bits which
+ * can be set in the ':out' fields of a test value; stored in 'stolen'
+ * bits from the real x86 MXCSR CPU register definition.
+ *
+ * 'BS3_MXCSR_?M_FIXED' bits prevent the mask randomizer from changing
+ * the corresponding bit of the mask.  These can be used to 'split' an
+ * entry which produces different results under different masks,
+ * allowing both sets of results to be properly tested.
+ *
+ * 'BS3_MXCSR_PE_FUZZY' marks test value entries which are considered
+ * to have passed the test regardless of the value of X86_MXCSR_PE in
+ * the result.  Many, most, or possibly all instances of this represent
+ * bugs in the test value definitions and/or the CPU emulator IEM; all
+ * need further investigation.
  */
 #define BS3_MXCSR_FIXED_SHIFT 11
@@ -3063,7 +2699,7 @@
 
 /**
- * Worker for bs3CpuInstr4_WorkerTestType1 [new WIP version]
+ * Worker for bs3CpuInstr4_WorkerTestType1.
  */
-static uint16_t bs3CpuInstr4_WorkerTestType1A_Inner(uint8_t bMode, PBS3CPUINSTR4_TEST1_CTX_T pTestCtx,
+static uint16_t bs3CpuInstr4_WorkerTestType1_Inner(uint8_t bMode, PBS3CPUINSTR4_TEST1_CTX_T pTestCtx,
                                                    PCBS3CPUINSTRX_CONFIG_SAVED_T pSavedCfg)
 {
@@ -3428,7 +3064,7 @@
 
 /**
- * Test type #1 worker [new WIP version].
+ * Test type #1 worker.
  */
-static uint8_t bs3CpuInstr4_WorkerTestType1A(uint8_t bMode, BS3CPUINSTR4_TEST1_T const BS3_FAR *paTests, unsigned cTests,
+static uint8_t bs3CpuInstr4_WorkerTestType1(uint8_t bMode, BS3CPUINSTR4_TEST1_T const BS3_FAR *paTests, unsigned cTests,
                                             PCBS3CPUINSTR4_CONFIG_T paConfigs, unsigned cConfigs)
 {
@@ -3559,5 +3195,5 @@
                             TestCtx.bXcptExpect  = bXcptExpect;
                             TestCtx.idTestStep   = idTestStep;
-                            cErrors = bs3CpuInstr4_WorkerTestType1A_Inner(bMode, &TestCtx, &SavedCfg);
+                            cErrors = bs3CpuInstr4_WorkerTestType1_Inner(bMode, &TestCtx, &SavedCfg);
                             if (cErrors != Bs3TestSubErrorCount())
                             {
@@ -3596,4 +3232,12 @@
     return 0;
 }
+
+
+/** @todo 'master switch' turns on all IEM misbehaviors documented below */
+#ifdef TODO_EXPOSE_IEM_ERRATA
+# define TODO_X86_MXCSR_PE_IEM
+# define TODO_X86_MXCSR_PE_IEM_SSE
+# define TODO_X86_MXCSR_UE_IEM
+#endif /* TODO_EXPOSE_IEM_ERRATA */
 
 
@@ -3983,5 +3627,5 @@
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     unsigned const                         iTest       = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
-    return bs3CpuInstr4_WorkerTestType1A(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+    return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
                                         g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
 }
@@ -4185,6 +3829,5 @@
               /*256:out  */ BS3_MXCSR_DM_FIXED | X86_MXCSR_DE,
               /*xcpt?    */ true, true },
-#ifdef TODO_X86_MXCSR_UE_HW /** @todo THIS FAILS ON IEM: X86_MXCSR_UE not set in 128:out or 256:out */
-          /* this is what works on HW (i7-10700) (same as below, plus out:_UE) */
+#ifdef TODO_X86_MXCSR_UE_IEM /** @todo THIS FAILS ON IEM: X86_MXCSR_UE not set in 128:out or 256:out */
  /*--|25*/{ { /*src2     */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
             { /*src1     */ { FP64_0(0),          FP64_0(0), FP64_0(0), FP64_0(0) } },
@@ -4193,14 +3836,4 @@
               /*128:out  */ X86_MXCSR_DM | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED | X86_MXCSR_DE | X86_MXCSR_UE,
               /*256:out  */ X86_MXCSR_DM | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED | X86_MXCSR_DE | X86_MXCSR_UE,
-              /*xcpt?    */ true, true },
-#endif /* TODO_X86_MXCSR_UE_HW */
-#ifdef TODO_X86_MXCSR_UE_IEM /** @todo THIS FAILS ON HW: X86_MXCSR_UE not set in 128:out or 256:out */
-          /* for comparison, this is what works on IEM (same as above, minus out:_UE) */
- /*--|25*/{ { /*src2     */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
-            { /*src1     */ { FP64_0(0),          FP64_0(0), FP64_0(0), FP64_0(0) } },
-            { /* =>      */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_DM,                 /* DM on,  UM off */
-              /*128:out  */ X86_MXCSR_DM | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED | X86_MXCSR_DE,
-              /*256:out  */ X86_MXCSR_DM | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED | X86_MXCSR_DE,
               /*xcpt?    */ true, true },
 #endif /* TODO_X86_MXCSR_UE_IEM */
@@ -4219,6 +3852,5 @@
               /*256:out  */ BS3_MXCSR_DM_FIXED | X86_MXCSR_DE,
               /*xcpt?    */ false, false },
-#ifdef TODO_X86_MXCSR_UE_HW /** @todo THIS FAILS ON IEM: X86_MXCSR_UE not set in 128:out or 256:out */
-         /* this is what works on HW (i7-10700) (same as below, plus 256:out:_UE) */
+#ifdef TODO_X86_MXCSR_UE_IEM /** @todo THIS FAILS ON IEM: X86_MXCSR_UE not set in 128:out or 256:out */
  /*--|28*/{ { /*src2     */ { FP64_0(0), FP64_0(0), FP64_0(0),          FP64_0(0) } },
             { /*src1     */ { FP64_0(0), FP64_0(0), FP64_DENORM_MAX(0), FP64_0(0) } },
@@ -4227,14 +3859,4 @@
               /*128:out  */ X86_MXCSR_DM,
               /*256:out  */ X86_MXCSR_DM | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED | X86_MXCSR_DE | X86_MXCSR_UE,
-              /*xcpt?    */ true, true },
-#endif /* TODO_X86_MXCSR_UE_HW */
-#ifdef TODO_X86_MXCSR_UE_IEM
-         /* for comparison, this is what works on IEM (same as above, minus 256:out:_UE) */
- /*--|28*/{ { /*src2     */ { FP64_0(0), FP64_0(0), FP64_0(0),          FP64_0(0) } },
-            { /*src1     */ { FP64_0(0), FP64_0(0), FP64_DENORM_MAX(0), FP64_0(0) } },
-            { /* =>      */ { FP64_0(0), FP64_0(0), FP64_DENORM_MAX(0), FP64_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_DM,                 /* DM on,  UM off */
-              /*128:out  */ X86_MXCSR_DM,
-              /*256:out  */ X86_MXCSR_DM | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED | X86_MXCSR_DE,
               /*xcpt?    */ true, true },
 #endif /* TODO_X86_MXCSR_UE_IEM */
@@ -4257,5 +3879,5 @@
      * Invalids.
      */
-    /*27*/ FP64_TABLE_D1_PD_INVALIDS
+ /*29|31*/ FP64_TABLE_D1_PD_INVALIDS
     /** @todo Underflow, Precision; Rounding; FZ etc. */
     };
@@ -4307,5 +3929,5 @@
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     unsigned const                         iTest       = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
-    return bs3CpuInstr4_WorkerTestType1A(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+    return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
                                         g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
 }
@@ -4554,5 +4176,5 @@
  /*--|31*/{ { /*src2     */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V5 } },
             { /*src1     */ { FP32_0(0),          FP32_RAND_x7_V4 } },
-            { /* =>      */ { FP32_0(0),          FP32_RAND_x7_V4 } },
+            { /* =>      */ { FP32_0(0),          FP32_RAND_x7_V4 } } /* result on HW (i7-10700) */,
     // IEM: { /* =>      */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V4 } } /* result on IEM */,
               /*mxcsr:in */ X86_MXCSR_DM,
@@ -4639,5 +4261,5 @@
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     unsigned const                         iTest       = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
-    return bs3CpuInstr4_WorkerTestType1A(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+    return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
                                         g_aXcptConfig3, RT_ELEMENTS(g_aXcptConfig3));
 }
@@ -4987,5 +4609,5 @@
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     unsigned const                         iTest       = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
-    return bs3CpuInstr4_WorkerTestType1A(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+    return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
                                         g_aXcptConfig3, RT_ELEMENTS(g_aXcptConfig3));
 }
@@ -5361,5 +4983,5 @@
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     unsigned const                         iTest       = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
-    return bs3CpuInstr4_WorkerTestType1A(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+    return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
                                         g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
 }
@@ -5700,5 +5322,5 @@
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     unsigned const                         iTest       = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
-    return bs3CpuInstr4_WorkerTestType1A(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+    return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
                                         g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
 }
@@ -6123,5 +5745,5 @@
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     unsigned const                         iTest       = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
-    return bs3CpuInstr4_WorkerTestType1A(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+    return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
                                         g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
 }
@@ -6360,6 +5982,5 @@
               /*256:out  */ X86_MXCSR_DE | BS3_MXCSR_DM_FIXED,
               /*xcpt?    */ true, true },
-#ifdef TODO_X86_MXCSR_UE_HW /** @todo THIS FAILS ON IEM: X86_MXCSR_UE not set in 128:out or 256:out */
-         /* this is what works on HW (i7-10700) (same as below, plus 256:out:_UE) */
+#ifdef TODO_X86_MXCSR_UE_IEM /** @todo THIS FAILS ON IEM: X86_MXCSR_UE not set in 128:out or 256:out */
  /*--|30*/{ { /*src2     */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
             { /*src1     */ { FP64_0(0),          FP64_0(0), FP64_0(0), FP64_0(0) } },
@@ -6368,14 +5989,4 @@
               /*128:out  */ X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED,
               /*256:out  */ X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED,
-              /*xcpt?    */ true, true },
-#endif /* TODO_X86_MXCSR_UE_HW */
-#ifdef TODO_X86_MXCSR_UE_IEM
-         /* for comparison, this is what works on IEM (same as above, minus 256:out:_UE) */
- /*--|30*/{ { /*src2     */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
-            { /*src1     */ { FP64_0(0),          FP64_0(0), FP64_0(0), FP64_0(0) } },
-            { /* =>      */ { FP64_DENORM_MAX(1), FP64_0(0), FP64_0(0), FP64_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_DM,
-              /*128:out  */ X86_MXCSR_DE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED,
-              /*256:out  */ X86_MXCSR_DE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED,
               /*xcpt?    */ true, true },
 #endif /* TODO_X86_MXCSR_UE_IEM */
@@ -6387,5 +5998,5 @@
               /*256:out  */ X86_MXCSR_DE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED,
               /*xcpt?    */ true, true },
- /*31|32*/{ { /*src2     */ { FP64_0(0), FP64_0(0),          FP64_0(0), FP64_0(0) } },
+          { { /*src2     */ { FP64_0(0), FP64_0(0),          FP64_0(0), FP64_0(0) } },
             { /*src1     */ { FP64_0(0), FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0) } },
             { /* =>      */ { FP64_0(0), FP64_0(0),          FP64_0(0), FP64_0(0) } },
@@ -6394,5 +6005,5 @@
               /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
               /*xcpt?    */ false, false },
- /*32|33*/{ { /*src2     */ { FP64_DENORM_MIN(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } },
+          { { /*src2     */ { FP64_DENORM_MIN(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } },
             { /*src1     */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } },
             { /* =>      */ { FP64_0(0),          FP64_0(0),          FP64_0(0),          FP64_0(0)          } },
@@ -6455,5 +6066,5 @@
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     unsigned const                         iTest       = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
-    return bs3CpuInstr4_WorkerTestType1A(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+    return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
                                         g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
 }
@@ -6794,5 +6405,5 @@
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     unsigned const                         iTest       = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
-    return bs3CpuInstr4_WorkerTestType1A(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+    return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
                                         g_aXcptConfig3, RT_ELEMENTS(g_aXcptConfig3));
 }
@@ -7167,5 +6778,5 @@
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     unsigned const                         iTest       = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
-    return bs3CpuInstr4_WorkerTestType1A(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+    return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
                                         g_aXcptConfig3, RT_ELEMENTS(g_aXcptConfig3));
 }
@@ -7541,5 +7152,5 @@
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     unsigned const                         iTest       = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
-    return bs3CpuInstr4_WorkerTestType1A(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+    return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
                                         g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
 }
@@ -7848,5 +7459,5 @@
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     unsigned const                         iTest       = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
-    return bs3CpuInstr4_WorkerTestType1A(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+    return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
                                         g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
 }
@@ -8298,5 +7909,5 @@
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     unsigned const                         iTest       = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
-    return bs3CpuInstr4_WorkerTestType1A(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+    return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
                                         g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
 }
@@ -8610,5 +8221,5 @@
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     unsigned const                         iTest       = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
-    return bs3CpuInstr4_WorkerTestType1A(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+    return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
                                         g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
 }
@@ -8867,5 +8478,5 @@
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     unsigned const                         iTest       = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
-    return bs3CpuInstr4_WorkerTestType1A(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+    return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
                                         g_aXcptConfig3, RT_ELEMENTS(g_aXcptConfig3));
 }
@@ -9201,5 +8812,5 @@
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     unsigned const                         iTest       = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
-    return bs3CpuInstr4_WorkerTestType1A(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+    return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
                                         g_aXcptConfig3, RT_ELEMENTS(g_aXcptConfig3));
 }
@@ -9330,5 +8941,5 @@
               /*256:out  */ X86_MXCSR_UM | X86_MXCSR_UE | X86_MXCSR_PE | BS3_MXCSR_UM_FIXED,
               /*xcpt?    */ false, true },
-#ifdef TODO_X86_MXCSR_PE /** @todo THIS FAILS ON IEM: X86_MXCSR_PE not set in 256:out */
+#ifdef TODO_X86_MXCSR_PE_IEM /** @todo THIS FAILS ON IEM: X86_MXCSR_PE not set in 256:out */
  /*--|15*/{ { /*src2     */ { FP32_V(0,0,0x7e)/*0.50*/, FP32_1(1), FP32_1(0), FP32_1(0), FP32_NORM_MAX(1), FP32_1(0), FP32_NORM_MAX(1),     FP32_NORM_MAX(0) } },
             { /*src1     */ { FP32_NORM_MAX(0),         FP32_1(0), FP32_0(0), FP32_1(0), FP32_0(0),        FP32_1(0), FP32_1(0),            FP32_0(0)        } },
@@ -9338,5 +8949,5 @@
               /*256:out  */ X86_MXCSR_OE | X86_MXCSR_PE | X86_MXCSR_UE | BS3_MXCSR_OM_FIXED | BS3_MXCSR_UM_FIXED,
               /*xcpt?    */ false, false },
-#endif /* TODO_X86_MXCSR_PE */
+#endif /* TODO_X86_MXCSR_PE_IEM */
  /*14|16*/{ { /*src2     */ { FP32_V(0,0,0x7e)/*0.50*/, FP32_1(1), FP32_1(0), FP32_1(0), FP32_NORM_MAX(1), FP32_1(0), FP32_NORM_MAX(1),     FP32_NORM_MAX(0) } },
             { /*src1     */ { FP32_NORM_MAX(0),         FP32_1(0), FP32_0(0), FP32_1(0), FP32_0(0),        FP32_1(0), FP32_1(0),            FP32_0(0)        } },
@@ -9353,5 +8964,5 @@
               /*256:out  */ X86_MXCSR_OM | X86_MXCSR_OE | X86_MXCSR_PE | X86_MXCSR_UE | BS3_MXCSR_OM_FIXED,
               /*xcpt?    */ false, false },
-#ifdef TODO_X86_MXCSR_PE /** @todo THIS FAILS ON IEM: X86_MXCSR_PE not set in 128:out or 256:out */
+#ifdef TODO_X86_MXCSR_PE_IEM /** @todo THIS FAILS ON IEM: X86_MXCSR_PE not set in 128:out or 256:out */
  /*--|18*/{ { /*src2     */ { FP32_NORM_MAX(0), FP32_NORM_MIN(0), FP32_1(0), FP32_1(0), FP32_NORM_MAX(0), FP32_1(1), FP32_1(0), FP32_NORM_MIN(0) } },
             { /*src1     */ { FP32_NORM_MIN(0), FP32_NORM_MAX(1), FP32_1(0), FP32_1(0), FP32_NORM_MIN(1), FP32_1(0), FP32_1(1), FP32_NORM_MAX(0) } },
@@ -9361,5 +8972,5 @@
               /*256:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | X86_MXCSR_UE | BS3_MXCSR_OM_FIXED | BS3_MXCSR_UM_FIXED,
               /*xcpt?    */ false, false },
-#endif /* TODO_X86_MXCSR_PE */
+#endif /* TODO_X86_MXCSR_PE_IEM */
  /*16|19*/{ { /*src2     */ { FP32_NORM_MAX(0), FP32_NORM_MIN(0), FP32_1(0), FP32_1(0), FP32_NORM_MAX(0), FP32_1(1), FP32_1(0), FP32_NORM_MIN(0) } },
             { /*src1     */ { FP32_NORM_MIN(0), FP32_NORM_MAX(1), FP32_1(0), FP32_1(0), FP32_NORM_MIN(1), FP32_1(0), FP32_1(1), FP32_NORM_MAX(0) } },
@@ -9603,5 +9214,5 @@
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     unsigned const                         iTest       = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
-    return bs3CpuInstr4_WorkerTestType1A(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+    return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
                                         g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
 }
@@ -9775,5 +9386,5 @@
               /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_DE | X86_MXCSR_UE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* i7-10700, IEM */,
               /*xcpt?    */ false, true },
-#ifdef TODO_X86_MXCSR_UE /** @todo THIS FAILS ON IEM: X86_MXCSR_UE not set in 256:out */
+#ifdef TODO_X86_MXCSR_UE_IEM /** @todo THIS FAILS ON IEM: X86_MXCSR_UE not set in 256:out */
  /*--|21*/{ { /*src2     */ { FP64_1(0), FP64_1(1), FP64_1(0),          FP64_1(0)          } },
             { /*src1     */ { FP64_0(0), FP64_0(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0) } },
@@ -9783,5 +9394,5 @@
               /*256:out  */ X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_UM_FIXED,
               /*xcpt?    */ false, false },
-#endif /* TODO_X86_MXCSR_UE */
+#endif /* TODO_X86_MXCSR_UE_IEM */
  /*21|22*/{ { /*src2     */ { FP64_1(0), FP64_1(1), FP64_1(0),          FP64_1(0)          } },
             { /*src1     */ { FP64_0(0), FP64_0(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0) } },
@@ -9791,5 +9402,5 @@
               /*256:out  */ X86_MXCSR_DE | BS3_MXCSR_UM_FIXED,
               /*xcpt?    */ false, false },
-#ifdef TODO_X86_MXCSR_UE /** @todo THIS FAILS ON IEM: X86_MXCSR_UE not set in 256:out */
+#ifdef TODO_X86_MXCSR_UE_IEM /** @todo THIS FAILS ON IEM: X86_MXCSR_UE not set in 256:out */
  /*--|23*/{ { /*src2     */ { FP64_1(0), FP64_1(1), FP64_1(0),          FP64_1(0)          } },
             { /*src1     */ { FP64_0(0), FP64_0(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0) } },
@@ -9799,5 +9410,5 @@
               /*256:out  */ X86_MXCSR_DM | X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_UM_FIXED,
               /*xcpt?    */ false, true },
-#endif /* TODO_X86_MXCSR_UE */
+#endif /* TODO_X86_MXCSR_UE_IEM */
  /*22|24*/{ { /*src2     */ { FP64_1(0), FP64_1(1), FP64_1(0),          FP64_1(0)          } },
             { /*src1     */ { FP64_0(0), FP64_0(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0) } },
@@ -9982,5 +9593,5 @@
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     unsigned const                         iTest       = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
-    return bs3CpuInstr4_WorkerTestType1A(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+    return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
                                         g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
 }
@@ -10241,5 +9852,5 @@
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     unsigned const                         iTest       = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
-    return bs3CpuInstr4_WorkerTestType1A(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+    return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
                                         g_aXcptConfig3, RT_ELEMENTS(g_aXcptConfig3));
 }
@@ -10569,5 +10180,5 @@
               /*256:out  */ -1,
               /*xcpt?    */ false, false },
-#ifdef TODO_X86_MXCSR_PE /** @todo THIS FAILS ON IEM: X86_MXCSR_PE not set in 128:out */
+#ifdef TODO_X86_MXCSR_PE_IEM /** @todo THIS FAILS ON IEM: X86_MXCSR_PE not set in 128:out */
  /*--|41*/{ { /*            DENORM_MAX /       -42.0 = -5e-310  &_DE &!_PE(if DM && !UM) &_UE */
               /*src2     */ { FP64_V(1, 0x5000000000000, 0x404)/*-42.0*/,    FP64_0(0),          FP64_RAND_V2(0), FP64_RAND_V1(1) } },
@@ -10578,5 +10189,5 @@
               /*256:out  */ -1,
               /*xcpt?    */ false, false },
-#endif /* TODO_X86_MXCSR_PE */
+#endif /* TODO_X86_MXCSR_PE_IEM */
  /*41|42*/{ { /*  UMASKED:  DENORM_MAX /        42.0 = 5e-310   &_DE &_PE(if UM) &_UE */
               /*src2     */ { FP64_V(0, 0x5000000000000, 0x404)/*-42.0*/,    FP64_0(0),          FP64_RAND_V2(0), FP64_RAND_V1(1) } },
@@ -10595,5 +10206,5 @@
               /*256:out  */ -1,
               /*xcpt?    */ true, true },
-#ifdef TODO_X86_MXCSR_PE /** @todo THIS FAILS ON IEM: X86_MXCSR_PE not set in 128:out */
+#ifdef TODO_X86_MXCSR_PE_IEM /** @todo THIS FAILS ON IEM: X86_MXCSR_PE not set in 128:out */
  /*--|44*/{ { /* D~UMASKED: DENORM_MAX /        42.0 = 5e-310   &_DE &!_PE(if DM && !UM) &_UE */
               /*src2     */ { FP64_V(0, 0x5000000000000, 0x404)/*-42.0*/,    FP64_0(0),          FP64_RAND_V2(0), FP64_RAND_V1(1) } },
@@ -10604,5 +10215,5 @@
               /*256:out  */ -1,
               /*xcpt?    */ true, true },
-#endif /* TODO_X86_MXCSR_PE */
+#endif /* TODO_X86_MXCSR_PE_IEM */
  /*43|45*/{ { /* DAZ:       DENORM_MAX /       -42.0 = -0       &- */
               /*src2     */ { FP64_V(1, 0x5000000000000, 0x404)/*-42.0*/, FP64_0(0),          FP64_RAND_V2(0), FP64_RAND_V1(1) } },
@@ -10664,5 +10275,5 @@
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     unsigned const                         iTest       = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
-    return bs3CpuInstr4_WorkerTestType1A(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+    return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
                                         g_aXcptConfig3, RT_ELEMENTS(g_aXcptConfig3));
 }
@@ -10937,5 +10548,5 @@
               /*256:out  */ X86_MXCSR_DE | BS3_MXCSR_DM_FIXED,
               /*xcpt?    */ false, false },
-#ifdef TODO_X86_MXCSR_UE /** @todo THIS FAILS ON IEM: X86_MXCSR_UE not set in 128:out or 256:out */
+#ifdef TODO_X86_MXCSR_UE_IEM /** @todo THIS FAILS ON IEM: X86_MXCSR_UE not set in 128:out or 256:out */
  /*--|35*/{ { /*src2     */ { FP32_DENORM_MAX(0), FP32_0(0),          FP32_DENORM_MAX(0), FP32_DENORM_MAX(0),                                   FP32_DENORM_MAX(0), FP32_DENORM_MAX(1),                                   FP32_0(0),          FP32_0(0)          } },
             { /*src1     */ { FP32_0(0),          FP32_DENORM_MAX(1), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0),                                   FP32_0(0),          FP32_DENORM_MAX(1),                                   FP32_DENORM_MAX(0), FP32_DENORM_MAX(1) } },
@@ -10945,5 +10556,5 @@
               /*256:out  */ X86_MXCSR_DM | X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED,
               /*xcpt?    */ false, false },
-#endif /* TODO_X86_MXCSR_UE */
+#endif /* TODO_X86_MXCSR_UE_IEM */
  /*35|36*/{ { /*src2     */ { FP32_DENORM_MAX(0), FP32_0(0),          FP32_DENORM_MAX(0), FP32_DENORM_MAX(0),                                   FP32_DENORM_MAX(0), FP32_DENORM_MAX(1),                                   FP32_0(0),          FP32_0(0)          } },
             { /*src1     */ { FP32_0(0),          FP32_DENORM_MAX(1), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0),                                   FP32_0(0),          FP32_DENORM_MAX(1),                                   FP32_DENORM_MAX(0), FP32_DENORM_MAX(1) } },
@@ -10974,5 +10585,5 @@
               /*256:out  */ X86_MXCSR_DE | BS3_MXCSR_DM_FIXED,
               /*xcpt?    */ false, false },
-#ifdef TODO_X86_MXCSR_UE /** @todo THIS FAILS ON IEM: X86_MXCSR_UE not set in 256:out */
+#ifdef TODO_X86_MXCSR_UE_IEM /** @todo THIS FAILS ON IEM: X86_MXCSR_UE not set in 256:out */
  /*--|40*/{ { /*src2     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0),          FP32_0(0), FP32_0(0), FP32_0(0)} },
             { /*src1     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0)} },
@@ -10982,5 +10593,5 @@
               /*256:out  */ X86_MXCSR_DM | X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED,
               /*xcpt?    */ false, false },
-#endif /* TODO_X86_MXCSR_UE */
+#endif /* TODO_X86_MXCSR_UE_IEM */
  /*39|41*/{ { /*src2     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0),          FP32_0(0), FP32_0(0), FP32_0(0)} },
             { /*src1     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0)} },
@@ -11079,5 +10690,5 @@
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     unsigned const                         iTest       = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
-    return bs3CpuInstr4_WorkerTestType1A(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+    return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
                                         g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
 }
@@ -11589,5 +11200,5 @@
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     unsigned const                         iTest       = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
-    return bs3CpuInstr4_WorkerTestType1A(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+    return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
                                         g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
 }
@@ -11909,5 +11520,5 @@
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     unsigned const                         iTest       = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
-    return bs3CpuInstr4_WorkerTestType1A(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+    return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
                                         g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
 }
@@ -12231,5 +11842,5 @@
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     unsigned const                         iTest       = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
-    return bs3CpuInstr4_WorkerTestType1A(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+    return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
                                         g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
 }
@@ -12688,5 +12299,5 @@
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     unsigned const                         iTest       = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
-    return bs3CpuInstr4_WorkerTestType1A(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+    return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
                                         g_aXcptConfig3, RT_ELEMENTS(g_aXcptConfig3));
 }
@@ -13147,5 +12758,5 @@
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     unsigned const                         iTest       = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
-    return bs3CpuInstr4_WorkerTestType1A(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+    return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
                                         g_aXcptConfig3, RT_ELEMENTS(g_aXcptConfig3));
 }
@@ -13467,5 +13078,5 @@
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     unsigned const                         iTest       = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
-    return bs3CpuInstr4_WorkerTestType1A(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+    return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
                                         g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
 }
@@ -13789,5 +13400,5 @@
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     unsigned const                         iTest       = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
-    return bs3CpuInstr4_WorkerTestType1A(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+    return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
                                         g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
 }
@@ -14246,5 +13857,5 @@
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     unsigned const                         iTest       = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
-    return bs3CpuInstr4_WorkerTestType1A(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+    return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
                                         g_aXcptConfig3, RT_ELEMENTS(g_aXcptConfig3));
 }
@@ -14705,5 +14316,5 @@
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     unsigned const                         iTest       = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
-    return bs3CpuInstr4_WorkerTestType1A(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+    return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
                                         g_aXcptConfig3, RT_ELEMENTS(g_aXcptConfig3));
 }
@@ -15068,6 +14679,6 @@
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     unsigned const                         iTest       = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
-    return bs3CpuInstr4_WorkerTestType1A(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
-                                         g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
+    return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+                                        g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
 }
 
@@ -15389,5 +15000,5 @@
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     unsigned const                         iTest       = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
-    return bs3CpuInstr4_WorkerTestType1A(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+    return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
                                         g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
 }
@@ -15666,5 +15277,5 @@
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     unsigned const                         iTest       = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
-    return bs3CpuInstr4_WorkerTestType1A(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+    return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
                                         g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
 }
