Index: trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4-template.mac
===================================================================
--- trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4-template.mac	(revision 106233)
+++ trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4-template.mac	(revision 106234)
@@ -631,4 +631,33 @@
 
 ;
+;; [v]rcpps
+;
+EMIT_INSTR_PLUS_ICEBP       rcpps, XMM1, XMM2
+EMIT_INSTR_PLUS_ICEBP       rcpps, XMM1, FSxBX
+EMIT_INSTR_PLUS_ICEBP_C64   rcpps, XMM8, XMM9
+EMIT_INSTR_PLUS_ICEBP_C64   rcpps, XMM8, FSxBX
+
+EMIT_INSTR_PLUS_ICEBP       vrcpps, XMM1, XMM2
+EMIT_INSTR_PLUS_ICEBP       vrcpps, XMM1, FSxBX
+EMIT_INSTR_PLUS_ICEBP_C64   vrcpps, XMM8, XMM9
+EMIT_INSTR_PLUS_ICEBP_C64   vrcpps, XMM8, FSxBX
+
+EMIT_INSTR_PLUS_ICEBP       vrcpps, YMM1, YMM2
+EMIT_INSTR_PLUS_ICEBP       vrcpps, YMM1, FSxBX
+EMIT_INSTR_PLUS_ICEBP_C64   vrcpps, YMM8, YMM9
+EMIT_INSTR_PLUS_ICEBP_C64   vrcpps, YMM8, FSxBX
+
+;
+;; [v]rcpss
+;
+EMIT_INSTR_PLUS_ICEBP       rcpss, XMM1, XMM2
+EMIT_INSTR_PLUS_ICEBP       rcpss, XMM1, FSxBX
+
+EMIT_INSTR_PLUS_ICEBP       vrcpss, XMM1,  XMM2,  XMM3
+EMIT_INSTR_PLUS_ICEBP       vrcpss, XMM1,  XMM2,  FSxBX
+EMIT_INSTR_PLUS_ICEBP_C64   vrcpss, XMM13, XMM14, XMM15
+EMIT_INSTR_PLUS_ICEBP_C64   vrcpss, XMM13, XMM14, FSxBX
+
+;
 ;; [v]sqrtps
 ;
@@ -666,22 +695,4 @@
 EMIT_INSTR_PLUS_ICEBP_C64   vsqrtpd, YMM8, FSxBX
 
-;
-;; [v]rcpps
-;
-EMIT_INSTR_PLUS_ICEBP       rcpps, XMM1, XMM2
-EMIT_INSTR_PLUS_ICEBP       rcpps, XMM1, FSxBX
-EMIT_INSTR_PLUS_ICEBP_C64   rcpps, XMM8, XMM9
-EMIT_INSTR_PLUS_ICEBP_C64   rcpps, XMM8, FSxBX
-
-EMIT_INSTR_PLUS_ICEBP       vrcpps, XMM1, XMM2
-EMIT_INSTR_PLUS_ICEBP       vrcpps, XMM1, FSxBX
-EMIT_INSTR_PLUS_ICEBP_C64   vrcpps, XMM8, XMM9
-EMIT_INSTR_PLUS_ICEBP_C64   vrcpps, XMM8, FSxBX
-
-EMIT_INSTR_PLUS_ICEBP       vrcpps, YMM1, YMM2
-EMIT_INSTR_PLUS_ICEBP       vrcpps, YMM1, FSxBX
-EMIT_INSTR_PLUS_ICEBP_C64   vrcpps, YMM8, YMM9
-EMIT_INSTR_PLUS_ICEBP_C64   vrcpps, YMM8, FSxBX
-
 %endif ; BS3_INSTANTIATING_CMN
 
Index: trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32
===================================================================
--- trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32	(revision 106233)
+++ trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32	(revision 106234)
@@ -688,4 +688,31 @@
     { 0, 0,  0,  1,      1,       1,         1,   1,       0,        0,      0,      X86_XCPT_GP, X86_XCPT_DB }, /* #10 */
     { 0, 0,  0,  1,      1,       1,         1,   1,       0,        1,      0,      X86_XCPT_GP, X86_XCPT_DB }, /* #11 */
+    { 0, 0,  0,  1,      1,       1,         1,   1,       1,        1,      0,      X86_XCPT_DB, X86_XCPT_DB }, /* #12 */
+    /* AMD only: */
+    { 0, 0,  0,  1,      1,       1,         1,   1,       0,        0,      1,      X86_XCPT_DB, X86_XCPT_GP }, /* #13 */
+    { 0, 0,  0,  1,      1,       1,         1,   1,       1,        1,      1,      X86_XCPT_AC, X86_XCPT_GP }, /* #14 */
+};
+
+/** Exceptions type 5 (<16 byte memory arguments and not floating-point exceptions). */
+static const BS3CPUINSTR4_CONFIG_T g_aXcptConfig5[] =
+{
+/*
+ *   X87 SSE SSE SSE     AVX      SSE        AVX  AVX      SSE       AVX     AMD/SSE <-- applies to
+ *                               +AVX       +AVX +AMD/SSE           +AMD/SSE
+ *   CR0 CR0 CR0 CR4     CR4      CR4        XCR0 XCR0                       MXCSR
+ *   MP, EM, TS, OSFXSR, OSXSAVE, OSXMMEXCPT SSE, AVX,     fAligned, AC/AM,  MM,     bXcptSse,    bXcptAvx */
+    { 0, 0,  0,  1,      1,       1,         1,   1,       1,        0,      0,      X86_XCPT_DB, X86_XCPT_DB }, /* #0 */
+    { 0, 0,  0,  1,      1,       0,         1,   1,       1,        0,      0,      X86_XCPT_DB, X86_XCPT_DB }, /* #1 */
+    { 1, 0,  0,  1,      1,       1,         1,   1,       1,        0,      0,      X86_XCPT_DB, X86_XCPT_DB }, /* #2 */
+    { 0, 1,  0,  1,      1,       1,         1,   1,       1,        0,      0,      X86_XCPT_UD, X86_XCPT_DB }, /* #3 */
+    { 0, 0,  1,  1,      1,       1,         1,   1,       1,        0,      0,      X86_XCPT_NM, X86_XCPT_NM }, /* #4 */
+    { 0, 1,  1,  1,      1,       1,         1,   1,       1,        0,      0,      X86_XCPT_UD, X86_XCPT_NM }, /* #5 */
+    { 0, 0,  0,  0,      1,       1,         1,   1,       1,        0,      0,      X86_XCPT_UD, X86_XCPT_DB }, /* #6 */
+    { 0, 0,  0,  1,      0,       1,         1,   1,       1,        0,      0,      X86_XCPT_DB, X86_XCPT_UD }, /* #7 */
+    { 0, 0,  0,  1,      1,       1,         1,   0,       1,        0,      0,      X86_XCPT_DB, X86_XCPT_UD }, /* #8 */
+    { 0, 0,  0,  1,      1,       1,         0,   0,       1,        0,      0,      X86_XCPT_DB, X86_XCPT_UD }, /* #9 */
+    /* Memory misalignment and alignment checks: */
+    { 0, 0,  0,  1,      1,       1,         1,   1,       0,        0,      0,      X86_XCPT_DB, X86_XCPT_DB }, /* #10 */
+    { 0, 0,  0,  1,      1,       1,         1,   1,       0,        1,      0,      X86_XCPT_AC, X86_XCPT_AC }, /* #11 */
     { 0, 0,  0,  1,      1,       1,         1,   1,       1,        1,      0,      X86_XCPT_DB, X86_XCPT_DB }, /* #12 */
     /* AMD only: */
@@ -13227,4 +13254,95 @@
 
 /*
+ * [V]RCPSS.
+ */
+BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_rcpss(uint8_t bMode)
+{
+    static BS3CPUINSTR4_TEST1_VALUES_SS_T const s_aValues[] =
+    {
+    /*
+     * Zero.
+     */
+    /* 0*/{ { /*src1     */ { FP32_0(0),   FP32_RAND_x7_V7 } },
+            { /*src2     */ { FP32_0(0),   FP32_RAND_x7_V2 } },
+            { /* =>      */ { FP32_INF(0), FP32_RAND_x7_V2 } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
+              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*256:out  */ -1,
+              /*xcpt?    */ false, false },
+          { { /*src1     */ { FP32_0(1),   FP32_RAND_x7_V0 } },
+            { /*src2     */ { FP32_0(1),   FP32_RAND_x7_V1 } },
+            { /* =>      */ { FP32_INF(1), FP32_RAND_x7_V1 } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
+              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*256:out  */ -1,
+              /*xcpt?    */ false, false },
+          { { /*src1     */ { FP32_0(1),   FP32_RAND_x7_V2 } },
+            { /*src2     */ { FP32_0(1),   FP32_RAND_x7_V1 } },
+            { /* =>      */ { FP32_INF(1), FP32_RAND_x7_V1 } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*256:out  */ -1,
+              /*xcpt?    */ false, false },
+          { { /*src1     */ { FP32_0(1),   FP32_RAND_x7_V0 } },
+            { /*src2     */ { FP32_0(1),   FP32_RAND_x7_V3 } },
+            { /* =>      */ { FP32_INF(1), FP32_RAND_x7_V3 } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
+              /*256:out  */ -1,
+              /*xcpt?    */ false, false },
+          { { /*src1     */ { FP32_0(1),   FP32_RAND_x7_V0 } },
+            { /*src2     */ { FP32_0(1),   FP32_RAND_x7_V3 } },
+            { /* =>      */ { FP32_INF(1), FP32_RAND_x7_V3 } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
+              /*256:out  */ -1,
+              /*xcpt?    */ false, false },
+          { { /*src1     */ { FP32_0(0),   FP32_RAND_x7_V0 } },
+            { /*src2     */ { FP32_0(0),   FP32_RAND_x7_V3 } },
+            { /* =>      */ { FP32_INF(0), FP32_RAND_x7_V3 } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ,
+              /*256:out  */ -1,
+              /*xcpt?    */ false, false },
+    };
+
+#define PASS_s_aValues RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues
+    static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
+    {
+        { bs3CpuInstr4_rcpss_XMM1_XMM2_icebp_c16,  255, RM_REG, T_SSE, 1, 1, 2,   PASS_s_aValues },
+        { bs3CpuInstr4_rcpss_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, PASS_s_aValues },
+
+        { bs3CpuInstr4_vrcpss_XMM1_XMM2_XMM3_icebp_c16,  X86_XCPT_AC, RM_REG, T_AVX_128, 1, 2, 3,   PASS_s_aValues },
+        { bs3CpuInstr4_vrcpss_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, PASS_s_aValues },
+    };
+    static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
+    {
+        { bs3CpuInstr4_rcpss_XMM1_XMM2_icebp_c32,  255, RM_REG, T_SSE, 1, 1, 2,   PASS_s_aValues },
+        { bs3CpuInstr4_rcpss_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, PASS_s_aValues },
+
+        { bs3CpuInstr4_vrcpss_XMM1_XMM2_XMM3_icebp_c32,  X86_XCPT_AC, RM_REG, T_AVX_128, 1,  2, 3,   PASS_s_aValues },
+        { bs3CpuInstr4_vrcpss_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1,  2, 255, PASS_s_aValues },
+    };
+    static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
+    {
+        { bs3CpuInstr4_rcpss_XMM1_XMM2_icebp_c64,  255, RM_REG, T_SSE, 1, 1, 2,   PASS_s_aValues },
+        { bs3CpuInstr4_rcpss_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, PASS_s_aValues },
+
+        { bs3CpuInstr4_vrcpss_XMM1_XMM2_XMM3_icebp_c64,  X86_XCPT_AC, RM_REG, T_AVX_128, 1,  2, 3,   PASS_s_aValues },
+        { bs3CpuInstr4_vrcpss_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1,  2, 255, PASS_s_aValues },
+
+        { bs3CpuInstr4_vrcpss_XMM13_XMM14_XMM15_icebp_c64, X86_XCPT_AC, RM_REG, T_AVX_128, 13, 14, 15,  PASS_s_aValues },
+        { bs3CpuInstr4_vrcpss_XMM13_XMM14_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 13, 14, 255, PASS_s_aValues },
+    };
+#undef PASS_s_aValues
+
+    static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
+    unsigned const                         iTest       = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
+    return bs3CpuInstr4_WorkerTestType1A(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+                                         g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5));
+}
+
+
+/*
  * [V]SQRTPS.
  */
@@ -13828,4 +13946,5 @@
         { "[v]minsd",       bs3CpuInstr4_v_minsd,    0 },
         { "[v]rcpps",       bs3CpuInstr4_v_rcpps,    0 },
+        { "[v]rcpss",       bs3CpuInstr4_v_rcpss,    0 },
         { "[v]sqrtps",      bs3CpuInstr4_v_sqrtps,   0 },
         { "[v]sqrtpd",      bs3CpuInstr4_v_sqrtpd,   0 },
