Changeset 106253 in vbox

Timestamp:

Oct 9, 2024 8:03:43 AM (7 weeks ago)

Author:

vboxsync

Message:

ValidationKit/bootsectors: bugref:10658 SIMD FP testcase: [v]rcpss -- While the upper single-precision values (bits [127:32]) from the first operand (xmm2 in VEX.VRCPSS variant) is copied to the destination, the first 32-bits are ignored.

File:

• trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32 (modified) (1 diff)

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32

@@ -13263 +13263 @@
      * Zero.
      */
-    /* 0*/{ { /*src1     */ { FP32_0(0),   FP32_RAND_x7_V7 } },
-            { /*src2     */ { FP32_0(0),   FP32_RAND_x7_V2 } },
-            { /* =>      */ { FP32_INF(0), FP32_RAND_x7_V2 } },
+    /* 0*/{ { /*src1     */ { FP32_0(0),       FP32_RAND_x7_V7 } },
+            { /*src2     */ { FP32_RAND_V2(0), FP32_RAND_x7_V2 } },
+            { /* =>      */ { FP32_INF(0),     FP32_RAND_x7_V2 } },
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
               /*128:out  */ X86_MXCSR_XCPT_MASK,
               /*256:out  */ -1,
               /*xcpt?    */ false, false },
-          { { /*src1     */ { FP32_0(1),   FP32_RAND_x7_V0 } },
-            { /*src2     */ { FP32_0(1),   FP32_RAND_x7_V1 } },
-            { /* =>      */ { FP32_INF(1), FP32_RAND_x7_V1 } },
+          { { /*src1     */ { FP32_0(1),       FP32_RAND_x7_V0 } },
+            { /*src2     */ { FP32_RAND_V3(1), FP32_RAND_x7_V1 } },
+            { /* =>      */ { FP32_INF(1),     FP32_RAND_x7_V1 } },
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
               /*128:out  */ X86_MXCSR_XCPT_MASK,
               /*256:out  */ -1,
               /*xcpt?    */ false, false },
-          { { /*src1     */ { FP32_0(1),   FP32_RAND_x7_V2 } },
-            { /*src2     */ { FP32_0(1),   FP32_RAND_x7_V1 } },
-            { /* =>      */ { FP32_INF(1), FP32_RAND_x7_V1 } },
+          { { /*src1     */ { FP32_0(1),       FP32_RAND_x7_V2 } },
+            { /*src2     */ { FP32_RAND_V5(0), FP32_RAND_x7_V1 } },
+            { /* =>      */ { FP32_INF(1),     FP32_RAND_x7_V1 } },
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
               /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
               /*256:out  */ -1,
               /*xcpt?    */ false, false },
-          { { /*src1     */ { FP32_0(1),   FP32_RAND_x7_V0 } },
-            { /*src2     */ { FP32_0(1),   FP32_RAND_x7_V3 } },
-            { /* =>      */ { FP32_INF(1), FP32_RAND_x7_V3 } },
+          { { /*src1     */ { FP32_0(1),       FP32_RAND_x7_V0 } },
+            { /*src2     */ { FP32_RAND_V5(0), FP32_RAND_x7_V3 } },
+            { /* =>      */ { FP32_INF(1),     FP32_RAND_x7_V3 } },
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
               /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
               /*256:out  */ -1,
               /*xcpt?    */ false, false },
-          { { /*src1     */ { FP32_0(1),   FP32_RAND_x7_V0 } },
-            { /*src2     */ { FP32_0(1),   FP32_RAND_x7_V3 } },
-            { /* =>      */ { FP32_INF(1), FP32_RAND_x7_V3 } },
+          { { /*src1     */ { FP32_0(1),       FP32_RAND_x7_V0 } },
+            { /*src2     */ { FP32_RAND_V1(1), FP32_RAND_x7_V3 } },
+            { /* =>      */ { FP32_INF(1),     FP32_RAND_x7_V3 } },
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
               /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
               /*256:out  */ -1,
               /*xcpt?    */ false, false },
-          { { /*src1     */ { FP32_0(0),   FP32_RAND_x7_V0 } },
-            { /*src2     */ { FP32_0(0),   FP32_RAND_x7_V3 } },
-            { /* =>      */ { FP32_INF(0), FP32_RAND_x7_V3 } },
+          { { /*src1     */ { FP32_0(0),       FP32_RAND_x7_V0 } },
+            { /*src2     */ { FP32_RAND_V0(1), FP32_RAND_x7_V3 } },
+            { /* =>      */ { FP32_INF(0),     FP32_RAND_x7_V3 } },
               /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ,
               /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ,