Changeset 106279 in vbox
- Timestamp:
- Oct 10, 2024 8:55:45 AM (7 weeks ago)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32
r106277 r106279 12924 12924 { /*unused */ { FP32_ROW_UNUSED } }, 12925 12925 { /* => */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0) } }, 12926 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,12927 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,12928 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_DAZ | X86_MXCSR_RC_UP },12926 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 12927 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 12928 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_DAZ | X86_MXCSR_RC_UP }, 12929 12929 { { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 12930 12930 { /*unused */ { FP32_ROW_UNUSED } }, 12931 12931 { /* => */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0) } }, 12932 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,12933 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,12934 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN },12932 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 12933 /*128:out */ X86_MXCSR_RC_DOWN, 12934 /*256:out */ X86_MXCSR_RC_DOWN }, 12935 12935 { { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 12936 12936 { /*unused */ { FP32_ROW_UNUSED } }, 12937 12937 { /* => */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0) } }, 12938 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12939 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12940 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO },12938 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 12939 /*128:out */ X86_MXCSR_RC_ZERO, 12940 /*256:out */ X86_MXCSR_RC_ZERO }, 12941 12941 /* 12942 12942 * Infinity. … … 12951 12951 { /*unused */ { FP32_ROW_UNUSED } }, 12952 12952 { /* => */ { FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0) } }, 12953 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12954 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12955 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO },12953 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 12954 /*128:out */ X86_MXCSR_RC_ZERO, 12955 /*256:out */ X86_MXCSR_RC_ZERO }, 12956 12956 { { /*src1 */ { FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(0) } }, 12957 12957 { /*unused */ { FP32_ROW_UNUSED } }, 12958 12958 { /* => */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0) } }, 12959 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,12960 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,12961 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },12959 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 12960 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 12961 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN }, 12962 12962 { { /*src1 */ { FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1) } }, 12963 12963 { /*unused */ { FP32_ROW_UNUSED } }, 12964 12964 { /* => */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1) } }, 12965 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,12966 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,12967 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP },12965 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 12966 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 12967 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP }, 12968 12968 /* 12969 12969 * Normals. … … 12979 12979 FP32_V(0, 0x7ff000, RTFLOAT32U_EXP_BIAS - 1), 12980 12980 FP32_V(1, 0x7ff000, RTFLOAT32U_EXP_BIAS - 1) } }, 12981 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ,12982 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ,12983 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ },12981 /*mxcsr:in */ X86_MXCSR_FZ, 12982 /*128:out */ X86_MXCSR_FZ, 12983 /*256:out */ X86_MXCSR_FZ }, 12984 12984 { { /*src1 */ { FP32_1(0), FP32_1(1), FP32_1(0), FP32_1(1), FP32_1(0), FP32_1(1), FP32_1(0), FP32_1(1) } }, 12985 12985 { /*unused */ { FP32_ROW_UNUSED } }, … … 12992 12992 FP32_V(0, 0x7ff000, RTFLOAT32U_EXP_BIAS - 1), 12993 12993 FP32_V(1, 0x7ff000, RTFLOAT32U_EXP_BIAS - 1) } }, 12994 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,12995 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,12996 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN },12994 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 12995 /*128:out */ X86_MXCSR_RC_DOWN, 12996 /*256:out */ X86_MXCSR_RC_DOWN }, 12997 12997 { { /*src1 */ { FP32_1(0), FP32_1(1), FP32_1(0), FP32_1(1), FP32_1(0), FP32_1(1), FP32_1(0), FP32_1(1) } }, 12998 12998 { /*unused */ { FP32_ROW_UNUSED } }, … … 13005 13005 FP32_V(0, 0x7ff000, RTFLOAT32U_EXP_BIAS - 1), 13006 13006 FP32_V(1, 0x7ff000, RTFLOAT32U_EXP_BIAS - 1) } }, 13007 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,13008 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,13009 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP },13007 /*mxcsr:in */ X86_MXCSR_RC_UP, 13008 /*128:out */ X86_MXCSR_RC_UP, 13009 /*256:out */ X86_MXCSR_RC_UP }, 13010 13010 { { /*src1 */ { FP32_1(0), FP32_1(1), FP32_1(0), FP32_1(1), FP32_1(0), FP32_1(1), FP32_1(0), FP32_1(1) } }, 13011 13011 { /*unused */ { FP32_ROW_UNUSED } }, … … 13018 13018 FP32_V(0, 0x7ff000, RTFLOAT32U_EXP_BIAS - 1), 13019 13019 FP32_V(1, 0x7ff000, RTFLOAT32U_EXP_BIAS - 1) } }, 13020 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,13021 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,13022 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO },13020 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 13021 /*128:out */ X86_MXCSR_RC_ZERO, 13022 /*256:out */ X86_MXCSR_RC_ZERO }, 13023 13023 { { /*src1 */ { FP32_V(0, 0, RTFLOAT32U_EXP_BIAS + 1)/* 2*/, 13024 13024 FP32_V(1, 0, RTFLOAT32U_EXP_BIAS + 2)/* -4*/, … … 13038 13038 FP32_0(1), 13039 13039 FP32_V(1, 0x7ff000, RTFLOAT32U_EXP_MAX - 3) } }, 13040 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,13041 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,13042 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO },13040 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 13041 /*128:out */ X86_MXCSR_RC_ZERO, 13042 /*256:out */ X86_MXCSR_RC_ZERO }, 13043 13043 { { /*src1 */ { FP32_V(0, 0x7fe800, RTFLOAT32U_EXP_BIAS - 2)/* 1.11111111110100000000000(bin)*2^0 */, 13044 13044 FP32_V(0, 0xc01, RTFLOAT32U_EXP_BIAS - 1)/* 1.00000000000110000000001(bin)*2^1 */, … … 13058 13058 FP32_0(0), 13059 13059 FP32_V(0, 4096, 1) } }, 13060 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,13061 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,13062 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO },13060 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 13061 /*128:out */ X86_MXCSR_RC_ZERO, 13062 /*256:out */ X86_MXCSR_RC_ZERO }, 13063 13063 { { /*src1 */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, 13064 13064 FP32_V(0, 0x1ea980, 0x8f)/*81235*/, … … 13078 13078 FP32_V(1, 8384512, 128), 13079 13079 FP32_V(1, 1775616, 119) } }, 13080 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,13081 /*128:out */ X86_MXCSR_XCPT_MASK,13082 /*256:out */ X86_MXCSR_XCPT_MASK},13080 /*mxcsr:in */ 0, 13081 /*128:out */ 0, 13082 /*256:out */ 0 }, 13083 13083 /* 13084 13084 * Denormals. … … 13093 13093 { /*unused */ { FP32_ROW_UNUSED } }, 13094 13094 { /* => */ { FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(0) } }, 13095 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,13096 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,13097 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN },13095 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 13096 /*128:out */ X86_MXCSR_RC_DOWN, 13097 /*256:out */ X86_MXCSR_RC_DOWN }, 13098 13098 { { /*src1 */ { FP32_DENORM_MIN(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MAX(1), FP32_DENORM_MIN(0), FP32_DENORM_MAX(1), FP32_DENORM_MAX(1), FP32_DENORM_MIN(0) } }, 13099 13099 { /*unused */ { FP32_ROW_UNUSED } }, 13100 13100 { /* => */ { FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(0) } }, 13101 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,13102 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,13103 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO },13101 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 13102 /*128:out */ X86_MXCSR_RC_ZERO, 13103 /*256:out */ X86_MXCSR_RC_ZERO }, 13104 13104 { { /*src1 */ { FP32_DENORM_MIN(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MAX(1), FP32_DENORM_MIN(0), FP32_DENORM_MAX(1), FP32_DENORM_MAX(1), FP32_DENORM_MIN(0) } }, 13105 13105 { /*unused */ { FP32_ROW_UNUSED } }, 13106 13106 { /* => */ { FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(0) } }, 13107 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP | X86_MXCSR_FZ,13108 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP | X86_MXCSR_FZ,13109 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP | X86_MXCSR_FZ },13107 /*mxcsr:in */ X86_MXCSR_RC_UP | X86_MXCSR_FZ, 13108 /*128:out */ X86_MXCSR_RC_UP | X86_MXCSR_FZ, 13109 /*256:out */ X86_MXCSR_RC_UP | X86_MXCSR_FZ }, 13110 13110 { { /*src1 */ { FP32_DENORM_V0(0), FP32_DENORM_V1(0), FP32_DENORM_V2(0), FP32_DENORM_V3(0), FP32_DENORM_V4(0), FP32_DENORM_V5(0), FP32_DENORM_V6(0), FP32_DENORM_V7(0) } }, 13111 13111 { /*unused */ { FP32_ROW_UNUSED } }, 13112 13112 { /* => */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0) } }, 13113 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,13114 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,13115 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP },13113 /*mxcsr:in */ X86_MXCSR_RC_UP, 13114 /*128:out */ X86_MXCSR_RC_UP, 13115 /*256:out */ X86_MXCSR_RC_UP }, 13116 13116 { { /*src1 */ { FP32_DENORM_V0(1), FP32_DENORM_V1(1), FP32_DENORM_V2(1), FP32_DENORM_V3(1), FP32_DENORM_V4(1), FP32_DENORM_V5(1), FP32_DENORM_V6(1), FP32_DENORM_V7(1) } }, 13117 13117 { /*unused */ { FP32_ROW_UNUSED } }, 13118 13118 { /* => */ { FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1) } }, 13119 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,13120 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,13121 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO },13119 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 13120 /*128:out */ X86_MXCSR_RC_ZERO, 13121 /*256:out */ X86_MXCSR_RC_ZERO }, 13122 13122 { { /*src1 */ { FP32_DENORM_V7(1), FP32_DENORM_V6(0), FP32_DENORM_V5(1), FP32_DENORM_V4(0), FP32_DENORM_V3(1), FP32_DENORM_V2(0), FP32_DENORM_V1(1), FP32_DENORM_V0(0) } }, 13123 13123 { /*unused */ { FP32_ROW_UNUSED } }, 13124 13124 { /* => */ { FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(0) } }, 13125 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,13126 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,13127 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN },13125 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 13126 /*128:out */ X86_MXCSR_RC_DOWN, 13127 /*256:out */ X86_MXCSR_RC_DOWN }, 13128 13128 { { /*src1 */ { FP32_DENORM_V7(1), FP32_DENORM_V6(0), FP32_DENORM_V5(1), FP32_DENORM_V4(0), FP32_DENORM_V3(1), FP32_DENORM_V2(0), FP32_DENORM_V1(1), FP32_DENORM_V0(0) } }, 13129 13129 { /*unused */ { FP32_ROW_UNUSED } }, 13130 13130 { /* => */ { FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(0) } }, 13131 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_DAZ,13132 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_DAZ,13133 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_DAZ },13131 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_DAZ, 13132 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_DAZ, 13133 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_DAZ }, 13134 13134 /** @todo More Denormals. */ 13135 13135 /* … … 13145 13145 { /*unused */ { FP32_ROW_UNUSED } }, 13146 13146 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(1, 1), FP32_QNAN(0), FP32_QNAN(1), FP32_QNAN_V(1, 1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN_V(1, 1) } }, 13147 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,13148 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,13149 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },13147 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 13148 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 13149 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO }, 13150 13150 { { /*src1 */ { FP32_SNAN(0), FP32_SNAN(1), FP32_QNAN(0), FP32_QNAN(1), FP32_SNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_SNAN(1) } }, 13151 13151 { /*unused */ { FP32_ROW_UNUSED } }, 13152 13152 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(1, 1), FP32_QNAN(0), FP32_QNAN(1), FP32_QNAN_V(1, 1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN_V(1, 1) } }, 13153 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,13154 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,13155 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP },13153 /*mxcsr:in */ X86_MXCSR_RC_UP, 13154 /*128:out */ X86_MXCSR_RC_UP, 13155 /*256:out */ X86_MXCSR_RC_UP }, 13156 13156 { { /*src1 */ { FP32_SNAN(0), FP32_SNAN(1), FP32_QNAN(0), FP32_QNAN(1), FP32_SNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_SNAN(1) } }, 13157 13157 { /*unused */ { FP32_ROW_UNUSED } }, 13158 13158 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(1, 1), FP32_QNAN(0), FP32_QNAN(1), FP32_QNAN_V(1, 1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN_V(1, 1) } }, 13159 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,13160 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,13161 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },13159 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 13160 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 13161 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN }, 13162 13162 { { /*src1 */ { FP32_SNAN_V0(0), FP32_SNAN_V1(1), FP32_SNAN_V2(0), FP32_SNAN_V3(1), FP32_SNAN_V4(1), FP32_SNAN_V5(1), FP32_SNAN_V6(1), FP32_SNAN_V7(1) } }, 13163 13163 { /*unused */ { FP32_ROW_UNUSED } }, 13164 13164 { /* => */ { FP32_QNAN_V0(0), FP32_QNAN_V1(1), FP32_QNAN_V2(0), FP32_QNAN_V3(1), FP32_QNAN_V4(1), FP32_QNAN_V5(1), FP32_QNAN_V6(1), FP32_QNAN_V7(1) } }, 13165 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,13166 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,13167 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },13165 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 13166 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 13167 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO }, 13168 13168 { { /*src1 */ { FP32_QNAN_V0(0), FP32_QNAN_V0(1), FP32_QNAN_V0(0), FP32_QNAN_V0(1), FP32_QNAN_V0(1), FP32_QNAN_V0(0), FP32_QNAN_V0(1), FP32_QNAN_V0(1) } }, 13169 13169 { /*unused */ { FP32_ROW_UNUSED } }, 13170 13170 { /* => */ { FP32_QNAN_V0(0), FP32_QNAN_V0(1), FP32_QNAN_V0(0), FP32_QNAN_V0(1), FP32_QNAN_V0(1), FP32_QNAN_V0(0), FP32_QNAN_V0(1), FP32_QNAN_V0(1) } }, 13171 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,13172 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,13173 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP },13171 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 13172 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 13173 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP }, 13174 13174 { { /*src1 */ { FP32_QNAN_V0(1), FP32_SNAN_V0(1), FP32_QNAN_V1(1), FP32_SNAN_V0(1), FP32_QNAN_V7(1), FP32_SNAN_V7(1), FP32_QNAN_V3(1), FP32_SNAN_V0(1) } }, 13175 13175 { /*unused */ { FP32_ROW_UNUSED } }, 13176 13176 { /* => */ { FP32_QNAN_V0(1), FP32_QNAN_V0(1), FP32_QNAN_V1(1), FP32_QNAN_V0(1), FP32_QNAN_V7(1), FP32_QNAN_V7(1), FP32_QNAN_V3(1), FP32_QNAN_V0(1) } }, 13177 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,13178 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,13179 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP },13177 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 13178 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 13179 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP }, 13180 13180 { { /*src1 */ { FP32_QNAN_V0(1), FP32_SNAN_V0(1), FP32_QNAN_V1(1), FP32_SNAN_V3(1), FP32_QNAN_V4(1), FP32_SNAN_V5(1), FP32_QNAN_V6(1), FP32_SNAN_V7(1) } }, 13181 13181 { /*unused */ { FP32_ROW_UNUSED } }, 13182 13182 { /* => */ { FP32_QNAN_V0(1), FP32_QNAN_V0(1), FP32_QNAN_V1(1), FP32_QNAN_V3(1), FP32_QNAN_V4(1), FP32_QNAN_V5(1), FP32_QNAN_V6(1), FP32_QNAN_V7(1) } }, 13183 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,13184 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,13185 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ },13183 /*mxcsr:in */ X86_MXCSR_DAZ, 13184 /*128:out */ X86_MXCSR_DAZ, 13185 /*256:out */ X86_MXCSR_DAZ }, 13186 13186 }; 13187 13187 … … 13262 13262 { /*src2 */ { FP32_RAND_V5(0), FP32_RAND_x7_V1 } }, 13263 13263 { /* => */ { FP32_INF(1), FP32_RAND_x7_V1 } }, 13264 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,13265 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,13264 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 13265 /*128:out */ X86_MXCSR_RC_ZERO, 13266 13266 /*256:out */ -1 }, 13267 13267 { { /*src1 */ { FP32_0(1), FP32_RAND_x7_V0 } }, 13268 13268 { /*src2 */ { FP32_RAND_V5(0), FP32_RAND_x7_V3 } }, 13269 13269 { /* => */ { FP32_INF(1), FP32_RAND_x7_V3 } }, 13270 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,13271 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,13270 /*mxcsr:in */ X86_MXCSR_RC_UP, 13271 /*128:out */ X86_MXCSR_RC_UP, 13272 13272 /*256:out */ -1 }, 13273 13273 { { /*src1 */ { FP32_0(1), FP32_RAND_x7_V0 } }, 13274 13274 { /*src2 */ { FP32_RAND_V1(1), FP32_RAND_x7_V3 } }, 13275 13275 { /* => */ { FP32_INF(1), FP32_RAND_x7_V3 } }, 13276 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,13277 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,13276 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 13277 /*128:out */ X86_MXCSR_RC_DOWN, 13278 13278 /*256:out */ -1 }, 13279 13279 { { /*src1 */ { FP32_0(0), FP32_RAND_x7_V0 } }, 13280 13280 { /*src2 */ { FP32_RAND_V0(1), FP32_RAND_x7_V3 } }, 13281 13281 { /* => */ { FP32_INF(0), FP32_RAND_x7_V3 } }, 13282 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ,13283 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ,13282 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 13283 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 13284 13284 /*256:out */ -1 }, 13285 13285 /* … … 13295 13295 { /*unused */ { FP32_RAND_V2(0), FP32_RAND_x7_V1 } }, 13296 13296 { /* => */ { FP32_0(0), FP32_RAND_x7_V1 } }, 13297 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,13298 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,13297 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 13298 /*128:out */ X86_MXCSR_RC_ZERO, 13299 13299 /*256:out */ -1 }, 13300 13300 { { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V5 } }, 13301 13301 { /*unused */ { FP32_RAND_V2(0), FP32_RAND_x7_V3 } }, 13302 13302 { /* => */ { FP32_0(0), FP32_RAND_x7_V3 } }, 13303 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,13304 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,13303 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 13304 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 13305 13305 /*256:out */ -1 }, 13306 13306 { { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V6 } }, 13307 13307 { /*unused */ { FP32_RAND_V2(0), FP32_RAND_x7_V0 } }, 13308 13308 { /* => */ { FP32_0(0), FP32_RAND_x7_V0 } }, 13309 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,13310 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,13309 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 13310 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 13311 13311 /*256:out */ -1 }, 13312 13312 { { /*src1 */ { FP32_INF(1), FP32_RAND_x7_V6 } }, 13313 13313 { /*unused */ { FP32_RAND_V2(0), FP32_RAND_x7_V2 } }, 13314 13314 { /* => */ { FP32_0(1), FP32_RAND_x7_V2 } }, 13315 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ,13316 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ,13315 /*mxcsr:in */ X86_MXCSR_FZ, 13316 /*128:out */ X86_MXCSR_FZ, 13317 13317 /*256:out */ -1 }, 13318 13318 { { /*src1 */ { FP32_INF(1), FP32_RAND_x7_V5 } }, 13319 13319 { /*unused */ { FP32_RAND_V2(0), FP32_RAND_x7_V1 } }, 13320 13320 { /* => */ { FP32_0(1), FP32_RAND_x7_V1 } }, 13321 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,13322 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,13321 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 13322 /*128:out */ X86_MXCSR_RC_ZERO, 13323 13323 /*256:out */ -1 }, 13324 13324 { { /*src1 */ { FP32_INF(1), FP32_RAND_x7_V6 } }, 13325 13325 { /*unused */ { FP32_RAND_V3(0), FP32_RAND_x7_V2 } }, 13326 13326 { /* => */ { FP32_0(1), FP32_RAND_x7_V2 } }, 13327 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,13328 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,13327 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 13328 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 13329 13329 /*256:out */ -1 }, 13330 13330 { { /*src1 */ { FP32_INF(1), FP32_RAND_x7_V3 } }, 13331 13331 { /*unused */ { FP32_RAND_V4(0), FP32_RAND_x7_V1 } }, 13332 13332 { /* => */ { FP32_0(1), FP32_RAND_x7_V1 } }, 13333 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,13334 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,13333 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 13334 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 13335 13335 /*256:out */ -1 }, 13336 13336 { { /*src1 */ { FP32_INF(1), FP32_RAND_x7_V6 } }, 13337 13337 { /*unused */ { FP32_RAND_V5(0), FP32_RAND_x7_V0 } }, 13338 13338 { /* => */ { FP32_0(1), FP32_RAND_x7_V0 } }, 13339 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ,13340 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ,13339 /*mxcsr:in */ X86_MXCSR_FZ, 13340 /*128:out */ X86_MXCSR_FZ, 13341 13341 /*256:out */ -1 }, 13342 13342 };
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