Changeset 106298 in vbox
- Timestamp:
- Oct 12, 2024 3:35:59 AM (7 weeks ago)
- File:
-
- 1 edited
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- Added
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trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32
r106285 r106298 729 729 { /*src1 */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } }, \ 730 730 { /* => */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } }, \ 731 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\732 /*128:out */ X86_MXCSR_XCPT_MASK,\733 /*256:out */ X86_MXCSR_XCPT_MASK },\731 /*mxcsr:in */ 0, \ 732 /*128:out */ 0, \ 733 /*256:out */ 0 }, \ 734 734 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \ 735 735 { /*src1 */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_MAX(0), FP32_SNAN_V2(0), FP32_SNAN_V6(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V4(0) } }, \ 736 736 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } }, \ 737 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\738 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\739 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE },\737 /*mxcsr:in */ 0, \ 738 /*128:out */ X86_MXCSR_IE, \ 739 /*256:out */ X86_MXCSR_IE }, \ 740 740 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_V1(0), FP32_SNAN_V1(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V5(0), FP32_SNAN_V6(0) } }, \ 741 741 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } }, \ 742 742 { /* => */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } }, \ 743 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ,\744 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,\745 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE },\743 /*mxcsr:in */ X86_MXCSR_FZ, \ 744 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_IE, \ 745 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_IE }, \ 746 746 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V7(0), FP32_SNAN_V1(0), FP32_SNAN_V6(0), FP32_SNAN_V1(0) } }, \ 747 747 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_MAX(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } }, \ 748 748 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_MAX(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V5(0), FP32_QNAN_V3(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0) } }, \ 749 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\750 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\751 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE },\749 /*mxcsr:in */ 0, \ 750 /*128:out */ X86_MXCSR_IE, \ 751 /*256:out */ X86_MXCSR_IE }, \ 752 752 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_MAX(1), FP32_NORM_V0(1), FP32_QNAN_V1(0), FP32_NORM_V3(0), FP32_QNAN_V3(1), FP32_NORM_V5(0), FP32_QNAN_V5(1) } }, \ 753 753 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V0(1), FP32_NORM_V2(1), FP32_QNAN_V2(0), FP32_NORM_V4(0), FP32_QNAN_V4(1), FP32_NORM_V6(1) } }, \ 754 754 { /* => */ { FP32_QNAN(0), FP32_QNAN_MAX(1), FP32_QNAN_MAX(1), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(1), FP32_QNAN_V4(1), FP32_QNAN_V5(1) } }, \ 755 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\756 /*128:out */ X86_MXCSR_XCPT_MASK,\757 /*256:out */ X86_MXCSR_XCPT_MASK },\755 /*mxcsr:in */ 0, \ 756 /*128:out */ 0, \ 757 /*256:out */ 0 }, \ 758 758 { { /*src2 */ { FP32_SNAN(1), FP32_SNAN_MAX(1), FP32_NORM_V0(1), FP32_SNAN_V1(0), FP32_NORM_V3(0), FP32_SNAN_V3(1), FP32_NORM_V5(0), FP32_SNAN_V5(1) } }, \ 759 759 { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V0(1), FP32_NORM_V2(1), FP32_SNAN_V2(1), FP32_NORM_V4(0), FP32_SNAN_V4(1), FP32_NORM_V6(1) } }, \ 760 760 { /* => */ { FP32_QNAN_V(1, 1), FP32_QNAN_MAX(1), FP32_QNAN_V0(1), FP32_QNAN_V1(0), FP32_QNAN_V2(1), FP32_QNAN_V3(1), FP32_QNAN_V4(1), FP32_QNAN_V5(1) } }, \ 761 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\762 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\763 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE },\761 /*mxcsr:in */ 0, \ 762 /*128:out */ X86_MXCSR_IE, \ 763 /*256:out */ X86_MXCSR_IE }, \ 764 764 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \ 765 765 { /*src1 */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } }, \ … … 807 807 { /*src1 */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V2(0) } }, \ 808 808 { /* => */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V2(0) } }, \ 809 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\810 /*128:out */ X86_MXCSR_XCPT_MASK,\811 /*256:out */ X86_MXCSR_XCPT_MASK },\809 /*mxcsr:in */ 0, \ 810 /*128:out */ 0, \ 811 /*256:out */ 0 }, \ 812 812 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V0(0), FP64_QNAN_V2(0) } }, \ 813 813 { /*src1 */ { FP64_SNAN(0), FP64_SNAN(0), FP64_SNAN_MAX(0), FP64_SNAN_V1(0) } }, \ 814 814 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_MAX(0), FP64_QNAN_V1(0) } }, \ 815 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\816 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\817 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE },\815 /*mxcsr:in */ 0, \ 816 /*128:out */ X86_MXCSR_IE, \ 817 /*256:out */ X86_MXCSR_IE }, \ 818 818 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN(0), FP64_SNAN_V0(0), FP64_SNAN_V1(0) } }, \ 819 819 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V2(0), FP64_QNAN_V3(0) } }, \ 820 820 { /* => */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V2(0), FP64_QNAN_V3(0) } }, \ 821 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\822 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\823 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE },\821 /*mxcsr:in */ 0, \ 822 /*128:out */ X86_MXCSR_IE, \ 823 /*256:out */ X86_MXCSR_IE }, \ 824 824 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN(0), FP64_SNAN_V1(0), FP64_SNAN_V2(0) } }, \ 825 825 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_MAX(0), FP64_SNAN_V3(0), FP64_SNAN_V0(0) } }, \ 826 826 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_MAX(0), FP64_QNAN_V3(0), FP64_QNAN_V0(0) } }, \ 827 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\828 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\829 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE },\827 /*mxcsr:in */ 0, \ 828 /*128:out */ X86_MXCSR_IE, \ 829 /*256:out */ X86_MXCSR_IE }, \ 830 830 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_MAX(1), FP64_NORM_V0(1), FP64_QNAN_V1(0) } }, \ 831 831 { /*src1 */ { FP64_1(0), FP64_1(1), FP64_QNAN_V0(1), FP64_NORM_V2(1) } }, \ 832 832 { /* => */ { FP64_QNAN(0), FP64_QNAN_MAX(1), FP64_QNAN_V0(1), FP64_QNAN_V1(0) } }, \ 833 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\834 /*128:out */ X86_MXCSR_XCPT_MASK,\835 /*256:out */ X86_MXCSR_XCPT_MASK },\833 /*mxcsr:in */ 0, \ 834 /*128:out */ 0, \ 835 /*256:out */ 0 }, \ 836 836 { { /*src2 */ { FP64_SNAN(1), FP64_SNAN_MAX(1), FP64_NORM_V0(1), FP64_SNAN_V1(0) } }, \ 837 837 { /*src1 */ { FP64_1(0), FP64_1(0), FP64_SNAN_V0(1), FP64_NORM_V2(1) } }, \ 838 838 { /* => */ { FP64_QNAN_V(1, 1), FP64_QNAN_MAX(1), FP64_QNAN_V0(1), FP64_QNAN_V1(0) } }, \ 839 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\840 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\841 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE },\839 /*mxcsr:in */ 0, \ 840 /*128:out */ X86_MXCSR_IE, \ 841 /*256:out */ X86_MXCSR_IE }, \ 842 842 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V0(0), FP64_QNAN_V2(0) } }, \ 843 843 { /*src1 */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V3(0) } }, \ … … 982 982 { /*src1 */ { FP64_QNAN(0), FP64_QNAN(1), FP64_QNAN_MAX(1), FP64_QNAN_V2(0) } }, \ 983 983 { /* => */ { FP64_QNAN(0), FP64_QNAN(1), FP64_QNAN_MAX(1), FP64_QNAN_V2(0) } }, \ 984 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\985 /*128:out */ X86_MXCSR_XCPT_MASK,\984 /*mxcsr:in */ 0, \ 985 /*128:out */ 0, \ 986 986 /*256:out */ -1 }, \ 987 987 { { /*src2 */ { FP64_QNAN_MAX(0), FP64_QNAN_V1(1), FP64_QNAN_V2(0), FP64_INF(0) } }, \ 988 988 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_V2(1), FP64_QNAN_V3(1), FP64_SNAN(1) } }, \ 989 989 { /* => */ { FP64_QNAN(0), FP64_QNAN_V2(1), FP64_QNAN_V3(1), FP64_SNAN(1) } }, \ 990 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\991 /*128:out */ X86_MXCSR_XCPT_MASK,\990 /*mxcsr:in */ 0, \ 991 /*128:out */ 0, \ 992 992 /*256:out */ -1 }, \ 993 993 { { /*src2 */ { FP64_QNAN_V1(0), FP64_QNAN_V1(0), FP64_QNAN_V2(0), FP64_INF(1) } }, \ 994 994 { /*src1 */ { FP64_QNAN_V0(0), FP64_QNAN_V2(0), FP64_QNAN_V3(1), FP64_QNAN(0) } }, \ 995 995 { /* => */ { FP64_QNAN_V0(0), FP64_QNAN_V2(0), FP64_QNAN_V3(1), FP64_QNAN(0) } }, \ 996 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\997 /*128:out */ X86_MXCSR_XCPT_MASK,\996 /*mxcsr:in */ 0, \ 997 /*128:out */ 0, \ 998 998 /*256:out */ -1 }, \ 999 999 /* QNan, SNan (Masked). */ \ … … 1001 1001 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_V2(1), FP64_SNAN_V1(0), FP64_SNAN_V2(1) } }, \ 1002 1002 { /* => */ { FP64_QNAN_V(0, 1), FP64_SNAN_V2(1), FP64_SNAN_V1(0), FP64_SNAN_V2(1) } }, \ 1003 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1004 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1003 /*mxcsr:in */ 0, \ 1004 /*128:out */ X86_MXCSR_IE, \ 1005 1005 /*256:out */ -1 }, \ 1006 1006 { { /*src2 */ { FP64_QNAN_MAX(0), FP64_QNAN_MAX(0), FP64_QNAN_V0(0), FP64_QNAN_V1(0) } }, \ 1007 1007 { /*src1 */ { FP64_SNAN(0), FP64_SNAN(1), FP64_SNAN_MAX(1), FP64_SNAN_V2(0) } }, \ 1008 1008 { /* => */ { FP64_QNAN_V(0, 1), FP64_SNAN(1), FP64_SNAN_MAX(1), FP64_SNAN_V2(0) } }, \ 1009 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1010 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1009 /*mxcsr:in */ 0, \ 1010 /*128:out */ X86_MXCSR_IE, \ 1011 1011 /*256:out */ -1 }, \ 1012 1012 { { /*src2 */ { FP64_QNAN_V1(0), FP64_QNAN_MAX(0), FP64_QNAN_V0(0), FP64_INF(0) } }, \ 1013 1013 { /*src1 */ { FP64_SNAN_V2(0), FP64_QNAN(0), FP64_QNAN_MAX(1), FP64_QNAN(1) } }, \ 1014 1014 { /* => */ { FP64_QNAN_V2(0), FP64_QNAN(0), FP64_QNAN_MAX(1), FP64_QNAN(1) } }, \ 1015 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1016 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1015 /*mxcsr:in */ 0, \ 1016 /*128:out */ X86_MXCSR_IE, \ 1017 1017 /*256:out */ -1 }, \ 1018 1018 /* SNan, QNan (Masked). */ \ … … 1020 1020 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V3(1), FP64_QNAN_V2(1) } }, \ 1021 1021 { /* => */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V3(1), FP64_QNAN_V2(1) } }, \ 1022 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1023 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1022 /*mxcsr:in */ 0, \ 1023 /*128:out */ X86_MXCSR_IE, \ 1024 1024 /*256:out */ -1 }, \ 1025 1025 { { /*src2 */ { FP64_SNAN_MAX(0), FP64_SNAN_MAX(1), FP64_SNAN_V1(0), FP64_SNAN_V1(0) } }, \ 1026 1026 { /*src1 */ { FP64_QNAN(0), FP64_QNAN(1), FP64_QNAN_V3(1), FP64_QNAN_V2(0) } }, \ 1027 1027 { /* => */ { FP64_QNAN(0), FP64_QNAN(1), FP64_QNAN_V3(1), FP64_QNAN_V2(0) } }, \ 1028 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1029 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1028 /*mxcsr:in */ 0, \ 1029 /*128:out */ X86_MXCSR_IE, \ 1030 1030 /*256:out */ -1 }, \ 1031 1031 { { /*src2 */ { FP64_SNAN_V0(0), FP64_SNAN_MAX(0), FP64_SNAN_V1(0), FP64_SNAN_V1(0) } }, \ 1032 1032 { /*src1 */ { FP64_QNAN_V1(0), FP64_QNAN(1), FP64_QNAN_V2(1), FP64_QNAN_V3(1) } }, \ 1033 1033 { /* => */ { FP64_QNAN_V1(0), FP64_QNAN(1), FP64_QNAN_V2(1), FP64_QNAN_V3(1) } }, \ 1034 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1035 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1034 /*mxcsr:in */ 0, \ 1035 /*128:out */ X86_MXCSR_IE, \ 1036 1036 /*256:out */ -1 }, \ 1037 1037 /* SNan, SNan (Masked). */ \ … … 1039 1039 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_MAX(0), FP64_SNAN_V0(0), FP64_SNAN_V3(0) } }, \ 1040 1040 { /* => */ { FP64_QNAN_V(0, 1), FP64_SNAN_MAX(0), FP64_SNAN_V0(0), FP64_SNAN_V3(0) } }, \ 1041 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1042 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1041 /*mxcsr:in */ 0, \ 1042 /*128:out */ X86_MXCSR_IE, \ 1043 1043 /*256:out */ -1 }, \ 1044 1044 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_V2(0), FP64_SNAN_V1(0), FP64_SNAN_V2(0) } }, \ 1045 1045 { /*src1 */ { FP64_SNAN_MAX(0), FP64_SNAN_V0(0), FP64_SNAN_V2(0), FP64_SNAN_V3(1) } }, \ 1046 1046 { /* => */ { FP64_QNAN_MAX(0), FP64_SNAN_V0(0), FP64_SNAN_V2(0), FP64_SNAN_V3(1) } }, \ 1047 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1048 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1047 /*mxcsr:in */ 0, \ 1048 /*128:out */ X86_MXCSR_IE, \ 1049 1049 /*256:out */ -1 }, \ 1050 1050 { { /*src2 */ { FP64_SNAN_V1(0), FP64_SNAN_V2(0), FP64_SNAN_V1(0), FP64_SNAN_V2(0) } }, \ 1051 1051 { /*src1 */ { FP64_SNAN_V0(0), FP64_SNAN_V3(0), FP64_SNAN_V0(0), FP64_SNAN_V3(0) } }, \ 1052 1052 { /* => */ { FP64_QNAN_V0(0), FP64_SNAN_V3(0), FP64_SNAN_V0(0), FP64_SNAN_V3(0) } }, \ 1053 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1054 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1053 /*mxcsr:in */ 0, \ 1054 /*128:out */ X86_MXCSR_IE, \ 1055 1055 /*256:out */ -1 }, \ 1056 1056 /* QNan, Norm FP (Masked). */ \ … … 1058 1058 { /*src1 */ { FP64_1(0), FP64_1(1), FP64_QNAN_V0(1), FP64_NORM_V2(1) } }, \ 1059 1059 { /* => */ { FP64_QNAN(0), FP64_1(1), FP64_QNAN_V0(1), FP64_NORM_V2(1) } }, \ 1060 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1061 /*128:out */ X86_MXCSR_XCPT_MASK,\1060 /*mxcsr:in */ 0, \ 1061 /*128:out */ 0, \ 1062 1062 /*256:out */ -1 }, \ 1063 1063 /* SNan, Norm FP (Masked). */ \ … … 1065 1065 { /*src1 */ { FP64_1(0), FP64_1(0), FP64_SNAN_V0(1), FP64_NORM_V2(1) } }, \ 1066 1066 { /* => */ { FP64_QNAN_V(1, 1), FP64_1(0), FP64_SNAN_V0(1), FP64_NORM_V2(1) } }, \ 1067 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1068 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1067 /*mxcsr:in */ 0, \ 1068 /*128:out */ X86_MXCSR_IE, \ 1069 1069 /*256:out */ -1 }, \ 1070 1070 /* QNan, QNan (Unmasked). */ \ … … 1167 1167 { /*src1 */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } }, \ 1168 1168 { /* => */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0), FP32_QNAN_V6(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0) } }, \ 1169 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1170 /*128:out */ X86_MXCSR_XCPT_MASK,\1171 /*256:out */ X86_MXCSR_XCPT_MASK },\1169 /*mxcsr:in */ 0, \ 1170 /*128:out */ 0, \ 1171 /*256:out */ 0 }, \ 1172 1172 { { /*src2 */ { FP32_QNAN(0), FP32_SNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_SNAN_V3(0), FP32_QNAN_V4(0), FP32_SNAN_V5(0) } }, \ 1173 1173 { /*src1 */ { FP32_QNAN(0), FP32_SNAN(0), FP32_QNAN(0), FP32_SNAN_V2(0), FP32_QNAN_V6(0), FP32_SNAN_V2(0), FP32_QNAN_V1(0), FP32_SNAN_V4(0) } }, \ 1174 1174 { /* => */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V6(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V4(0) } }, \ 1175 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1176 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1177 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE },\1175 /*mxcsr:in */ 0, \ 1176 /*128:out */ X86_MXCSR_IE, \ 1177 /*256:out */ X86_MXCSR_IE }, \ 1178 1178 { { /*src2 */ { FP32_SNAN_MAX(0), FP32_QNAN_V2(0), FP32_SNAN_V1(0), FP32_QNAN_V2(0), FP32_SNAN_V3(0), FP32_QNAN_V4(0), FP32_SNAN_V5(0), FP32_QNAN_V6(0) } }, \ 1179 1179 { /*src1 */ { FP32_SNAN(0), FP32_QNAN(0), FP32_SNAN(0), FP32_QNAN_V5(0), FP32_SNAN_V4(0), FP32_QNAN_V3(0), FP32_SNAN_V2(0), FP32_QNAN_V1(0) } }, \ 1180 1180 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_MAX(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V5(0) } }, \ 1181 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1182 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1183 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE },\1181 /*mxcsr:in */ 0, \ 1182 /*128:out */ X86_MXCSR_IE, \ 1183 /*256:out */ X86_MXCSR_IE }, \ 1184 1184 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN_MAX(0), FP32_SNAN_MAX(0), FP32_SNAN(0), FP32_SNAN_V7(0), FP32_SNAN_V1(0), FP32_SNAN_V6(0), FP32_SNAN_V1(0) } }, \ 1185 1185 { /*src1 */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_MAX(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } }, \ 1186 1186 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_MAX(0), FP32_QNAN_V5(0), FP32_QNAN_V1(0), FP32_QNAN_V7(0), FP32_QNAN_V6(0) } }, \ 1187 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1188 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1189 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE },\1187 /*mxcsr:in */ 0, \ 1188 /*128:out */ X86_MXCSR_IE, \ 1189 /*256:out */ X86_MXCSR_IE }, \ 1190 1190 { { /*src2 */ { FP32_QNAN(0), FP32_NORM_V1(0), FP32_QNAN_MAX(0), FP32_QNAN_V1(0), FP32_QNAN_V1(0), FP32_NORM_V3(1), FP32_QNAN_V5(0), FP32_NORM_V5(1) } }, \ 1191 1191 { /*src1 */ { FP32_QNAN(0), FP32_1(1), FP32_QNAN_MAX(1), FP32_NORM_V2(1), FP32_QNAN_V2(0), FP32_NORM_V4(0), FP32_QNAN_V4(1), FP32_NORM_V6(1) } }, \ 1192 1192 { /* => */ { FP32_QNAN(0), FP32_QNAN_MAX(1), FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V4(1), FP32_QNAN_V1(0), FP32_QNAN_V5(0) } }, \ 1193 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1194 /*128:out */ X86_MXCSR_XCPT_MASK,\1195 /*256:out */ X86_MXCSR_XCPT_MASK },\1193 /*mxcsr:in */ 0, \ 1194 /*128:out */ 0, \ 1195 /*256:out */ 0 }, \ 1196 1196 { { /*src2 */ { FP32_SNAN_MAX(1), FP32_1(0), FP32_SNAN_V1(0), FP32_NORM_V3(0), FP32_SNAN_V0(0), FP32_NORM_V3(1), FP32_SNAN_V6(0), FP32_NORM_V7(1) } }, \ 1197 1197 { /*src1 */ { FP32_SNAN(0), FP32_1(1), FP32_SNAN_MAX(0), FP32_NORM_V2(1), FP32_SNAN_V2(1), FP32_NORM_V4(0), FP32_SNAN_V4(1), FP32_NORM_V6(1) } }, \ 1198 1198 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_MAX(0), FP32_QNAN_MAX(1), FP32_QNAN_V1(0), FP32_QNAN_V2(1), FP32_QNAN_V4(1), FP32_QNAN_V0(0), FP32_QNAN_V6(0) } }, \ 1199 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1200 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1201 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE },\1199 /*mxcsr:in */ 0, \ 1200 /*128:out */ X86_MXCSR_IE, \ 1201 /*256:out */ X86_MXCSR_IE }, \ 1202 1202 { { /*src2 */ { FP32_QNAN_MAX(0), FP32_QNAN(0), FP32_QNAN_V0(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V3(0), FP32_QNAN_V5(0) } }, \ 1203 1203 { /*src1 */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } }, \ … … 1245 1245 { /*src1 */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_MAX(0) } }, \ 1246 1246 { /* => */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN(0), FP64_QNAN_V0(0) } }, \ 1247 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1248 /*128:out */ X86_MXCSR_XCPT_MASK,\1249 /*256:out */ X86_MXCSR_XCPT_MASK },\1247 /*mxcsr:in */ 0, \ 1248 /*128:out */ 0, \ 1249 /*256:out */ 0 }, \ 1250 1250 { { /*src2 */ { FP64_QNAN(0), FP64_SNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V1(0) } }, \ 1251 1251 { /*src1 */ { FP64_QNAN(0), FP64_SNAN(0), FP64_QNAN(0), FP64_SNAN_V2(0) } }, \ 1252 1252 { /* => */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_MAX(0) } }, \ 1253 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1254 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1255 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE },\1253 /*mxcsr:in */ 0, \ 1254 /*128:out */ X86_MXCSR_IE, \ 1255 /*256:out */ X86_MXCSR_IE }, \ 1256 1256 { { /*src2 */ { FP64_SNAN_MAX(0), FP64_QNAN_V2(0), FP64_SNAN_V1(0), FP64_QNAN_V2(0) } }, \ 1257 1257 { /*src1 */ { FP64_SNAN(0), FP64_QNAN(0), FP64_SNAN(0), FP64_QNAN_V3(0) } }, \ 1258 1258 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_MAX(0), FP64_QNAN_V(0, 1), FP64_QNAN_V1(0) } }, \ 1259 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1260 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1261 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE },\1259 /*mxcsr:in */ 0, \ 1260 /*128:out */ X86_MXCSR_IE, \ 1261 /*256:out */ X86_MXCSR_IE }, \ 1262 1262 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN_MAX(0), FP64_SNAN_MAX(0), FP64_SNAN(0) } }, \ 1263 1263 { /*src1 */ { FP64_SNAN(0), FP64_SNAN(0), FP64_SNAN(0), FP64_SNAN_MAX(0) } }, \ 1264 1264 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_MAX(0) } }, \ 1265 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1266 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1267 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE },\1265 /*mxcsr:in */ 0, \ 1266 /*128:out */ X86_MXCSR_IE, \ 1267 /*256:out */ X86_MXCSR_IE }, \ 1268 1268 { { /*src2 */ { FP64_QNAN(0), FP64_NORM_V1(0), FP64_QNAN_MAX(0), FP64_QNAN_V1(0) } }, \ 1269 1269 { /*src1 */ { FP64_QNAN(0), FP64_1(1), FP64_QNAN_MAX(1), FP64_NORM_V2(1) } }, \ 1270 1270 { /* => */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_MAX(1), FP64_QNAN_MAX(0) } }, \ 1271 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1272 /*128:out */ X86_MXCSR_XCPT_MASK,\1273 /*256:out */ X86_MXCSR_XCPT_MASK },\1271 /*mxcsr:in */ 0, \ 1272 /*128:out */ 0, \ 1273 /*256:out */ 0 }, \ 1274 1274 { { /*src2 */ { FP64_SNAN_MAX(1), FP64_1(0), FP64_SNAN_V1(0), FP64_NORM_V3(0) } }, \ 1275 1275 { /*src1 */ { FP64_SNAN(0), FP64_1(1), FP64_SNAN_MAX(0), FP64_NORM_V2(1) } }, \ 1276 1276 { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_MAX(1), FP64_QNAN_MAX(0), FP64_QNAN_V1(0) } }, \ 1277 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1278 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1279 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE },\1277 /*mxcsr:in */ 0, \ 1278 /*128:out */ X86_MXCSR_IE, \ 1279 /*256:out */ X86_MXCSR_IE }, \ 1280 1280 { { /*src2 */ { FP64_QNAN_MAX(0), FP64_QNAN(0), FP64_QNAN_V0(0), FP64_QNAN_V1(0) } }, \ 1281 1281 { /*src1 */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_MAX(0) } }, \ … … 1323 1323 { /*src1 */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } }, \ 1324 1324 { /* => */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \ 1325 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1326 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1327 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE },\1325 /*mxcsr:in */ 0, \ 1326 /*128:out */ X86_MXCSR_IE, \ 1327 /*256:out */ X86_MXCSR_IE }, \ 1328 1328 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \ 1329 1329 { /*src1 */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_MAX(0), FP32_SNAN_V2(0), FP32_SNAN_V6(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V4(0) } }, \ 1330 1330 { /* => */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \ 1331 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1332 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1333 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE },\1331 /*mxcsr:in */ 0, \ 1332 /*128:out */ X86_MXCSR_IE, \ 1333 /*256:out */ X86_MXCSR_IE }, \ 1334 1334 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_V1(0), FP32_SNAN_V1(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V5(0), FP32_SNAN_V6(0) } }, \ 1335 1335 { /*src1 */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } }, \ 1336 1336 { /* => */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_V1(0), FP32_SNAN_V1(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V5(0), FP32_SNAN_V6(0) } }, \ 1337 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ,\1338 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,\1339 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE },\1337 /*mxcsr:in */ X86_MXCSR_FZ, \ 1338 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_IE, \ 1339 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_IE }, \ 1340 1340 { { /*src2 */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V7(0), FP32_SNAN_V1(0), FP32_SNAN_V6(0), FP32_SNAN_V1(0) } }, \ 1341 1341 { /*src1 */ { FP32_SNAN(0), FP32_SNAN_MAX(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } }, \ 1342 1342 { /* => */ { FP32_SNAN(0), FP32_SNAN(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V7(0), FP32_SNAN_V1(0), FP32_SNAN_V6(0), FP32_SNAN_V1(0) } }, \ 1343 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1344 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1345 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE },\1343 /*mxcsr:in */ 0, \ 1344 /*128:out */ X86_MXCSR_IE, \ 1345 /*256:out */ X86_MXCSR_IE }, \ 1346 1346 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_MAX(1), FP32_NORM_V0(1), FP32_QNAN_V1(0), FP32_NORM_V3(0), FP32_QNAN_V3(1), FP32_NORM_V5(0), FP32_QNAN_V5(1) } }, \ 1347 1347 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_QNAN_V0(1), FP32_NORM_V2(1), FP32_QNAN_V2(0), FP32_NORM_V4(0), FP32_QNAN_V4(1), FP32_NORM_V6(1) } }, \ 1348 1348 { /* => */ { FP32_QNAN(0), FP32_QNAN_MAX(1), FP32_NORM_V0(1), FP32_QNAN_V1(0), FP32_NORM_V3(0), FP32_QNAN_V3(1), FP32_NORM_V5(0), FP32_QNAN_V5(1) } }, \ 1349 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1350 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1351 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE },\1349 /*mxcsr:in */ 0, \ 1350 /*128:out */ X86_MXCSR_IE, \ 1351 /*256:out */ X86_MXCSR_IE }, \ 1352 1352 { { /*src2 */ { FP32_SNAN(1), FP32_SNAN_MAX(1), FP32_NORM_V0(1), FP32_SNAN_V1(0), FP32_NORM_V3(0), FP32_SNAN_V3(1), FP32_NORM_V5(0), FP32_SNAN_V5(1) } }, \ 1353 1353 { /*src1 */ { FP32_1(0), FP32_1(0), FP32_SNAN_V0(1), FP32_NORM_V2(1), FP32_SNAN_V2(1), FP32_NORM_V4(0), FP32_SNAN_V4(1), FP32_NORM_V6(1) } }, \ 1354 1354 { /* => */ { FP32_SNAN(1), FP32_SNAN_MAX(1), FP32_NORM_V0(1), FP32_SNAN_V1(0), FP32_NORM_V3(0), FP32_SNAN_V3(1), FP32_NORM_V5(0), FP32_SNAN_V5(1) } }, \ 1355 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1356 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1357 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE },\1355 /*mxcsr:in */ 0, \ 1356 /*128:out */ X86_MXCSR_IE, \ 1357 /*256:out */ X86_MXCSR_IE }, \ 1358 1358 { { /*src2 */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \ 1359 1359 { /*src1 */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } }, \ … … 1389 1389 { /*src1 */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V2(0) } }, \ 1390 1390 { /* => */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V0(0), FP64_QNAN_V1(0) } }, \ 1391 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1392 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1393 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE },\1391 /*mxcsr:in */ 0, \ 1392 /*128:out */ X86_MXCSR_IE, \ 1393 /*256:out */ X86_MXCSR_IE }, \ 1394 1394 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V0(0), FP64_QNAN_V1(0) } }, \ 1395 1395 { /*src1 */ { FP64_SNAN(0), FP64_SNAN(0), FP64_SNAN_MAX(0), FP64_SNAN_V2(0) } }, \ 1396 1396 { /* => */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V0(0), FP64_QNAN_V1(0) } }, \ 1397 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1398 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1399 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE },\1397 /*mxcsr:in */ 0, \ 1398 /*128:out */ X86_MXCSR_IE, \ 1399 /*256:out */ X86_MXCSR_IE }, \ 1400 1400 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN(0), FP64_SNAN_V1(0), FP64_SNAN_V1(0) } }, \ 1401 1401 { /*src1 */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V2(0), FP64_QNAN_V3(0) } }, \ 1402 1402 { /* => */ { FP64_SNAN(0), FP64_SNAN(0), FP64_SNAN_V1(0), FP64_SNAN_V1(0) } }, \ 1403 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ,\1404 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,\1405 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE },\1403 /*mxcsr:in */ X86_MXCSR_FZ, \ 1404 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_IE, \ 1405 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_IE }, \ 1406 1406 { { /*src2 */ { FP64_SNAN(0), FP64_SNAN(0), FP64_SNAN_V1(0), FP64_SNAN_V2(0) } }, \ 1407 1407 { /*src1 */ { FP64_SNAN(0), FP64_SNAN_MAX(0), FP64_SNAN_V2(0), FP64_SNAN_V3(0) } }, \ 1408 1408 { /* => */ { FP64_SNAN(0), FP64_SNAN(0), FP64_SNAN_V1(0), FP64_SNAN_V2(0) } }, \ 1409 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1410 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1411 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE },\1409 /*mxcsr:in */ 0, \ 1410 /*128:out */ X86_MXCSR_IE, \ 1411 /*256:out */ X86_MXCSR_IE }, \ 1412 1412 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_MAX(1), FP64_NORM_V0(1), FP64_QNAN_V1(0) } }, \ 1413 1413 { /*src1 */ { FP64_1(0), FP64_1(1), FP64_QNAN_V0(1), FP64_NORM_V2(1) } }, \ 1414 1414 { /* => */ { FP64_QNAN(0), FP64_QNAN_MAX(1), FP64_NORM_V0(1), FP64_QNAN_V1(0) } }, \ 1415 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1416 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1417 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE },\1415 /*mxcsr:in */ 0, \ 1416 /*128:out */ X86_MXCSR_IE, \ 1417 /*256:out */ X86_MXCSR_IE }, \ 1418 1418 { { /*src2 */ { FP64_SNAN(1), FP64_SNAN_MAX(1), FP64_NORM_V0(1), FP64_SNAN_V1(0) } }, \ 1419 1419 { /*src1 */ { FP64_1(0), FP64_1(0), FP64_SNAN_V0(1), FP64_NORM_V2(1) } }, \ 1420 1420 { /* => */ { FP64_SNAN(1), FP64_SNAN_MAX(1), FP64_NORM_V0(1), FP64_SNAN_V1(0) } }, \ 1421 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1422 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1423 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE },\1421 /*mxcsr:in */ 0, \ 1422 /*128:out */ X86_MXCSR_IE, \ 1423 /*256:out */ X86_MXCSR_IE }, \ 1424 1424 { { /*src2 */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V0(0), FP64_QNAN_V1(0) } }, \ 1425 1425 { /*src1 */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V2(0) } }, \ … … 1456 1456 { /*src1 */ { FP32_QNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V5(1), FP32_RAND_V6(1), FP32_RAND_V7(1), FP32_RAND_V1(1) } }, \ 1457 1457 { /* => */ { FP32_QNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V5(1), FP32_RAND_V6(1), FP32_RAND_V7(1), FP32_RAND_V1(1) } }, \ 1458 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1459 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1458 /*mxcsr:in */ 0, \ 1459 /*128:out */ X86_MXCSR_IE, \ 1460 1460 /*256:out */ -1 }, \ 1461 1461 { { /*src2 */ { FP32_QNAN_MAX(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(0), FP32_RAND_V6(1) } }, \ 1462 1462 { /*src1 */ { FP32_QNAN(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V1(0) } }, \ 1463 1463 { /* => */ { FP32_QNAN_MAX(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V1(0) } }, \ 1464 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1465 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1464 /*mxcsr:in */ 0, \ 1465 /*128:out */ X86_MXCSR_IE, \ 1466 1466 /*256:out */ -1 }, \ 1467 1467 { { /*src2 */ { FP32_QNAN_V0(0), FP32_RAND_V0(1), FP32_RAND_V7(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } }, \ 1468 1468 { /*src1 */ { FP32_QNAN_MAX(0), FP32_RAND_V1(0), FP32_RAND_V7(0), FP32_RAND_V2(1), FP32_RAND_V6(1), FP32_RAND_V3(1), FP32_RAND_V5(0), FP32_RAND_V4(1) } }, \ 1469 1469 { /* => */ { FP32_QNAN_V0(0), FP32_RAND_V1(0), FP32_RAND_V7(0), FP32_RAND_V2(1), FP32_RAND_V6(1), FP32_RAND_V3(1), FP32_RAND_V5(0), FP32_RAND_V4(1) } }, \ 1470 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1471 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1470 /*mxcsr:in */ 0, \ 1471 /*128:out */ X86_MXCSR_IE, \ 1472 1472 /*256:out */ -1 }, \ 1473 1473 /* QNan, SNan (Masked). */ \ … … 1475 1475 { /*src1 */ { FP32_SNAN(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, \ 1476 1476 { /* => */ { FP32_QNAN(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } }, \ 1477 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1478 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1477 /*mxcsr:in */ 0, \ 1478 /*128:out */ X86_MXCSR_IE, \ 1479 1479 /*256:out */ -1 }, \ 1480 1480 { { /*src2 */ { FP32_QNAN_MAX(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V1(1), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, \ 1481 1481 { /*src1 */ { FP32_SNAN(0), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V3(0) } }, \ 1482 1482 { /* => */ { FP32_QNAN_MAX(0), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V3(0) } }, \ 1483 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1484 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1483 /*mxcsr:in */ 0, \ 1484 /*128:out */ X86_MXCSR_IE, \ 1485 1485 /*256:out */ -1 }, \ 1486 1486 { { /*src2 */ { FP32_QNAN_V0(0), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V1(1), FP32_RAND_V0(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, \ 1487 1487 { /*src1 */ { FP32_SNAN_MAX(0), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V1(0) } }, \ 1488 1488 { /* => */ { FP32_QNAN_V0(0), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V1(0) } }, \ 1489 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1490 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1489 /*mxcsr:in */ 0, \ 1490 /*128:out */ X86_MXCSR_IE, \ 1491 1491 /*256:out */ -1 }, \ 1492 1492 /* SNan, QNan (Masked). */ \ … … 1494 1494 { /*src1 */ { FP32_QNAN(0), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V3(0) } }, \ 1495 1495 { /* => */ { FP32_SNAN(0), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V3(0) } }, \ 1496 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ,\1497 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,\1496 /*mxcsr:in */ X86_MXCSR_FZ, \ 1497 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_IE, \ 1498 1498 /*256:out */ -1 }, \ 1499 1499 { { /*src2 */ { FP32_SNAN(0), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V7(1) } }, \ 1500 1500 { /*src1 */ { FP32_QNAN_MAX(0), FP32_RAND_V2(0), FP32_RAND_V4(0), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V2(0) } }, \ 1501 1501 { /* => */ { FP32_SNAN(0), FP32_RAND_V2(0), FP32_RAND_V4(0), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V2(0) } }, \ 1502 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1503 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1502 /*mxcsr:in */ 0, \ 1503 /*128:out */ X86_MXCSR_IE, \ 1504 1504 /*256:out */ -1 }, \ 1505 1505 { { /*src2 */ { FP32_SNAN_V1(0), FP32_RAND_V1(1), FP32_RAND_V7(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } }, \ 1506 1506 { /*src1 */ { FP32_QNAN_V6(0), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V0(1), FP32_RAND_V2(0), FP32_RAND_V3(1) } }, \ 1507 1507 { /* => */ { FP32_SNAN_V1(0), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V0(1), FP32_RAND_V2(0), FP32_RAND_V3(1) } }, \ 1508 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1509 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1508 /*mxcsr:in */ 0, \ 1509 /*128:out */ X86_MXCSR_IE, \ 1510 1510 /*256:out */ -1 }, \ 1511 1511 /* SNan, SNan (Masked). */ \ … … 1513 1513 { /*src1 */ { FP32_SNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V7(0) } }, \ 1514 1514 { /* => */ { FP32_SNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V7(0) } }, \ 1515 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1516 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1515 /*mxcsr:in */ 0, \ 1516 /*128:out */ X86_MXCSR_IE, \ 1517 1517 /*256:out */ -1 }, \ 1518 1518 { { /*src2 */ { FP32_SNAN(0), FP32_RAND_V1(0), FP32_RAND_V7(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V1(1), FP32_RAND_V2(1) } }, \ 1519 1519 { /*src1 */ { FP32_SNAN_MAX(0), FP32_RAND_V7(0), FP32_RAND_V5(0), FP32_RAND_V7(1), FP32_RAND_V6(1), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V2(1) } }, \ 1520 1520 { /* => */ { FP32_SNAN(0), FP32_RAND_V7(0), FP32_RAND_V5(0), FP32_RAND_V7(1), FP32_RAND_V6(1), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V2(1) } }, \ 1521 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1522 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1521 /*mxcsr:in */ 0, \ 1522 /*128:out */ X86_MXCSR_IE, \ 1523 1523 /*256:out */ -1 }, \ 1524 1524 { { /*src2 */ { FP32_SNAN_V1(0), FP32_RAND_V1(1), FP32_RAND_V6(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } }, \ 1525 1525 { /*src1 */ { FP32_SNAN_V4(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V0(1) } }, \ 1526 1526 { /* => */ { FP32_SNAN_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V0(1) } }, \ 1527 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1528 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1527 /*mxcsr:in */ 0, \ 1528 /*128:out */ X86_MXCSR_IE, \ 1529 1529 /*256:out */ -1 }, \ 1530 1530 /* QNan, Normal (Masked). */ \ … … 1532 1532 { /*src1 */ { FP32_1(0), FP32_RAND_V2(1), FP32_RAND_V4(1), FP32_RAND_V6(1), FP32_RAND_V2(1), FP32_RAND_V7(0), FP32_RAND_V3(0), FP32_RAND_V4(1) } }, \ 1533 1533 { /* => */ { FP32_QNAN(0), FP32_RAND_V2(1), FP32_RAND_V4(1), FP32_RAND_V6(1), FP32_RAND_V2(1), FP32_RAND_V7(0), FP32_RAND_V3(0), FP32_RAND_V4(1) } }, \ 1534 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1535 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1534 /*mxcsr:in */ 0, \ 1535 /*128:out */ X86_MXCSR_IE, \ 1536 1536 /*256:out */ -1 }, \ 1537 1537 /* SNan, Normal (Masked). */ \ … … 1539 1539 { /*src1 */ { FP32_1(0), FP32_RAND_V0(1), FP32_RAND_V1(1), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V6(0), FP32_RAND_V7(0), FP32_RAND_V1(1) } }, \ 1540 1540 { /* => */ { FP32_SNAN(1), FP32_RAND_V0(1), FP32_RAND_V1(1), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V6(0), FP32_RAND_V7(0), FP32_RAND_V1(1) } }, \ 1541 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1542 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1541 /*mxcsr:in */ 0, \ 1542 /*128:out */ X86_MXCSR_IE, \ 1543 1543 /*256:out */ -1 }, \ 1544 1544 /* QNan, QNan (Unmasked). */ \ … … 1642 1642 { /*src1 */ { FP64_QNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, \ 1643 1643 { /* => */ { FP64_QNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, \ 1644 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1645 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1644 /*mxcsr:in */ 0, \ 1645 /*128:out */ X86_MXCSR_IE, \ 1646 1646 /*256:out */ -1 }, \ 1647 1647 { { /*src2 */ { FP64_QNAN_MAX(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(0) } }, \ 1648 1648 { /*src1 */ { FP64_QNAN(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V3(1) } }, \ 1649 1649 { /* => */ { FP64_QNAN_MAX(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V3(1) } }, \ 1650 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1651 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1650 /*mxcsr:in */ 0, \ 1651 /*128:out */ X86_MXCSR_IE, \ 1652 1652 /*256:out */ -1 }, \ 1653 1653 { { /*src2 */ { FP64_QNAN_V0(0), FP64_RAND_V0(1), FP64_RAND_V0(1), FP64_RAND_V2(0) } }, \ 1654 1654 { /*src1 */ { FP64_QNAN_MAX(0), FP64_RAND_V1(0), FP64_RAND_V0(0), FP64_RAND_V2(1) } }, \ 1655 1655 { /* => */ { FP64_QNAN_V0(0), FP64_RAND_V1(0), FP64_RAND_V0(0), FP64_RAND_V2(1) } }, \ 1656 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1657 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1656 /*mxcsr:in */ 0, \ 1657 /*128:out */ X86_MXCSR_IE, \ 1658 1658 /*256:out */ -1 }, \ 1659 1659 /* QNan, SNan (Masked). */ \ … … 1661 1661 { /*src1 */ { FP64_SNAN(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(0) } }, \ 1662 1662 { /* => */ { FP64_QNAN(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(0) } }, \ 1663 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1664 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1663 /*mxcsr:in */ 0, \ 1664 /*128:out */ X86_MXCSR_IE, \ 1665 1665 /*256:out */ -1 }, \ 1666 1666 { { /*src2 */ { FP64_QNAN_MAX(0), FP64_RAND_V2(1), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, \ 1667 1667 { /*src1 */ { FP64_SNAN(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, \ 1668 1668 { /* => */ { FP64_QNAN_MAX(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, \ 1669 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1670 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1669 /*mxcsr:in */ 0, \ 1670 /*128:out */ X86_MXCSR_IE, \ 1671 1671 /*256:out */ -1 }, \ 1672 1672 { { /*src2 */ { FP64_QNAN_V0(0), FP64_RAND_V1(1), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, \ 1673 1673 { /*src1 */ { FP64_SNAN_MAX(0), FP64_RAND_V3(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } }, \ 1674 1674 { /* => */ { FP64_QNAN_V0(0), FP64_RAND_V3(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } }, \ 1675 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1676 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1675 /*mxcsr:in */ 0, \ 1676 /*128:out */ X86_MXCSR_IE, \ 1677 1677 /*256:out */ -1 }, \ 1678 1678 /* SNan, QNan (Masked). */ \ … … 1680 1680 { /*src1 */ { FP64_QNAN(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, \ 1681 1681 { /* => */ { FP64_SNAN(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, \ 1682 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ,\1683 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,\1682 /*mxcsr:in */ X86_MXCSR_FZ, \ 1683 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_IE, \ 1684 1684 /*256:out */ -1 }, \ 1685 1685 { { /*src2 */ { FP64_SNAN(0), FP64_RAND_V1(1), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, \ 1686 1686 { /*src1 */ { FP64_QNAN_MAX(0), FP64_RAND_V2(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, \ 1687 1687 { /* => */ { FP64_SNAN(0), FP64_RAND_V2(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, \ 1688 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1689 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1688 /*mxcsr:in */ 0, \ 1689 /*128:out */ X86_MXCSR_IE, \ 1690 1690 /*256:out */ -1 }, \ 1691 1691 { { /*src2 */ { FP64_SNAN_V1(0), FP64_RAND_V1(1), FP64_RAND_V0(1), FP64_RAND_V2(0) } }, \ 1692 1692 { /*src1 */ { FP64_QNAN_V1(0), FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } }, \ 1693 1693 { /* => */ { FP64_SNAN_V1(0), FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } }, \ 1694 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1695 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1694 /*mxcsr:in */ 0, \ 1695 /*128:out */ X86_MXCSR_IE, \ 1696 1696 /*256:out */ -1 }, \ 1697 1697 /* SNan, SNan (Masked). */ \ … … 1699 1699 { /*src1 */ { FP64_SNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, \ 1700 1700 { /* => */ { FP64_SNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, \ 1701 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1702 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1701 /*mxcsr:in */ 0, \ 1702 /*128:out */ X86_MXCSR_IE, \ 1703 1703 /*256:out */ -1 }, \ 1704 1704 { { /*src2 */ { FP64_SNAN(0), FP64_RAND_V1(0), FP64_RAND_V0(1), FP64_RAND_V2(1) } }, \ 1705 1705 { /*src1 */ { FP64_SNAN_MAX(0), FP64_RAND_V0(0), FP64_RAND_V3(0), FP64_RAND_V0(1) } }, \ 1706 1706 { /* => */ { FP64_SNAN(0), FP64_RAND_V0(0), FP64_RAND_V3(0), FP64_RAND_V0(1) } }, \ 1707 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1708 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1707 /*mxcsr:in */ 0, \ 1708 /*128:out */ X86_MXCSR_IE, \ 1709 1709 /*256:out */ -1 }, \ 1710 1710 { { /*src2 */ { FP64_SNAN_V1(0), FP64_RAND_V1(1), FP64_RAND_V1(1), FP64_RAND_V2(0) } }, \ 1711 1711 { /*src1 */ { FP64_SNAN_V2(0), FP64_RAND_V2(1), FP64_RAND_V3(1), FP64_RAND_V1(1) } }, \ 1712 1712 { /* => */ { FP64_SNAN_V1(0), FP64_RAND_V2(1), FP64_RAND_V3(1), FP64_RAND_V1(1) } }, \ 1713 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1714 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1713 /*mxcsr:in */ 0, \ 1714 /*128:out */ X86_MXCSR_IE, \ 1715 1715 /*256:out */ -1 }, \ 1716 1716 /* QNan, Normal (Masked). */ \ … … 1718 1718 { /*src1 */ { FP64_1(0), FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V1(1) } }, \ 1719 1719 { /* => */ { FP64_QNAN(0), FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V1(1) } }, \ 1720 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1721 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1720 /*mxcsr:in */ 0, \ 1721 /*128:out */ X86_MXCSR_IE, \ 1722 1722 /*256:out */ -1 }, \ 1723 1723 /* SNan, Normal (Masked). */ \ … … 1725 1725 { /*src1 */ { FP64_1(0), FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V3(1) } }, \ 1726 1726 { /* => */ { FP64_SNAN(1), FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V3(1) } }, \ 1727 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,\1728 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,\1727 /*mxcsr:in */ 0, \ 1728 /*128:out */ X86_MXCSR_IE, \ 1729 1729 /*256:out */ -1 }, \ 1730 1730 /* QNan, QNan (Unmasked). */ \ … … 3111 3111 { /*src1 */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 3112 3112 { /* => */ { FP32_QNAN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 3113 /*mxcsr:in */ X86_MXCSR_IM,3114 /*128:out */ X86_MXCSR_I M | X86_MXCSR_IE,3115 /*256:out */ X86_MXCSR_I M | X86_MXCSR_IE },3113 /*mxcsr:in */ 0, 3114 /*128:out */ X86_MXCSR_IE, 3115 /*256:out */ X86_MXCSR_IE }, 3116 3116 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 3117 3117 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, … … 3225 3225 { /*src1 */ { FP32_V(1, 0, 0x7d)/*-0.25*/, FP32_NORM_MAX(1), FP32_0(0), FP32_V(0, 0, 0x7e)/*0.50*/, FP32_V(1, 0, 0x7d)/*-0.25*/, FP32_NORM_MAX(1), FP32_0(0), FP32_V(0, 0, 0x7e)/*0.50*/ } }, 3226 3226 { /* => */ { FP32_V(0, 0x400000, 0x7f)/* 1.50*/, FP32_0(1), FP32_0(0), FP32_V(0, 0x400000, 0x7e)/*0.75*/, FP32_V(0, 0x400000, 0x7f)/* 1.50*/, FP32_0(1), FP32_0(0), FP32_V(0, 0x400000, 0x7e)/*0.75*/ } }, 3227 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,3228 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,3229 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },3227 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 3228 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 3229 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN }, 3230 3230 { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_V1(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_V1(0), FP32_0(0), FP32_0(0) } }, 3231 3231 { /*src1 */ { FP32_NORM_MAX(1), FP32_NORM_V1(1), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_V1(1), FP32_0(0), FP32_0(0) } }, … … 3237 3237 { /*src1 */ { FP32_V(0, 0x1ea980, 0x8f)/* 81235*/, FP32_V(0, 0x600000, 0x81)/* 7*/, FP32_V(0, 0x7c9000, 0x88)/* 1010.25*/, FP32_0(0), FP32_V(0, 0x600000, 0x81)/* 7*/, FP32_V(0, 0x7c9000, 0x88)/* 1010.25*/, FP32_1(1) /*- 1.00*/, FP32_0(0) } }, 3238 3238 { /* => */ { FP32_V(0, 0x669050, 0x93)/*1888778*/, FP32_V(0, 0x780000, 0x84)/*62*/, FP32_V(0, 0x253468, 0x93)/*1353357.00*/, FP32_0(0), FP32_V(0, 0x780000, 0x84)/*62*/, FP32_V(0, 0x253468, 0x93)/*1353357.00*/, FP32_V(0, 0x524000, 0x86)/*210.25*/, FP32_0(0) } }, 3239 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,3240 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,3241 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO },3239 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 3240 /*128:out */ X86_MXCSR_RC_ZERO, 3241 /*256:out */ X86_MXCSR_RC_ZERO }, 3242 3242 { { /*src2 */ { FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_V(0, 0x3c614e, 0x96)/*12345678*/, FP32_0(0), FP32_0(0), FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_V(0, 0x3c614e, 0x96)/*12345678*/, FP32_1(1), FP32_0(0) } }, 3243 3243 { /*src1 */ { FP32_V(1, 0x712060, 0x92)/*- 987654*/, FP32_V(0, 0x3c614e, 0x96)/*12345678*/, FP32_0(0), FP32_1(0), FP32_V(1, 0x712060, 0x92)/*- 987654*/, FP32_V(0, 0x3c614e, 0x96)/*12345678*/, FP32_1(0), FP32_1(0) } }, … … 3317 3317 { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0) } }, 3318 3318 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 3319 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,3320 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,3321 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP },3319 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 3320 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 3321 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP }, 3322 3322 { { /*src2 */ { FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 3323 3323 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, … … 3344 3344 { /*src1 */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 3345 3345 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 3346 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,3347 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,3348 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ },3346 /*mxcsr:in */ X86_MXCSR_DAZ, 3347 /*128:out */ X86_MXCSR_DAZ, 3348 /*256:out */ X86_MXCSR_DAZ }, 3349 3349 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } }, 3350 3350 { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0) } }, 3351 3351 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 3352 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,3353 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,3354 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP },3352 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 3353 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 3354 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP }, 3355 3355 /** @todo More Denormals. */ 3356 3356 /* … … 3425 3425 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 3426 3426 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 3427 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,3428 /*128:out */ X86_MXCSR_XCPT_MASK,3429 /*256:out */ X86_MXCSR_XCPT_MASK},3427 /*mxcsr:in */ 0, 3428 /*128:out */ 0, 3429 /*256:out */ 0 }, 3430 3430 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 3431 3431 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, … … 3437 3437 { /*src1 */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(0) } }, 3438 3438 { /* => */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(0) } }, 3439 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN,3440 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN,3441 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN },3439 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN, 3440 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN, 3441 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN }, 3442 3442 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(1) } }, 3443 3443 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(1) } }, … … 3449 3449 { /*src1 */ { FP64_0(1), FP64_0(0), FP64_0(1), FP64_0(0) } }, 3450 3450 { /* => */ { FP64_0(1), FP64_0(0), FP64_0(1), FP64_0(0) } }, 3451 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,3452 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,3453 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },3451 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 3452 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 3453 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO }, 3454 3454 /* 3455 3455 * Infinity. … … 3458 3458 { /*src1 */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, 3459 3459 { /* => */ { FP64_QNAN(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, 3460 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM,3461 /*128:out */ X86_MXCSR_ DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_IE,3462 /*256:out */ X86_MXCSR_ DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_IE },3460 /*mxcsr:in */ 0, 3461 /*128:out */ X86_MXCSR_IE, 3462 /*256:out */ X86_MXCSR_IE }, 3463 3463 { { /*src2 */ { FP64_0(0), FP64_INF(1), FP64_0(0), FP64_0(0) } }, 3464 3464 { /*src1 */ { FP64_0(0), FP64_INF(0), FP64_0(0), FP64_0(0) } }, 3465 3465 { /* => */ { FP64_0(0), FP64_QNAN(1), FP64_0(0), FP64_0(0) } }, 3466 /*mxcsr:in */ X86_MXCSR_ DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,3467 /*128:out */ X86_MXCSR_ DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,3468 /*256:out */ X86_MXCSR_ DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE },3466 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 3467 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, 3468 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE }, 3469 3469 { { /*src2 */ { FP64_0(0), FP64_INF(1), FP64_0(0), FP64_0(0) } }, 3470 3470 { /*src1 */ { FP64_0(0), FP64_INF(0), FP64_0(0), FP64_0(0) } }, 3471 3471 { /* => */ { FP64_0(0), FP64_QNAN(1), FP64_0(0), FP64_0(0) } }, 3472 /*mxcsr:in */ X86_MXCSR_D M | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,3473 /*128:out */ X86_MXCSR_D M | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,3474 /*256:out */ X86_MXCSR_D M | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE },3472 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 3473 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, 3474 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE }, 3475 3475 { { /*src2 */ { FP64_INF(0), FP64_INF(1), FP64_0(0), FP64_INF(1) } }, 3476 3476 { /*src1 */ { FP64_INF(1), FP64_INF(0), FP64_0(0), FP64_INF(0) } }, 3477 3477 { /* => */ { FP64_QNAN(1), FP64_QNAN(1), FP64_0(0), FP64_QNAN(1) } }, 3478 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,3479 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,3480 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE },3478 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 3479 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 3480 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE }, 3481 3481 { { /*src2 */ { FP64_V(0, 0, 0x3fd)/*0.25*/, FP64_0(1), FP64_0(0), FP64_INF(1) } }, 3482 3482 { /*src1 */ { FP64_V(0, 0, 0x3fe)/*0.50*/, FP64_0(1), FP64_0(0), FP64_INF(0) } }, 3483 3483 { /* => */ { FP64_V(0, 0x8000000000000, 0x3fe)/*0.75*/, FP64_0(1), FP64_0(0), FP64_QNAN(1) } }, 3484 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,3485 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,3486 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_IE },3484 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 3485 /*128:out */ X86_MXCSR_RC_ZERO, 3486 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE }, 3487 3487 /* 3488 3488 * Overflow, Precision. … … 3503 3503 { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_0(0), FP64_NORM_MAX(0) } }, 3504 3504 { /* => */ { FP64_INF(0), FP64_V(1, 0, FP32_EXP_NORM_MIN + 1), FP64_0(0), FP64_INF(0) } }, 3505 /*mxcsr:in */ X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ,3506 /*128:out */ X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* i7-10700, IEM */,3507 /*256:out */ X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* i7-10700, IEM */ },3505 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 3506 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* i7-10700, IEM */, 3507 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* i7-10700, IEM */ }, 3508 3508 { { /*src2 */ { FP64_NORM_MIN(1), FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_0(0) } }, 3509 3509 { /*src1 */ { FP64_NORM_MIN(1), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_0(0) } }, 3510 3510 { /* => */ { FP64_V(1, 0, FP32_EXP_NORM_MIN + 1), FP64_INF(0), FP64_0(0), FP64_0(0) } }, 3511 /*mxcsr:in */ X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_FZ,3512 /*128:out */ X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* i7-10700, IEM */,3513 /*256:out */ X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* i7-10700, IEM */ },3511 /*mxcsr:in */ X86_MXCSR_FZ, 3512 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* i7-10700, IEM */, 3513 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* i7-10700, IEM */ }, 3514 3514 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } }, 3515 3515 { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } }, 3516 3516 { /* => */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } }, 3517 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,3518 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* i7-10700, IEM */,3519 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* i7-10700, IEM */ },3517 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 3518 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* i7-10700, IEM */, 3519 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* i7-10700, IEM */ }, 3520 3520 { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_MAX(0), FP64_0(0), FP64_NORM_SAFE_INT_MAX(1) } }, 3521 3521 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_MAX(1), FP64_0(0), FP64_NORM_SAFE_INT_MAX(1) } }, … … 3536 3536 { /*src1 */ { FP64_V(0, 0, 0x408)/* 512*/, FP64_V(0, 0xc000000000000, 0x401)/* 7*/, FP64_0(0), FP64_0(0) } }, 3537 3537 { /* => */ { FP64_V(0, 0x8000000000000, 0x409)/*1536*/, FP64_V(0, 0xf000000000000, 0x404)/*62*/, FP64_0(0), FP64_0(0) } }, 3538 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,3539 /*128:out */ X86_MXCSR_XCPT_MASK,3540 /*256:out */ X86_MXCSR_XCPT_MASK},3538 /*mxcsr:in */ 0, 3539 /*128:out */ 0, 3540 /*256:out */ 0 }, 3541 3541 { { /*src2 */ { FP64_V(0, 0x26580b4800000, 0x41d)/* 1234567890*/, FP64_V(0, 0xd6f3458800000, 0x41c)/*987654321*/, FP64_0(0), FP64_V(0, 0xcf0033a34f337, 0x432)/*4072598000007579.5*/ } }, 3542 3542 { /*src1 */ { FP64_V(1, 0x26580b4800000, 0x41d)/*-1234567890*/, FP64_V(1, 0x9000000000000, 0x405)/* -100*/, FP64_0(0), FP64_V(0, 0xd6eca42000000, 0x419)/* 123450000.5*/ } }, … … 3548 3548 { /*src1 */ { FP64_1(0), FP64_1(1), FP64_0(0), FP64_0(0) } }, 3549 3549 { /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_0(0), FP64_0(0) } }, 3550 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,3551 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,3552 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },3550 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 3551 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 3552 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO }, 3553 3553 { { /*src2 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_1(1), FP64_0(0), FP64_0(0) } }, 3554 3554 { /*src1 */ { FP64_1(0), FP64_NORM_SAFE_INT_MAX(1), FP64_0(0), FP64_0(0) } }, … … 3572 3572 { /*src1 */ { FP64_V(1, 0, 0x3fd)/*-0.25*/, FP64_NORM_MAX(1), FP64_0(0), FP64_V(0, 0, 0x3fe)/*0.50*/ } }, 3573 3573 { /* => */ { FP64_V(0, 0x8000000000000, 0x3ff)/* 1.50*/, FP64_0(1), FP64_0(0), FP64_V(0, 0x8000000000000, 0x3fe)/*0.75*/ } }, 3574 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,3575 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,3576 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },3574 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 3575 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 3576 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN }, 3577 3577 /* 3578 3578 * Denormals. … … 3621 3621 { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } }, 3622 3622 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 3623 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,3624 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,3625 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP },3623 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 3624 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 3625 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP }, 3626 3626 /** @todo More denormals. */ 3627 3627 /* … … 3696 3696 { /*src1 */ { FP32_0(0), FP32_0_x7(0) } }, 3697 3697 { /* => */ { FP32_0(0), FP32_0_x7(0) } }, 3698 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,3699 /*128:out */ X86_MXCSR_XCPT_MASK,3698 /*mxcsr:in */ 0, 3699 /*128:out */ 0, 3700 3700 /*256:out */ -1 }, 3701 3701 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V7 } }, … … 3735 3735 { /*src1 */ { FP32_INF(1), FP32_0_x7(0) } }, 3736 3736 { /* => */ { FP32_QNAN(1), FP32_0_x7(0) } }, 3737 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM,3738 /*128:out */ X86_MXCSR_ DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_IE,3737 /*mxcsr:in */ 0, 3738 /*128:out */ X86_MXCSR_IE, 3739 3739 /*256:out */ -1 }, 3740 3740 { { /*src2 */ { FP32_INF(0), FP32_RAND_x7_V1 } }, 3741 3741 { /*src1 */ { FP32_INF(1), FP32_RAND_x7_V2 } }, 3742 3742 { /* => */ { FP32_QNAN(1), FP32_RAND_x7_V2 } }, 3743 /*mxcsr:in */ X86_MXCSR_ DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,3744 /*128:out */ X86_MXCSR_ DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,3743 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 3744 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 3745 3745 /*256:out */ -1 }, 3746 3746 { { /*src2 */ { FP32_INF(1), FP32_RAND_x7_V4 } }, 3747 3747 { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V5 } }, 3748 3748 { /* => */ { FP32_QNAN(1), FP32_RAND_x7_V5 } }, 3749 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,3750 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,3749 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 3750 /*128:out */ X86_MXCSR_RC_DOWN | X86_MXCSR_IE, 3751 3751 /*256:out */ -1 }, 3752 3752 { { /*src2 */ { FP32_INF(0), FP32_RAND_x7_V6 } }, 3753 3753 { /*src1 */ { FP32_INF(1), FP32_RAND_x7_V3 } }, 3754 3754 { /* => */ { FP32_QNAN(1), FP32_RAND_x7_V3 } }, 3755 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ,3756 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,3755 /*mxcsr:in */ X86_MXCSR_FZ, 3756 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_IE, 3757 3757 /*256:out */ -1 }, 3758 3758 { { /*src2 */ { FP32_INF(0), FP32_RAND_x7_V5 } }, … … 3798 3798 { /*src1 */ { FP32_NORM_MAX(1), FP32_RAND_x7_V1 } }, 3799 3799 { /* => */ { FP32_NORM_MAX(1), FP32_RAND_x7_V1 } }, 3800 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM,3801 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_PE,3800 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 3801 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_PE, 3802 3802 /*256:out */ -1 }, 3803 3803 { { /*src2 */ { FP32_NORM_MAX(1), FP32_RAND_x7_V5 } }, … … 3831 3831 { /*src1 */ { FP32_V(1, 0, 0x7d)/*-0.25*/, FP32_RAND_x7_V2 } }, 3832 3832 { /* => */ { FP32_V(0, 0x400000, 0x7f)/* 1.50*/, FP32_RAND_x7_V2 } }, 3833 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,3834 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,3833 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 3834 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 3835 3835 /*256:out */ -1 }, 3836 3836 { { /*src2 */ { FP32_NORM_MAX(0), FP32_RAND_x7_V3 } }, 3837 3837 { /*src1 */ { FP32_NORM_MAX(1), FP32_RAND_x7_V3 } }, 3838 3838 { /* => */ { FP32_0(0), FP32_RAND_x7_V3 } }, 3839 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,3840 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,3839 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 3840 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 3841 3841 /*256:out */ -1 }, 3842 3842 { { /*src2 */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_RAND_x7_V2 } }, 3843 3843 { /*src1 */ { FP32_V(0, 0x1ea980, 0x8f)/* 81235*/, FP32_RAND_x7_V1 } }, 3844 3844 { /* => */ { FP32_V(0, 0x669050, 0x93)/*1888778*/, FP32_RAND_x7_V1 } }, 3845 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,3846 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,3845 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 3846 /*128:out */ X86_MXCSR_RC_ZERO, 3847 3847 /*256:out */ -1 }, 3848 3848 { { /*src2 */ { FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_RAND_x7_V1 } }, … … 3861 3861 { /*src1 */ { FP32_1(0), FP32_RAND_x7_V2 } }, 3862 3862 { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V2 } }, 3863 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,3864 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,3863 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 3864 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 3865 3865 /*256:out */ -1 }, 3866 3866 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V4 } }, 3867 3867 { /*src1 */ { FP32_1(1), FP32_RAND_x7_V3 } }, 3868 3868 { /* => */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_RAND_x7_V3 } }, 3869 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,3870 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,3869 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 3870 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 3871 3871 /*256:out */ -1 }, 3872 3872 { { /*src2 */ { FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_RAND_x7_V1 } }, … … 3991 3991 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 3992 3992 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 3993 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,3994 /*128:out */ X86_MXCSR_XCPT_MASK,3993 /*mxcsr:in */ 0, 3994 /*128:out */ 0, 3995 3995 /*256:out */ -1 }, 3996 3996 { { /*src2 */ { FP64_0(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, … … 4030 4030 { /*src1 */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, 4031 4031 { /* => */ { FP64_QNAN(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, 4032 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM,4033 /*128:out */ X86_MXCSR_ DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_IE,4032 /*mxcsr:in */ 0, 4033 /*128:out */ X86_MXCSR_IE, 4034 4034 /*256:out */ -1 }, 4035 4035 { { /*src2 */ { FP64_INF(0), FP64_RAND_V1(0), FP64_RAND_V2(0), FP32_RAND_V3(1) } }, 4036 4036 { /*src1 */ { FP64_INF(1), FP64_RAND_V0(0), FP64_RAND_V1(1), FP32_RAND_V1(1) } }, 4037 4037 { /* => */ { FP64_QNAN(1), FP64_RAND_V0(0), FP64_RAND_V1(1), FP32_RAND_V1(1) } }, 4038 /*mxcsr:in */ X86_MXCSR_ DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,4039 /*128:out */ X86_MXCSR_ DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,4038 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 4039 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 4040 4040 /*256:out */ -1 }, 4041 4041 { { /*src2 */ { FP64_INF(1), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 4042 4042 { /*src1 */ { FP64_INF(0), FP64_RAND_V1(1), FP64_RAND_V1(0), FP64_RAND_V0(1) } }, 4043 4043 { /* => */ { FP64_QNAN(1), FP64_RAND_V1(1), FP64_RAND_V1(0), FP64_RAND_V0(1) } }, 4044 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,4045 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,4044 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 4045 /*128:out */ X86_MXCSR_RC_DOWN | X86_MXCSR_IE, 4046 4046 /*256:out */ -1 }, 4047 4047 { { /*src2 */ { FP64_INF(0), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, 4048 4048 { /*src1 */ { FP64_INF(1), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V1(0) } }, 4049 4049 { /* => */ { FP64_QNAN(1), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V1(0) } }, 4050 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ,4051 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,4050 /*mxcsr:in */ X86_MXCSR_FZ, 4051 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_IE, 4052 4052 /*256:out */ -1 }, 4053 4053 { { /*src2 */ { FP64_INF(0), FP64_RAND_V0(0), FP64_RAND_V0(0), FP64_RAND_V0(1) } }, … … 4093 4093 { /*src1 */ { FP64_NORM_MAX(1), FP64_RAND_V2(0), FP64_RAND_V0(1), FP64_RAND_V1(0) } }, 4094 4094 { /* => */ { FP64_NORM_MAX(1), FP64_RAND_V2(0), FP64_RAND_V0(1), FP64_RAND_V1(0) } }, 4095 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM,4096 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_PE,4095 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 4096 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_PE, 4097 4097 /*256:out */ -1 }, 4098 4098 { { /*src2 */ { FP64_NORM_MAX(1), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V0(1) } }, … … 4132 4132 { /*src1 */ { FP64_V(0, 0, 0x408)/* 512*/, FP64_RAND_V2(1), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 4133 4133 { /* => */ { FP64_V(0, 0x8000000000000, 0x409)/*1536*/, FP64_RAND_V2(1), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 4134 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,4135 /*128:out */ X86_MXCSR_XCPT_MASK,4134 /*mxcsr:in */ 0, 4135 /*128:out */ 0, 4136 4136 /*256:out */ -1 }, 4137 4137 { { /*src2 */ { FP64_V(0, 0xb800000000000, 0x404)/*55*/, FP64_RAND_V2(1), FP64_RAND_V1(0), FP64_RAND_V0(1) } }, 4138 4138 { /*src1 */ { FP64_V(0, 0xc000000000000, 0x401)/* 7*/, FP64_RAND_V1(1), FP64_RAND_V3(1), FP64_RAND_V2(0) } }, 4139 4139 { /* => */ { FP64_V(0, 0xf000000000000, 0x404)/*62*/, FP64_RAND_V1(1), FP64_RAND_V3(1), FP64_RAND_V2(0) } }, 4140 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,4141 /*128:out */ X86_MXCSR_XCPT_MASK,4140 /*mxcsr:in */ 0, 4141 /*128:out */ 0, 4142 4142 /*256:out */ -1 }, 4143 4143 { { /*src2 */ { FP64_V(0, 0x26580b4800000, 0x41d)/* 1234567890*/, FP64_RAND_V0(1), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, … … 4162 4162 { /*src1 */ { FP64_1(0), FP64_RAND_V2(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, 4163 4163 { /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_RAND_V2(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, 4164 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,4165 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,4164 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 4165 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 4166 4166 /*256:out */ -1 }, 4167 4167 { { /*src2 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(0) } }, … … 4236 4236 { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } }, 4237 4237 { /* => */ { FP64_0(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } }, 4238 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,4239 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,4238 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 4239 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 4240 4240 /*256:out */ -1 }, 4241 4241 /** @todo More Denormals. */ … … 4324 4324 { /*src1 */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } }, 4325 4325 { /* => */ { FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1) } }, 4326 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,4327 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,4328 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },4326 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 4327 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 4328 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN }, 4329 4329 /* 4330 4330 * Infinity. … … 4333 4333 { /*src1 */ { FP32_INF(1), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_INF(0), FP32_INF(1), FP32_0(0), FP32_0(0) } }, 4334 4334 { /* => */ { FP32_QNAN(1), FP32_0(0), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_0(0), FP32_QNAN(1), FP32_QNAN(1) } }, 4335 /*mxcsr:in */ X86_MXCSR_IM,4336 /*128:out */ X86_MXCSR_I M | X86_MXCSR_IE,4337 /*256:out */ X86_MXCSR_I M | X86_MXCSR_IE },4335 /*mxcsr:in */ 0, 4336 /*128:out */ X86_MXCSR_IE, 4337 /*256:out */ X86_MXCSR_IE }, 4338 4338 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_INF(1), FP32_0(0), FP32_0(0) } }, 4339 4339 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_INF(0), FP32_INF(0), FP32_INF(0) } }, 4340 4340 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN(1), FP32_INF(0), FP32_INF(1), FP32_0(0) } }, 4341 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,4342 /*128:out */ X86_MXCSR_XCPT_MASK,4343 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE },4341 /*mxcsr:in */ 0, 4342 /*128:out */ 0, 4343 /*256:out */ X86_MXCSR_IE }, 4344 4344 { { /*src2 */ { FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_0(0), FP32_0(0) } }, 4345 4345 { /*src1 */ { FP32_INF(1), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_INF(0), FP32_INF(0), FP32_INF(0) } }, … … 4357 4357 { /*src1 */ { FP32_INF(0), FP32_QNAN(0), FP32_INF(1), FP32_QNAN(0), FP32_INF(1), FP32_QNAN(1), FP32_INF(0), FP32_INF(0) } }, 4358 4358 { /* => */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN(1), FP32_QNAN(0), FP32_QNAN(1), FP32_INF(0), FP32_INF(1), FP32_0(0) } }, 4359 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,4360 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,4361 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO },4359 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 4360 /*128:out */ X86_MXCSR_RC_ZERO, 4361 /*256:out */ X86_MXCSR_RC_ZERO }, 4362 4362 /* 4363 4363 * Overflow, Precision. … … 4438 4438 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1) } }, 4439 4439 { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_V(1, FP32_FRAC_NORM_MAX, FP32_EXP_SAFE_INT_MAX + 1), FP32_NORM_MAX(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_MAX(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_MAX(0), FP32_NORM_SAFE_INT_MAX(1) } }, 4440 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,4441 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_PE,4442 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_PE },4440 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 4441 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, 4442 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE }, 4443 4443 /* 4444 4444 * Normals. … … 4447 4447 { /*src1 */ { FP32_V(1, 0, 0x7d)/*-0.25*/, FP32_V(0, 0x600000, 0x7f)/*1.75*/, FP32_NORM_MAX(1), FP32_0(0), FP32_V(0, 0, 0x7e)/*0.50*/, FP32_V(0, 0, 0x7d)/*0.25*/, FP32_0(0), FP32_0(0) } }, 4448 4448 { /* => */ { FP32_V(0, 0x400000, 0x7f)/* 1.50*/, FP32_NORM_MAX(1), FP32_V(0, 0x400000, 0x7e)/*0.75*/, FP32_NORM_MAX(0), FP32_V(0, 0x400000, 0x7e)/*0.75*/, FP32_0(0), FP32_NORM_MAX(0), FP32_V(0, 0x600000, 0x7f)/*1.75*/ } }, 4449 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,4450 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,4451 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },4449 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 4450 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 4451 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN }, 4452 4452 { { /*src2 */ { FP32_NORM_V1(1), FP32_NORM_V1(0), FP32_NORM_V4(1), FP32_NORM_V4(0), FP32_NORM_V1(1), FP32_NORM_V1(0), FP32_NORM_V2(1), FP32_NORM_V2(0) } }, 4453 4453 { /*src1 */ { FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_NORM_MIN(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_V3(0), FP32_NORM_V3(1) } }, … … 4459 4459 { /*src1 */ { FP32_V(0, 0x669050, 0x93)/*1888778*/, FP32_V(1, 0x1ea980, 0x8f)/* -81235.00*/, FP32_V(0, 0x253468, 0x93)/*1353357*/, FP32_V(1, 0x7c9000, 0x88)/*-1010.25*/, FP32_V(0, 0x5c0000, 0x84)/* 55*/, FP32_V(0, 0x600000, 0x81)/*7*/, FP32_V(0, 0x534000, 0x86)/* 211.25*/, FP32_1(1) } }, 4460 4460 { /* => */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_V(0, 0x780000, 0x84)/* 62*/, FP32_V(0, 0x5c0000, 0x84)/* 55.00*/, FP32_V(0, 0x780000, 0x84)/* 62*/, FP32_V(0, 0x524000, 0x86)/*210.25*/, FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_V(0, 0x534000, 0x86)/*211.25*/ } }, 4461 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,4462 /*128:out */ X86_MXCSR_XCPT_MASK,4463 /*256:out */ X86_MXCSR_XCPT_MASK},4461 /*mxcsr:in */ 0, 4462 /*128:out */ 0, 4463 /*256:out */ 0 }, 4464 4464 { { /*src2 */ { FP32_V(0, 0x3c614e, 0x96)/*12345678*/, FP32_V(0, 0x3c614e, 0x96)/*12345678*/, FP32_0(0), FP32_NORM_V1(0), FP32_V(0, 0x3c614e, 0x97)/*24691356*/, FP32_V(1, 0x3c614e, 0x96)/*-12345678*/, FP32_0(0), FP32_1(1) } }, 4465 4465 { /*src1 */ { FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_V(1, 0x712060, 0x92)/* -987654*/, FP32_NORM_V3(1), FP32_0(0), FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_V(1, 0x712060, 0x92)/* -987654*/, FP32_0(0), FP32_1(0) } }, 4466 4466 { /* => */ { FP32_V(0, 0x6cb99c, 0x97)/*31028024*/, FP32_NORM_V3(1), FP32_V(0, 0x3c614e, 0x97)/*24691356*/, FP32_NORM_V1(0), FP32_V(0, 0x6cb99c, 0x97)/*31028024*/, FP32_1(0), FP32_V(0, 0x3c614e, 0x96)/*12345678*/, FP32_1(1) } }, 4467 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,4468 /*128:out */ X86_MXCSR_XCPT_MASK,4469 /*256:out */ X86_MXCSR_XCPT_MASK},4467 /*mxcsr:in */ 0, 4468 /*128:out */ 0, 4469 /*256:out */ 0 }, 4470 4470 { { /*src2 */ { FP32_1(0), FP32_1(1), FP32_1(1), FP32_0(0), FP32_1(0), FP32_1(1), FP32_1(1), FP32_0(0) } }, 4471 4471 { /*src1 */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_1(0), FP32_NORM_SAFE_INT_MAX(0), FP32_1(1), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_1(0), FP32_NORM_SAFE_INT_MAX(0), FP32_1(1) } }, 4472 4472 { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_0(0), FP32_1(1), FP32_NORM_SAFE_INT_MAX(0), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_0(0), FP32_1(1) } }, 4473 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,4474 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,4475 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO },4473 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 4474 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 4475 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO }, 4476 4476 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_1(1), FP32_0(0), FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_1(1), FP32_0(0) } }, 4477 4477 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_NORM_SAFE_INT_MAX(1), FP32_1(1), FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_NORM_SAFE_INT_MAX(1), FP32_1(1) } }, … … 4489 4489 { /*src1 */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_V(0, 0x430ebc, 0x91)/*399477.875*/, FP32_V(0, 0x3ce348, 0x90)/*193421.125*/, FP32_V(0, 0x16b43a, 0x93)/*1234567.25*/, FP32_V(0, 0x00c6d3, 0x94)/*2109876.75*/, FP32_V(0, 0x792318, 0x91)/*510232.750*/, FP32_V(1, 0x316740, 0x8e)/* -45415.250*/ } }, 4490 4490 { /* => */ { FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/, FP32_V(0, 0x10c030, 0x92)/*592899.000*/, FP32_V(0, 0x52e0b4, 0x92)/*863755.250*/, FP32_V(1, 0, FP32_EXP_SAFE_INT_MIN + 1), FP32_V(0, 0x4c20f0, 0x94)/*3344444.00*/, FP32_V(0, 0x62f630, 0x91)/*464817.50*/, FP32_V(0, 0, FP32_EXP_SAFE_INT_MIN + 1), FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/ } }, 4491 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,4492 /*128:out */ X86_MXCSR_XCPT_MASK,4493 /*256:out */ X86_MXCSR_XCPT_MASK},4491 /*mxcsr:in */ 0, 4492 /*128:out */ 0, 4493 /*256:out */ 0 }, 4494 4494 /* 4495 4495 * Denormals. … … 4519 4519 { /*src1 */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0) } }, 4520 4520 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 4521 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,4522 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,4523 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK},4521 /*mxcsr:in */ X86_MXCSR_DAZ, 4522 /*128:out */ X86_MXCSR_DAZ, 4523 /*256:out */ X86_MXCSR_DAZ }, 4524 4524 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } }, 4525 4525 { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0) } }, … … 4552 4552 { /*src1 */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 4553 4553 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 4554 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,4555 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,4556 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK},4554 /*mxcsr:in */ X86_MXCSR_DAZ, 4555 /*128:out */ X86_MXCSR_DAZ, 4556 /*256:out */ X86_MXCSR_DAZ }, 4557 4557 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } }, 4558 4558 { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0) } }, 4559 4559 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 4560 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,4561 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,4562 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP },4560 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 4561 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 4562 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP }, 4563 4563 /** @todo More Denormals. */ 4564 4564 /* … … 4657 4657 { /*src1 */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } }, 4658 4658 { /* => */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_0(1) } }, 4659 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,4660 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,4661 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },4659 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 4660 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 4661 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN }, 4662 4662 /* 4663 4663 * Infinity. … … 4666 4666 { /*src1 */ { FP64_INF(1), FP64_INF(0), FP64_0(0), FP64_0(0) } }, 4667 4667 { /* => */ { FP64_QNAN(1), FP64_QNAN(1), FP64_0(0), FP64_QNAN(1) } }, 4668 /*mxcsr:in */ X86_MXCSR_IM,4669 /*128:out */ X86_MXCSR_I M | X86_MXCSR_IE,4670 /*256:out */ X86_MXCSR_I M | X86_MXCSR_IE },4668 /*mxcsr:in */ 0, 4669 /*128:out */ X86_MXCSR_IE, 4670 /*256:out */ X86_MXCSR_IE }, 4671 4671 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_INF(1), FP64_INF(1) } }, 4672 4672 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_INF(1), FP64_INF(0) } }, 4673 4673 { /* => */ { FP64_0(0), FP64_0(0), FP64_QNAN(1), FP64_INF(1) } }, 4674 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,4675 /*128:out */ X86_MXCSR_XCPT_MASK,4676 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE },4674 /*mxcsr:in */ 0, 4675 /*128:out */ 0, 4676 /*256:out */ X86_MXCSR_IE }, 4677 4677 { { /*src2 */ { FP64_INF(0), FP64_INF(1), FP64_INF(0), FP64_INF(1) } }, 4678 4678 { /*src1 */ { FP64_INF(1), FP64_INF(0), FP64_0(0), FP64_0(0) } }, … … 4690 4690 { /*src1 */ { FP64_INF(0), FP64_QNAN(0), FP64_INF(1), FP64_QNAN(0) } }, 4691 4691 { /* => */ { FP64_QNAN(0), FP64_QNAN(1), FP64_QNAN(0), FP64_QNAN(0) } }, 4692 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,4693 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,4694 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO },4692 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 4693 /*128:out */ X86_MXCSR_RC_ZERO, 4694 /*256:out */ X86_MXCSR_RC_ZERO }, 4695 4695 /* 4696 4696 * Overflow, Precision. … … 4705 4705 { /*src1 */ { FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(1) } }, 4706 4706 { /* => */ { FP64_INF(1), FP64_V(1, FP32_FRAC_NORM_MIN, FP32_EXP_NORM_MIN + 1), FP64_INF(1), FP64_INF(0) } }, 4707 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM,4708 /*128:out */ X86_MXCSR_O M | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY,4709 /*256:out */ X86_MXCSR_O M | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY },4707 /*mxcsr:in */ 0, 4708 /*128:out */ X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY, 4709 /*256:out */ X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY }, 4710 4710 { { /*src2 */ { FP64_NORM_MAX(1), FP64_NORM_MAX(0), FP64_0(0), FP64_0(0) } }, 4711 4711 { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1) } }, 4712 4712 { /* => */ { FP64_NORM_MAX(0), FP64_0(0), FP64_NORM_MAX(1), FP64_0(0) } }, 4713 /*mxcsr:in */ X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,4714 /*128:out */ X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY,4715 /*256:out */ X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY },4713 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 4714 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY, 4715 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY }, 4716 4716 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_0(0), FP64_NORM_MIN(1) } }, 4717 4717 { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MIN(1) } }, 4718 4718 { /* => */ { FP64_INF(0), FP64_0(0), FP64_V(1, 0, FP32_EXP_NORM_MIN + 1), FP64_NORM_MIN(1) } }, 4719 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_RC_UP,4720 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY,4721 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY },4719 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 4720 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY, 4721 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY }, 4722 4722 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_0(0), FP64_NORM_MAX(0) } }, 4723 4723 { /*src1 */ { FP64_NORM_MIN(1), FP64_NORM_MAX(0), FP64_NORM_MIN(0), FP64_NORM_MAX(1) } }, 4724 4724 { /* => */ { FP64_NORM_MAX(0), FP64_INF(0), FP64_V(1, FP64_FRAC_NORM_MAX - 1, FP64_EXP_NORM_MAX), FP64_NORM_MAX(0) } }, 4725 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_RC_UP,4726 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE,4727 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE },4725 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 4726 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE, 4727 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE }, 4728 4728 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_0(0) } }, 4729 4729 { /*src1 */ { FP64_NORM_MIN(1), FP64_NORM_MIN(1), FP64_NORM_MIN(0), FP64_NORM_MIN(0) } }, 4730 4730 { /* => */ { FP64_V(1, 0, FP32_EXP_NORM_MIN + 1), FP64_NORM_MAX(0), FP64_V(0, 0, FP32_EXP_NORM_MIN + 1), FP64_NORM_MAX(0) } }, 4731 /*mxcsr:in */ X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,4732 /*128:out */ X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY,4733 /*256:out */ X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY },4731 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 4732 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY, 4733 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY }, 4734 4734 { { /*src2 */ { FP64_0(0), FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MIN(0) } }, 4735 4735 { /*src1 */ { FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MIN(1), FP64_NORM_MIN(1) } }, 4736 4736 { /* => */ { FP64_V(1, FP64_FRAC_NORM_MAX, FP64_EXP_NORM_MAX), FP64_NORM_MAX(0), FP64_V(1, 0, FP32_EXP_NORM_MIN + 1), FP64_0(0) } }, 4737 /*mxcsr:in */ X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,4738 /*128:out */ X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY,4739 /*256:out */ X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY },4737 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 4738 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY, 4739 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY }, 4740 4740 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1) } }, 4741 4741 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_NORM_MAX(0), FP64_NORM_MAX(0) } }, … … 4747 4747 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MIN(0) } }, 4748 4748 { /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0), FP64_0(0) } }, 4749 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,4750 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_PE,4751 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_PE },4749 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 4750 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, 4751 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE }, 4752 4752 /* 4753 4753 * Normals. … … 4756 4756 { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_V1(0), FP64_NORM_V1(1) } }, 4757 4757 { /* => */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_0(1) } }, 4758 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,4759 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,4760 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },4758 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 4759 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 4760 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN }, 4761 4761 { { /*src2 */ { FP64_V(0, 0xb800000000000, 0x404)/* 55*/, FP64_V(0, 0xc000000000000, 0x401)/* 7*/, FP64_V(0, 0x26580b4800000, 0x41d)/*1234567890*/, FP64_V(1, 0x26580b4800000, 0x41d)/*-1234567890*/ } }, 4762 4762 { /*src1 */ { FP64_V(0, 0, 0x409)/*1024*/, FP64_V(0, 0, 0x408)/*512*/, FP64_V(0, 0xd6f3458800000, 0x41c)/* 987654321*/, FP64_V(1, 0x9000000000000, 0x405)/* -100*/ } }, 4763 4763 { /* => */ { FP64_V(0, 0x8000000000000, 0x409)/*1536*/, FP64_V(0, 0xf000000000000, 0x404)/* 62*/, FP64_V(0, 0xd6f3426800000, 0x41c)/* 987654221*/, FP64_0(0) } }, 4764 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,4765 /*128:out */ X86_MXCSR_XCPT_MASK,4766 /*256:out */ X86_MXCSR_XCPT_MASK},4764 /*mxcsr:in */ 0, 4765 /*128:out */ 0, 4766 /*256:out */ 0 }, 4767 4767 { { /*src2 */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_NORM_V2(1), FP64_NORM_V2(0) } }, 4768 4768 { /*src1 */ { FP64_V(0, 0xcf0033a34f337, 0x432)/*4072598000007579.5*/, FP64_V(0, 0xd6eca42000000, 0x419)/* 123450000.50*/, FP64_NORM_V0(1), FP64_NORM_V0(0) } }, … … 4774 4774 { /*src1 */ { FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_1(0), FP64_NORM_V1(0), FP64_NORM_V1(1) } }, 4775 4775 { /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_0(0), FP64_0(0) } }, 4776 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,4777 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,4778 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },4776 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 4777 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 4778 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO }, 4779 4779 { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_0(0), FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(1) } }, 4780 4780 { /*src1 */ { FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(0) } }, … … 4815 4815 { /*src1 */ { FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(1), FP64_DENORM_MAX(1) } }, 4816 4816 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(1) } }, 4817 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,4818 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,4819 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK},4817 /*mxcsr:in */ X86_MXCSR_DAZ, 4818 /*128:out */ X86_MXCSR_DAZ, 4819 /*256:out */ X86_MXCSR_DAZ }, 4820 4820 { { /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 4821 4821 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0) } }, … … 4842 4842 { /*src1 */ { FP64_0(1), FP64_DENORM_MAX(0), FP64_DENORM_MAX(1), FP64_0(0) } }, 4843 4843 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(1) } }, 4844 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK,4845 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK,4846 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK},4844 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 4845 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 4846 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO }, 4847 4847 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } }, 4848 4848 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_DENORM_MIN(1), FP64_DENORM_MIN(1) } }, … … 4954 4954 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } }, 4955 4955 { /* => */ { FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1) } }, 4956 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,4957 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,4958 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN },4956 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 4957 /*128:out */ X86_MXCSR_RC_DOWN, 4958 /*256:out */ X86_MXCSR_RC_DOWN }, 4959 4959 { { /*src2 */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } }, 4960 4960 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } }, 4961 4961 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 4962 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ,4963 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ,4964 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ },4962 /*mxcsr:in */ X86_MXCSR_FZ, 4963 /*128:out */ X86_MXCSR_FZ, 4964 /*256:out */ X86_MXCSR_FZ }, 4965 4965 /* 4966 4966 * Infinity. … … 4969 4969 { /*src1 */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0) } }, 4970 4970 { /* => */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0) } }, 4971 /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,4972 /*128:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,4973 /*256:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM},4971 /*mxcsr:in */ 0, 4972 /*128:out */ 0, 4973 /*256:out */ 0 }, 4974 4974 { { /*src2 */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_INF(1), FP32_0(0), FP32_0(0), FP32_INF(1) } }, 4975 4975 { /*src1 */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_INF(1) } }, 4976 4976 { /* => */ { FP32_QNAN(1), FP32_0(0), FP32_0(0), FP32_QNAN(1), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_QNAN(1) } }, 4977 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,4978 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,4979 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE },4977 /*mxcsr:in */ 0, 4978 /*128:out */ X86_MXCSR_IE, 4979 /*256:out */ X86_MXCSR_IE }, 4980 4980 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1) } }, 4981 4981 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1) } }, 4982 4982 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN(1) } }, 4983 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,4984 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,4985 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE },4983 /*mxcsr:in */ 0, 4984 /*128:out */ X86_MXCSR_IE, 4985 /*256:out */ X86_MXCSR_IE }, 4986 4986 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(1), FP32_0(1), FP32_0(0) } }, 4987 4987 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(1), FP32_0(1), FP32_0(0) } }, 4988 4988 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN(1), FP32_0(0), FP32_0(0), FP32_0(0) } }, 4989 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ,4990 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ,4991 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE },4989 /*mxcsr:in */ X86_MXCSR_FZ, 4990 /*128:out */ X86_MXCSR_FZ, 4991 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_IE }, 4992 4992 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0) } }, 4993 4993 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0) } }, … … 5123 5123 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_1(0), FP32_1(1), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_1(0), FP32_0(1), FP32_0(0) } }, 5124 5124 { /* => */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_NORM_SAFE_INT_MAX(0), FP32_0(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(0), FP32_V(1, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_0(0), FP32_0(0) } }, 5125 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ,5126 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ,5127 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ },5125 /*mxcsr:in */ X86_MXCSR_FZ, 5126 /*128:out */ X86_MXCSR_FZ, 5127 /*256:out */ X86_MXCSR_FZ }, 5128 5128 { { /*src2 */ { FP32_1(0), FP32_1(0), FP32_0(1), FP32_1(1), FP32_0(1), FP32_1(1), FP32_1(1), FP32_NORM_SAFE_INT_MAX(0) } }, 5129 5129 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_NORM_SAFE_INT_MAX(0), FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1) } }, … … 5141 5141 { /*src1 */ { FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/, FP32_V(0, 0x10c030, 0x92)/*592899.000*/, FP32_V(0, 0x52e0b4, 0x92)/*863755.250*/, FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_V(0, 0x4c20f0, 0x94)/*3344444.00*/, FP32_V(0, 0x792318, 0x91)/*510232.75*/, FP32_V(1, 0x769b50, 0x92)/*-1010101.000*/ } }, 5142 5142 { /* => */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_V(0, 0x430ebc, 0x91)/*399477.875*/, FP32_V(0, 0x6423f2, 0x92)/*934463.125*/, FP32_V(0, 0, FP32_EXP_SAFE_INT_MIN + 1), FP32_V(1, 0, FP32_EXP_SAFE_INT_MIN + 1), FP32_V(0, 0x16b43a, 0x93)/*1234567.25*/, FP32_V(0, 0x62f630, 0x91)/*464817.50*/, FP32_V(1, 0x769b5e, 0x92)/*-1010101.875*/ } }, 5143 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,5144 /*128:out */ X86_MXCSR_XCPT_MASK,5145 /*256:out */ X86_MXCSR_XCPT_MASK},5143 /*mxcsr:in */ 0, 5144 /*128:out */ 0, 5145 /*256:out */ 0 }, 5146 5146 /* 5147 5147 * Denormals. … … 5191 5191 { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0) } }, 5192 5192 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 5193 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,5194 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,5195 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP },5193 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 5194 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 5195 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP }, 5196 5196 { { /*src2 */ { FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 5197 5197 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, … … 5238 5238 { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(1), FP32_DENORM_MIN(0) } }, 5239 5239 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 5240 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,5241 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,5242 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK},5240 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 5241 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 5242 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP }, 5243 5243 /** @todo More denormals. */ 5244 5244 /* … … 5313 5313 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 5314 5314 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 5315 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,5316 /*128:out */ X86_MXCSR_XCPT_MASK,5317 /*256:out */ X86_MXCSR_XCPT_MASK},5315 /*mxcsr:in */ 0, 5316 /*128:out */ 0, 5317 /*256:out */ 0 }, 5318 5318 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 5319 5319 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, … … 5352 5352 { /*src1 */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_INF(0) } }, 5353 5353 { /* => */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_INF(0) } }, 5354 /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,5355 /*128:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,5356 /*256:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM},5354 /*mxcsr:in */ 0, 5355 /*128:out */ 0, 5356 /*256:out */ 0 }, 5357 5357 { { /*src2 */ { FP64_INF(0), FP64_INF(1), FP64_INF(1), FP64_INF(1) } }, 5358 5358 { /*src1 */ { FP64_INF(0), FP64_INF(1), FP64_INF(0), FP64_INF(1) } }, 5359 5359 { /* => */ { FP64_QNAN(1), FP64_QNAN(1), FP64_INF(0), FP64_QNAN(1) } }, 5360 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,5361 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,5362 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE },5360 /*mxcsr:in */ 0, 5361 /*128:out */ X86_MXCSR_IE, 5362 /*256:out */ X86_MXCSR_IE }, 5363 5363 { { /*src2 */ { FP64_INF(0), FP64_INF(0), FP64_INF(1), FP64_INF(1) } }, 5364 5364 { /*src1 */ { FP64_INF(0), FP64_INF(1), FP64_INF(0), FP64_INF(1) } }, 5365 5365 { /* => */ { FP64_QNAN(1), FP64_INF(1), FP64_INF(0), FP64_QNAN(1) } }, 5366 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,5367 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,5368 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE },5366 /*mxcsr:in */ 0, 5367 /*128:out */ X86_MXCSR_IE, 5368 /*256:out */ X86_MXCSR_IE }, 5369 5369 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_INF(1), FP64_INF(1) } }, 5370 5370 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_INF(0), FP64_INF(1) } }, 5371 5371 { /* => */ { FP64_0(0), FP64_0(0), FP64_INF(0), FP64_QNAN(1) } }, 5372 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ,5373 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ,5374 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE },5372 /*mxcsr:in */ X86_MXCSR_FZ, 5373 /*128:out */ X86_MXCSR_FZ, 5374 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_IE }, 5375 5375 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_INF(0) } }, 5376 5376 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_INF(0) } }, … … 5415 5415 { /*src1 */ { FP64_NORM_MAX(1), FP64_0(0), FP64_0(0), FP64_NORM_MAX(1) } }, 5416 5416 { /* => */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_INF(1) } }, 5417 /*mxcsr:in */ X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_FZ,5418 /*128:out */ X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY,5419 /*256:out */ X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY },5417 /*mxcsr:in */ X86_MXCSR_FZ, 5418 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY, 5419 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY }, 5420 5420 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_V(1, 0, FP32_EXP_NORM_MIN + 1), FP64_NORM_MIN(1) } }, 5421 5421 { /*src1 */ { FP64_NORM_MAX(1), FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MIN(1) } }, 5422 5422 { /* => */ { FP64_INF(1), FP64_NORM_MAX(0), FP64_NORM_MIN(0), FP64_0(0) } }, 5423 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM,5424 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_O M | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,5425 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_O M | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE },5423 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 5424 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE, 5425 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE }, 5426 5426 { { /*src2 */ { FP64_V(1, 0, FP32_EXP_NORM_MIN + 1), FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_V(1, 0, 2) } }, 5427 5427 { /*src1 */ { FP64_NORM_MIN(1), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MIN(1) } }, 5428 5428 { /* => */ { FP64_NORM_MIN(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MIN(0) } }, 5429 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM,5430 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_O M | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY,5431 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_O M | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY },5429 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 5430 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY, 5431 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY }, 5432 5432 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_NORM_MIN(0), FP64_NORM_MAX(0) } }, 5433 5433 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_NORM_MIN(0), FP64_NORM_MAX(1) } }, 5434 5434 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_NORM_MAX(1) } }, 5435 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,5436 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,5437 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY },5435 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 5436 /*128:out */ X86_MXCSR_RC_ZERO, 5437 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY }, 5438 5438 { { /*src2 */ { FP64_NORM_MIN(0), FP64_NORM_MIN(0), FP64_NORM_MIN(1), FP64_NORM_MIN(0) } }, 5439 5439 { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } }, 5440 5440 { /* => */ { FP64_V(0,0xffffffffffffe,0x7fe), FP64_V(0,0xffffffffffffe,0x7fe), FP64_V(1,0xffffffffffffe,0x7fe), FP64_V(0,0xffffffffffffe,0x7fe) } }, 5441 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM) | X86_MXCSR_RC_ZERO,5442 /*128:out */ X86_MXCSR_ XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM) | X86_MXCSR_RC_ZERO | X86_MXCSR_PE,5443 /*256:out */ X86_MXCSR_ XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM) | X86_MXCSR_RC_ZERO | X86_MXCSR_PE },5441 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 5442 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, 5443 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE }, 5444 5444 { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_MAX(0), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MAX(1) } }, 5445 5445 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_MAX(1), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MAX(1) } }, … … 5460 5460 { /*src1 */ { FP64_V(0, 0x8000000000000, 0x409)/*1536*/, FP64_V(1, 0xc000000000000, 0x401)/* 7*/, FP64_V(0, 0xb800000000000, 0x404)/*55*/, FP64_V(0, 0, 0x409)/*1024*/ } }, 5461 5461 { /* => */ { FP64_V(0, 0, 0x408)/* 512*/, FP64_V(1, 0xf000000000000, 0x404)/*62*/, FP64_V(0, 0xf000000000000, 0x404)/*62*/, FP64_V(1, 0, 0x408)/* 512*/ } }, 5462 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,5463 /*128:out */ X86_MXCSR_XCPT_MASK,5464 /*256:out */ X86_MXCSR_XCPT_MASK},5462 /*mxcsr:in */ 0, 5463 /*128:out */ 0, 5464 /*256:out */ 0 }, 5465 5465 { { /*src2 */ { FP64_V(0, 0x26580b4800000, 0x41d)/*1234567890*/, FP64_V(0, 0x9000000000000, 0x405)/* 100*/, FP64_0(0), FP64_V(0, 0xd6eca42000000, 0x419)/* 123450000.5*/ } }, 5466 5466 { /*src1 */ { FP64_V(0, 0x26580b4800000, 0x41d)/*1234567890*/, FP64_V(0, 0xd6f3458800000, 0x41c)/*987654321*/, FP64_0(0), FP64_V(0, 0xcf00348ec5858, 0x432)/*4072598123457580.0*/ } }, 5467 5467 { /* => */ { FP64_0(0), FP64_V(0, 0xd6f3426800000, 0x41c)/*987654221*/, FP64_0(0), FP64_V(0, 0xcf0033a34f337, 0x432)/*4072598000007579.5*/ } }, 5468 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,5469 /*128:out */ X86_MXCSR_XCPT_MASK,5470 /*256:out */ X86_MXCSR_XCPT_MASK},5468 /*mxcsr:in */ 0, 5469 /*128:out */ 0, 5470 /*256:out */ 0 }, 5471 5471 { { /*src2 */ { FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_NORM_SAFE_INT_MAX(0), FP64_0(0), FP64_0(0) } }, 5472 5472 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_1(0), FP64_0(0), FP64_0(0) } }, 5473 5473 { /* => */ { FP64_1(0), FP64_V(1, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_0(0), FP64_0(0) } }, 5474 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,5475 /*128:out */ X86_MXCSR_XCPT_MASK,5476 /*256:out */ X86_MXCSR_XCPT_MASK},5474 /*mxcsr:in */ 0, 5475 /*128:out */ 0, 5476 /*256:out */ 0 }, 5477 5477 { { /*src2 */ { FP64_1(0), FP64_1(1), FP64_1(1), FP64_NORM_SAFE_INT_MAX(0) } }, 5478 5478 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_1(0) } }, 5479 5479 { /* => */ { FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0), FP64_V(1, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX) } }, 5480 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK,5481 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK,5482 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK},5480 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 5481 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 5482 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO }, 5483 5483 { { /*src2 */ { FP64_NORM_SAFE_INT_MAX(1), FP64_0(0), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(1) } }, 5484 5484 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MIN(1), FP64_0(0), FP64_NORM_SAFE_INT_MIN(0) } }, 5485 5485 { /* => */ { FP64_0(0), FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(1), FP64_V(0, 0, FP32_EXP_SAFE_INT_MIN + 1) } }, 5486 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,5487 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,5488 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK},5486 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 5487 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 5488 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP }, 5489 5489 { { /*src2 */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_0(0), FP64_0(1), FP64_NORM_SAFE_INT_MIN(0) } }, 5490 5490 { /*src1 */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_0(0), FP64_0(1), FP64_NORM_SAFE_INT_MIN(1) } }, 5491 5491 { /* => */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_0(1), FP64_0(1), FP64_V(1, 0, FP32_EXP_SAFE_INT_MIN + 1) } }, 5492 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_XCPT_MASK,5493 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_XCPT_MASK,5494 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_XCPT_MASK},5492 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 5493 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 5494 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN }, 5495 5495 /* 5496 5496 * Denormals. … … 5519 5519 { /*src1 */ { FP64_0(0), FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0) } }, 5520 5520 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 5521 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,5522 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,5523 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK},5521 /*mxcsr:in */ X86_MXCSR_DAZ, 5522 /*128:out */ X86_MXCSR_DAZ, 5523 /*256:out */ X86_MXCSR_DAZ }, 5524 5524 { { /*src2 */ { FP64_DENORM_MIN(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } }, 5525 5525 { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } }, 5526 5526 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 5527 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,5528 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,5529 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK},5527 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 5528 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 5529 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP }, 5530 5530 /** @todo More denormals. */ 5531 5531 /* … … 5600 5600 { /*src1 */ { FP32_0(0), FP32_0_x7(0) } }, 5601 5601 { /* => */ { FP32_0(0), FP32_0_x7(0) } }, 5602 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,5603 /*128:out */ X86_MXCSR_XCPT_MASK,5602 /*mxcsr:in */ 0, 5603 /*128:out */ 0, 5604 5604 /*256:out */ -1 }, 5605 5605 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V0 } }, … … 5639 5639 { /*src1 */ { FP32_INF(1), FP32_0_x7(0) } }, 5640 5640 { /* => */ { FP32_INF(1), FP32_0_x7(0) } }, 5641 /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,5642 /*128:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,5641 /*mxcsr:in */ 0, 5642 /*128:out */ 0, 5643 5643 /*256:out */ -1 }, 5644 5644 { { /*src2 */ { FP32_INF(0), FP32_RAND_x7_V6 } }, 5645 5645 { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V7 } }, 5646 5646 { /* => */ { FP32_QNAN(1), FP32_RAND_x7_V7 } }, 5647 /*mxcsr:in */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM),5648 /*128:out */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) |X86_MXCSR_IE,5647 /*mxcsr:in */ 0, 5648 /*128:out */ X86_MXCSR_IE, 5649 5649 /*256:out */ -1 }, 5650 5650 { { /*src2 */ { FP32_INF(1), FP32_RAND_x7_V0 } }, 5651 5651 { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V1 } }, 5652 5652 { /* => */ { FP32_INF(0), FP32_RAND_x7_V1 } }, 5653 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,5654 /*128:out */ X86_MXCSR_XCPT_MASK,5653 /*mxcsr:in */ 0, 5654 /*128:out */ 0, 5655 5655 /*256:out */ -1 }, 5656 5656 { { /*src2 */ { FP32_INF(1), FP32_RAND_x7_V4 } }, 5657 5657 { /*src1 */ { FP32_INF(1), FP32_RAND_x7_V3 } }, 5658 5658 { /* => */ { FP32_QNAN(1), FP32_RAND_x7_V3 } }, 5659 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ,5660 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,5659 /*mxcsr:in */ X86_MXCSR_FZ, 5660 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_IE, 5661 5661 /*256:out */ -1 }, 5662 5662 { { /*src2 */ { FP32_INF(0), FP32_RAND_x7_V5 } }, … … 5669 5669 { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V2 } }, 5670 5670 { /* => */ { FP32_INF(0), FP32_RAND_x7_V2 } }, 5671 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,5672 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,5671 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 5672 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 5673 5673 /*256:out */ -1 }, 5674 5674 /* … … 5720 5720 { /*src1 */ { FP32_NORM_MAX(0), FP32_0_x7(0) } }, 5721 5721 { /* => */ { FP32_NORM_MAX(0), FP32_0_x7(0) } }, 5722 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM,5723 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_PE,5722 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 5723 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_PE, 5724 5724 /*256:out */ -1 }, 5725 5725 { { /*src2 */ { FP32_NORM_MAX(0), FP32_0_x7(0) } }, … … 5759 5759 { /*src1 */ { FP32_V(0, 0, 0x7d)/*0.25*/, FP32_RAND_x7_V2 } }, 5760 5760 { /* => */ { FP32_V(1, 0x400000, 0x7f)/*1.50*/, FP32_RAND_x7_V2 } }, 5761 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,5762 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,5761 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 5762 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 5763 5763 /*256:out */ -1 }, 5764 5764 { { /*src2 */ { FP32_NORM_MAX(1), FP32_RAND_x7_V3 } }, 5765 5765 { /*src1 */ { FP32_NORM_MAX(1), FP32_RAND_x7_V4 } }, 5766 5766 { /* => */ { FP32_0(0), FP32_RAND_x7_V4 } }, 5767 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,5768 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,5767 /*mxcsr:in */ X86_MXCSR_RC_UP, 5768 /*128:out */ X86_MXCSR_RC_UP, 5769 5769 /*256:out */ -1 }, 5770 5770 { { /*src2 */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_RAND_x7_V5 } }, 5771 5771 { /*src1 */ { FP32_V(0, 0x669050, 0x93)/*1888778*/, FP32_RAND_x7_V6 } }, 5772 5772 { /* => */ { FP32_V(0, 0x1ea980, 0x8f)/* 81235*/, FP32_RAND_x7_V6 } }, 5773 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,5774 /*128:out */ X86_MXCSR_XCPT_MASK,5773 /*mxcsr:in */ 0, 5774 /*128:out */ 0, 5775 5775 /*256:out */ -1 }, 5776 5776 { { /*src2 */ { FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_RAND_x7_V7 } }, 5777 5777 { /*src1 */ { FP32_V(0, 0x253468, 0x93)/*1353357.00*/, FP32_RAND_x7_V0 } }, 5778 5778 { /* => */ { FP32_V(0, 0x7c9000, 0x88)/* 1010.25*/, FP32_RAND_x7_V0 } }, 5779 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,5780 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,5779 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 5780 /*128:out */ X86_MXCSR_RC_ZERO, 5781 5781 /*256:out */ -1 }, 5782 5782 { { /*src2 */ { FP32_V(0, 0x712060, 0x92)/* 987654*/, FP32_RAND_x7_V0 } }, … … 5789 5789 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V4 } }, 5790 5790 { /* => */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_RAND_x7_V4 } }, 5791 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,5792 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,5791 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 5792 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 5793 5793 /*256:out */ -1 }, 5794 5794 { { /*src2 */ { FP32_V(1, 0x600000, 0x7e)/* -0.875*/, FP32_RAND_x7_V5 } }, 5795 5795 { /*src1 */ { FP32_V(0, 0x769b50, 0x92)/* 1010101.000*/, FP32_RAND_x7_V6 } }, 5796 5796 { /* => */ { FP32_V(0, 0x769b5e, 0x92)/* 1010101.875*/, FP32_RAND_x7_V6 } }, 5797 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,5798 /*128:out */ X86_MXCSR_XCPT_MASK,5797 /*mxcsr:in */ 0, 5798 /*128:out */ 0, 5799 5799 /*256:out */ -1 }, 5800 5800 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_x7_V1 } }, … … 5831 5831 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V3 } }, 5832 5832 { /* => */ { FP32_0(0), FP32_RAND_x7_V3 } }, 5833 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,5834 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,5833 /*mxcsr:in */ X86_MXCSR_DAZ, 5834 /*128:out */ X86_MXCSR_DAZ, 5835 5835 /*256:out */ -1 }, 5836 5836 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_RAND_x7_V6 } }, 5837 5837 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V6 } }, 5838 5838 { /* => */ { FP32_0(0), FP32_RAND_x7_V6 } }, 5839 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,5840 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,5839 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 5840 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 5841 5841 /*256:out */ -1 }, 5842 5842 /** @todo More denormals. */ … … 5901 5901 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 5902 5902 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 5903 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,5904 /*128:out */ X86_MXCSR_XCPT_MASK,5903 /*mxcsr:in */ 0, 5904 /*128:out */ 0, 5905 5905 /*256:out */ -1 }, 5906 5906 { { /*src2 */ { FP64_0(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, … … 5940 5940 { /*src1 */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, 5941 5941 { /* => */ { FP64_QNAN(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, 5942 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM,5943 /*128:out */ X86_MXCSR_ DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_IE,5942 /*mxcsr:in */ 0, 5943 /*128:out */ X86_MXCSR_IE, 5944 5944 /*256:out */ -1 }, 5945 5945 { { /*src2 */ { FP64_INF(1), FP64_RAND_V1(0), FP64_RAND_V2(0), FP32_RAND_V3(1) } }, 5946 5946 { /*src1 */ { FP64_INF(1), FP64_RAND_V0(0), FP64_RAND_V1(1), FP32_RAND_V1(1) } }, 5947 5947 { /* => */ { FP64_QNAN(1), FP64_RAND_V0(0), FP64_RAND_V1(1), FP32_RAND_V1(1) } }, 5948 /*mxcsr:in */ X86_MXCSR_ DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,5949 /*128:out */ X86_MXCSR_ DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,5948 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 5949 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 5950 5950 /*256:out */ -1 }, 5951 5951 { { /*src2 */ { FP64_INF(1), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 5952 5952 { /*src1 */ { FP64_INF(1), FP64_RAND_V1(1), FP64_RAND_V1(0), FP64_RAND_V0(1) } }, 5953 5953 { /* => */ { FP64_QNAN(1), FP64_RAND_V1(1), FP64_RAND_V1(0), FP64_RAND_V0(1) } }, 5954 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,5955 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,5954 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 5955 /*128:out */ X86_MXCSR_RC_DOWN | X86_MXCSR_IE, 5956 5956 /*256:out */ -1 }, 5957 5957 { { /*src2 */ { FP64_INF(1), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, 5958 5958 { /*src1 */ { FP64_INF(1), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V1(0) } }, 5959 5959 { /* => */ { FP64_QNAN(1), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V1(0) } }, 5960 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ,5961 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,5960 /*mxcsr:in */ X86_MXCSR_FZ, 5961 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_IE, 5962 5962 /*256:out */ -1 }, 5963 5963 { { /*src2 */ { FP64_INF(1), FP64_RAND_V0(0), FP64_RAND_V0(0), FP64_RAND_V0(1) } }, … … 5976 5976 { /*src1 */ { FP64_INF(1), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V1(0) } }, 5977 5977 { /* => */ { FP64_INF(1), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V1(0) } }, 5978 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,5979 /*128:out */ X86_MXCSR_XCPT_MASK,5978 /*mxcsr:in */ 0, 5979 /*128:out */ 0, 5980 5980 /*256:out */ -1 }, 5981 5981 { { /*src2 */ { FP64_INF(1), FP64_RAND_V1(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } }, 5982 5982 { /*src1 */ { FP64_INF(0), FP64_RAND_V0(1), FP64_RAND_V2(1), FP64_RAND_V1(0) } }, 5983 5983 { /* => */ { FP64_INF(0), FP64_RAND_V0(1), FP64_RAND_V2(1), FP64_RAND_V1(0) } }, 5984 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,5985 /*128:out */ X86_MXCSR_XCPT_MASK,5984 /*mxcsr:in */ 0, 5985 /*128:out */ 0, 5986 5986 /*256:out */ -1 }, 5987 5987 /* … … 6051 6051 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_NORM_MIN(0), FP64_NORM_MAX(1) } }, 6052 6052 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_NORM_MAX(1) } }, 6053 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,6054 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,6053 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 6054 /*128:out */ X86_MXCSR_RC_ZERO, 6055 6055 /*256:out */ -1 }, 6056 6056 { { /*src2 */ { FP64_NORM_MIN(0), FP64_NORM_MIN(0), FP64_NORM_MIN(1), FP64_NORM_MIN(0) } }, … … 6084 6084 { /*src1 */ { FP64_V(0, 0x8000000000000, 0x409)/*1536*/, FP64_RAND_V2(1), FP64_RAND_V3(0), FP64_RAND_V1(0) } }, 6085 6085 { /* => */ { FP64_V(0, 0, 0x408)/* 512*/, FP64_RAND_V2(1), FP64_RAND_V3(0), FP64_RAND_V1(0) } }, 6086 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,6087 /*128:out */ X86_MXCSR_XCPT_MASK,6086 /*mxcsr:in */ 0, 6087 /*128:out */ 0, 6088 6088 /*256:out */ -1 }, 6089 6089 { { /*src2 */ { FP64_V(0, 0xc000000000000, 0x401)/* 7*/, FP64_RAND_V2(0), FP64_RAND_V2(0), FP64_RAND_V0(1) } }, 6090 6090 { /*src1 */ { FP64_V(0, 0xf000000000000, 0x404)/*62*/, FP64_RAND_V0(1), FP64_RAND_V2(1), FP64_RAND_V1(1) } }, 6091 6091 { /* => */ { FP64_V(0, 0xb800000000000, 0x404)/*55*/, FP64_RAND_V0(1), FP64_RAND_V2(1), FP64_RAND_V1(1) } }, 6092 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,6093 /*128:out */ X86_MXCSR_XCPT_MASK,6092 /*mxcsr:in */ 0, 6093 /*128:out */ 0, 6094 6094 /*256:out */ -1 }, 6095 6095 { { /*src2 */ { FP64_V(0, 0x26580b4800000, 0x41d)/*1234567890*/, FP64_RAND_V3(0), FP64_RAND_V0(0), FP64_RAND_V1(1) } }, 6096 6096 { /*src1 */ { FP64_V(0, 0x26580b4800000, 0x41d)/*1234567890*/, FP64_RAND_V3(1), FP64_RAND_V1(0), FP64_RAND_V2(0) } }, 6097 6097 { /* => */ { FP64_0(0), FP64_RAND_V3(1), FP64_RAND_V1(0), FP64_RAND_V2(0) } }, 6098 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,6099 /*128:out */ X86_MXCSR_XCPT_MASK,6098 /*mxcsr:in */ 0, 6099 /*128:out */ 0, 6100 6100 /*256:out */ -1 }, 6101 6101 { { /*src2 */ { FP64_V(0, 0x9000000000000, 0x405)/* 100*/, FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, 6102 6102 { /*src1 */ { FP64_V(1, 0xd6f3426800000, 0x41c)/*-987654221*/, FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(0) } }, 6103 6103 { /* => */ { FP64_V(1, 0xd6f3458800000, 0x41c)/*-987654321*/, FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(0) } }, 6104 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,6105 /*128:out */ X86_MXCSR_XCPT_MASK,6104 /*mxcsr:in */ 0, 6105 /*128:out */ 0, 6106 6106 /*256:out */ -1 }, 6107 6107 { { /*src2 */ { FP64_V(0, 0xd6eca42000000, 0x419)/* 123450000.5*/, FP64_RAND_V0(0), FP64_RAND_V0(1), FP64_RAND_V0(1) } }, 6108 6108 { /*src1 */ { FP64_V(0, 0xcf00348ec5858, 0x432)/*4072598123457580.0*/, FP64_RAND_V1(1), FP64_RAND_V1(0), FP64_RAND_V1(0) } }, 6109 6109 { /* => */ { FP64_V(0, 0xcf0033a34f337, 0x432)/*4072598000007579.5*/, FP64_RAND_V1(1), FP64_RAND_V1(0), FP64_RAND_V1(0) } }, 6110 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,6111 /*128:out */ X86_MXCSR_XCPT_MASK,6110 /*mxcsr:in */ 0, 6111 /*128:out */ 0, 6112 6112 /*256:out */ -1 }, 6113 6113 { { /*src2 */ { FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V1(1) } }, 6114 6114 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_RAND_V0(1), FP64_RAND_V3(1), FP64_RAND_V2(0) } }, 6115 6115 { /* => */ { FP64_1(0), FP64_RAND_V0(1), FP64_RAND_V3(1), FP64_RAND_V2(0) } }, 6116 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,6117 /*128:out */ X86_MXCSR_XCPT_MASK,6116 /*mxcsr:in */ 0, 6117 /*128:out */ 0, 6118 6118 /*256:out */ -1 }, 6119 6119 { { /*src2 */ { FP64_1(0), FP64_RAND_V3(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } }, 6120 6120 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_RAND_V1(0), FP64_RAND_V0(0), FP64_RAND_V1(0) } }, 6121 6121 { /* => */ { FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_RAND_V1(0), FP64_RAND_V0(0), FP64_RAND_V1(0) } }, 6122 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK,6123 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK,6122 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 6123 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 6124 6124 /*256:out */ -1 }, 6125 6125 { { /*src2 */ { FP64_NORM_SAFE_INT_MAX(1), FP64_RAND_V0(0), FP64_RAND_V0(1), FP64_RAND_V0(1) } }, 6126 6126 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(1), FP64_RAND_V1(1), FP64_RAND_V1(0), FP64_RAND_V1(0) } }, 6127 6127 { /* => */ { FP64_0(0), FP64_RAND_V1(1), FP64_RAND_V1(0), FP64_RAND_V1(0) } }, 6128 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,6129 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,6128 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 6129 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 6130 6130 /*256:out */ -1 }, 6131 6131 { { /*src2 */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_RAND_V0(0), FP64_RAND_V0(1), FP64_RAND_V0(1) } }, 6132 6132 { /*src1 */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_RAND_V1(1), FP64_RAND_V1(0), FP64_RAND_V1(0) } }, 6133 6133 { /* => */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_RAND_V1(1), FP64_RAND_V1(0), FP64_RAND_V1(0) } }, 6134 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_XCPT_MASK,6135 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_XCPT_MASK,6134 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 6135 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 6136 6136 /*256:out */ -1 }, 6137 6137 /* … … 6161 6161 { /*src1 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_0(1), FP64_0(0) } }, 6162 6162 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(0) } }, 6163 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,6164 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,6163 /*mxcsr:in */ X86_MXCSR_DAZ, 6164 /*128:out */ X86_MXCSR_DAZ, 6165 6165 /*256:out */ -1 }, 6166 6166 { { /*src2 */ { FP64_DENORM_MIN(0), FP64_RAND_V1(0), FP64_RAND_V0(0), FP64_RAND_V0(1) } }, 6167 6167 { /*src1 */ { FP64_DENORM_MAX(0), FP64_RAND_V2(1), FP64_RAND_V3(0), FP64_RAND_V1(0) } }, 6168 6168 { /* => */ { FP64_0(0), FP64_RAND_V2(1), FP64_RAND_V3(0), FP64_RAND_V1(0) } }, 6169 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,6170 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,6169 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 6170 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 6171 6171 /*256:out */ -1 }, 6172 6172 /** @todo More Denormals. */ … … 6255 6255 { /*src1 */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } }, 6256 6256 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 6257 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,6258 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,6259 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },6257 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 6258 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 6259 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN }, 6260 6260 /* 6261 6261 * Infinity. … … 6264 6264 { /*src1 */ { FP32_INF(0), FP32_INF(1), FP32_0(0), FP32_0(0), FP32_INF(0), FP32_INF(1), FP32_0(0), FP32_0(0) } }, 6265 6265 { /* => */ { FP32_INF(0), FP32_0(0), FP32_INF(1), FP32_INF(0), FP32_INF(0), FP32_0(0), FP32_INF(0), FP32_INF(0) } }, 6266 /*mxcsr:in */ X86_MXCSR_IM,6267 /*128:out */ X86_MXCSR_IM,6268 /*256:out */ X86_MXCSR_IM},6266 /*mxcsr:in */ 0, 6267 /*128:out */ 0, 6268 /*256:out */ 0 }, 6269 6269 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_INF(1), FP32_0(0), FP32_0(0) } }, 6270 6270 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_INF(0), FP32_INF(0), FP32_INF(0) } }, 6271 6271 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_QNAN(1), FP32_QNAN(1), FP32_0(0) } }, 6272 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,6273 /*128:out */ X86_MXCSR_XCPT_MASK,6274 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE },6272 /*mxcsr:in */ 0, 6273 /*128:out */ 0, 6274 /*256:out */ X86_MXCSR_IE }, 6275 6275 { { /*src2 */ { FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_0(0), FP32_0(0) } }, 6276 6276 { /*src1 */ { FP32_INF(1), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_INF(0), FP32_INF(0), FP32_INF(0) } }, … … 6288 6288 { /*src1 */ { FP32_INF(0), FP32_QNAN(0), FP32_INF(1), FP32_QNAN(0), FP32_INF(1), FP32_QNAN(1), FP32_INF(0), FP32_INF(0) } }, 6289 6289 { /* => */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN(1), FP32_QNAN(0), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_0(0) } }, 6290 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,6291 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,6292 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_IE },6290 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 6291 /*128:out */ X86_MXCSR_RC_ZERO, 6292 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE }, 6293 6293 /* 6294 6294 * Overflow, Precision. … … 6303 6303 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MIN(1), FP32_NORM_MAX(1), FP32_NORM_MIN(1) } }, 6304 6304 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0) } }, 6305 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,6306 /*128:out */ X86_MXCSR_XCPT_MASK,6307 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_PE },6305 /*mxcsr:in */ 0, 6306 /*128:out */ 0, 6307 /*256:out */ X86_MXCSR_PE }, 6308 6308 { { /*src2 */ { FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 6309 6309 { /*src1 */ { FP32_NORM_MAX(1), FP32_NORM_MIN(1), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 6310 6310 { /* => */ { FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 6311 /*mxcsr:in */ X86_MXCSR_PM,6312 /*128:out */ X86_MXCSR_P M | X86_MXCSR_PE,6313 /*256:out */ X86_MXCSR_P M | X86_MXCSR_PE },6311 /*mxcsr:in */ 0, 6312 /*128:out */ X86_MXCSR_PE, 6313 /*256:out */ X86_MXCSR_PE }, 6314 6314 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1) } }, 6315 6315 { /*src1 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(1), FP32_0(0), FP32_NORM_MAX(0) } }, … … 6366 6366 { /*src1 */ { FP32_V(0, 0x600000, 0x7f)/*1.75*/, FP32_V(0, 0, 0x7d)/*0.25*/, FP32_NORM_MAX(1), FP32_0(0), FP32_V(1, 0, 0x7e)/*-0.50*/, FP32_V(0, 0, 0x7d)/*-0.25*/, FP32_0(0), FP32_0(0) } }, 6367 6367 { /* => */ { FP32_V(0, 0x400000, 0x7f)/*1.50*/, FP32_NORM_MAX(1), FP32_V(1, 0, 0x7e)/*-0.50*/, FP32_NORM_MAX(0), FP32_V(1, 0x400000, 0x7e)/*-0.75*/, FP32_0(0), FP32_NORM_MAX(1), FP32_V(0, 0x400000, 0x7f)/*1.50*/ } }, 6368 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,6369 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,6370 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },6368 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 6369 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 6370 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO }, 6371 6371 { { /*src2 */ { FP32_V(0, 0, 0x7d)/*0.25*/, FP32_V(0, 0x400000, 0x7e)/*0.75*/, FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_V(0, 0x600000, 0x7f)/*1.75*/, FP32_V(0, 0, 0x7d)/*0.25*/ } }, 6372 6372 { /*src1 */ { FP32_V(0, 0x600000, 0x7f)/*1.75*/, FP32_V(0, 0, 0x7d)/*0.25*/, FP32_NORM_MAX(1), FP32_0(0), FP32_V(1, 0, 0x7e)/*-0.50*/, FP32_V(0, 0, 0x7d)/*-0.25*/, FP32_0(0), FP32_0(0) } }, 6373 6373 { /* => */ { FP32_V(0, 0x400000, 0x7f)/*1.50*/, FP32_NORM_MAX(1), FP32_V(1, 0, 0x7e)/*-0.50*/, FP32_NORM_MAX(0), FP32_V(1, 0x400000, 0x7e)/*-0.75*/, FP32_0(1), FP32_NORM_MAX(1), FP32_V(0, 0x400000, 0x7f)/*1.50*/ } }, 6374 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,6375 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,6376 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN },6374 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 6375 /*128:out */ X86_MXCSR_RC_DOWN, 6376 /*256:out */ X86_MXCSR_RC_DOWN }, 6377 6377 { { /*src2 */ { FP32_NORM_V1(0), FP32_NORM_V1(0), FP32_NORM_V4(0), FP32_NORM_V4(0), FP32_NORM_V1(0), FP32_NORM_V1(0), FP32_NORM_V2(0), FP32_NORM_V2(0) } }, 6378 6378 { /*src1 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MIN(0), FP32_NORM_MIN(0), FP32_NORM_MIN(0), FP32_NORM_MIN(0), FP32_NORM_V3(0), FP32_NORM_V3(0) } }, … … 6390 6390 { /*src1 */ { FP32_V(0, 0x669050, 0x93)/*1888778*/, FP32_V(0, 0x1ea980, 0x8f)/* 81235.00*/, FP32_V(0, 0x253468, 0x93)/*1353357*/, FP32_V(0, 0x7c9000, 0x88)/*1010.25*/, FP32_V(0, 0x780000, 0x84)/* 62*/, FP32_V(0, 0x600000, 0x81)/*7*/, FP32_V(0, 0x534000, 0x86)/* 211.25*/, FP32_1(0) } }, 6391 6391 { /* => */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_V(1, 0x780000, 0x84)/* -62*/, FP32_V(1, 0x5c0000, 0x84)/* -55.00*/, FP32_V(0, 0x5c0000, 0x84)/* 55*/, FP32_V(0, 0x524000, 0x86)/*210.25*/, FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_V(1, 0x534000, 0x86)/*-211.25*/ } }, 6392 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,6393 /*128:out */ X86_MXCSR_XCPT_MASK,6394 /*256:out */ X86_MXCSR_XCPT_MASK},6392 /*mxcsr:in */ 0, 6393 /*128:out */ 0, 6394 /*256:out */ 0 }, 6395 6395 { { /*src2 */ { FP32_V(0, 0x3c614e, 0x97)/*24691356*/, FP32_V(0, 0x3c614e, 0x96)/*12345678*/, FP32_0(0), FP32_NORM_V1(0), FP32_V(0, 0x3c614e, 0x97)/*24691356*/, FP32_V(0, 0x3c614e, 0x96)/*12345678*/, FP32_2(0), FP32_1(0) } }, 6396 6396 { /*src1 */ { FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_V(0, 0x712060, 0x92)/* 987654*/, FP32_NORM_V5(0), FP32_0(0), FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_V(0, 0x712060, 0x92)/* 987654*/, FP32_0(0), FP32_1(0) } }, 6397 6397 { /* => */ { FP32_V(0, 0x6cb99c, 0x97)/*31028024*/, FP32_NORM_V5(0), FP32_V(0, 0x3c614e, 0x96)/*12345678*/, FP32_NORM_V1(1), FP32_V(0, 0x6cb99c, 0x97)/*31028024*/, FP32_1(1), FP32_V(0, 0x3c614e, 0x96)/*12345678*/, FP32_1(0) } }, 6398 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,6399 /*128:out */ X86_MXCSR_XCPT_MASK,6400 /*256:out */ X86_MXCSR_XCPT_MASK},6398 /*mxcsr:in */ 0, 6399 /*128:out */ 0, 6400 /*256:out */ 0 }, 6401 6401 { { /*src2 */ { FP32_V(0, 0x6423f2, 0x92)/* 934463.125*/, FP32_V(0, 0x0a19f0, 0x8f)/* 70707.875*/, FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1), FP32_1(1), FP32_1(0), FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/, FP32_V(0, 0x600000, 0x7e)/* 0.875*/ } }, 6402 6402 { /*src1 */ { FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/, FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_V(0, 0x10c030, 0x92)/*592899.000*/, FP32_V(0, 0x3ce348, 0x90)/*193421.125*/, FP32_V(1, 0x16b43a, 0x93)/*-1234567.25*/, FP32_V(0, 0x00c6d3, 0x94)/*2109876.75*/, FP32_V(0, 0x792318, 0x91)/*510232.750*/, FP32_V(0, 0x316740, 0x8e)/* 45415.250*/ } }, 6403 6403 { /* => */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_V(0, 0x430ebc, 0x91)/*399477.875*/, FP32_V(0, 0x52e0b4, 0x92)/*863755.250*/, FP32_0(0), FP32_V(1, 0x4c20f0, 0x94)/*-3344444.00*/, FP32_V(0, 0x62f630, 0x91)/* 464817.50*/, FP32_2(1), FP32_V(0, 0x769b50, 0x92)/*1010101.000*/ } }, 6404 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,6405 /*128:out */ X86_MXCSR_XCPT_MASK,6406 /*256:out */ X86_MXCSR_XCPT_MASK},6404 /*mxcsr:in */ 0, 6405 /*128:out */ 0, 6406 /*256:out */ 0 }, 6407 6407 { { /*src2 */ { FP32_2(0), FP32_1(0), FP32_1(1), FP32_1(0), FP32_2(0), FP32_1(0), FP32_1(0), FP32_1(0) } }, 6408 6408 { /*src1 */ { FP32_V(1, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_1(0), FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_V(1, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_1(0), FP32_NORM_SAFE_INT_MAX(0), FP32_1(0) } }, 6409 6409 { /* => */ { FP32_NORM_SAFE_INT_MAX(1), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_1(0), FP32_2(1), FP32_NORM_SAFE_INT_MAX(1), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_1(0), FP32_0(0) } }, 6410 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,6411 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,6412 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO },6410 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 6411 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 6412 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO }, 6413 6413 { { /*src2 */ { FP32_2(0), FP32_1(0), FP32_1(1), FP32_1(0), FP32_2(0), FP32_1(0), FP32_1(0), FP32_1(0) } }, 6414 6414 { /*src1 */ { FP32_V(1, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_1(0), FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_V(1, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_1(0), FP32_NORM_SAFE_INT_MAX(0), FP32_1(0) } }, … … 6450 6450 { /*src1 */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0) } }, 6451 6451 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 6452 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,6453 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,6454 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK},6452 /*mxcsr:in */ X86_MXCSR_DAZ, 6453 /*128:out */ X86_MXCSR_DAZ, 6454 /*256:out */ X86_MXCSR_DAZ }, 6455 6455 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } }, 6456 6456 { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0) } }, … … 6483 6483 { /*src1 */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 6484 6484 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 6485 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,6486 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,6487 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK},6485 /*mxcsr:in */ X86_MXCSR_DAZ, 6486 /*128:out */ X86_MXCSR_DAZ, 6487 /*256:out */ X86_MXCSR_DAZ }, 6488 6488 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } }, 6489 6489 { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0) } }, 6490 6490 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 6491 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,6492 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,6493 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP },6491 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 6492 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 6493 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP }, 6494 6494 /** @todo More Denormals. */ 6495 6495 /* … … 6588 6588 { /*src1 */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } }, 6589 6589 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 6590 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,6591 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,6592 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },6590 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 6591 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 6592 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN }, 6593 6593 { { /*src2 */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(1) } }, 6594 6594 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(0) } }, 6595 6595 { /* => */ { FP64_0(1), FP64_0(0), FP64_0(1), FP64_0(1) } }, 6596 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,6597 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,6598 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN },6596 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 6597 /*128:out */ X86_MXCSR_RC_DOWN, 6598 /*256:out */ X86_MXCSR_RC_DOWN }, 6599 6599 /* 6600 6600 * Infinity. … … 6603 6603 { /*src1 */ { FP64_INF(1), FP64_INF(0), FP64_0(0), FP64_0(0) } }, 6604 6604 { /* => */ { FP64_INF(1), FP64_INF(0), FP64_0(0), FP64_INF(0) } }, 6605 /*mxcsr:in */ X86_MXCSR_IM,6606 /*128:out */ X86_MXCSR_IM,6607 /*256:out */ X86_MXCSR_IM},6605 /*mxcsr:in */ 0, 6606 /*128:out */ 0, 6607 /*256:out */ 0 }, 6608 6608 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_INF(1), FP64_INF(1) } }, 6609 6609 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_INF(1), FP64_INF(0) } }, 6610 6610 { /* => */ { FP64_0(0), FP64_0(0), FP64_INF(1), FP64_QNAN(1) } }, 6611 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,6612 /*128:out */ X86_MXCSR_XCPT_MASK,6613 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE },6611 /*mxcsr:in */ 0, 6612 /*128:out */ 0, 6613 /*256:out */ X86_MXCSR_IE }, 6614 6614 { { /*src2 */ { FP64_INF(0), FP64_INF(1), FP64_INF(0), FP64_INF(1) } }, 6615 6615 { /*src1 */ { FP64_INF(1), FP64_INF(0), FP64_0(0), FP64_0(0) } }, 6616 6616 { /* => */ { FP64_INF(1), FP64_INF(0), FP64_0(0), FP64_INF(0) } }, 6617 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ,6618 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ,6619 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ },6617 /*mxcsr:in */ X86_MXCSR_FZ, 6618 /*128:out */ X86_MXCSR_FZ, 6619 /*256:out */ X86_MXCSR_FZ }, 6620 6620 { { /*src2 */ { FP64_INF(1), FP64_INF(1), FP64_INF(0), FP64_0(0) } }, 6621 6621 { /*src1 */ { FP64_INF(0), FP64_INF(0), FP64_INF(1), FP64_0(0) } }, … … 6627 6627 { /*src1 */ { FP64_INF(0), FP64_QNAN(0), FP64_INF(1), FP64_QNAN(0) } }, 6628 6628 { /* => */ { FP64_QNAN(0), FP64_QNAN(1), FP64_QNAN(0), FP64_QNAN(0) } }, 6629 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,6630 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,6631 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP },6629 /*mxcsr:in */ X86_MXCSR_RC_UP, 6630 /*128:out */ X86_MXCSR_RC_UP, 6631 /*256:out */ X86_MXCSR_RC_UP }, 6632 6632 /* 6633 6633 * Overflow, Precision. … … 6642 6642 { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MIN(0), FP64_NORM_MAX(0) } }, 6643 6643 { /* => */ { FP64_INF(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_0(0) } }, 6644 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM,6645 /*128:out */ X86_MXCSR_O M | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,6646 /*256:out */ X86_MXCSR_O M | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE },6644 /*mxcsr:in */ 0, 6645 /*128:out */ X86_MXCSR_OE | X86_MXCSR_PE, 6646 /*256:out */ X86_MXCSR_OE | X86_MXCSR_PE }, 6647 6647 { { /*src2 */ { FP64_NORM_MAX(1), FP64_NORM_MAX(0), FP64_2(0), FP64_1(0) } }, 6648 6648 { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } }, … … 6672 6672 { /*src1 */ { FP64_NORM_MIN(1), FP64_NORM_MAX(0), FP64_NORM_MIN(0), FP64_NORM_MAX(1) } }, 6673 6673 { /* => */ { FP64_NORM_MAX(1), FP64_0(0), FP64_INF(0), FP64_NORM_MAX(1) } }, 6674 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_RC_UP,6675 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_PE,6676 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE },6674 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 6675 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_PE, 6676 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE }, 6677 6677 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MAX(0) } }, 6678 6678 { /*src1 */ { FP64_NORM_MIN(1), FP64_NORM_MIN(1), FP64_NORM_MIN(0), FP64_NORM_MAX(0) } }, … … 6690 6690 { /*src1 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MIN(0) } }, 6691 6691 { /* => */ { FP64_V(1, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_NORM_SAFE_INT_MAX(1), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_0(0) } }, 6692 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,6693 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_PE,6694 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_PE },6692 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 6693 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, 6694 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE }, 6695 6695 { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0) } }, 6696 6696 { /*src1 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MIN(0) } }, 6697 6697 { /* => */ { FP64_V(1, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MAX(0), FP64_0(0) } }, 6698 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,6699 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_PE,6700 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_PE },6698 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 6699 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_PE, 6700 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_PE }, 6701 6701 /* 6702 6702 * Denormals. … … 6726 6726 { /*src1 */ { FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(1), FP64_DENORM_MAX(1) } }, 6727 6727 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 6728 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,6729 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,6730 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK},6728 /*mxcsr:in */ X86_MXCSR_DAZ, 6729 /*128:out */ X86_MXCSR_DAZ, 6730 /*256:out */ X86_MXCSR_DAZ }, 6731 6731 /*26|27*/{ { /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 6732 6732 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0) } }, … … 6753 6753 { /*src1 */ { FP64_0(1), FP64_DENORM_MAX(0), FP64_DENORM_MAX(1), FP64_0(0) } }, 6754 6754 { /* => */ { FP64_0(1), FP64_0(0), FP64_0(1), FP64_0(0) } }, 6755 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK,6756 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK,6757 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK},6755 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 6756 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 6757 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO }, 6758 6758 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } }, 6759 6759 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_DENORM_MIN(1), FP64_DENORM_MIN(1) } }, … … 6863 6863 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1) } }, 6864 6864 { /* => */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0) } }, 6865 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,6866 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,6867 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO },6865 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 6866 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 6867 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO }, 6868 6868 { { /*src2 */ { FP32_NORM_V0(0), FP32_NORM_V1(1), FP32_0(0), FP32_NORM_V3(1), FP32_0(0), FP32_NORM_V1(1), FP32_NORM_V4(0), FP32_NORM_V3(0) } }, 6869 6869 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_NORM_V2(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } }, 6870 6870 { /* => */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } }, 6871 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,6872 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,6873 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },6871 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 6872 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 6873 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN }, 6874 6874 /* 6875 6875 * Infinity. … … 6878 6878 { /*src1 */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 6879 6879 { /* => */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 6880 /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,6881 /*128:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,6882 /*256:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM},6880 /*mxcsr:in */ 0, 6881 /*128:out */ 0, 6882 /*256:out */ 0 }, 6883 6883 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 6884 6884 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 6885 6885 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 6886 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,6887 /*128:out */ X86_MXCSR_XCPT_MASK,6888 /*256:out */ X86_MXCSR_XCPT_MASK},6886 /*mxcsr:in */ 0, 6887 /*128:out */ 0, 6888 /*256:out */ 0 }, 6889 6889 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0), FP32_0(1), FP32_0(1), FP32_0(0) } }, 6890 6890 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(1), FP32_0(1), FP32_0(0) } }, 6891 6891 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0) } }, 6892 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK,6893 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK,6894 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK},6892 /*mxcsr:in */ X86_MXCSR_FZ, 6893 /*128:out */ X86_MXCSR_FZ, 6894 /*256:out */ X86_MXCSR_FZ }, 6895 6895 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0) } }, 6896 6896 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1) } }, … … 6908 6908 { /*src1 */ { FP32_0(0), FP32_INF(1), FP32_0(1), FP32_INF(1), FP32_0(0), FP32_INF(0), FP32_0(0), FP32_INF(1) } }, 6909 6909 { /* => */ { FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1) } }, 6910 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,6911 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,6912 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE },6910 /*mxcsr:in */ 0, 6911 /*128:out */ X86_MXCSR_IE, 6912 /*256:out */ X86_MXCSR_IE }, 6913 6913 { { /*src2 */ { FP32_INF(0), FP32_0(0), FP32_INF(0), FP32_0(1), FP32_INF(0), FP32_0(1), FP32_INF(1), FP32_0(1) } }, 6914 6914 { /*src1 */ { FP32_0(0), FP32_INF(1), FP32_0(1), FP32_INF(1), FP32_0(0), FP32_INF(0), FP32_0(0), FP32_INF(1) } }, … … 7043 7043 { /*src1 */ { FP32_V(0, 0, 0x7d)/*0.2500*/, FP32_1(0), FP32_1(1), FP32_0(0), FP32_NORM_V0(1), FP32_NORM_V3(0), FP32_NORM_V4(0), FP32_1(0) } }, 7044 7044 { /* => */ { FP32_V(0, 0x600000, 0x7d)/*0.4375*/, FP32_NORM_V0(0), FP32_NORM_V1(1), FP32_0(1), FP32_NORM_V0(0), FP32_NORM_V3(0), FP32_NORM_V4(1), FP32_NORM_V6(1) } }, 7045 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,7046 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,7047 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },7045 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 7046 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 7047 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN }, 7048 7048 { { /*src2 */ { FP32_V(0, 0x61e000, 0x89)/* 1807*/, FP32_V(0, 0x61e000, 0x89)/* 1807*/, FP32_V(0, 0x4a30b8, 0x8f)/* 103521.4375*/, FP32_V(0, 0x1a5200, 0x8c)/* 9876.5*/, FP32_V(0, 0x23b6a0, 0x8e)/*41910.625000*/, FP32_V(0, 0x23b6a0, 0x8e)/*41910.625000*/, FP32_V(0, 0, 0x7d)/*0.2500*/, FP32_V(0, 0x504000, 0x8a)/* 3332*/ } }, 7049 7049 { /*src1 */ { FP32_V(0, 0x504000, 0x8a)/* 3332*/, FP32_V(0, 0x504000, 0x8a)/* 3332*/, FP32_V(0, 0x600000, 0x82)/* 14.0000*/, FP32_V(1, 0x1a4000, 0x89)/* -1234.0*/, FP32_V(0, 0, 0x7c)/* 0.125000*/, FP32_V(0, 0, 0x7c)/* 0.125000*/, FP32_V(0, 0x600000, 0x7f)/*1.7500*/, FP32_V(1, 0x61e000, 0x89)/* -1807*/ } }, 7050 7050 { /* => */ { FP32_V(0, 0x37be78, 0x95)/*6020924*/, FP32_V(0, 0x37be78, 0x95)/*6020924*/, FP32_V(0, 0x30eaa1, 0x93)/*1449300.1250*/, FP32_V(1, 0x39f7d1, 0x96)/*-12187601.0*/, FP32_V(0, 0x23b6a0, 0x8b)/* 5238.828125*/, FP32_V(0, 0x23b6a0, 0x8b)/* 5238.828125*/, FP32_V(0, 0x600000, 0x7d)/*0.4375*/, FP32_V(1, 0x37be78, 0x95)/*-6020924*/ } }, 7051 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,7052 /*128:out */ X86_MXCSR_XCPT_MASK,7053 /*256:out */ X86_MXCSR_XCPT_MASK},7051 /*mxcsr:in */ 0, 7052 /*128:out */ 0, 7053 /*256:out */ 0 }, 7054 7054 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_NORM_SAFE_INT_MAX(1), FP32_1(1), FP32_NORM_SAFE_INT_MIN(1), FP32_1(1), FP32_NORM_SAFE_INT_MIN(0), FP32_0(1) } }, 7055 7055 { /*src1 */ { FP32_1(0), FP32_NORM_SAFE_INT_MIN(0), FP32_1(0), FP32_NORM_SAFE_INT_MAX(1), FP32_1(0), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0), FP32_NORM_SAFE_INT_MAX(0) } }, 7056 7056 { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_0(0), FP32_0(1) } }, 7057 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,7058 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,7059 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },7057 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 7058 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 7059 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO }, 7060 7060 { { /*src2 */ { FP32_NORM_MAX(0), FP32_1(0), FP32_NORM_MAX(1), FP32_1(1), FP32_NORM_MIN(0), FP32_NORM_MIN(0), FP32_1(0), FP32_1(1) } }, 7061 7061 { /*src1 */ { FP32_1(0), FP32_NORM_MAX(1), FP32_1(0), FP32_NORM_MAX(1), FP32_1(0), FP32_1(1), FP32_NORM_MIN(1), FP32_NORM_MIN(1) } }, … … 7097 7097 { /*src1 */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_DENORM_MAX(0), FP32_DENORM_MAX(1), FP32_DENORM_MAX(0), FP32_DENORM_MAX(1) } }, 7098 7098 { /* => */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0) } }, 7099 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,7100 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,7101 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ },7099 /*mxcsr:in */ X86_MXCSR_DAZ, 7100 /*128:out */ X86_MXCSR_DAZ, 7101 /*256:out */ X86_MXCSR_DAZ }, 7102 7102 { { /*src2 */ { FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(1), FP32_DENORM_MAX(1), FP32_1(0), FP32_1(0), FP32_1(1), FP32_1(1) } }, 7103 7103 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_1(0), FP32_1(1), FP32_DENORM_MAX(0), FP32_DENORM_MAX(1), FP32_DENORM_MAX(0), FP32_DENORM_MAX(1) } }, 7104 7104 { /* => */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0) } }, 7105 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,7106 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,7107 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ },7105 /*mxcsr:in */ X86_MXCSR_DAZ, 7106 /*128:out */ X86_MXCSR_DAZ, 7107 /*256:out */ X86_MXCSR_DAZ }, 7108 7108 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(1), FP32_DENORM_MIN(1), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1) } }, 7109 7109 { /*src1 */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_DENORM_MIN(0), FP32_DENORM_MIN(1), FP32_DENORM_MIN(0), FP32_DENORM_MIN(1) } }, … … 7135 7135 { /*src1 */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_DENORM_MIN(0), FP32_DENORM_MIN(1), FP32_DENORM_MIN(0), FP32_DENORM_MIN(1) } }, 7136 7136 { /* => */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0) } }, 7137 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,7138 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,7139 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ },7137 /*mxcsr:in */ X86_MXCSR_DAZ, 7138 /*128:out */ X86_MXCSR_DAZ, 7139 /*256:out */ X86_MXCSR_DAZ }, 7140 7140 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(1), FP32_DENORM_MIN(1), FP32_1(0), FP32_1(0), FP32_1(1), FP32_1(1) } }, 7141 7141 { /*src1 */ { FP32_1(0), FP32_1(1), FP32_1(0), FP32_1(1), FP32_DENORM_MIN(0), FP32_DENORM_MIN(1), FP32_DENORM_MIN(0), FP32_DENORM_MIN(1) } }, 7142 7142 { /* => */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0) } }, 7143 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,7144 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,7145 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ },7143 /*mxcsr:in */ X86_MXCSR_DAZ, 7144 /*128:out */ X86_MXCSR_DAZ, 7145 /*256:out */ X86_MXCSR_DAZ }, 7146 7146 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(1), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(1) } }, 7147 7147 { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(1), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1) } }, 7148 7148 { /* => */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0) } }, 7149 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,7150 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,7151 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP },7149 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 7150 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 7151 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP }, 7152 7152 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(1), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(1) } }, 7153 7153 { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(1), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1) } }, 7154 7154 { /* => */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0) } }, 7155 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN,7156 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN,7157 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN },7155 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN, 7156 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN, 7157 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN }, 7158 7158 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(1), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(1) } }, 7159 7159 { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(1), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1) } }, 7160 7160 { /* => */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0) } }, 7161 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,7162 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,7163 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO },7161 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 7162 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 7163 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO }, 7164 7164 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(1), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(1) } }, 7165 7165 { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(1), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1) } }, 7166 7166 { /* => */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0) } }, 7167 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ,7168 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ,7169 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ },7167 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 7168 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 7169 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ }, 7170 7170 /** @todo More Denormals. */ 7171 7171 /* … … 7240 7240 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 7241 7241 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 7242 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,7243 /*128:out */ X86_MXCSR_XCPT_MASK,7244 /*256:out */ X86_MXCSR_XCPT_MASK},7242 /*mxcsr:in */ 0, 7243 /*128:out */ 0, 7244 /*256:out */ 0 }, 7245 7245 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 7246 7246 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, … … 7270 7270 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(1) } }, 7271 7271 { /* => */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(0) } }, 7272 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,7273 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,7274 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },7272 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 7273 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 7274 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN }, 7275 7275 { { /*src2 */ { FP64_NORM_V0(0), FP64_NORM_V1(1), FP64_0(0), FP64_NORM_V3(1) } }, 7276 7276 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_NORM_V2(1), FP64_0(1) } }, 7277 7277 { /* => */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(0) } }, 7278 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,7279 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,7280 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },7278 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 7279 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 7280 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN }, 7281 7281 /* 7282 7282 * Infinity. … … 7285 7285 { /*src1 */ { FP64_INF(1), FP64_0(0), FP64_INF(0), FP64_0(0) } }, 7286 7286 { /* => */ { FP64_INF(1), FP64_0(0), FP64_INF(1), FP64_0(0) } }, 7287 /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,7288 /*128:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,7289 /*256:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM},7287 /*mxcsr:in */ 0, 7288 /*128:out */ 0, 7289 /*256:out */ 0 }, 7290 7290 { { /*src2 */ { FP64_INF(0), FP64_INF(0), FP64_INF(1), FP64_INF(1) } }, 7291 7291 { /*src1 */ { FP64_INF(1), FP64_INF(0), FP64_INF(1), FP64_INF(0) } }, 7292 7292 { /* => */ { FP64_INF(1), FP64_INF(0), FP64_INF(0), FP64_INF(1) } }, 7293 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,7294 /*128:out */ X86_MXCSR_XCPT_MASK,7295 /*256:out */ X86_MXCSR_XCPT_MASK},7293 /*mxcsr:in */ 0, 7294 /*128:out */ 0, 7295 /*256:out */ 0 }, 7296 7296 { { /*src2 */ { FP64_INF(0), FP64_INF(1), FP64_0(1), FP64_INF(0) } }, 7297 7297 { /*src1 */ { FP64_INF(1), FP64_INF(0), FP64_0(1), FP64_INF(0) } }, … … 7303 7303 { /*src1 */ { FP64_INF(1), FP64_INF(0), FP64_0(1), FP64_INF(0) } }, 7304 7304 { /* => */ { FP64_INF(1), FP64_INF(1), FP64_0(0), FP64_INF(0) } }, 7305 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,7306 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,7307 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },7305 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 7306 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 7307 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO }, 7308 7308 { { /*src2 */ { FP64_INF(0), FP64_INF(0), FP64_1(0), FP64_INF(0) } }, 7309 7309 { /*src1 */ { FP64_1(0), FP64_NORM_V0(0), FP64_INF(0), FP64_NORM_V1(0) } }, 7310 7310 { /* => */ { FP64_INF(0), FP64_INF(0), FP64_INF(0), FP64_INF(0) } }, 7311 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,7312 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,7313 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN },7311 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 7312 /*128:out */ X86_MXCSR_RC_DOWN, 7313 /*256:out */ X86_MXCSR_RC_DOWN }, 7314 7314 { { /*src2 */ { FP64_INF(1), FP64_INF(0), FP64_NORM_V3(0), FP64_INF(1) } }, 7315 7315 { /*src1 */ { FP64_1(1), FP64_NORM_V3(1), FP64_INF(1), FP64_NORM_V1(1) } }, 7316 7316 { /* => */ { FP64_INF(0), FP64_INF(1), FP64_INF(1), FP64_INF(0) } }, 7317 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,7318 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,7319 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP },7317 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 7318 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 7319 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP }, 7320 7320 /* 7321 7321 * Normals. … … 7324 7324 { /*src1 */ { FP64_1(0), FP64_V(0, 0x2d69a80000000, 0x413)/* 1234586.50*/, FP64_V(1, 0x4000000000000, 0x400)/* -2.50*/, FP64_V(0, 0xb800000000000, 0x402)/* 13.75000*/ } }, 7325 7325 { /* => */ { FP64_V(0, 0xe66f500000000, 0x40d)/*31131.828125*/, FP64_V(0, 0xfb74e1d800000, 0x41a)/*266053390.75*/, FP64_V(0, 0x549270a11c760, 0x42c)/* 46807863534478.75*/, FP64_V(0, 0x3c30944926c00, 0x424)/*169753086244.84375*/ } }, 7326 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,7327 /*128:out */ X86_MXCSR_XCPT_MASK,7328 /*256:out */ X86_MXCSR_XCPT_MASK},7326 /*mxcsr:in */ 0, 7327 /*128:out */ 0, 7328 /*256:out */ 0 }, 7329 7329 { { /*src2 */ { FP64_NORM_MAX(1), FP64_NORM_V3(1), FP64_1(0), FP64_1(1) } }, 7330 7330 { /*src1 */ { FP64_1(1), FP64_1(0), FP64_NORM_V1(0), FP64_NORM_MIN(1) } }, 7331 7331 { /* => */ { FP64_NORM_MAX(0), FP64_NORM_V3(1), FP64_NORM_V1(0), FP64_NORM_MIN(0) } }, 7332 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,7333 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,7334 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN },7332 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 7333 /*128:out */ X86_MXCSR_RC_DOWN, 7334 /*256:out */ X86_MXCSR_RC_DOWN }, 7335 7335 { { /*src2 */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_V(1, 0x68b83b1ed4000, 0x41e)/*-3025935759.4140625*/, FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646*/, FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/ } }, 7336 7336 { /*src1 */ { FP64_V(0, 0x8000000000000, 0x3fe)/* 0.75*/, FP64_V(1, 0, 0x400)/* -2.0000000*/, FP64_1(0), FP64_V(0, 0x8000000000000, 0x400)/* 3.00*/ } }, 7337 7337 { /* => */ { FP64_V(0, 0x4da20a80c6990, 0x42e)/*183416666481484.50*/, FP64_V(0, 0x68b83b1ed4000, 0x41f)/* 6051871518.8281250*/, FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646*/, FP64_V(0, 0x4a6a82b05f744, 0x42f)/*363296296296308.25*/ } }, 7338 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,7339 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,7340 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN },7338 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 7339 /*128:out */ X86_MXCSR_RC_DOWN, 7340 /*256:out */ X86_MXCSR_RC_DOWN }, 7341 7341 { { /*src2 */ { FP64_1(0), FP64_1(0), FP64_NORM_SAFE_INT_MIN(0), FP64_1(0) } }, 7342 7342 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_1(0), FP64_NORM_SAFE_INT_MIN(1) } }, 7343 7343 { /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(1) } }, 7344 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,7345 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,7346 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },7344 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 7345 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 7346 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO }, 7347 7347 { { /*src2 */ { FP64_NORM_V0(0), FP64_NORM_V1(1), FP64_NORM_V2(0), FP64_NORM_V3(1) } }, 7348 7348 { /*src1 */ { FP64_1(0), FP64_1(1), FP64_1(1), FP64_1(1) } }, 7349 7349 { /* => */ { FP64_NORM_V0(0), FP64_NORM_V1(0), FP64_NORM_V2(1), FP64_NORM_V3(0) } }, 7350 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,7351 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,7352 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN },7350 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 7351 /*128:out */ X86_MXCSR_RC_DOWN, 7352 /*256:out */ X86_MXCSR_RC_DOWN }, 7353 7353 /** @todo More Normals. */ 7354 7354 /* … … 7376 7376 { /*src1 */ { FP64_1(0), FP64_DENORM_MAX(0), FP64_1(0), FP64_DENORM_MIN(0) } }, 7377 7377 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 7378 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ,7379 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ,7380 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ },7378 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 7379 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 7380 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ }, 7381 7381 { { /*src2 */ { FP64_DENORM_MIN(1), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(1) } }, 7382 7382 { /*src1 */ { FP64_DENORM_MAX(1), FP64_DENORM_MIN(1), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } }, 7383 7383 { /* => */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } }, 7384 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,7385 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,7386 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP },7384 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 7385 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 7386 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP }, 7387 7387 { { /*src2 */ { FP64_1(0), FP64_NORM_V1(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } }, 7388 7388 { /*src1 */ { FP64_NORM_V0(0), FP64_1(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } }, 7389 7389 { /* => */ { FP64_NORM_V0(0), FP64_NORM_V1(0), FP64_0(0), FP64_0(0) } }, 7390 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,7391 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,7392 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_DE | X86_MXCSR_UE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */ },7390 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 7391 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 7392 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_DE | X86_MXCSR_UE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */ }, 7393 7393 { { /*src2 */ { FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(1) } }, 7394 7394 { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(1), FP64_DENORM_MIN(1) } }, … … 7409 7409 { /*src1 */ { FP64_1(0), FP64_1(0), FP64_1(0), FP64_NORM_MAX(0) } }, 7410 7410 { /* => */ { FP64_NORM_V3(1), FP64_1(0), FP64_NORM_MAX(0), FP64_INF(0) } }, 7411 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,7412 /*128:out */ X86_MXCSR_XCPT_MASK,7413 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */ },7411 /*mxcsr:in */ 0, 7412 /*128:out */ 0, 7413 /*256:out */ X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */ }, 7414 7414 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_V3(1), FP64_1(0) } }, 7415 7415 { /*src1 */ { FP64_1(0), FP64_NORM_MAX(0), FP64_1(0), FP64_1(0) } }, 7416 7416 { /* => */ { FP64_NORM_MAX(0), FP64_INF(0), FP64_NORM_V3(1), FP64_1(0) } }, 7417 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,7418 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */,7419 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */ },7417 /*mxcsr:in */ 0, 7418 /*128:out */ X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */, 7419 /*256:out */ X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */ }, 7420 7420 { { /*src2 */ { FP64_NORM_V3(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_1(0) } }, 7421 7421 { /*src1 */ { FP64_1(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_V1(0) } }, 7422 7422 { /* => */ { FP64_NORM_V3(0), FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_V1(0) } }, 7423 /*mxcsr:in */ (X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM)) |X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,7424 /*128:out */ (X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM)) |X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */,7425 /*256:out */ (X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM)) |X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */ },7423 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 7424 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */, 7425 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */ }, 7426 7426 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MIN(1), FP64_NORM_MAX(0) } }, 7427 7427 { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } }, 7428 7428 { /* => */ { FP64_INF(0), FP64_0(0), FP64_V(0, FP64_FRAC_NORM_MAX, RTFLOAT64U_EXP_BIAS + 1), FP64_INF(0) } }, 7429 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM,7430 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_O M | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_UE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */,7431 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_O M | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_UE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */ },7429 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 7430 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_UE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */, 7431 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_UE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */ }, 7432 7432 { { /*src2 */ { FP64_NORM_V3(0), FP64_1(1), FP64_NORM_MAX(1), FP64_NORM_MIN(0) } }, 7433 7433 { /*src1 */ { FP64_1(0), FP64_NORM_V2(1), FP64_NORM_MAX(1), FP64_NORM_MAX(1) } }, 7434 7434 { /* => */ { FP64_NORM_V3(0), FP64_NORM_V2(0), FP64_NORM_MAX(0), FP64_V(1, FP64_FRAC_NORM_MAX, RTFLOAT64U_EXP_BIAS + 1) } }, 7435 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM) | X86_MXCSR_RC_ZERO,7436 /*128:out */ X86_MXCSR_ XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM) | X86_MXCSR_RC_ZERO,7437 /*256:out */ X86_MXCSR_ XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM) | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */ },7435 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 7436 /*128:out */ X86_MXCSR_RC_ZERO, 7437 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */ }, 7438 7438 { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_MAX(0), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MIN(0) } }, 7439 7439 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_MAX(1), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MAX(0) } }, 7440 7440 { /* => */ { FP64_V(0, FP64_FRAC_NORM_MAX, FP64_FRAC_BITS + 1), FP64_NORM_MAX(1), FP64_V(0, FP64_FRAC_NORM_MAX - 1, 0x468), FP64_V(0, FP64_FRAC_NORM_MAX, 0x035) } }, 7441 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,7442 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */,7443 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */ },7441 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 7442 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */, 7443 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */ }, 7444 7444 { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_MAX(0), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MIN(0) } }, 7445 7445 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_MAX(1), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MAX(0) } }, 7446 7446 { /* => */ { FP64_V(0, FP64_FRAC_NORM_MAX, FP64_FRAC_BITS + 1), FP64_INF(1), FP64_V(0, FP64_FRAC_NORM_MAX - 1, 0x468), FP64_V(0, FP64_FRAC_NORM_MAX, 0x035) } }, 7447 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,7448 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */,7449 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_OE | X86_MXCSR_PE },7447 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 7448 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */, 7449 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_OE | X86_MXCSR_PE }, 7450 7450 /* 7451 7451 * Invalids. … … 7525 7525 { /*src1 */ { FP32_0(0), FP32_0_x7(0) } }, 7526 7526 { /* => */ { FP32_0(0), FP32_0_x7(0) } }, 7527 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,7528 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,7527 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 7528 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 7529 7529 /*256:out */ -1 }, 7530 7530 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V1 } }, 7531 7531 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V2 } }, 7532 7532 { /* => */ { FP32_0(0), FP32_RAND_x7_V2 } }, 7533 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,7534 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,7533 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 7534 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 7535 7535 /*256:out */ -1 }, 7536 7536 { { /*src2 */ { FP32_0(1), FP32_RAND_x7_V4 } }, … … 7549 7549 { /*src1 */ { FP32_0(1), FP32_RAND_x7_V1 } }, 7550 7550 { /* => */ { FP32_0(1), FP32_RAND_x7_V1 } }, 7551 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,7552 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,7551 /*mxcsr:in */ X86_MXCSR_DAZ, 7552 /*128:out */ X86_MXCSR_DAZ, 7553 7553 /*256:out */ -1 }, 7554 7554 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V5 } }, 7555 7555 { /*src1 */ { FP32_1(0), FP32_RAND_x7_V2 } }, 7556 7556 { /* => */ { FP32_0(0), FP32_RAND_x7_V2 } }, 7557 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,7558 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,7557 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 7558 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 7559 7559 /*256:out */ -1 }, 7560 7560 /* … … 7564 7564 { /*src1 */ { FP32_1(1), FP32_0_x7(0) } }, 7565 7565 { /* => */ { FP32_INF(1), FP32_0_x7(0) } }, 7566 /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,7567 /*128:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,7566 /*mxcsr:in */ 0, 7567 /*128:out */ 0, 7568 7568 /*256:out */ -1 }, 7569 7569 { { /*src2 */ { FP32_INF(1), FP32_0_x7(0) } }, 7570 7570 { /*src1 */ { FP32_1(1), FP32_0_x7(0) } }, 7571 7571 { /* => */ { FP32_INF(0), FP32_0_x7(0) } }, 7572 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,7573 /*128:out */ X86_MXCSR_XCPT_MASK,7572 /*mxcsr:in */ 0, 7573 /*128:out */ 0, 7574 7574 /*256:out */ -1 }, 7575 7575 { { /*src2 */ { FP32_INF(0), FP32_RAND_x7_V7 } }, 7576 7576 { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V0 } }, 7577 7577 { /* => */ { FP32_INF(0), FP32_RAND_x7_V0 } }, 7578 /*mxcsr:in */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) |X86_MXCSR_DAZ | X86_MXCSR_FZ,7579 /*128:out */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) |X86_MXCSR_DAZ | X86_MXCSR_FZ,7578 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 7579 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 7580 7580 /*256:out */ -1 }, 7581 7581 { { /*src2 */ { FP32_INF(1), FP32_RAND_x7_V7 } }, 7582 7582 { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V1 } }, 7583 7583 { /* => */ { FP32_INF(1), FP32_RAND_x7_V1 } }, 7584 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,7585 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,7584 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 7585 /*128:out */ X86_MXCSR_RC_ZERO, 7586 7586 /*256:out */ -1 }, 7587 7587 { { /*src2 */ { FP32_1(0), FP32_RAND_x7_V3 } }, 7588 7588 { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V2 } }, 7589 7589 { /* => */ { FP32_INF(0), FP32_RAND_x7_V2 } }, 7590 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ,7591 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ,7590 /*mxcsr:in */ X86_MXCSR_FZ, 7591 /*128:out */ X86_MXCSR_FZ, 7592 7592 /*256:out */ -1 }, 7593 7593 { { /*src2 */ { FP32_INF(0), FP32_RAND_x7_V0 } }, … … 7609 7609 { /*src1 */ { FP32_V(0, 0, 0x7d)/*0.2500*/, FP32_RAND_x7_V4 } }, 7610 7610 { /* => */ { FP32_V(0, 0x600000, 0x7d)/*0.4375*/, FP32_RAND_x7_V4 } }, 7611 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,7612 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,7611 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 7612 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 7613 7613 /*256:out */ -1 }, 7614 7614 { { /*src2 */ { FP32_V(0, 0x61e000, 0x89)/* 1807*/, FP32_RAND_x7_V4 } }, 7615 7615 { /*src1 */ { FP32_V(0, 0x504000, 0x8a)/* 3332*/, FP32_RAND_x7_V5 } }, 7616 7616 { /* => */ { FP32_V(0, 0x37be78, 0x95)/*6020924*/, FP32_RAND_x7_V5 } }, 7617 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,7618 /*128:out */ X86_MXCSR_XCPT_MASK,7617 /*mxcsr:in */ 0, 7618 /*128:out */ 0, 7619 7619 /*256:out */ -1 }, 7620 7620 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V6 } }, 7621 7621 { /*src1 */ { FP32_1(0), FP32_RAND_x7_V6 } }, 7622 7622 { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V6 } }, 7623 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,7624 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,7623 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 7624 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 7625 7625 /*256:out */ -1 }, 7626 7626 { { /*src2 */ { FP32_V(0, 0x61e000, 0x89)/* 1807*/, FP32_RAND_x7_V6 } }, 7627 7627 { /*src1 */ { FP32_V(0, 0x504000, 0x8a)/* 3332*/, FP32_RAND_x7_V2 } }, 7628 7628 { /* => */ { FP32_V(0, 0x37be78, 0x95)/*6020924*/, FP32_RAND_x7_V2 } }, 7629 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,7630 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,7629 /*mxcsr:in */ X86_MXCSR_RC_UP, 7630 /*128:out */ X86_MXCSR_RC_UP, 7631 7631 /*256:out */ -1 }, 7632 7632 { { /*src2 */ { FP32_V(0, 0x4a30b8, 0x8f)/* 103521.4375*/, FP32_RAND_x7_V7 } }, 7633 7633 { /*src1 */ { FP32_V(0, 0x600000, 0x82)/* 14.0000*/, FP32_RAND_x7_V2 } }, 7634 7634 { /* => */ { FP32_V(0, 0x30eaa1, 0x93)/*1449300.1250*/, FP32_RAND_x7_V2 } }, 7635 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,7636 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,7635 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 7636 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 7637 7637 /*256:out */ -1 }, 7638 7638 { { /*src2 */ { FP32_V(0, 0x1a5200, 0x8c)/* 9876.5*/, FP32_RAND_x7_V3 } }, … … 7679 7679 { /*src1 */ { FP32_DENORM_MIN(1), FP32_RAND_x7_V2 } }, 7680 7680 { /* => */ { FP32_0(1), FP32_RAND_x7_V2 } }, 7681 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,7682 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE,7681 /*mxcsr:in */ 0, 7682 /*128:out */ X86_MXCSR_DE, 7683 7683 /*256:out */ -1 }, 7684 7684 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_RAND_x7_V3 } }, 7685 7685 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V3 } }, 7686 7686 { /* => */ { FP32_0(0), FP32_RAND_x7_V3 } }, 7687 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,7688 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,7687 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 7688 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 7689 7689 /*256:out */ -1 }, 7690 7690 /** @todo More Denormals. */ … … 7755 7755 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 7756 7756 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 7757 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,7758 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,7757 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 7758 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 7759 7759 /*256:out */ -1 }, 7760 7760 { { /*src2 */ { FP64_0(0), FP64_NORM_V3(0), FP64_NORM_V2(0), FP64_0(0) } }, 7761 7761 { /*src1 */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_NORM_V1(0) } }, 7762 7762 { /* => */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_NORM_V1(0) } }, 7763 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,7764 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,7763 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 7764 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 7765 7765 /*256:out */ -1 }, 7766 7766 { { /*src2 */ { FP64_0(1), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V1(1) } }, … … 7779 7779 { /*src1 */ { FP64_0(1), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V0(0) } }, 7780 7780 { /* => */ { FP64_0(1), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V0(0) } }, 7781 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,7782 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,7781 /*mxcsr:in */ X86_MXCSR_DAZ, 7782 /*128:out */ X86_MXCSR_DAZ, 7783 7783 /*256:out */ -1 }, 7784 7784 { { /*src2 */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, 7785 7785 { /*src1 */ { FP64_1(0), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V0(0) } }, 7786 7786 { /* => */ { FP64_0(0), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V0(0) } }, 7787 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,7788 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,7787 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 7788 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 7789 7789 /*256:out */ -1 }, 7790 7790 /* … … 7794 7794 { /*src1 */ { FP64_1(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, 7795 7795 { /* => */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, 7796 /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,7797 /*128:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,7796 /*mxcsr:in */ 0, 7797 /*128:out */ 0, 7798 7798 /*256:out */ -1 }, 7799 7799 { { /*src2 */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, 7800 7800 { /*src1 */ { FP64_1(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, 7801 7801 { /* => */ { FP64_INF(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 7802 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,7803 /*128:out */ X86_MXCSR_XCPT_MASK,7802 /*mxcsr:in */ 0, 7803 /*128:out */ 0, 7804 7804 /*256:out */ -1 }, 7805 7805 { { /*src2 */ { FP64_INF(0), FP64_RAND_V1(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, 7806 7806 { /*src1 */ { FP64_INF(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } }, 7807 7807 { /* => */ { FP64_INF(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } }, 7808 /*mxcsr:in */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) |X86_MXCSR_DAZ | X86_MXCSR_FZ,7809 /*128:out */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) |X86_MXCSR_DAZ | X86_MXCSR_FZ,7808 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 7809 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 7810 7810 /*256:out */ -1 }, 7811 7811 { { /*src2 */ { FP64_INF(1), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V1(1) } }, 7812 7812 { /*src1 */ { FP64_INF(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V0(0) } }, 7813 7813 { /* => */ { FP64_INF(1), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V0(0) } }, 7814 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,7815 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,7814 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 7815 /*128:out */ X86_MXCSR_RC_ZERO, 7816 7816 /*256:out */ -1 }, 7817 7817 { { /*src2 */ { FP64_1(0), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } }, 7818 7818 { /*src1 */ { FP64_INF(0), FP64_RAND_V1(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, 7819 7819 { /* => */ { FP64_INF(0), FP64_RAND_V1(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, 7820 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ,7821 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ,7820 /*mxcsr:in */ X86_MXCSR_FZ, 7821 /*128:out */ X86_MXCSR_FZ, 7822 7822 /*256:out */ -1 }, 7823 7823 { { /*src2 */ { FP64_INF(0), FP64_INF(0), FP64_INF(1), FP64_INF(1) } }, … … 7839 7839 { /*src1 */ { FP64_1(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } }, 7840 7840 { /* => */ { FP64_V(0, 0xe66f500000000, 0x40d)/*31131.828125*/, FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } }, 7841 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,7842 /*128:out */ X86_MXCSR_XCPT_MASK,7841 /*mxcsr:in */ 0, 7842 /*128:out */ 0, 7843 7843 /*256:out */ -1 }, 7844 7844 { { /*src2 */ { FP64_V(0, 0xaf00000000000, 0x406)/* 215.50*/, FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } }, 7845 7845 { /*src1 */ { FP64_V(0, 0x2d69a80000000, 0x413)/* 1234586.50*/, FP64_RAND_V1(0), FP64_RAND_V1(1), FP64_RAND_V0(1) } }, 7846 7846 { /* => */ { FP64_V(0, 0xfb74e1d800000, 0x41a)/*266053390.75*/, FP64_RAND_V1(0), FP64_RAND_V1(1), FP64_RAND_V0(1) } }, 7847 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,7848 /*128:out */ X86_MXCSR_XCPT_MASK,7847 /*mxcsr:in */ 0, 7848 /*128:out */ 0, 7849 7849 /*256:out */ -1 }, 7850 7850 { { /*src2 */ { FP64_V(1, 0x107526e749f80, 0x42b)/*-18723145413791.50*/, FP64_RAND_V3(0), FP64_RAND_V1(0), FP64_RAND_V1(1) } }, 7851 7851 { /*src1 */ { FP64_V(1, 0x4000000000000, 0x400)/* -2.50*/, FP64_RAND_V0(0), FP64_RAND_V2(1), FP64_RAND_V2(1) } }, 7852 7852 { /* => */ { FP64_V(0, 0x549270a11c760, 0x42c)/* 46807863534478.75*/, FP64_RAND_V0(0), FP64_RAND_V2(1), FP64_RAND_V2(1) } }, 7853 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,7854 /*128:out */ X86_MXCSR_XCPT_MASK,7853 /*mxcsr:in */ 0, 7854 /*128:out */ 0, 7855 7855 /*256:out */ -1 }, 7856 7856 { { /*src2 */ { FP64_V(0, 0x6fee0e4bd0000, 0x420)/* 12345678999.62500*/, FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 7857 7857 { /*src1 */ { FP64_V(0, 0xb800000000000, 0x402)/* 13.75000*/, FP64_RAND_V2(0), FP64_RAND_V1(1), FP64_RAND_V3(1) } }, 7858 7858 { /* => */ { FP64_V(0, 0x3c30944926c00, 0x424)/*169753086244.84375*/, FP64_RAND_V2(0), FP64_RAND_V1(1), FP64_RAND_V3(1) } }, 7859 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,7860 /*128:out */ X86_MXCSR_XCPT_MASK,7859 /*mxcsr:in */ 0, 7860 /*128:out */ 0, 7861 7861 /*256:out */ -1 }, 7862 7862 { { /*src2 */ { FP64_NORM_MAX(1), FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } }, 7863 7863 { /*src1 */ { FP64_1(1), FP64_RAND_V1(1), FP64_RAND_V0(0), FP64_RAND_V2(0) } }, 7864 7864 { /* => */ { FP64_NORM_MAX(0), FP64_RAND_V1(1), FP64_RAND_V0(0), FP64_RAND_V2(0) } }, 7865 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,7866 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,7865 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 7866 /*128:out */ X86_MXCSR_RC_DOWN, 7867 7867 /*256:out */ -1 }, 7868 7868 { { /*src2 */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_RAND_V2(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 7869 7869 { /*src1 */ { FP64_V(0, 0x8000000000000, 0x3fe)/* 0.75*/, FP64_RAND_V1(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } }, 7870 7870 { /* => */ { FP64_V(0, 0x4da20a80c6990, 0x42e)/*183416666481484.50*/, FP64_RAND_V1(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } }, 7871 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,7872 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,7871 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 7872 /*128:out */ X86_MXCSR_RC_DOWN, 7873 7873 /*256:out */ -1 }, 7874 7874 { { /*src2 */ { FP64_V(1, 0x68b83b1ed4000, 0x41e)/*-3025935759.4140625*/, FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, 7875 7875 { /*src1 */ { FP64_V(1, 0, 0x400)/* -2.0000000*/, FP64_RAND_V2(0), FP64_RAND_V1(1), FP64_RAND_V3(1) } }, 7876 7876 { /* => */ { FP64_V(0, 0x68b83b1ed4000, 0x41f)/* 6051871518.8281250*/, FP64_RAND_V2(0), FP64_RAND_V1(1), FP64_RAND_V3(1) } }, 7877 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,7878 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,7877 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 7878 /*128:out */ X86_MXCSR_RC_DOWN, 7879 7879 /*256:out */ -1 }, 7880 7880 { { /*src2 */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 7881 7881 { /*src1 */ { FP64_V(0, 0x8000000000000, 0x400)/* 3.00*/, FP64_RAND_V1(1), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 7882 7882 { /* => */ { FP64_V(0, 0x4a6a82b05f744, 0x42f)/*363296296296308.25*/, FP64_RAND_V1(1), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 7883 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,7884 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,7883 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 7884 /*128:out */ X86_MXCSR_RC_DOWN, 7885 7885 /*256:out */ -1 }, 7886 7886 { { /*src2 */ { FP64_1(0), FP64_0(0), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_MAX(1) } }, 7887 7887 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_INF(1), FP64_NORM_SAFE_INT_MIN(1) } }, 7888 7888 { /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_INF(1), FP64_NORM_SAFE_INT_MIN(1) } }, 7889 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,7890 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,7889 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 7890 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 7891 7891 /*256:out */ -1 }, 7892 7892 { { /*src2 */ { FP64_NORM_V0(0), FP64_NORM_V1(1), FP64_NORM_V2(0), FP64_NORM_V3(1) } }, 7893 7893 { /*src1 */ { FP64_1(0), FP64_SNAN(0), FP64_SNAN(1), FP64_QNAN(0) } }, 7894 7894 { /* => */ { FP64_NORM_V0(0), FP64_SNAN(0), FP64_SNAN(1), FP64_QNAN(0) } }, 7895 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,7896 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,7895 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 7896 /*128:out */ X86_MXCSR_RC_DOWN, 7897 7897 /*256:out */ -1 }, 7898 7898 /* … … 7920 7920 { /*src1 */ { FP64_1(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V3(1) } }, 7921 7921 { /* => */ { FP64_0(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V3(1) } }, 7922 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ,7923 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ,7922 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 7923 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 7924 7924 /*256:out */ -1 }, 7925 7925 { { /*src2 */ { FP64_DENORM_MIN(1), FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, 7926 7926 { /*src1 */ { FP64_DENORM_MAX(1), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V2(1) } }, 7927 7927 { /* => */ { FP64_0(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V2(1) } }, 7928 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,7929 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,7928 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 7929 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 7930 7930 /*256:out */ -1 }, 7931 7931 { { /*src2 */ { FP64_1(1), FP64_RAND_V3(0), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, … … 8070 8070 { /*src1 */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0) } }, 8071 8071 { /* => */ { FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1) } }, 8072 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,8073 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,8074 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE },8072 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 8073 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 8074 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE }, 8075 8075 { { /*src2 */ { FP32_NORM_V0(0), FP32_NORM_V1(1), FP32_0(0), FP32_NORM_V3(1), FP32_0(0), FP32_NORM_V1(1), FP32_NORM_V4(0), FP32_NORM_V3(0) } }, 8076 8076 { /*src1 */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } }, 8077 8077 { /* => */ { FP32_0(0), FP32_0(0), FP32_QNAN(1), FP32_0(1), FP32_QNAN(1), FP32_0(1), FP32_0(0), FP32_0(1) } }, 8078 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,8079 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,8080 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE },8078 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 8079 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, 8080 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE }, 8081 8081 /* 8082 8082 * Infinity. … … 8085 8085 { /*src1 */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 8086 8086 { /* => */ { FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1) } }, 8087 /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,8088 /*128:out */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) |X86_MXCSR_IE,8089 /*256:out */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) |X86_MXCSR_IE },8087 /*mxcsr:in */ 0, 8088 /*128:out */ X86_MXCSR_IE, 8089 /*256:out */ X86_MXCSR_IE }, 8090 8090 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 8091 8091 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 8092 8092 { /* => */ { FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1) } }, 8093 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,8094 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,8095 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE },8093 /*mxcsr:in */ 0, 8094 /*128:out */ X86_MXCSR_IE, 8095 /*256:out */ X86_MXCSR_IE }, 8096 8096 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0), FP32_0(1), FP32_0(1), FP32_0(0) } }, 8097 8097 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0) } }, 8098 8098 { /* => */ { FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1) } }, 8099 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK,8100 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,8101 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE },8099 /*mxcsr:in */ X86_MXCSR_FZ, 8100 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_IE, 8101 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_IE }, 8102 8102 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0) } }, 8103 8103 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1) } }, … … 8115 8115 { /*src1 */ { FP32_QNAN(0), FP32_QNAN(0), FP32_INF(1), FP32_INF(1), FP32_QNAN(1), FP32_INF(0), FP32_INF(0), FP32_QNAN(1) } }, 8116 8116 { /* => */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(0), FP32_QNAN(1) } }, 8117 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,8118 /*128:out */ X86_MXCSR_XCPT_MASK,8119 /*256:out */ X86_MXCSR_XCPT_MASK},8117 /*mxcsr:in */ 0, 8118 /*128:out */ 0, 8119 /*256:out */ 0 }, 8120 8120 { { /*src2 */ { FP32_INF(0), FP32_INF(1), FP32_QNAN(0), FP32_QNAN(1), FP32_INF(0), FP32_QNAN(1), FP32_QNAN(0), FP32_INF(1) } }, 8121 8121 { /*src1 */ { FP32_QNAN(0), FP32_QNAN(0), FP32_INF(1), FP32_INF(1), FP32_QNAN(1), FP32_INF(0), FP32_INF(0), FP32_QNAN(1) } }, … … 8184 8184 { /*src1 */ { FP32_INF(0), FP32_0(0), FP32_NORM_V1(0), FP32_INF(0), FP32_INF(0), FP32_0(1), FP32_0(1), FP32_INF(1) } }, 8185 8185 { /* => */ { FP32_INF(0), FP32_0(1), FP32_1(0), FP32_INF(0), FP32_INF(1), FP32_0(1), FP32_0(0), FP32_INF(1) } }, 8186 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM,8187 /*128:out */ X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM,8188 /*256:out */ X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM},8186 /*mxcsr:in */ 0, 8187 /*128:out */ 0, 8188 /*256:out */ 0 }, 8189 8189 { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_MIN(0), FP32_NORM_V3(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MIN(0), FP32_NORM_MIN(1), FP32_NORM_MAX(0) } }, 8190 8190 { /*src1 */ { FP32_NORM_MAX(0), FP32_0(1), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(1), FP32_0(1), FP32_INF(1) } }, 8191 8191 { /* => */ { FP32_1(0), FP32_0(1), FP32_0(0), FP32_1(0), FP32_1(1), FP32_0(1), FP32_0(0), FP32_INF(1) } }, 8192 /*mxcsr:in */ X86_MXCSR_ OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,8193 /*128:out */ X86_MXCSR_ OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,8194 /*256:out */ X86_MXCSR_ OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },8192 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 8193 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 8194 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN }, 8195 8195 { { /*src2 */ { FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_2(0), FP32_1(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MIN(1) } }, 8196 8196 { /*src1 */ { FP32_0(0), FP32_NORM_MAX(0), FP32_INF(1), FP32_2(1), FP32_2(0), FP32_INF(1), FP32_NORM_MAX(0), FP32_0(0) } }, 8197 8197 { /* => */ { FP32_0(1), FP32_1(0), FP32_INF(1), FP32_1(1), FP32_2(1), FP32_INF(1), FP32_1(0), FP32_0(1) } }, 8198 /*mxcsr:in */ X86_MXCSR_ OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,8199 /*128:out */ X86_MXCSR_ OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,8200 /*256:out */ X86_MXCSR_ OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },8198 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 8199 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 8200 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN }, 8201 8201 { { /*src2 */ { FP32_1(0), FP32_NORM_V2(1), FP32_1(1), FP32_NORM_V6(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } }, 8202 8202 { /*src1 */ { FP32_NORM_V7(0), FP32_NORM_V2(0), FP32_NORM_V4(1), FP32_NORM_V6(1), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0) } }, … … 8212 8212 { /*src1 */ { FP32_V(0, 0x600000, 0x7d)/*0.4375*/, FP32_NORM_V0(0), FP32_NORM_V1(1), FP32_0(1), FP32_NORM_V0(0), FP32_NORM_V3(0), FP32_NORM_V4(1), FP32_NORM_V6(1) } }, 8213 8213 { /* => */ { FP32_V(0, 0, 0x7d)/*0.2500*/, FP32_1(0), FP32_1(1), FP32_0(0), FP32_NORM_V0(1), FP32_NORM_V3(0), FP32_NORM_V4(0), FP32_1(0) } }, 8214 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,8215 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,8216 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },8214 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 8215 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 8216 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN }, 8217 8217 { { /*src2 */ { FP32_V(0, 0x61e000, 0x89)/* 1807*/, FP32_V(0, 0x61e000, 0x89)/* 1807*/, FP32_V(0, 0x4a30b8, 0x8f)/* 103521.4375*/, FP32_V(0, 0x1a5200, 0x8c)/* 9876.5*/, FP32_V(0, 0x23b6a0, 0x8e)/*41910.625000*/, FP32_V(0, 0x23b6a0, 0x8e)/*41910.625000*/, FP32_V(0, 0, 0x7d)/*0.2500*/, FP32_V(0, 0x504000, 0x8a)/* 3332*/ } }, 8218 8218 { /*src1 */ { FP32_V(0, 0x37be78, 0x95)/*6020924*/, FP32_V(0, 0x37be78, 0x95)/*6020924*/, FP32_V(0, 0x30eaa1, 0x93)/*1449300.1250*/, FP32_V(1, 0x39f7d1, 0x96)/*-12187601.0*/, FP32_V(0, 0x23b6a0, 0x8b)/* 5238.828125*/, FP32_V(0, 0x23b6a0, 0x8b)/* 5238.828125*/, FP32_V(0, 0x600000, 0x7d)/*0.4375*/, FP32_V(1, 0x37be78, 0x95)/*-6020924*/ } }, 8219 8219 { /* => */ { FP32_V(0, 0x504000, 0x8a)/* 3332*/, FP32_V(0, 0x504000, 0x8a)/* 3332*/, FP32_V(0, 0x600000, 0x82)/* 14.0000*/, FP32_V(1, 0x1a4000, 0x89)/* -1234.0*/, FP32_V(0, 0, 0x7c)/* 0.125000*/, FP32_V(0, 0, 0x7c)/* 0.125000*/, FP32_V(0, 0x600000, 0x7f)/*1.7500*/, FP32_V(1, 0x61e000, 0x89)/* -1807*/ } }, 8220 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,8221 /*128:out */ X86_MXCSR_XCPT_MASK,8222 /*256:out */ X86_MXCSR_XCPT_MASK},8220 /*mxcsr:in */ 0, 8221 /*128:out */ 0, 8222 /*256:out */ 0 }, 8223 8223 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_NORM_SAFE_INT_MAX(1), FP32_1(1), FP32_NORM_SAFE_INT_MIN(1), FP32_1(1), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MAX(0) } }, 8224 8224 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_0(0), FP32_0(1) } }, 8225 8225 { /* => */ { FP32_1(0), FP32_NORM_SAFE_INT_MIN(0), FP32_1(0), FP32_NORM_SAFE_INT_MAX(1), FP32_1(0), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0), FP32_0(1) } }, 8226 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,8227 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,8228 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },8226 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 8227 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 8228 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO }, 8229 8229 { { /*src2 */ { FP32_NORM_MAX(0), FP32_1(0), FP32_NORM_MAX(1), FP32_1(1), FP32_NORM_MIN(0), FP32_NORM_MIN(0), FP32_1(0), FP32_1(1) } }, 8230 8230 { /*src1 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_MIN(0), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MIN(0) } }, … … 8260 8260 { /*src1 */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(1), FP32_DENORM_MAX(0), FP32_DENORM_MAX(1) } }, 8261 8261 { /* => */ { FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1) } }, 8262 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,8263 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_IE,8264 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_IE },8262 /*mxcsr:in */ X86_MXCSR_DAZ, 8263 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_IE, 8264 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_IE }, 8265 8265 { { /*src2 */ { FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(1), FP32_DENORM_MAX(1), FP32_1(0), FP32_1(0), FP32_1(1), FP32_1(1) } }, 8266 8266 { /*src1 */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(1), FP32_DENORM_MAX(0), FP32_DENORM_MAX(1) } }, 8267 8267 { /* => */ { FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0) } }, 8268 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,8269 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_IE,8270 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_IE },8268 /*mxcsr:in */ X86_MXCSR_DAZ, 8269 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_IE, 8270 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_IE }, 8271 8271 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(1), FP32_DENORM_MIN(1), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1) } }, 8272 8272 { /*src1 */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(1), FP32_DENORM_MIN(0), FP32_DENORM_MIN(1) } }, … … 8298 8298 { /*src1 */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(1), FP32_DENORM_MIN(0), FP32_DENORM_MIN(1) } }, 8299 8299 { /* => */ { FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1) } }, 8300 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,8301 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_IE,8302 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_IE },8300 /*mxcsr:in */ X86_MXCSR_DAZ, 8301 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_IE, 8302 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_IE }, 8303 8303 { { /*src2 */ { FP32_1(0), FP32_1(0), FP32_1(1), FP32_1(1), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(1), FP32_DENORM_MIN(1) } }, 8304 8304 { /*src1 */ { FP32_DENORM_MIN(0), FP32_DENORM_MIN(1), FP32_DENORM_MIN(0), FP32_DENORM_MIN(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0) } }, 8305 8305 { /* => */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1) } }, 8306 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,8307 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,8308 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_IE },8306 /*mxcsr:in */ X86_MXCSR_DAZ, 8307 /*128:out */ X86_MXCSR_DAZ, 8308 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_IE }, 8309 8309 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(1), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(1) } }, 8310 8310 { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(1), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1) } }, 8311 8311 { /* => */ { FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1) } }, 8312 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,8313 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,8314 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_IE },8312 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 8313 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, 8314 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_IE }, 8315 8315 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(1), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(1) } }, 8316 8316 { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(1), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1) } }, 8317 8317 { /* => */ { FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1) } }, 8318 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN,8319 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,8320 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE },8318 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN, 8319 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, 8320 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE }, 8321 8321 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(1), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(1) } }, 8322 8322 { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(1), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1) } }, 8323 8323 { /* => */ { FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1) } }, 8324 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,8325 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,8326 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE },8324 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 8325 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 8326 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE }, 8327 8327 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(1), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(1) } }, 8328 8328 { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(1), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1) } }, 8329 8329 { /* => */ { FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1) } }, 8330 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ,8331 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE,8332 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE },8330 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 8331 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE, 8332 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE }, 8333 8333 /** @todo More Denormals. */ 8334 8334 /* … … 8403 8403 { /*src1 */ { FP64_0(1), FP64_0(0), FP64_0(1), FP64_0(0) } }, 8404 8404 { /* => */ { FP64_QNAN(1), FP64_QNAN(1), FP64_QNAN(1), FP64_QNAN(1) } }, 8405 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,8406 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE,8407 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_IE },8405 /*mxcsr:in */ 0, 8406 /*128:out */ X86_MXCSR_IE, 8407 /*256:out */ X86_MXCSR_IE }, 8408 8408 { { /*src2 */ { FP64_0(1), FP64_0(1), FP64_0(0), FP64_0(0) } }, 8409 8409 { /*src1 */ { FP64_0(1), FP64_0(0), FP64_0(1), FP64_0(0) } }, … … 8433 8433 { /*src1 */ { FP64_0(1), FP64_0(0), FP64_0(1), FP64_0(0) } }, 8434 8434 { /* => */ { FP64_QNAN(1), FP64_QNAN(1), FP64_QNAN(1), FP64_QNAN(1) } }, 8435 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,8436 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,8437 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE },8435 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 8436 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, 8437 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE }, 8438 8438 { { /*src2 */ { FP64_NORM_V0(0), FP64_NORM_V1(1), FP64_0(0), FP64_0(1) } }, 8439 8439 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_NORM_V2(1), FP64_NORM_V3(1) } }, 8440 8440 { /* => */ { FP64_0(0), FP64_0(1), FP64_INF(1), FP64_INF(0) } }, 8441 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,8442 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,8443 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_ZE },8441 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 8442 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 8443 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_ZE }, 8444 8444 /* 8445 8445 * Infinity. … … 8454 8454 { /*src1 */ { FP64_INF(0), FP64_INF(1), FP64_INF(0), FP64_INF(1) } }, 8455 8455 { /* => */ { FP64_INF(0), FP64_INF(1), FP64_INF(1), FP64_INF(0) } }, 8456 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,8457 /*128:out */ X86_MXCSR_XCPT_MASK,8458 /*256:out */ X86_MXCSR_XCPT_MASK},8456 /*mxcsr:in */ 0, 8457 /*128:out */ 0, 8458 /*256:out */ 0 }, 8459 8459 { { /*src2 */ { FP64_INF(0), FP64_INF(0), FP64_INF(1), FP64_INF(1) } }, 8460 8460 { /*src1 */ { FP64_INF(0), FP64_INF(1), FP64_INF(0), FP64_INF(1) } }, … … 8466 8466 { /*src1 */ { FP64_INF(0), FP64_INF(1), FP64_INF(0), FP64_INF(1) } }, 8467 8467 { /* => */ { FP64_QNAN(1), FP64_QNAN(1), FP64_QNAN(1), FP64_QNAN(1) } }, 8468 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,8469 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,8470 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE },8468 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 8469 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 8470 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE }, 8471 8471 { { /*src2 */ { FP64_INF(0), FP64_INF(0), FP64_1(1), FP64_NORM_V1(1) } }, 8472 8472 { /*src1 */ { FP64_1(0), FP64_NORM_V0(1), FP64_INF(0), FP64_INF(1) } }, 8473 8473 { /* => */ { FP64_0(0), FP64_0(1), FP64_INF(1), FP64_INF(0) } }, 8474 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,8475 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,8476 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN },8474 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 8475 /*128:out */ X86_MXCSR_RC_DOWN, 8476 /*256:out */ X86_MXCSR_RC_DOWN }, 8477 8477 { { /*src2 */ { FP64_INF(0), FP64_INF(0), FP64_1(1), FP64_NORM_V2(1) } }, 8478 8478 { /*src1 */ { FP64_1(0), FP64_NORM_V3(1), FP64_INF(0), FP64_INF(1) } }, 8479 8479 { /* => */ { FP64_0(0), FP64_0(1), FP64_INF(1), FP64_INF(0) } }, 8480 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,8481 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,8482 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP },8480 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 8481 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 8482 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP }, 8483 8483 /* 8484 8484 * Normals. … … 8487 8487 { /*src1 */ { FP64_V(0, 0xe66f500000000, 0x40d)/*31131.828125*/, FP64_V(0, 0xfb74e1d800000, 0x41a)/*266053390.75*/, FP64_V(0, 0x549270a11c760, 0x42c)/* 46807863534478.75*/, FP64_V(0, 0x3c30944926c00, 0x424)/*169753086244.84375*/ } }, 8488 8488 { /* => */ { FP64_1(0), FP64_V(0, 0x2d69a80000000, 0x413)/* 1234586.50*/, FP64_V(1, 0x4000000000000, 0x400)/* -2.50*/, FP64_V(0, 0xb800000000000, 0x402)/* 13.75000*/ } }, 8489 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,8490 /*128:out */ X86_MXCSR_XCPT_MASK,8491 /*256:out */ X86_MXCSR_XCPT_MASK},8489 /*mxcsr:in */ 0, 8490 /*128:out */ 0, 8491 /*256:out */ 0 }, 8492 8492 { { /*src2 */ { FP64_NORM_MAX(1), FP64_NORM_V3(1), FP64_1(0), FP64_1(1) } }, 8493 8493 { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_V3(1), FP64_NORM_V1(0), FP64_NORM_MIN(0) } }, 8494 8494 { /* => */ { FP64_1(1), FP64_1(0), FP64_NORM_V1(0), FP64_NORM_MIN(1) } }, 8495 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,8496 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,8497 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN },8495 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 8496 /*128:out */ X86_MXCSR_RC_DOWN, 8497 /*256:out */ X86_MXCSR_RC_DOWN }, 8498 8498 { { /*src2 */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_V(1, 0x68b83b1ed4000, 0x41e)/*-3025935759.4140625*/, FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646*/, FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/ } }, 8499 8499 { /*src1 */ { FP64_V(0, 0x4da20a80c6990, 0x42e)/*183416666481484.50*/, FP64_V(0, 0x68b83b1ed4000, 0x41f)/* 6051871518.8281250*/, FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646*/, FP64_V(0, 0x4a6a82b05f744, 0x42f)/*363296296296308.25*/ } }, 8500 8500 { /* => */ { FP64_V(0, 0x8000000000000, 0x3fe)/* 0.75*/, FP64_V(1, 0, 0x400)/* -2.0000000*/, FP64_1(0), FP64_V(0, 0x8000000000000, 0x400)/* 3.00*/ } }, 8501 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,8502 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,8503 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN },8501 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 8502 /*128:out */ X86_MXCSR_RC_DOWN, 8503 /*256:out */ X86_MXCSR_RC_DOWN }, 8504 8504 { { /*src2 */ { FP64_1(0), FP64_1(0), FP64_NORM_SAFE_INT_MIN(0), FP64_1(0) } }, 8505 8505 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(1) } }, 8506 8506 { /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_1(0), FP64_NORM_SAFE_INT_MIN(1) } }, 8507 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,8508 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,8509 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },8507 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 8508 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 8509 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO }, 8510 8510 { { /*src2 */ { FP64_NORM_V0(0), FP64_NORM_V1(1), FP64_NORM_V2(0), FP64_NORM_V3(1) } }, 8511 8511 { /*src1 */ { FP64_NORM_V0(0), FP64_NORM_V1(0), FP64_NORM_V2(1), FP64_NORM_V3(0) } }, 8512 8512 { /* => */ { FP64_1(0), FP64_1(1), FP64_1(1), FP64_1(1) } }, 8513 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,8514 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,8515 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN },8513 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 8514 /*128:out */ X86_MXCSR_RC_DOWN, 8515 /*256:out */ X86_MXCSR_RC_DOWN }, 8516 8516 /** @todo More Normals. */ 8517 8517 /* … … 8573 8573 { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_1(0), FP64_1(0) } }, 8574 8574 { /* => */ { FP64_0(0), FP64_0(0), FP64_INF(0), FP64_INF(0) } }, 8575 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ,8576 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ,8577 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_ZE },8575 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 8576 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 8577 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_ZE }, 8578 8578 { { /*src2 */ { FP64_DENORM_MIN(1), FP64_DENORM_MIN(1), FP64_DENORM_MIN(0), FP64_DENORM_MAX(1) } }, 8579 8579 { /*src1 */ { FP64_1(0), FP64_1(1), FP64_DENORM_MIN(0), FP64_DENORM_MAX(1) } }, 8580 8580 { /* => */ { FP64_INF(1), FP64_INF(0), FP64_QNAN(1), FP64_QNAN(1) } }, 8581 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,8582 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_ZE,8583 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_ZE | X86_MXCSR_IE },8581 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 8582 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_ZE, 8583 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_ZE | X86_MXCSR_IE }, 8584 8584 { { /*src2 */ { FP64_1(0), FP64_NORM_V1(0), FP64_DENORM_MAX(0), FP64_1(0) } }, 8585 8585 { /*src1 */ { FP64_NORM_V0(0), FP64_NORM_V1(0), FP64_0(0), FP64_DENORM_MAX(0) } }, 8586 8586 { /* => */ { FP64_NORM_V0(0), FP64_1(0), FP64_0(0), FP64_0(0) } }, 8587 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,8588 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,8589 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_DE | X86_MXCSR_UE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY },8587 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 8588 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 8589 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_DE | X86_MXCSR_UE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY }, 8590 8590 { { /*src2 */ { FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(1) } }, 8591 8591 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_INF(1), FP64_INF(0) } }, … … 8606 8606 { /*src1 */ { FP64_NORM_V3(1), FP64_1(0), FP64_NORM_MAX(0), FP64_INF(0) } }, 8607 8607 { /* => */ { FP64_1(0), FP64_1(0), FP64_1(0), FP64_INF(0) } }, 8608 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,8609 /*128:out */ X86_MXCSR_XCPT_MASK,8610 /*256:out */ X86_MXCSR_XCPT_MASK},8608 /*mxcsr:in */ 0, 8609 /*128:out */ 0, 8610 /*256:out */ 0 }, 8611 8611 { { /*src2 */ { FP64_NORM_V3(1), FP64_1(1), FP64_NORM_MIN(0), FP64_NORM_MIN(0) } }, 8612 8612 { /*src1 */ { FP64_NORM_V3(0), FP64_1(1), FP64_NORM_MIN(1), FP64_NORM_MAX(0) } }, 8613 8613 { /* => */ { FP64_1(1), FP64_1(0), FP64_1(1), FP64_INF(0) } }, 8614 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,8615 /*128:out */ X86_MXCSR_XCPT_MASK,8616 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* i7-10700, IEM */ },8614 /*mxcsr:in */ 0, 8615 /*128:out */ 0, 8616 /*256:out */ X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* i7-10700, IEM */ }, 8617 8617 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_V3(1), FP64_NORM_MAX(1) } }, 8618 8618 { /*src1 */ { FP64_NORM_MAX(0), FP64_INF(0), FP64_NORM_V3(1), FP64_NORM_MIN(0) } }, 8619 8619 { /* => */ { FP64_1(0), FP64_INF(0), FP64_1(0), FP64_0(1) } }, 8620 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,8621 /*128:out */ X86_MXCSR_XCPT_MASK,8622 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_UE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */ },8620 /*mxcsr:in */ 0, 8621 /*128:out */ 0, 8622 /*256:out */ X86_MXCSR_UE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */ }, 8623 8623 { { /*src2 */ { FP64_NORM_V3(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_V(1, 0, 0x3fe)/*-0.5*/ } }, 8624 8624 { /*src1 */ { FP64_NORM_V3(1), FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1) } }, … … 8636 8636 { /*src1 */ { FP64_NORM_V3(1), FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1) } }, 8637 8637 { /* => */ { FP64_1(1), FP64_1(0), FP64_1(1), FP64_NORM_MAX(0) } }, 8638 /*mxcsr:in */ (X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM)) |X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,8639 /*128:out */ (X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM)) |X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,8640 /*256:out */ (X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM)) |X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* i7-10700, IEM */ },8638 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 8639 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 8640 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* i7-10700, IEM */ }, 8641 8641 { { /*src2 */ { FP64_NORM_V3(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_V(1, 0, 0x3fe)/*-0.5*/ } }, 8642 8642 { /*src1 */ { FP64_NORM_V3(1), FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1) } }, 8643 8643 { /* => */ { FP64_1(1), FP64_1(0), FP64_1(1), FP64_INF(0) } }, 8644 /*mxcsr:in */ (X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM)) |X86_MXCSR_DAZ,8645 /*128:out */ (X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM)) |X86_MXCSR_DAZ,8646 /*256:out */ (X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM)) |X86_MXCSR_DAZ | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* i7-10700, IEM */ },8644 /*mxcsr:in */ X86_MXCSR_DAZ, 8645 /*128:out */ X86_MXCSR_DAZ, 8646 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* i7-10700, IEM */ }, 8647 8647 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MIN(1), FP64_NORM_MAX(0) } }, 8648 8648 { /*src1 */ { FP64_INF(0), FP64_0(0), FP64_V(0, FP64_FRAC_NORM_MAX, RTFLOAT64U_EXP_BIAS + 1), FP64_INF(0) } }, 8649 8649 { /* => */ { FP64_INF(0), FP64_0(1), FP64_NORM_MAX(1), FP64_INF(0) } }, 8650 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM,8651 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM,8652 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM},8650 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 8651 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 8652 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ }, 8653 8653 { { /*src2 */ { FP64_NORM_V3(0), FP64_1(1), FP64_V(1, 0, 0x3fe)/*-0.5*/, FP64_NORM_MIN(0) } }, 8654 8654 { /*src1 */ { FP64_NORM_V3(0), FP64_NORM_V2(0), FP64_NORM_MAX(0), FP64_V(1, FP64_FRAC_NORM_MAX, RTFLOAT64U_EXP_BIAS + 1) } }, 8655 8655 { /* => */ { FP64_1(0), FP64_NORM_V2(1), FP64_NORM_MAX(1), FP64_NORM_MAX(1) } }, 8656 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM) | X86_MXCSR_RC_ZERO,8657 /*128:out */ X86_MXCSR_ XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM) | X86_MXCSR_RC_ZERO,8658 /*256:out */ X86_MXCSR_ XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM) | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* i7-10700, IEM */ },8656 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 8657 /*128:out */ X86_MXCSR_RC_ZERO, 8658 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* i7-10700, IEM */ }, 8659 8659 { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_MAX(0), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MIN(0) } }, 8660 8660 { /*src1 */ { FP64_V(0, FP64_FRAC_NORM_MAX, FP64_FRAC_BITS + 1), FP64_NORM_MAX(1), FP64_V(0, FP64_FRAC_NORM_MAX - 1, 0x468), FP64_V(0, FP64_FRAC_NORM_MAX, 0x035) } }, 8661 8661 { /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_1(1), FP64_V(1, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_NORM_SAFE_INT_MAX(0) } }, 8662 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,8663 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,8664 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_PE },8662 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 8663 /*128:out */ X86_MXCSR_RC_ZERO, 8664 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE }, 8665 8665 { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_MAX(0), FP64_V(0, 0x8000000000000, 0x400)/*3.0*/, FP64_1(1) } }, 8666 8666 { /*src1 */ { FP64_V(0, FP64_FRAC_NORM_MAX, FP64_FRAC_BITS + 1), FP64_INF(1), FP64_1(1), FP64_1(0) } }, 8667 8667 { /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_INF(1), FP64_V(1, 0x5555555555556, 0x3fd)/*1/3*/, FP64_1(1) } }, 8668 /*mxcsr:in */ X86_MXCSR_ PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,8669 /*128:out */ X86_MXCSR_ PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,8670 /*256:out */ X86_MXCSR_ PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_PE },8668 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 8669 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 8670 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_PE }, 8671 8671 /* 8672 8672 * Invalids. … … 8746 8746 { /*src1 */ { FP32_0(0), FP32_0_x7(0) } }, 8747 8747 { /* => */ { FP32_QNAN(1), FP32_0_x7(0) } }, 8748 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,8749 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,8748 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 8749 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 8750 8750 /*256:out */ -1 }, 8751 8751 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V1 } }, 8752 8752 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V2 } }, 8753 8753 { /* => */ { FP32_QNAN(1), FP32_RAND_x7_V2 } }, 8754 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,8755 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,8754 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 8755 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, 8756 8756 /*256:out */ -1 }, 8757 8757 { { /*src2 */ { FP32_0(1), FP32_RAND_x7_V2 } }, … … 8770 8770 { /*src1 */ { FP32_0(1), FP32_RAND_x7_V5 } }, 8771 8771 { /* => */ { FP32_QNAN(1), FP32_RAND_x7_V5 } }, 8772 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,8773 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_IE,8772 /*mxcsr:in */ X86_MXCSR_DAZ, 8773 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_IE, 8774 8774 /*256:out */ -1 }, 8775 8775 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V5 } }, 8776 8776 { /*src1 */ { FP32_1(0), FP32_RAND_x7_V6 } }, 8777 8777 { /* => */ { FP32_INF(0), FP32_RAND_x7_V6 } }, 8778 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,8779 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_FSW_ZE,8778 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 8779 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_FSW_ZE, 8780 8780 /*256:out */ -1 }, 8781 8781 /* … … 8785 8785 { /*src1 */ { FP32_1(1), FP32_0_x7(0) } }, 8786 8786 { /* => */ { FP32_0(1), FP32_0_x7(0) } }, 8787 /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,8788 /*128:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,8787 /*mxcsr:in */ 0, 8788 /*128:out */ 0, 8789 8789 /*256:out */ -1 }, 8790 8790 { { /*src2 */ { FP32_INF(1), FP32_0_x7(0) } }, 8791 8791 { /*src1 */ { FP32_1(1), FP32_0_x7(0) } }, 8792 8792 { /* => */ { FP32_0(0), FP32_0_x7(0) } }, 8793 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,8794 /*128:out */ X86_MXCSR_XCPT_MASK,8793 /*mxcsr:in */ 0, 8794 /*128:out */ 0, 8795 8795 /*256:out */ -1 }, 8796 8796 { { /*src2 */ { FP32_INF(0), FP32_RAND_x7_V7 } }, 8797 8797 { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V0 } }, 8798 8798 { /* => */ { FP32_QNAN(1), FP32_RAND_x7_V0 } }, 8799 /*mxcsr:in */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) |X86_MXCSR_DAZ | X86_MXCSR_FZ,8800 /*128:out */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) |X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE,8799 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 8800 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE, 8801 8801 /*256:out */ -1 }, 8802 8802 { { /*src2 */ { FP32_INF(1), FP32_RAND_x7_V7 } }, 8803 8803 { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V1 } }, 8804 8804 { /* => */ { FP32_QNAN(1), FP32_RAND_x7_V1 } }, 8805 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,8806 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,8805 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 8806 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 8807 8807 /*256:out */ -1 }, 8808 8808 { { /*src2 */ { FP32_1(0), FP32_RAND_x7_V7 } }, 8809 8809 { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V6 } }, 8810 8810 { /* => */ { FP32_INF(0), FP32_RAND_x7_V6 } }, 8811 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ,8812 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ,8811 /*mxcsr:in */ X86_MXCSR_FZ, 8812 /*128:out */ X86_MXCSR_FZ, 8813 8813 /*256:out */ -1 }, 8814 8814 { { /*src2 */ { FP32_INF(0), FP32_RAND_x7_V5 } }, … … 8830 8830 { /*src1 */ { FP32_V(0, 0x600000, 0x7d)/*0.4375*/, FP32_RAND_x7_V6 } }, 8831 8831 { /* => */ { FP32_V(0, 0, 0x7d)/*0.2500*/, FP32_RAND_x7_V6 } }, 8832 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,8833 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,8832 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 8833 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 8834 8834 /*256:out */ -1 }, 8835 8835 { { /*src2 */ { FP32_V(0, 0x61e000, 0x89)/* 1807*/, FP32_RAND_x7_V6 } }, 8836 8836 { /*src1 */ { FP32_V(0, 0x37be78, 0x95)/*6020924*/, FP32_RAND_x7_V1 } }, 8837 8837 { /* => */ { FP32_V(0, 0x504000, 0x8a)/* 3332*/, FP32_RAND_x7_V1 } }, 8838 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,8839 /*128:out */ X86_MXCSR_XCPT_MASK,8838 /*mxcsr:in */ 0, 8839 /*128:out */ 0, 8840 8840 /*256:out */ -1 }, 8841 8841 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V4 } }, 8842 8842 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V2 } }, 8843 8843 { /* => */ { FP32_1(0), FP32_RAND_x7_V2 } }, 8844 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,8845 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,8844 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 8845 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 8846 8846 /*256:out */ -1 }, 8847 8847 { { /*src2 */ { FP32_V(0, 0x61e000, 0x89)/* 1807*/, FP32_RAND_x7_V0 } }, 8848 8848 { /*src1 */ { FP32_V(0, 0x37be78, 0x95)/*6020924*/, FP32_RAND_x7_V7 } }, 8849 8849 { /* => */ { FP32_V(0, 0x504000, 0x8a)/* 3332*/, FP32_RAND_x7_V7 } }, 8850 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,8851 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,8850 /*mxcsr:in */ X86_MXCSR_RC_UP, 8851 /*128:out */ X86_MXCSR_RC_UP, 8852 8852 /*256:out */ -1 }, 8853 8853 { { /*src2 */ { FP32_V(0, 0x4a30b8, 0x8f)/* 103521.4375*/, FP32_RAND_x7_V1 } }, 8854 8854 { /*src1 */ { FP32_V(0, 0x30eaa1, 0x93)/*1449300.1250*/, FP32_RAND_x7_V3 } }, 8855 8855 { /* => */ { FP32_V(0, 0x600000, 0x82)/* 14.0000*/, FP32_RAND_x7_V3 } }, 8856 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,8857 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,8856 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 8857 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 8858 8858 /*256:out */ -1 }, 8859 8859 { { /*src2 */ { FP32_V(0, 0x1a5200, 0x8c)/* 9876.5*/, FP32_RAND_x7_V6 } }, … … 8900 8900 { /*src1 */ { FP32_DENORM_MIN(1), FP32_RAND_x7_V2 } }, 8901 8901 { /* => */ { FP32_INF(1), FP32_RAND_x7_V2 } }, 8902 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,8903 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_ZE,8902 /*mxcsr:in */ 0, 8903 /*128:out */ X86_MXCSR_ZE, 8904 8904 /*256:out */ -1 }, 8905 8905 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_RAND_x7_V1 } }, 8906 8906 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V4 } }, 8907 8907 { /* => */ { FP32_QNAN(1), FP32_RAND_x7_V4 } }, 8908 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,8909 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,8908 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 8909 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, 8910 8910 /*256:out */ -1 }, 8911 8911 /** @todo More Denormals. */ … … 8978 8978 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 8979 8979 { /* => */ { FP64_QNAN(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, 8980 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,8981 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,8980 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 8981 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 8982 8982 /*256:out */ -1 }, 8983 8983 { { /*src2 */ { FP64_0(0), FP64_NORM_V3(0), FP64_NORM_V2(0), FP64_0(0) } }, 8984 8984 { /*src1 */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_NORM_V1(0) } }, 8985 8985 { /* => */ { FP64_QNAN(1), FP64_0(1), FP64_0(1), FP64_NORM_V1(0) } }, 8986 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,8987 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,8986 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 8987 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, 8988 8988 /*256:out */ -1 }, 8989 8989 { { /*src2 */ { FP64_0(1), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V1(1) } }, … … 9002 9002 { /*src1 */ { FP64_0(1), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V0(0) } }, 9003 9003 { /* => */ { FP64_QNAN(1), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V0(0) } }, 9004 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,9005 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_IE,9004 /*mxcsr:in */ X86_MXCSR_DAZ, 9005 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_IE, 9006 9006 /*256:out */ -1 }, 9007 9007 { { /*src2 */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, 9008 9008 { /*src1 */ { FP64_1(0), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V0(0) } }, 9009 9009 { /* => */ { FP64_INF(0), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V0(0) } }, 9010 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,9011 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_FSW_ZE,9010 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 9011 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_FSW_ZE, 9012 9012 /*256:out */ -1 }, 9013 9013 /* … … 9017 9017 { /*src1 */ { FP64_1(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, 9018 9018 { /* => */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, 9019 /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,9020 /*128:out */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,9019 /*mxcsr:in */ 0, 9020 /*128:out */ 0, 9021 9021 /*256:out */ -1 }, 9022 9022 { { /*src2 */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, 9023 9023 { /*src1 */ { FP64_1(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, 9024 9024 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 9025 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,9026 /*128:out */ X86_MXCSR_XCPT_MASK,9025 /*mxcsr:in */ 0, 9026 /*128:out */ 0, 9027 9027 /*256:out */ -1 }, 9028 9028 { { /*src2 */ { FP64_INF(0), FP64_RAND_V1(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, 9029 9029 { /*src1 */ { FP64_INF(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } }, 9030 9030 { /* => */ { FP64_QNAN(1), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } }, 9031 /*mxcsr:in */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) |X86_MXCSR_DAZ | X86_MXCSR_FZ,9032 /*128:out */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) |X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE,9031 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 9032 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE, 9033 9033 /*256:out */ -1 }, 9034 9034 { { /*src2 */ { FP64_INF(1), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V1(1) } }, 9035 9035 { /*src1 */ { FP64_INF(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V0(0) } }, 9036 9036 { /* => */ { FP64_QNAN(1), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V0(0) } }, 9037 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,9038 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,9037 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 9038 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 9039 9039 /*256:out */ -1 }, 9040 9040 { { /*src2 */ { FP64_1(0), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } }, 9041 9041 { /*src1 */ { FP64_INF(0), FP64_RAND_V1(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, 9042 9042 { /* => */ { FP64_INF(0), FP64_RAND_V1(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, 9043 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ,9044 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ,9043 /*mxcsr:in */ X86_MXCSR_FZ, 9044 /*128:out */ X86_MXCSR_FZ, 9045 9045 /*256:out */ -1 }, 9046 9046 { { /*src2 */ { FP64_INF(0), FP64_INF(0), FP64_INF(1), FP64_INF(1) } }, … … 9062 9062 { /*src1 */ { FP64_V(0, 0xe66f500000000, 0x40d)/*31131.828125*/, FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } }, 9063 9063 { /* => */ { FP64_1(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } }, 9064 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,9065 /*128:out */ X86_MXCSR_XCPT_MASK,9064 /*mxcsr:in */ 0, 9065 /*128:out */ 0, 9066 9066 /*256:out */ -1 }, 9067 9067 { { /*src2 */ { FP64_V(0, 0xaf00000000000, 0x406)/* 215.50*/, FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } }, 9068 9068 { /*src1 */ { FP64_V(0, 0xfb74e1d800000, 0x41a)/*266053390.75*/, FP64_RAND_V1(0), FP64_RAND_V1(1), FP64_RAND_V0(1) } }, 9069 9069 { /* => */ { FP64_V(0, 0x2d69a80000000, 0x413)/* 1234586.50*/, FP64_RAND_V1(0), FP64_RAND_V1(1), FP64_RAND_V0(1) } }, 9070 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,9071 /*128:out */ X86_MXCSR_XCPT_MASK,9070 /*mxcsr:in */ 0, 9071 /*128:out */ 0, 9072 9072 /*256:out */ -1 }, 9073 9073 { { /*src2 */ { FP64_V(1, 0x107526e749f80, 0x42b)/*-18723145413791.50*/, FP64_RAND_V3(0), FP64_RAND_V1(0), FP64_RAND_V1(1) } }, 9074 9074 { /*src1 */ { FP64_V(0, 0x549270a11c760, 0x42c)/* 46807863534478.75*/, FP64_RAND_V0(0), FP64_RAND_V2(1), FP64_RAND_V2(1) } }, 9075 9075 { /* => */ { FP64_V(1, 0x4000000000000, 0x400)/* -2.50*/, FP64_RAND_V0(0), FP64_RAND_V2(1), FP64_RAND_V2(1) } }, 9076 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,9077 /*128:out */ X86_MXCSR_XCPT_MASK,9076 /*mxcsr:in */ 0, 9077 /*128:out */ 0, 9078 9078 /*256:out */ -1 }, 9079 9079 { { /*src2 */ { FP64_V(0, 0x6fee0e4bd0000, 0x420)/* 12345678999.62500*/, FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 9080 9080 { /*src1 */ { FP64_V(0, 0x3c30944926c00, 0x424)/*169753086244.84375*/, FP64_RAND_V2(0), FP64_RAND_V1(1), FP64_RAND_V3(1) } }, 9081 9081 { /* => */ { FP64_V(0, 0xb800000000000, 0x402)/* 13.75000*/, FP64_RAND_V2(0), FP64_RAND_V1(1), FP64_RAND_V3(1) } }, 9082 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,9083 /*128:out */ X86_MXCSR_XCPT_MASK,9082 /*mxcsr:in */ 0, 9083 /*128:out */ 0, 9084 9084 /*256:out */ -1 }, 9085 9085 { { /*src2 */ { FP64_NORM_MAX(1), FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } }, 9086 9086 { /*src1 */ { FP64_NORM_MAX(0), FP64_RAND_V1(1), FP64_RAND_V0(0), FP64_RAND_V2(0) } }, 9087 9087 { /* => */ { FP64_1(1), FP64_RAND_V1(1), FP64_RAND_V0(0), FP64_RAND_V2(0) } }, 9088 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,9089 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,9088 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 9089 /*128:out */ X86_MXCSR_RC_DOWN, 9090 9090 /*256:out */ -1 }, 9091 9091 { { /*src2 */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_RAND_V2(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 9092 9092 { /*src1 */ { FP64_V(0, 0x4da20a80c6990, 0x42e)/*183416666481484.50*/, FP64_RAND_V1(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } }, 9093 9093 { /* => */ { FP64_V(0, 0x8000000000000, 0x3fe)/* 0.75*/, FP64_RAND_V1(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } }, 9094 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,9095 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,9094 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 9095 /*128:out */ X86_MXCSR_RC_DOWN, 9096 9096 /*256:out */ -1 }, 9097 9097 { { /*src2 */ { FP64_V(1, 0x68b83b1ed4000, 0x41e)/*-3025935759.4140625*/, FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, 9098 9098 { /*src1 */ { FP64_V(0, 0x68b83b1ed4000, 0x41f)/* 6051871518.8281250*/, FP64_RAND_V2(0), FP64_RAND_V1(1), FP64_RAND_V3(1) } }, 9099 9099 { /* => */ { FP64_V(1, 0, 0x400)/* -2.0000000*/, FP64_RAND_V2(0), FP64_RAND_V1(1), FP64_RAND_V3(1) } }, 9100 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,9101 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,9100 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 9101 /*128:out */ X86_MXCSR_RC_DOWN, 9102 9102 /*256:out */ -1 }, 9103 9103 { { /*src2 */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } }, 9104 9104 { /*src1 */ { FP64_V(0, 0x4a6a82b05f744, 0x42f)/*363296296296308.25*/, FP64_RAND_V1(1), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 9105 9105 { /* => */ { FP64_V(0, 0x8000000000000, 0x400)/* 3.00*/, FP64_RAND_V1(1), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 9106 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,9107 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,9106 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 9107 /*128:out */ X86_MXCSR_RC_DOWN, 9108 9108 /*256:out */ -1 }, 9109 9109 { { /*src2 */ { FP64_1(0), FP64_0(0), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_MAX(1) } }, 9110 9110 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_INF(1), FP64_NORM_SAFE_INT_MIN(1) } }, 9111 9111 { /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_INF(1), FP64_NORM_SAFE_INT_MIN(1) } }, 9112 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,9113 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,9112 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 9113 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 9114 9114 /*256:out */ -1 }, 9115 9115 { { /*src2 */ { FP64_NORM_V0(0), FP64_NORM_V1(1), FP64_NORM_V2(0), FP64_NORM_V3(1) } }, 9116 9116 { /*src1 */ { FP64_NORM_V0(0), FP64_SNAN(0), FP64_SNAN(1), FP64_QNAN(0) } }, 9117 9117 { /* => */ { FP64_1(0), FP64_SNAN(0), FP64_SNAN(1), FP64_QNAN(0) } }, 9118 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,9119 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,9118 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 9119 /*128:out */ X86_MXCSR_RC_DOWN, 9120 9120 /*256:out */ -1 }, 9121 9121 /* … … 9140 9140 { /*src1 */ { FP64_DENORM_MAX(1), FP64_DENORM_MIN(0), FP64_0(0), FP64_DENORM_MAX(0) } }, 9141 9141 { /* => */ { FP64_INF(0), FP64_DENORM_MIN(0), FP64_0(0), FP64_DENORM_MAX(0) } }, 9142 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,9143 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_ZE,9142 /*mxcsr:in */ 0, 9143 /*128:out */ X86_MXCSR_ZE, 9144 9144 /*256:out */ -1 }, 9145 9145 { { /* -DENORM_MAX / DENORM_MIN = (-huge) &_DE */ … … 9147 9147 { /*src1 */ { FP64_DENORM_MAX(1), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 9148 9148 { /* => */ { FP64_V(1, 0xffffffffffffe, 0x432)/*-4503599627370495.0*/, FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 9149 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,9150 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP | X86_MXCSR_DE,9149 /*mxcsr:in */ X86_MXCSR_RC_UP, 9150 /*128:out */ X86_MXCSR_RC_UP | X86_MXCSR_DE, 9151 9151 /*256:out */ -1 }, 9152 9152 { { /* -DENORM_MAX / -DENORM_MIN = (huge) &_DE */ … … 9161 9161 { /*src1 */ { FP64_DENORM_MIN(1), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 9162 9162 { /* => */ { FP64_V(1, 0x0000000000001, 0x3cb)/*-22204460492503135739e-35*/, FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 9163 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,9164 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_PE,9163 /*mxcsr:in */ 0, 9164 /*128:out */ X86_MXCSR_DE | X86_MXCSR_PE, 9165 9165 /*256:out */ -1 }, 9166 9166 { { /* -0 / DENORM_MIN = -0 &_DE */ … … 9168 9168 { /*src1 */ { FP64_0(1), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 9169 9169 { /* => */ { FP64_0(1), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 9170 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,9171 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE,9170 /*mxcsr:in */ 0, 9171 /*128:out */ X86_MXCSR_DE, 9172 9172 /*256:out */ -1 }, 9173 9173 { { /* -0.25 / DENORM_MAX = (-HUGE) &_DE &_PE */ … … 9175 9175 { /*src1 */ { FP64_V(1, 0, 0x3fd)/*0.25*/, FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 9176 9176 { /* => */ { FP64_V(1, 1, 0x7fb)/*1.1XYZe307*/, FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 9177 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,9178 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_PE,9177 /*mxcsr:in */ 0, 9178 /*128:out */ X86_MXCSR_DE | X86_MXCSR_PE, 9179 9179 /*256:out */ -1 }, 9180 9180 { { /* 42.0 / DENORM_MIN = INF &_DE &_PE(if OM) &_OE */ … … 9224 9224 { /*src1 */ { FP64_V(0, 0x5000000000000, 0x404)/*42.0*/, FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 9225 9225 { /* => */ { FP64_INF(0), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 9226 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,9227 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_ZE | X86_MXCSR_DAZ,9226 /*mxcsr:in */ X86_MXCSR_DAZ, 9227 /*128:out */ X86_MXCSR_ZE | X86_MXCSR_DAZ, 9228 9228 /*256:out */ -1 }, 9229 9229 { { /* DENORM_MAX / -42.0 = -5e-310 &_DE &_PE(if UM) &_UE */ … … 9277 9277 { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 9278 9278 { /* => */ { FP64_0(1), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 9279 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,9280 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,9279 /*mxcsr:in */ X86_MXCSR_DAZ, 9280 /*128:out */ X86_MXCSR_DAZ, 9281 9281 /*256:out */ -1 }, 9282 9282 { { /* DAZ+FZ: DENORM_MAX / -42.0 = -0 &- */ … … 9284 9284 { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 9285 9285 { /* => */ { FP64_0(1), FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 9286 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ,9287 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ,9286 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 9287 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 9288 9288 /*256:out */ -1 }, 9289 9289 /** @todo how to usefully test FZ, RC_{NEAREST,UP,DOWN,ZERO} ? */ … … 9399 9399 { /*src1 */ { FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(1) } }, 9400 9400 { /* => */ { FP32_QNAN(1), FP32_INF(0), FP32_INF(1), FP32_QNAN(1), FP32_INF(0), FP32_QNAN(1), FP32_QNAN(1), FP32_INF(1) } }, 9401 /*mxcsr:in */ X86_MXCSR_IM,9402 /*128:out */ X86_MXCSR_I M | X86_MXCSR_IE,9403 /*256:out */ X86_MXCSR_I M | X86_MXCSR_IE },9401 /*mxcsr:in */ 0, 9402 /*128:out */ X86_MXCSR_IE, 9403 /*256:out */ X86_MXCSR_IE }, 9404 9404 { { /*src2 */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1) } }, 9405 9405 { /*src1 */ { FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(1) } }, 9406 9406 { /* => */ { FP32_QNAN(1), FP32_INF(0), FP32_INF(1), FP32_QNAN(1), FP32_INF(0), FP32_QNAN(1), FP32_QNAN(1), FP32_INF(1) } }, 9407 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,9408 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,9409 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE },9407 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 9408 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 9409 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE }, 9410 9410 { { /*src2 */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1) } }, 9411 9411 { /*src1 */ { FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(1) } }, 9412 9412 { /* => */ { FP32_QNAN(1), FP32_INF(0), FP32_INF(1), FP32_QNAN(1), FP32_INF(0), FP32_QNAN(1), FP32_QNAN(1), FP32_INF(1) } }, 9413 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,9414 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,9415 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE },9413 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 9414 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, 9415 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE }, 9416 9416 { { /*src2 */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1) } }, 9417 9417 { /*src1 */ { FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(1) } }, 9418 9418 { /* => */ { FP32_QNAN(1), FP32_INF(0), FP32_INF(1), FP32_QNAN(1), FP32_INF(0), FP32_QNAN(1), FP32_QNAN(1), FP32_INF(1) } }, 9419 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,9420 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,9421 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE },9419 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 9420 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, 9421 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE }, 9422 9422 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1) } }, 9423 9423 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(1) } }, … … 9429 9429 { /*src1 */ { FP32_0(0), FP32_INF(0), FP32_INF(1), FP32_0(1), FP32_INF(0), FP32_INF(0), FP32_0(1), FP32_0(1) } }, 9430 9430 { /* => */ { FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(1) } }, 9431 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,9432 /*128:out */ X86_MXCSR_XCPT_MASK,9433 /*256:out */ X86_MXCSR_XCPT_MASK},9431 /*mxcsr:in */ 0, 9432 /*128:out */ 0, 9433 /*256:out */ 0 }, 9434 9434 { { /*src2 */ { FP32_INF(0), FP32_NORM_V1(0), FP32_NORM_V2(0), FP32_INF(0), FP32_NORM_V3(1), FP32_NORM_V2(1), FP32_INF(1), FP32_INF(1) } }, 9435 9435 { /*src1 */ { FP32_NORM_V0(0), FP32_INF(0), FP32_INF(1), FP32_NORM_V3(1), FP32_INF(0), FP32_INF(0), FP32_NORM_V1(1), FP32_NORM_V0(1) } }, 9436 9436 { /* => */ { FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(1) } }, 9437 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,9438 /*128:out */ X86_MXCSR_XCPT_MASK,9439 /*256:out */ X86_MXCSR_XCPT_MASK},9437 /*mxcsr:in */ 0, 9438 /*128:out */ 0, 9439 /*256:out */ 0 }, 9440 9440 { { /*src2 */ { FP32_NORM_V7(0), FP32_NORM_V6(0), FP32_NORM_V5(0), FP32_NORM_V4(0), FP32_NORM_V3(1), FP32_NORM_V2(1), FP32_NORM_V1(1), FP32_NORM_V0(1) } }, 9441 9441 { /*src1 */ { FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(1) } }, 9442 9442 { /* => */ { FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(1) } }, 9443 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,9444 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,9445 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO },9443 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 9444 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 9445 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO }, 9446 9446 /* 9447 9447 * Overflow, Precision. … … 9462 9462 { /*src1 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_2(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_1(0), FP32_NORM_V7(1), FP32_NORM_MAX(0) } }, 9463 9463 { /* => */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_NORM_MAX), FP32_NORM_MAX(0), FP32_1(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_2(0), FP32_NORM_V7(1), FP32_NORM_MAX(0) } }, 9464 /*mxcsr:in */ X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,9465 /*128:out */ X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,9466 /*256:out */ X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE },9464 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 9465 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, 9466 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE }, 9467 9467 { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_NORM_V3(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_0(0), FP32_NORM_MAX(0) } }, 9468 9468 { /*src1 */ { FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_NORM_V3(0), FP32_NORM_MAX(0), FP32_NORM_MIN(0), FP32_NORM_MIN(1), FP32_0(0), FP32_NORM_MAX(0) } }, … … 9525 9525 { /*src1 */ { FP32_V(0, 0x600000, 0x7f)/*1.75*/, FP32_V(1, 0, 0x7d)/*-0.25*/, FP32_V(0, 0x400000, 0x7e)/*0.75*/, FP32_V(1, 0, 0x7d)/*-0.25*/, FP32_V(0, 0, 0x7e)/* 0.50*/, FP32_V(1, 0, 0x7d)/*-0.25*/, FP32_V(0, 0x400000, 0x7e)/*0.75*/, FP32_1(1) /*- 1.00*/} }, 9526 9526 { /* => */ { FP32_V(0, 0x400000, 0x7f)/*1.50*/, FP32_V(0, 0x400000, 0x7f)/* 1.50*/, FP32_V(0, 0, 0x7e)/*0.50*/, FP32_V(1, 0x400000, 0x7e)/*-0.75*/, FP32_V(1, 0, 0x7d)/*-0.25*/, FP32_V(0, 0x400000, 0x7f)/* 1.50*/, FP32_V(0, 0, 0x7d)/*0.25*/, FP32_V(0, 0x524000, 0x86)/*210.25*/} }, 9527 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,9528 /*128:out */ X86_MXCSR_XCPT_MASK,9529 /*256:out */ X86_MXCSR_XCPT_MASK},9527 /*mxcsr:in */ 0, 9528 /*128:out */ 0, 9529 /*256:out */ 0 }, 9530 9530 { { /*src2 */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_V(0, 0x600000, 0x81)/* 7*/, FP32_V(0, 0x5c0000, 0x84)/*55*/, FP32_V(0, 0x534000, 0x86)/*211.25*/, FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_V(0, 0x7c9000, 0x88)/* 1010.25*/, FP32_V(0, 0x534000, 0x86)/*211.25*/ } }, 9531 9531 { /*src1 */ { FP32_V(0, 0x669050, 0x93)/*1888778*/, FP32_V(0, 0x1ea980, 0x8f)/* 81235*/, FP32_V(0, 0x780000, 0x84)/*62*/, FP32_V(0, 0x600000, 0x81)/* 7*/, FP32_1(0) /* 1.00*/, FP32_V(0, 0x7c9000, 0x88)/* 1010.25*/, FP32_V(0, 0x253468, 0x93)/*1353357.00*/, FP32_1(1) /*- 1.00*/ } }, … … 9617 9617 { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0) } }, 9618 9618 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 9619 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,9620 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,9621 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP },9619 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 9620 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 9621 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP }, 9622 9622 { { /*src2 */ { FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } }, 9623 9623 { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0) } }, 9624 9624 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 9625 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,9626 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,9627 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ },9625 /*mxcsr:in */ X86_MXCSR_DAZ, 9626 /*128:out */ X86_MXCSR_DAZ, 9627 /*256:out */ X86_MXCSR_DAZ }, 9628 9628 { { /*src2 */ { FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } }, 9629 9629 { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0) } }, 9630 9630 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 9631 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,9632 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,9633 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },9631 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 9632 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 9633 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO }, 9634 9634 { { /*src2 */ { FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } }, 9635 9635 { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0) } }, … … 9773 9773 { /*src1 */ { FP64_INF(0), FP64_INF(0), FP64_INF(1), FP64_INF(1) } }, 9774 9774 { /* => */ { FP64_QNAN(1), FP64_INF(0), FP64_INF(1), FP64_QNAN(1) } }, 9775 /*mxcsr:in */ X86_MXCSR_IM,9776 /*128:out */ X86_MXCSR_I M | X86_MXCSR_IE,9777 /*256:out */ X86_MXCSR_I M | X86_MXCSR_IE },9775 /*mxcsr:in */ 0, 9776 /*128:out */ X86_MXCSR_IE, 9777 /*256:out */ X86_MXCSR_IE }, 9778 9778 { { /*src2 */ { FP64_INF(0), FP64_QNAN(1), FP64_QNAN(1), FP64_INF(1) } }, 9779 9779 { /*src1 */ { FP64_INF(0), FP64_QNAN(1), FP64_QNAN(1), FP64_INF(1) } }, 9780 9780 { /* => */ { FP64_QNAN(1), FP64_QNAN(1), FP64_QNAN(1), FP64_INF(1) } }, 9781 /*mxcsr:in */ X86_MXCSR_IM,9782 /*128:out */ X86_MXCSR_I M | X86_MXCSR_IE,9783 /*256:out */ X86_MXCSR_I M | X86_MXCSR_IE },9781 /*mxcsr:in */ 0, 9782 /*128:out */ X86_MXCSR_IE, 9783 /*256:out */ X86_MXCSR_IE }, 9784 9784 { { /*src2 */ { FP64_INF(0), FP64_INF(0), FP64_INF(0), FP64_INF(0) } }, 9785 9785 { /*src1 */ { FP64_INF(0), FP64_INF(0), FP64_INF(1), FP64_INF(1) } }, 9786 9786 { /* => */ { FP64_QNAN(1), FP64_INF(0), FP64_INF(1), FP64_QNAN(1) } }, 9787 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,9788 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,9789 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE },9787 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 9788 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 9789 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE }, 9790 9790 { { /*src2 */ { FP64_INF(1), FP64_INF(1), FP64_INF(1), FP64_INF(1) } }, 9791 9791 { /*src1 */ { FP64_INF(0), FP64_INF(0), FP64_INF(1), FP64_INF(1) } }, 9792 9792 { /* => */ { FP64_INF(0), FP64_QNAN(1), FP64_QNAN(1), FP64_INF(1) } }, 9793 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,9794 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,9795 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE },9793 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 9794 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE, 9795 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE }, 9796 9796 { { /*src2 */ { FP64_INF(0), FP64_INF(0), FP64_INF(0), FP64_INF(0) } }, 9797 9797 { /*src1 */ { FP64_INF(0), FP64_INF(0), FP64_INF(1), FP64_INF(1) } }, 9798 9798 { /* => */ { FP64_QNAN(1), FP64_INF(0), FP64_INF(1), FP64_QNAN(1) } }, 9799 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,9800 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,9801 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE },9799 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 9800 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, 9801 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE }, 9802 9802 { { /*src2 */ { FP64_INF(1), FP64_INF(1), FP64_INF(1), FP64_INF(1) } }, 9803 9803 { /*src1 */ { FP64_INF(0), FP64_INF(0), FP64_INF(1), FP64_INF(1) } }, 9804 9804 { /* => */ { FP64_INF(0), FP64_QNAN(1), FP64_QNAN(1), FP64_INF(1) } }, 9805 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,9806 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,9807 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE },9805 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 9806 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE, 9807 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE }, 9808 9808 { { /*src2 */ { FP64_INF(0), FP64_INF(0), FP64_INF(0), FP64_INF(0) } }, 9809 9809 { /*src1 */ { FP64_INF(0), FP64_INF(0), FP64_INF(1), FP64_INF(1) } }, 9810 9810 { /* => */ { FP64_QNAN(1), FP64_INF(0), FP64_INF(1), FP64_QNAN(1) } }, 9811 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,9812 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,9813 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE },9811 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 9812 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, 9813 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE }, 9814 9814 { { /*src2 */ { FP64_INF(1), FP64_INF(1), FP64_INF(1), FP64_INF(1) } }, 9815 9815 { /*src1 */ { FP64_INF(0), FP64_INF(0), FP64_INF(1), FP64_INF(1) } }, 9816 9816 { /* => */ { FP64_INF(0), FP64_QNAN(1), FP64_QNAN(1), FP64_INF(1) } }, 9817 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,9818 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,9819 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE },9817 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 9818 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE, 9819 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE }, 9820 9820 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_INF(1), FP64_INF(1) } }, 9821 9821 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_INF(0), FP64_INF(0) } }, … … 9827 9827 { /*src1 */ { FP64_0(0), FP64_INF(0), FP64_INF(0), FP64_INF(0) } }, 9828 9828 { /* => */ { FP64_INF(1), FP64_INF(0), FP64_INF(0), FP64_INF(0) } }, 9829 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,9830 /*128:out */ X86_MXCSR_XCPT_MASK,9831 /*256:out */ X86_MXCSR_XCPT_MASK},9829 /*mxcsr:in */ 0, 9830 /*128:out */ 0, 9831 /*256:out */ 0 }, 9832 9832 { { /*src2 */ { FP64_INF(0), FP64_NORM_V1(0), FP64_INF(1), FP64_INF(1) } }, 9833 9833 { /*src1 */ { FP64_NORM_V0(0), FP64_INF(0), FP64_NORM_V1(1), FP64_NORM_V0(1) } }, 9834 9834 { /* => */ { FP64_INF(1), FP64_INF(0), FP64_INF(0), FP64_INF(1) } }, 9835 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,9836 /*128:out */ X86_MXCSR_XCPT_MASK,9837 /*256:out */ X86_MXCSR_XCPT_MASK},9835 /*mxcsr:in */ 0, 9836 /*128:out */ 0, 9837 /*256:out */ 0 }, 9838 9838 { { /*src2 */ { FP64_NORM_V3(0), FP64_NORM_V3(0), FP64_NORM_V1(1), FP64_NORM_V0(1) } }, 9839 9839 { /*src1 */ { FP64_INF(0), FP64_INF(0), FP64_INF(1), FP64_INF(1) } }, 9840 9840 { /* => */ { FP64_INF(0), FP64_INF(0), FP64_INF(1), FP64_INF(1) } }, 9841 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,9842 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,9843 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO },9841 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 9842 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, 9843 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO }, 9844 9844 /* 9845 9845 * Overflow, Precision. … … 9854 9854 { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_2(0), FP64_NORM_MAX(1) } }, 9855 9855 { /* => */ { FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_NORM_MAX), FP64_NORM_MAX(0), FP64_1(0), FP64_NORM_MAX(1) } }, 9856 /*mxcsr:in */ X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,9857 /*128:out */ X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,9858 /*256:out */ X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE },9856 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 9857 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, 9858 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE }, 9859 9859 { { /*src2 */ { FP64_NORM_MAX(0), FP64_1(0), FP64_0(0), FP64_NORM_MAX(0) } }, 9860 9860 { /*src1 */ { FP64_NORM_MAX(1), FP64_1(0), FP64_NORM_V3(1), FP64_NORM_MAX(0) } }, 9861 9861 { /* => */ { FP64_NORM_MAX(1), FP64_2(0), FP64_NORM_V3(1), FP64_NORM_MAX(0) } }, 9862 /*mxcsr:in */ X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,9863 /*128:out */ X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY,9864 /*256:out */ X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY },9862 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 9863 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY, 9864 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY }, 9865 9865 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_V3(0), FP64_NORM_MAX(0) } }, 9866 9866 { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_V3(0), FP64_NORM_MAX(0) } }, 9867 9867 { /* => */ { FP64_0(0), FP64_V(1, 0, FP64_EXP_NORM_MIN + 1), FP64_0(0), FP64_INF(0) } }, 9868 /*mxcsr:in */ X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,9869 /*128:out */ X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,9870 /*256:out */ X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY },9868 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 9869 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 9870 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY }, 9871 9871 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_0(0), FP64_NORM_MAX(0) } }, 9872 9872 { /*src1 */ { FP64_NORM_MIN(0), FP64_NORM_MIN(1), FP64_0(0), FP64_NORM_MAX(0) } }, 9873 9873 { /* => */ { FP64_V(1, FP64_FRAC_NORM_MAX - 1, FP64_EXP_NORM_MAX), FP64_V(1, 0, FP64_EXP_NORM_MIN + 1), FP64_0(0), FP64_INF(0) } }, 9874 /*mxcsr:in */ X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,9875 /*128:out */ X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_PE,9876 /*256:out */ X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE },9874 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 9875 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_PE, 9876 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE }, 9877 9877 { { /*src2 */ { FP64_NORM_MIN(1), FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_V2(1) } }, 9878 9878 { /*src1 */ { FP64_NORM_MIN(1), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_0(0) } }, 9879 9879 { /* => */ { FP64_0(1), FP64_NORM_MAX(0), FP64_INF(1), FP64_NORM_V2(1) } }, 9880 /*mxcsr:in */ X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,9881 /*128:out */ X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY,9882 /*256:out */ X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY },9880 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 9881 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY, 9882 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY }, 9883 9883 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } }, 9884 9884 { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } }, … … 9890 9890 { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } }, 9891 9891 { /* => */ { FP64_0(0), FP64_NORM_MAX(1), FP64_0(0), FP64_NORM_MAX(0) } }, 9892 /*mxcsr:in */ X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,9893 /*128:out */ X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY,9894 /*256:out */ X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY },9892 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 9893 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY, 9894 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY }, 9895 9895 { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } }, 9896 9896 { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } }, 9897 9897 { /* => */ { FP64_0(0), FP64_NORM_MAX(1), FP64_0(0), FP64_INF(0) } }, 9898 /*mxcsr:in */ X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_RC_UP,9899 /*128:out */ X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY,9900 /*256:out */ X86_MXCSR_ OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY },9898 /*mxcsr:in */ X86_MXCSR_RC_UP, 9899 /*128:out */ X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY, 9900 /*256:out */ X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY }, 9901 9901 { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_MAX(0), FP64_0(0), FP64_NORM_SAFE_INT_MAX(1) } }, 9902 9902 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_MAX(1), FP64_0(0), FP64_NORM_SAFE_INT_MAX(1) } }, … … 9917 9917 { /*src1 */ { FP64_V(0, 0x8000000000000, 0x409)/*1536*/, FP64_V(0, 0, 0x408)/* 512*/, FP64_V(0, 0xb800000000000, 0x404)/*55*/, FP64_V(0, 0xc000000000000, 0x401)/* 7*/ } }, 9918 9918 { /* => */ { FP64_V(0, 0, 0x408)/* 512*/, FP64_V(0, 0x8000000000000, 0x409)/*1536*/, FP64_V(0, 0xf000000000000, 0x404)/*62*/, FP64_V(0, 0xf000000000000, 0x404)/*62*/ } }, 9919 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,9920 /*128:out */ X86_MXCSR_XCPT_MASK,9921 /*256:out */ X86_MXCSR_XCPT_MASK},9919 /*mxcsr:in */ 0, 9920 /*128:out */ 0, 9921 /*256:out */ 0 }, 9922 9922 { { /*src2 */ { FP64_V(0, 0x9000000000000, 0x405)/* 100*/, FP64_V(0, 0xd6f3458800000, 0x41c)/*987654321*/, FP64_V(0, 0xd6eca42000000, 0x419)/* 123450000.5*/, FP64_V(0, 0xcf0033a34f337, 0x432)/*4072598000007579.5*/ } }, 9923 9923 { /*src1 */ { FP64_V(0, 0xd6f3458800000, 0x41c)/*987654321*/, FP64_V(1, 0x9000000000000, 0x405)/* -100*/, FP64_V(0, 0xcf00348ec5858, 0x432)/*4072598123457580.0*/, FP64_V(0, 0xd6eca42000000, 0x419)/* 123450000.5*/ } }, 9924 9924 { /* => */ { FP64_V(0, 0xd6f3426800000, 0x41c)/*987654221*/, FP64_V(0, 0xd6f3426800000, 0x41c)/*987654221*/, FP64_V(0, 0xcf0033a34f337, 0x432)/*4072598000007579.5*/, FP64_V(0, 0xcf00348ec5858, 0x432)/*4072598123457580.0*/ } }, 9925 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,9926 /*128:out */ X86_MXCSR_XCPT_MASK,9927 /*256:out */ X86_MXCSR_XCPT_MASK},9925 /*mxcsr:in */ 0, 9926 /*128:out */ 0, 9927 /*256:out */ 0 }, 9928 9928 { { /*src2 */ { FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0) } }, 9929 9929 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_1(0), FP64_1(0), FP64_1(1) } }, 9930 9930 { /* => */ { FP64_1(0), FP64_NORM_SAFE_INT_MAX(0), FP64_V(1, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX) } }, 9931 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,9932 /*128:out */ X86_MXCSR_XCPT_MASK,9933 /*256:out */ X86_MXCSR_XCPT_MASK},9931 /*mxcsr:in */ 0, 9932 /*128:out */ 0, 9933 /*256:out */ 0 }, 9934 9934 { { /*src2 */ { FP64_1(0), FP64_NORM_SAFE_INT_MAX(0), FP64_1(1), FP64_1(1) } }, 9935 9935 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_1(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_NORM_SAFE_INT_MAX(1) } }, 9936 9936 { /* => */ { FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_V(0, 0, FP64_EXP_SAFE_INT_MAX + 1), FP64_NORM_SAFE_INT_MAX(0), FP64_V(1, 0, FP64_EXP_SAFE_INT_MAX + 1) } }, 9937 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK,9938 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK,9939 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK},9937 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 9938 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 9939 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO }, 9940 9940 { { /*src2 */ { FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(0) } }, 9941 9941 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(0), FP64_0(0) } }, 9942 9942 { /* => */ { FP64_0(0), FP64_V(0, 0, FP64_EXP_SAFE_INT_MIN + 1), FP64_V(0, 0, FP64_EXP_SAFE_INT_MIN + 1), FP64_NORM_SAFE_INT_MIN(0) } }, 9943 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,9944 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,9945 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK},9943 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 9944 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 9945 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP }, 9946 9946 { { /*src2 */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(0), FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/ } }, 9947 9947 { /*src1 */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(1), FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/ } }, 9948 9948 { /* => */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_V(1, 0, FP64_EXP_SAFE_INT_MIN + 1), FP64_V(1, 0, FP64_EXP_SAFE_INT_MIN + 1), FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/ } }, 9949 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_XCPT_MASK,9950 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_XCPT_MASK,9951 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_XCPT_MASK},9949 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 9950 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 9951 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN }, 9952 9952 /** @todo More Normals. */ 9953 9953 /* … … 10037 10037 { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } }, 10038 10038 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 10039 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,10040 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,10041 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP },10039 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 10040 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 10041 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP }, 10042 10042 { { /*src2 */ { FP64_DENORM_MIN(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } }, 10043 10043 { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } }, 10044 10044 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 10045 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,10046 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,10047 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP },10045 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 10046 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 10047 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP }, 10048 10048 { { /*src2 */ { FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MIN(0) } }, 10049 10049 { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } }, 10050 10050 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 10051 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,10052 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,10053 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ },10051 /*mxcsr:in */ X86_MXCSR_DAZ, 10052 /*128:out */ X86_MXCSR_DAZ, 10053 /*256:out */ X86_MXCSR_DAZ }, 10054 10054 { { /*src2 */ { FP64_DENORM_MIN(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } }, 10055 10055 { /*src1 */ { FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0) } }, 10056 10056 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 10057 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,10058 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,10059 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ },10057 /*mxcsr:in */ X86_MXCSR_DAZ, 10058 /*128:out */ X86_MXCSR_DAZ, 10059 /*256:out */ X86_MXCSR_DAZ }, 10060 10060 { { /*src2 */ { FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MIN(0) } }, 10061 10061 { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } }, 10062 10062 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 10063 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,10064 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,10065 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },10063 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 10064 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 10065 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO }, 10066 10066 { { /*src2 */ { FP64_DENORM_MIN(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } }, 10067 10067 { /*src1 */ { FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0) } }, 10068 10068 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 10069 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,10070 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,10071 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },10069 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 10070 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 10071 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO }, 10072 10072 { { /*src2 */ { FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MIN(0) } }, 10073 10073 { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } }, … … 10166 10166 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 10167 10167 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 10168 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,10169 /*128:out */ X86_MXCSR_XCPT_MASK,10170 /*256:out */ X86_MXCSR_XCPT_MASK},10168 /*mxcsr:in */ 0, 10169 /*128:out */ 0, 10170 /*256:out */ 0 }, 10171 10171 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 10172 10172 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 10173 10173 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 10174 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,10175 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,10176 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO },10174 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 10175 /*128:out */ X86_MXCSR_RC_ZERO, 10176 /*256:out */ X86_MXCSR_RC_ZERO }, 10177 10177 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 10178 10178 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 10179 10179 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 10180 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,10181 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,10182 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },10180 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 10181 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 10182 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO }, 10183 10183 { { /*src2 */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1) } }, 10184 10184 { /*src1 */ { FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0) } }, 10185 10185 { /* => */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1) } }, 10186 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,10187 /*128:out */ X86_MXCSR_XCPT_MASK,10188 /*256:out */ X86_MXCSR_XCPT_MASK},10186 /*mxcsr:in */ 0, 10187 /*128:out */ 0, 10188 /*256:out */ 0 }, 10189 10189 { { /*src2 */ { FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0) } }, 10190 10190 { /*src1 */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0) } }, … … 10196 10196 { /*src1 */ { FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0) } }, 10197 10197 { /* => */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1) } }, 10198 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,10199 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,10200 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN },10198 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 10199 /*128:out */ X86_MXCSR_RC_DOWN, 10200 /*256:out */ X86_MXCSR_RC_DOWN }, 10201 10201 { { /*src2 */ { FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0) } }, 10202 10202 { /*src1 */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0) } }, 10203 10203 { /* => */ { FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0) } }, 10204 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,10205 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,10206 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP },10204 /*mxcsr:in */ X86_MXCSR_RC_UP, 10205 /*128:out */ X86_MXCSR_RC_UP, 10206 /*256:out */ X86_MXCSR_RC_UP }, 10207 10207 { { /*src2 */ { FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0) } }, 10208 10208 { /*src1 */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0) } }, 10209 10209 { /* => */ { FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0) } }, 10210 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,10211 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,10212 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },10210 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 10211 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 10212 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO }, 10213 10213 { { /*src2 */ { FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1) } }, 10214 10214 { /*src1 */ { FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(0) } }, 10215 10215 { /* => */ { FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1) } }, 10216 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,10217 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,10218 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },10216 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 10217 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 10218 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN }, 10219 10219 /* 10220 10220 * Infinity. … … 10223 10223 { /*src1 */ { FP32_0(0), FP32_INF(0), FP32_0(1), FP32_INF(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_INF(1) } }, 10224 10224 { /* => */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 10225 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,10226 /*128:out */ X86_MXCSR_XCPT_MASK,10227 /*256:out */ X86_MXCSR_XCPT_MASK},10225 /*mxcsr:in */ 0, 10226 /*128:out */ 0, 10227 /*256:out */ 0 }, 10228 10228 { { /*src2 */ { FP32_INF(0), FP32_0(0), FP32_INF(0), FP32_0(1), FP32_INF(1), FP32_0(0), FP32_INF(1), FP32_0(0) } }, 10229 10229 { /*src1 */ { FP32_0(0), FP32_INF(0), FP32_0(1), FP32_INF(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_INF(1) } }, 10230 10230 { /* => */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 10231 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,10232 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,10233 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP },10231 /*mxcsr:in */ X86_MXCSR_RC_UP, 10232 /*128:out */ X86_MXCSR_RC_UP, 10233 /*256:out */ X86_MXCSR_RC_UP }, 10234 10234 { { /*src2 */ { FP32_INF(0), FP32_0(0), FP32_INF(0), FP32_0(1), FP32_INF(1), FP32_0(0), FP32_INF(1), FP32_0(0) } }, 10235 10235 { /*src1 */ { FP32_0(0), FP32_INF(0), FP32_0(1), FP32_INF(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_INF(1) } }, 10236 10236 { /* => */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 10237 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,10238 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,10239 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN },10237 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 10238 /*128:out */ X86_MXCSR_RC_DOWN, 10239 /*256:out */ X86_MXCSR_RC_DOWN }, 10240 10240 { { /*src2 */ { FP32_INF(0), FP32_0(0), FP32_INF(0), FP32_0(1), FP32_INF(1), FP32_0(0), FP32_INF(1), FP32_0(0) } }, 10241 10241 { /*src1 */ { FP32_0(0), FP32_INF(0), FP32_0(1), FP32_INF(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_INF(1) } }, 10242 10242 { /* => */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 10243 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,10244 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,10245 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO },10243 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 10244 /*128:out */ X86_MXCSR_RC_ZERO, 10245 /*256:out */ X86_MXCSR_RC_ZERO }, 10246 10246 { { /*src2 */ { FP32_INF(0), FP32_0(0), FP32_INF(0), FP32_0(1), FP32_INF(1), FP32_0(0), FP32_INF(1), FP32_0(0) } }, 10247 10247 { /*src1 */ { FP32_0(0), FP32_INF(0), FP32_0(1), FP32_INF(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_INF(1) } }, 10248 10248 { /* => */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 10249 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,10250 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,10251 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },10249 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 10250 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 10251 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO }, 10252 10252 { { /*src2 */ { FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(0) } }, 10253 10253 { /*src1 */ { FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_INF(0) } }, … … 10259 10259 { /*src1 */ { FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_INF(0) } }, 10260 10260 { /* => */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_INF(0), FP32_INF(0) } }, 10261 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,10262 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,10263 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO },10261 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 10262 /*128:out */ X86_MXCSR_RC_ZERO, 10263 /*256:out */ X86_MXCSR_RC_ZERO }, 10264 10264 { { /*src2 */ { FP32_INF(0), FP32_NORM_V1(0), FP32_INF(1), FP32_NORM_V3(1), FP32_INF(1), FP32_NORM_V5(0), FP32_INF(1), FP32_NORM_V7(0) } }, 10265 10265 { /*src1 */ { FP32_NORM_V0(0), FP32_INF(1), FP32_NORM_V2(0), FP32_INF(1), FP32_NORM_V4(1), FP32_INF(1), FP32_NORM_V6(0), FP32_INF(0) } }, 10266 10266 { /* => */ { FP32_INF(0), FP32_NORM_V1(0), FP32_NORM_V2(0), FP32_NORM_V3(1), FP32_NORM_V4(1), FP32_NORM_V5(0), FP32_NORM_V6(0), FP32_INF(0) } }, 10267 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,10268 /*128:out */ X86_MXCSR_XCPT_MASK,10269 /*256:out */ X86_MXCSR_XCPT_MASK},10267 /*mxcsr:in */ 0, 10268 /*128:out */ 0, 10269 /*256:out */ 0 }, 10270 10270 { { /*src2 */ { FP32_INF(0), FP32_NORM_V1(0), FP32_INF(1), FP32_NORM_V3(1), FP32_INF(1), FP32_NORM_V5(0), FP32_INF(1), FP32_NORM_V7(0) } }, 10271 10271 { /*src1 */ { FP32_NORM_V0(0), FP32_INF(1), FP32_NORM_V2(0), FP32_INF(1), FP32_NORM_V4(1), FP32_INF(1), FP32_NORM_V6(0), FP32_INF(0) } }, 10272 10272 { /* => */ { FP32_INF(0), FP32_NORM_V1(0), FP32_NORM_V2(0), FP32_NORM_V3(1), FP32_NORM_V4(1), FP32_NORM_V5(0), FP32_NORM_V6(0), FP32_INF(0) } }, 10273 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,10274 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,10275 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },10273 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 10274 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 10275 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN }, 10276 10276 { { /*src2 */ { FP32_NORM_V7(0), FP32_INF(1), FP32_NORM_V5(1), FP32_INF(1), FP32_NORM_V3(0), FP32_INF(1), FP32_NORM_V1(0), FP32_INF(0) } }, 10277 10277 { /*src1 */ { FP32_INF(1), FP32_NORM_V6(0), FP32_INF(1), FP32_NORM_V4(1), FP32_INF(1), FP32_NORM_V2(0), FP32_INF(0), FP32_NORM_V0(0) } }, 10278 10278 { /* => */ { FP32_NORM_V7(0), FP32_NORM_V6(0), FP32_NORM_V5(1), FP32_NORM_V4(1), FP32_NORM_V3(0), FP32_NORM_V2(0), FP32_INF(0), FP32_INF(0) } }, 10279 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,10280 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,10281 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP },10279 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 10280 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 10281 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP }, 10282 10282 { { /*src2 */ { FP32_NORM_V7(0), FP32_INF(1), FP32_NORM_V5(1), FP32_INF(1), FP32_NORM_V3(0), FP32_INF(1), FP32_NORM_V1(0), FP32_INF(0) } }, 10283 10283 { /*src1 */ { FP32_INF(0), FP32_NORM_V6(0), FP32_INF(0), FP32_NORM_V4(1), FP32_INF(0), FP32_NORM_V2(0), FP32_INF(1), FP32_NORM_V0(0) } }, 10284 10284 { /* => */ { FP32_INF(0), FP32_NORM_V6(0), FP32_INF(0), FP32_NORM_V4(1), FP32_INF(0), FP32_NORM_V2(0), FP32_NORM_V1(0), FP32_INF(0) } }, 10285 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,10286 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,10287 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO },10285 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 10286 /*128:out */ X86_MXCSR_RC_ZERO, 10287 /*256:out */ X86_MXCSR_RC_ZERO }, 10288 10288 /* 10289 10289 * Normals. … … 10292 10292 { /*src1 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_0(1), FP32_NORM_MAX(0) } }, 10293 10293 { /* => */ { FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_MAX(1), FP32_0(1), FP32_0(1), FP32_NORM_MAX(0) } }, 10294 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,10295 /*128:out */ X86_MXCSR_XCPT_MASK,10296 /*256:out */ X86_MXCSR_XCPT_MASK},10294 /*mxcsr:in */ 0, 10295 /*128:out */ 0, 10296 /*256:out */ 0 }, 10297 10297 { { /*src2 */ { FP32_NORM_MIN(0), FP32_0(0), FP32_NORM_MIN(0), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_0(1), FP32_NORM_MIN(1), FP32_NORM_MIN(1) } }, 10298 10298 { /*src1 */ { FP32_NORM_MIN(0), FP32_NORM_MIN(0), FP32_0(0), FP32_0(0), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_0(1), FP32_NORM_MIN(0) } }, 10299 10299 { /* => */ { FP32_NORM_MIN(0), FP32_NORM_MIN(0), FP32_NORM_MIN(0), FP32_0(0), FP32_NORM_MIN(1), FP32_0(1), FP32_0(1), FP32_NORM_MIN(0) } }, 10300 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,10301 /*128:out */ X86_MXCSR_XCPT_MASK,10302 /*256:out */ X86_MXCSR_XCPT_MASK},10300 /*mxcsr:in */ 0, 10301 /*128:out */ 0, 10302 /*256:out */ 0 }, 10303 10303 { { /*src2 */ { FP32_NORM_MIN(0), FP32_NORM_MIN(0), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1) } }, 10304 10304 { /*src1 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MIN(0), FP32_NORM_MIN(1), FP32_NORM_MIN(0), FP32_NORM_MIN(1) } }, 10305 10305 { /* => */ { FP32_NORM_MAX(0), FP32_NORM_MIN(0), FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MIN(0), FP32_NORM_MIN(1) } }, 10306 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,10307 /*128:out */ X86_MXCSR_XCPT_MASK,10308 /*256:out */ X86_MXCSR_XCPT_MASK},10306 /*mxcsr:in */ 0, 10307 /*128:out */ 0, 10308 /*256:out */ 0 }, 10309 10309 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(1) } }, 10310 10310 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1) } }, 10311 10311 { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1) } }, 10312 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,10313 /*128:out */ X86_MXCSR_XCPT_MASK,10314 /*256:out */ X86_MXCSR_XCPT_MASK},10312 /*mxcsr:in */ 0, 10313 /*128:out */ 0, 10314 /*256:out */ 0 }, 10315 10315 { { /*src2 */ { FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_V(0, 0, 0x7d)/*0.25*/, FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_V(0, 0, 0x7d)/*0.25*/, FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_V(0, 0, 0x7d)/* 0.25*/, FP32_V(0, 0x600000, 0x7f)/*1.75*/, FP32_V(1, 0, 0x7d)/*-0.25*/ } }, 10316 10316 { /*src1 */ { FP32_V(1, 0, 0x7d)/*-0.25*/, FP32_V(0, 0, 0x7e)/*0.50*/, FP32_V(1, 0, 0x7d)/*-0.25*/, FP32_V(0, 0, 0x7e)/*0.50*/, FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_V(1, 0, 0x7e)/*-0.50*/, FP32_V(1, 0, 0x7d)/*0.25*/, FP32_V(1, 0, 0x7e)/*-0.50*/ } }, 10317 10317 { /* => */ { FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_V(0, 0, 0x7e)/*0.50*/, FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_V(0, 0, 0x7e)/*0.50*/, FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_V(0, 0, 0x7d)/* 0.25*/, FP32_V(0, 0x600000, 0x7f)/*1.75*/, FP32_V(1, 0, 0x7d)/*-0.25*/ } }, 10318 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,10319 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,10320 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },10318 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 10319 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 10320 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN }, 10321 10321 { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_V1(0), FP32_NORM_V2(1), FP32_NORM_V3(1), FP32_NORM_V5(0), FP32_0(1), FP32_NORM_V5(1), FP32_0(0) } }, 10322 10322 { /*src1 */ { FP32_NORM_V1(0), FP32_NORM_V1(1), FP32_NORM_V2(0), FP32_NORM_V3(1), FP32_0(1), FP32_NORM_V6(0), FP32_0(1), FP32_NORM_V7(0) } }, 10323 10323 { /* => */ { FP32_NORM_MAX(0), FP32_NORM_V1(0), FP32_NORM_V2(0), FP32_NORM_V3(1), FP32_NORM_V5(0), FP32_NORM_V6(0), FP32_0(1), FP32_NORM_V7(0) } }, 10324 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,10325 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,10326 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN },10324 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 10325 /*128:out */ X86_MXCSR_RC_DOWN, 10326 /*256:out */ X86_MXCSR_RC_DOWN }, 10327 10327 { { /*src2 */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_V(0, 0x5c0000, 0x84)/*55*/, FP32_V(1, 0x2514d6, 0x93)/*-1352346.75*/, FP32_V(1, 0x5c0000, 0x84)/*-55*/, FP32_V(1, 0x2514d6, 0x93)/*-1352346.75*/, FP32_V(1, 0x534000, 0x86)/*-211.25*/, FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_1(1) } }, 10328 10328 { /*src1 */ { FP32_V(0, 0x1ea980, 0x8f)/* 81235*/, FP32_V(0, 0x600000, 0x81)/* 7*/, FP32_V(0, 0x7c9000, 0x88)/* 1010.25*/, FP32_V(0, 0x600000, 0x81)/* 7*/, FP32_V(0, 0x253468, 0x93)/* 1353357.00*/, FP32_1(1), FP32_V(1, 0x712060, 0x92)/*- 987654*/, FP32_1(0) } }, 10329 10329 { /* => */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_V(0, 0x5c0000, 0x84)/*55*/, FP32_V(0, 0x7c9000, 0x88)/* 1010.25*/, FP32_V(0, 0x600000, 0x81)/* 7*/, FP32_V(0, 0x253468, 0x93)/* 1353357.00*/, FP32_1(1), FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_1(0) } }, 10330 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,10331 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,10332 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO },10330 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 10331 /*128:out */ X86_MXCSR_RC_ZERO, 10332 /*256:out */ X86_MXCSR_RC_ZERO }, 10333 10333 { { /*src2 */ { FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_V(0, 0x3ce348, 0x90)/*193421.125*/, FP32_V(0, 0x6423f2, 0x92)/*934463.125*/, FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0x16b43a, 0x93)/*1234567.25*/, FP32_V(0, 0x792318, 0x91)/*510232.75*/, FP32_V(0, 0x600000, 0x7e)/* 0.875*/ } }, 10334 10334 { /*src1 */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_V(0, 0x430ebc, 0x91)/*399477.875*/, FP32_V(0, 0x52e0b4, 0x92)/*863755.250*/, FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MAX(1), FP32_V(0, 0x00c6d3, 0x94)/*2109876.75*/, FP32_V(1, 0x316740, 0x8e)/*-45415.25*/, FP32_V(1, 0, 0x7d)/*-0.250*/ } }, 10335 10335 { /* => */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_V(0, 0x430ebc, 0x91)/*399477.875*/, FP32_V(0, 0x6423f2, 0x92)/*934463.125*/, FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0x00c6d3, 0x94)/*2109876.75*/, FP32_V(0, 0x792318, 0x91)/*510232.75*/, FP32_V(0, 0x600000, 0x7e)/* 0.875*/ } }, 10336 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,10337 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,10338 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN },10336 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 10337 /*128:out */ X86_MXCSR_RC_DOWN, 10338 /*256:out */ X86_MXCSR_RC_DOWN }, 10339 10339 { { /*src2 */ { FP32_V(0, 0x490fda, 0x80)/*3.1415926*/, FP32_V(0, 0x620b2e, 0x92)/*925874.9*/, FP32_V(0, 0x5dd520, 0x8e)/* 56789.125*/, FP32_V(1, 0x40e6b6, 0x8c)/*-12345.678*/, FP32_V(1, 0x490fda, 0x80)/*-3.1415926*/, FP32_V(1, 0x620b2e, 0x92)/*-925874.8*/, FP32_V(0, 0x5dd520, 0x8e)/*56789.125*/, FP32_V(0, 0x40e6b6, 0x8c)/*12345.678*/ } }, 10340 10340 { /*src1 */ { FP32_V(0, 0x490fdb, 0x80)/*3.1415927*/, FP32_V(0, 0x620b2d, 0x92)/*925874.8*/, FP32_V(1, 0x5dd521, 0x8e)/*-56789.127*/, FP32_V(1, 0x40e6b7, 0x8c)/*-12345.679*/, FP32_V(1, 0x490fdb, 0x80)/*-3.1415927*/, FP32_V(0, 0x620b2d, 0x92)/* 925874.9*/, FP32_V(0, 0x5dd521, 0x8e)/*56789.127*/, FP32_V(0, 0x40e6b7, 0x8c)/*12345.679*/ } }, 10341 10341 { /* => */ { FP32_V(0, 0x490fdb, 0x80)/*3.1415927*/, FP32_V(0, 0x620b2e, 0x92)/*925874.9*/, FP32_V(0, 0x5dd520, 0x8e)/* 56789.125*/, FP32_V(1, 0x40e6b6, 0x8c)/*-12345.678*/, FP32_V(1, 0x490fda, 0x80)/*-3.1415926*/, FP32_V(0, 0x620b2d, 0x92)/* 925874.9*/, FP32_V(0, 0x5dd521, 0x8e)/*56789.127*/, FP32_V(0, 0x40e6b7, 0x8c)/*12345.678*/ } }, 10342 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,10343 /*128:out */ X86_MXCSR_XCPT_MASK,10344 /*256:out */ X86_MXCSR_XCPT_MASK},10342 /*mxcsr:in */ 0, 10343 /*128:out */ 0, 10344 /*256:out */ 0 }, 10345 10345 /** @todo More Normals. */ 10346 10346 /* … … 10356 10356 { /*src1 */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0) } }, 10357 10357 { /* => */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0) } }, 10358 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,10359 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE,10360 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE },10358 /*mxcsr:in */ 0, 10359 /*128:out */ X86_MXCSR_DE, 10360 /*256:out */ X86_MXCSR_DE }, 10361 10361 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } }, 10362 10362 { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0) } }, 10363 10363 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 10364 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,10365 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,10366 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP },10364 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 10365 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 10366 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP }, 10367 10367 { { /*src2 */ { FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 10368 10368 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, … … 10374 10374 { /*src1 */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 10375 10375 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } }, 10376 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,10377 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,10378 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ },10376 /*mxcsr:in */ X86_MXCSR_DAZ, 10377 /*128:out */ X86_MXCSR_DAZ, 10378 /*256:out */ X86_MXCSR_DAZ }, 10379 10379 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } }, 10380 10380 { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0) } }, 10381 10381 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 10382 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,10383 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,10384 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP },10382 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 10383 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 10384 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP }, 10385 10385 /** @todo More Denormals. */ 10386 10386 /*35*/ FP32_TABLE_D9_PS_INVALIDS … … 10451 10451 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 10452 10452 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 10453 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,10454 /*128:out */ X86_MXCSR_XCPT_MASK,10455 /*256:out */ X86_MXCSR_XCPT_MASK},10453 /*mxcsr:in */ 0, 10454 /*128:out */ 0, 10455 /*256:out */ 0 }, 10456 10456 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 10457 10457 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 10458 10458 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 10459 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,10460 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,10461 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO },10459 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 10460 /*128:out */ X86_MXCSR_RC_ZERO, 10461 /*256:out */ X86_MXCSR_RC_ZERO }, 10462 10462 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 10463 10463 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 10464 10464 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 10465 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,10466 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,10467 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },10465 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 10466 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 10467 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO }, 10468 10468 { { /*src2 */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } }, 10469 10469 { /*src1 */ { FP64_0(1), FP64_0(0), FP64_0(1), FP64_0(1) } }, 10470 10470 { /* => */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } }, 10471 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,10472 /*128:out */ X86_MXCSR_XCPT_MASK,10473 /*256:out */ X86_MXCSR_XCPT_MASK},10471 /*mxcsr:in */ 0, 10472 /*128:out */ 0, 10473 /*256:out */ 0 }, 10474 10474 { { /*src2 */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_0(0) } }, 10475 10475 { /*src1 */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, … … 10481 10481 { /*src1 */ { FP64_0(1), FP64_0(0), FP64_0(1), FP64_0(1) } }, 10482 10482 { /* => */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } }, 10483 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,10484 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,10485 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN },10483 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 10484 /*128:out */ X86_MXCSR_RC_DOWN, 10485 /*256:out */ X86_MXCSR_RC_DOWN }, 10486 10486 { { /*src2 */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_0(0) } }, 10487 10487 { /*src1 */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, 10488 10488 { /* => */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_0(0) } }, 10489 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,10490 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,10491 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP },10489 /*mxcsr:in */ X86_MXCSR_RC_UP, 10490 /*128:out */ X86_MXCSR_RC_UP, 10491 /*256:out */ X86_MXCSR_RC_UP }, 10492 10492 { { /*src2 */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_0(0) } }, 10493 10493 { /*src1 */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, 10494 10494 { /* => */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_0(0) } }, 10495 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,10496 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,10497 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },10495 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 10496 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 10497 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO }, 10498 10498 { { /*src2 */ { FP64_0(1), FP64_0(1), FP64_0(0), FP64_0(0) } }, 10499 10499 { /*src1 */ { FP64_0(1), FP64_0(1), FP64_0(0), FP64_0(0) } }, 10500 10500 { /* => */ { FP64_0(1), FP64_0(1), FP64_0(0), FP64_0(0) } }, 10501 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,10502 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,10503 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },10501 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 10502 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 10503 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN }, 10504 10504 /* 10505 10505 * Infinity. … … 10508 10508 { /*src1 */ { FP64_0(0), FP64_INF(0), FP64_0(1), FP64_INF(0) } }, 10509 10509 { /* => */ { FP64_INF(0), FP64_INF(0), FP64_INF(0), FP64_INF(0) } }, 10510 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,10511 /*128:out */ X86_MXCSR_XCPT_MASK,10512 /*256:out */ X86_MXCSR_XCPT_MASK},10510 /*mxcsr:in */ 0, 10511 /*128:out */ 0, 10512 /*256:out */ 0 }, 10513 10513 { { /*src2 */ { FP64_INF(0), FP64_0(0), FP64_INF(0), FP64_0(1) } }, 10514 10514 { /*src1 */ { FP64_0(0), FP64_INF(0), FP64_0(1), FP64_INF(0) } }, 10515 10515 { /* => */ { FP64_INF(0), FP64_INF(0), FP64_INF(0), FP64_INF(0) } }, 10516 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,10517 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,10518 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP },10516 /*mxcsr:in */ X86_MXCSR_RC_UP, 10517 /*128:out */ X86_MXCSR_RC_UP, 10518 /*256:out */ X86_MXCSR_RC_UP }, 10519 10519 { { /*src2 */ { FP64_INF(0), FP64_0(0), FP64_INF(0), FP64_0(1) } }, 10520 10520 { /*src1 */ { FP64_0(0), FP64_INF(0), FP64_0(1), FP64_INF(0) } }, 10521 10521 { /* => */ { FP64_INF(0), FP64_INF(0), FP64_INF(0), FP64_INF(0) } }, 10522 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,10523 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,10524 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN },10522 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 10523 /*128:out */ X86_MXCSR_RC_DOWN, 10524 /*256:out */ X86_MXCSR_RC_DOWN }, 10525 10525 { { /*src2 */ { FP64_INF(0), FP64_0(0), FP64_INF(0), FP64_0(1) } }, 10526 10526 { /*src1 */ { FP64_0(0), FP64_INF(0), FP64_0(1), FP64_INF(0) } }, 10527 10527 { /* => */ { FP64_INF(0), FP64_INF(0), FP64_INF(0), FP64_INF(0) } }, 10528 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,10529 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,10530 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO },10528 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 10529 /*128:out */ X86_MXCSR_RC_ZERO, 10530 /*256:out */ X86_MXCSR_RC_ZERO }, 10531 10531 { { /*src2 */ { FP64_INF(0), FP64_0(0), FP64_INF(0), FP64_0(1) } }, 10532 10532 { /*src1 */ { FP64_0(0), FP64_INF(0), FP64_0(1), FP64_INF(0) } }, 10533 10533 { /* => */ { FP64_INF(0), FP64_INF(0), FP64_INF(0), FP64_INF(0) } }, 10534 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,10535 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,10536 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },10534 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 10535 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 10536 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO }, 10537 10537 { { /*src2 */ { FP64_INF(0), FP64_INF(0), FP64_INF(1), FP64_INF(1) } }, 10538 10538 { /*src1 */ { FP64_INF(0), FP64_INF(1), FP64_INF(0), FP64_INF(1) } }, … … 10544 10544 { /*src1 */ { FP64_INF(0), FP64_INF(1), FP64_INF(0), FP64_INF(1) } }, 10545 10545 { /* => */ { FP64_INF(0), FP64_INF(0), FP64_INF(0), FP64_INF(1) } }, 10546 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,10547 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,10548 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO },10546 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 10547 /*128:out */ X86_MXCSR_RC_ZERO, 10548 /*256:out */ X86_MXCSR_RC_ZERO }, 10549 10549 { { /*src2 */ { FP64_INF(0), FP64_NORM_V1(0), FP64_INF(1), FP64_NORM_V3(1) } }, 10550 10550 { /*src1 */ { FP64_NORM_V0(0), FP64_INF(1), FP64_NORM_V2(0), FP64_INF(1) } }, 10551 10551 { /* => */ { FP64_INF(0), FP64_NORM_V1(0), FP64_NORM_V2(0), FP64_NORM_V3(1) } }, 10552 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,10553 /*128:out */ X86_MXCSR_XCPT_MASK,10554 /*256:out */ X86_MXCSR_XCPT_MASK},10552 /*mxcsr:in */ 0, 10553 /*128:out */ 0, 10554 /*256:out */ 0 }, 10555 10555 { { /*src2 */ { FP64_INF(0), FP64_NORM_V1(0), FP64_INF(1), FP64_NORM_V3(1) } }, 10556 10556 { /*src1 */ { FP64_NORM_V0(0), FP64_INF(1), FP64_NORM_V2(0), FP64_INF(1) } }, 10557 10557 { /* => */ { FP64_INF(0), FP64_NORM_V1(0), FP64_NORM_V2(0), FP64_NORM_V3(1) } }, 10558 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,10559 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,10560 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },10558 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 10559 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 10560 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN }, 10561 10561 { { /*src2 */ { FP64_NORM_V1(0), FP64_INF(1), FP64_NORM_V2(1), FP64_INF(1) } }, 10562 10562 { /*src1 */ { FP64_INF(1), FP64_NORM_V3(0), FP64_INF(1), FP64_NORM_V0(1) } }, 10563 10563 { /* => */ { FP64_NORM_V1(0), FP64_NORM_V3(0), FP64_NORM_V2(1), FP64_NORM_V0(1) } }, 10564 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,10565 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,10566 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP },10564 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 10565 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 10566 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP }, 10567 10567 { { /*src2 */ { FP64_NORM_V1(0), FP64_INF(1), FP64_NORM_V3(1), FP64_INF(1) } }, 10568 10568 { /*src1 */ { FP64_INF(0), FP64_NORM_V2(0), FP64_INF(0), FP64_NORM_V0(1) } }, 10569 10569 { /* => */ { FP64_INF(0), FP64_NORM_V2(0), FP64_INF(0), FP64_NORM_V0(1) } }, 10570 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,10571 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,10572 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO },10570 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 10571 /*128:out */ X86_MXCSR_RC_ZERO, 10572 /*256:out */ X86_MXCSR_RC_ZERO }, 10573 10573 /* 10574 10574 * Normals. … … 10577 10577 { /*src1 */ { FP64_NORM_V3(1), FP64_NORM_V1(0), FP64_NORM_V2(1), FP64_NORM_V1(0) } }, 10578 10578 { /* => */ { FP64_NORM_V0(0), FP64_NORM_V1(0), FP64_NORM_V2(0), FP64_NORM_V1(0) } }, 10579 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,10580 /*128:out */ X86_MXCSR_XCPT_MASK,10581 /*256:out */ X86_MXCSR_XCPT_MASK},10579 /*mxcsr:in */ 0, 10580 /*128:out */ 0, 10581 /*256:out */ 0 }, 10582 10582 { { /*src2 */ { FP64_NORM_V0(0), FP64_0(1), FP64_NORM_V2(0), FP64_0(1) } }, 10583 10583 { /*src1 */ { FP64_0(0), FP64_NORM_V1(1), FP64_0(0), FP64_NORM_V1(0) } }, 10584 10584 { /* => */ { FP64_NORM_V0(0), FP64_0(1), FP64_NORM_V2(0), FP64_NORM_V1(0) } }, 10585 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,10586 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,10587 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO },10585 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 10586 /*128:out */ X86_MXCSR_RC_ZERO, 10587 /*256:out */ X86_MXCSR_RC_ZERO }, 10588 10588 { { /*src2 */ { FP64_V(0, 0, 0x409)/*1024*/, FP64_V(0, 0xb800000000000, 0x404)/*55*/, FP64_V(0, 0x8000000000000, 0x409)/*1536*/, FP64_V(0, 0xf000000000000, 0x404)/* 62*/ } }, 10589 10589 { /*src1 */ { FP64_V(0, 0, 0x408)/* 512*/, FP64_V(0, 0xc000000000000, 0x401)/* 7*/, FP64_1(1), FP64_V(1, 0xf000000000000, 0x404)/*-62*/ } }, 10590 10590 { /* => */ { FP64_V(0, 0, 0x409)/*1024*/, FP64_V(0, 0xb800000000000, 0x404)/*55*/, FP64_V(0, 0x8000000000000, 0x409)/*1536*/, FP64_V(0, 0xf000000000000, 0x404)/* 62*/ } }, 10591 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ,10592 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ,10593 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ },10591 /*mxcsr:in */ X86_MXCSR_FZ, 10592 /*128:out */ X86_MXCSR_FZ, 10593 /*256:out */ X86_MXCSR_FZ }, 10594 10594 { { /*src2 */ { FP64_V(0, 0x26580b4800000, 0x41d)/* 1234567890*/, FP64_V(0, 0xd6f3458800000, 0x41c)/*987654321*/, FP64_V(0, 0xd6f3426800000, 0x41c)/*987654221*/, FP64_V(0, 0xcf0033a34f337, 0x432)/*4072598000007579.5*/ } }, 10595 10595 { /*src1 */ { FP64_V(1, 0x26580b4800000, 0x41d)/*-1234567890*/, FP64_V(0, 0x9000000000000, 0x405)/* 100*/, FP64_1(0), FP64_V(0, 0xd6eca42000000, 0x419)/* 123450000.5*/ } }, 10596 10596 { /* => */ { FP64_V(0, 0x26580b4800000, 0x41d)/* 1234567890*/, FP64_V(0, 0xd6f3458800000, 0x41c)/*987654321*/, FP64_V(0, 0xd6f3426800000, 0x41c)/*987654221*/, FP64_V(0, 0xcf0033a34f337, 0x432)/*4072598000007579.5*/ } }, 10597 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,10598 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,10599 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ },10597 /*mxcsr:in */ X86_MXCSR_DAZ, 10598 /*128:out */ X86_MXCSR_DAZ, 10599 /*256:out */ X86_MXCSR_DAZ }, 10600 10600 { { /*src2 */ { FP64_V(0, 0x26580b4800000, 0x41d)/* 1234567890*/, FP64_V(0, 0xd6f3458800000, 0x41c)/*987654321*/, FP64_V(0, 0xd6f3426800000, 0x41c)/*987654221*/, FP64_V(0, 0xcf0033a34f337, 0x432)/*4072598000007579.5*/ } }, 10601 10601 { /*src1 */ { FP64_V(1, 0x26580b4800000, 0x41d)/*-1234567890*/, FP64_V(0, 0x9000000000000, 0x405)/* -100*/, FP64_1(0), FP64_V(0, 0xd6eca42000000, 0x419)/* 123450000.5*/ } }, … … 10607 10607 { /*src1 */ { FP64_1(0), FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(0), FP64_0(0) } }, 10608 10608 { /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MIN(0) } }, 10609 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,10610 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,10611 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },10609 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 10610 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 10611 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO }, 10612 10612 { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_0(0), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(1) } }, 10613 10613 { /*src1 */ { FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(1), FP64_0(0), FP64_NORM_SAFE_INT_MIN(0) } }, … … 10619 10619 { /*src1 */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_V(0, 0xb88e0395d49b0, 0x42d)/* 121098765432102.75*/ } }, 10620 10620 { /* => */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_V(0, 0xb88e0395d49b0, 0x42d)/* 121098765432102.75*/ } }, 10621 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,10622 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,10623 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP },10621 /*mxcsr:in */ X86_MXCSR_RC_UP, 10622 /*128:out */ X86_MXCSR_RC_UP, 10623 /*256:out */ X86_MXCSR_RC_UP }, 10624 10624 { { /*src2 */ { FP64_V(0, 0xc000000000000, 0x3ff)/*1.75*/, FP64_V(0, 0, 0x3fd)/*0.25*/, FP64_V(0, 0x26580b4c7e6b7, 0x41d)/*1234567891.1234567*/, FP64_V(0, 0xf9b0207d06184, 0x3fb)/*0.1234589833333129*/ } }, 10625 10625 { /*src1 */ { FP64_V(0, 0, 0x3fd)/*0.25*/, FP64_V(0, 0, 0x3fe)/*0.50*/, FP64_V(0, 0x26580b4c7e6bc, 0x41d)/*1234567891.1234580*/, FP64_V(0, 0xf9b0207d0617d, 0x3fb)/*0.1234589833333128*/ } }, 10626 10626 { /* => */ { FP64_V(0, 0xc000000000000, 0x3ff)/*1.75*/, FP64_V(0, 0, 0x3fe)/*0.50*/, FP64_V(0, 0x26580b4c7e6bc, 0x41d)/*1234567891.1234580*/, FP64_V(0, 0xf9b0207d06184, 0x3fb)/*0.1234589833333129*/ } }, 10627 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,10628 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,10629 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },10627 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 10628 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 10629 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN }, 10630 10630 /* 10631 10631 * Denormals. … … 10640 10640 { /*src1 */ { FP64_0(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_0(0) } }, 10641 10641 { /* => */ { FP64_0(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } }, 10642 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,10643 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE,10644 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE },10642 /*mxcsr:in */ 0, 10643 /*128:out */ X86_MXCSR_DE, 10644 /*256:out */ X86_MXCSR_DE }, 10645 10645 { { /*src2 */ { FP64_DENORM_MIN(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } }, 10646 10646 { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } }, 10647 10647 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 10648 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,10649 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,10650 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP },10648 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 10649 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 10650 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP }, 10651 10651 { { /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_DENORM_MAX(0), FP64_0(0) } }, 10652 10652 { /*src1 */ { FP64_0(0), FP64_DENORM_MAX(0), FP64_0(0), FP64_DENORM_MAX(0) } }, … … 10658 10658 { /*src1 */ { FP64_0(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_0(0) } }, 10659 10659 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(1) } }, 10660 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,10661 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,10662 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ },10660 /*mxcsr:in */ X86_MXCSR_DAZ, 10661 /*128:out */ X86_MXCSR_DAZ, 10662 /*256:out */ X86_MXCSR_DAZ }, 10663 10663 { { /*src2 */ { FP64_DENORM_MIN(0), FP64_DENORM_MIN(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0) } }, 10664 10664 { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } }, 10665 10665 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 10666 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,10667 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,10668 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP },10666 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 10667 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 10668 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP }, 10669 10669 /** @todo Denormals. */ 10670 10670 /* … … 10738 10738 { /*src1 */ { FP32_0(0), FP32_0_x7(0) } }, 10739 10739 { /* => */ { FP32_0(0), FP32_0_x7(0) } }, 10740 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,10741 /*128:out */ X86_MXCSR_XCPT_MASK,10740 /*mxcsr:in */ 0, 10741 /*128:out */ 0, 10742 10742 /*256:out */ -1 }, 10743 10743 { { /*src2 */ { FP32_0(0), FP32_0_x7(0) } }, … … 10750 10750 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V2 } }, 10751 10751 { /* => */ { FP32_0(0), FP32_RAND_x7_V2 } }, 10752 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,10753 /*128:out */ X86_MXCSR_XCPT_MASK,10752 /*mxcsr:in */ 0, 10753 /*128:out */ 0, 10754 10754 /*256:out */ -1 }, 10755 10755 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V2 } }, 10756 10756 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V3 } }, 10757 10757 { /* => */ { FP32_0(0), FP32_RAND_x7_V3 } }, 10758 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,10759 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,10758 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 10759 /*128:out */ X86_MXCSR_RC_ZERO, 10760 10760 /*256:out */ -1 }, 10761 10761 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V3 } }, 10762 10762 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V4 } }, 10763 10763 { /* => */ { FP32_0(0), FP32_RAND_x7_V4 } }, 10764 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,10765 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,10764 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 10765 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 10766 10766 /*256:out */ -1 }, 10767 10767 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V4 } }, 10768 10768 { /*src1 */ { FP32_0(1), FP32_RAND_x7_V5 } }, 10769 10769 { /* => */ { FP32_0(0), FP32_RAND_x7_V5 } }, 10770 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,10771 /*128:out */ X86_MXCSR_XCPT_MASK,10770 /*mxcsr:in */ 0, 10771 /*128:out */ 0, 10772 10772 /*256:out */ -1 }, 10773 10773 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V5 } }, 10774 10774 { /*src1 */ { FP32_0(1), FP32_RAND_x7_V6 } }, 10775 10775 { /* => */ { FP32_0(0), FP32_RAND_x7_V6 } }, 10776 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,10777 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,10776 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 10777 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 10778 10778 /*256:out */ -1 }, 10779 10779 { { /*src2 */ { FP32_0(1), FP32_RAND_x7_V6 } }, 10780 10780 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V5 } }, 10781 10781 { /* => */ { FP32_0(1), FP32_RAND_x7_V5 } }, 10782 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,10783 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,10782 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 10783 /*128:out */ X86_MXCSR_RC_ZERO, 10784 10784 /*256:out */ -1 }, 10785 10785 { { /*src2 */ { FP32_0(1), FP32_RAND_x7_V7 } }, 10786 10786 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V2 } }, 10787 10787 { /* => */ { FP32_0(1), FP32_RAND_x7_V2 } }, 10788 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,10789 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,10788 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 10789 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 10790 10790 /*256:out */ -1 }, 10791 10791 { { /*src2 */ { FP32_0(1), FP32_RAND_x7_V1 } }, … … 10798 10798 { /*src1 */ { FP32_0(1), FP32_RAND_x7_V5 } }, 10799 10799 { /* => */ { FP32_0(1), FP32_RAND_x7_V5 } }, 10800 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,10801 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,10800 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 10801 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 10802 10802 /*256:out */ -1 }, 10803 10803 /* … … 10807 10807 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V1 } }, 10808 10808 { /* => */ { FP32_INF(0), FP32_RAND_x7_V1 } }, 10809 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,10810 /*128:out */ X86_MXCSR_XCPT_MASK,10809 /*mxcsr:in */ 0, 10810 /*128:out */ 0, 10811 10811 /*256:out */ -1 }, 10812 10812 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V5 } }, 10813 10813 { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V3 } }, 10814 10814 { /* => */ { FP32_INF(0), FP32_RAND_x7_V3 } }, 10815 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,10816 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,10815 /*mxcsr:in */ X86_MXCSR_RC_UP, 10816 /*128:out */ X86_MXCSR_RC_UP, 10817 10817 /*256:out */ -1 }, 10818 10818 { { /*src2 */ { FP32_INF(0), FP32_RAND_x7_V0 } }, 10819 10819 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V3 } }, 10820 10820 { /* => */ { FP32_INF(0), FP32_RAND_x7_V3 } }, 10821 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,10822 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,10821 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 10822 /*128:out */ X86_MXCSR_RC_ZERO, 10823 10823 /*256:out */ -1 }, 10824 10824 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V2 } }, 10825 10825 { /*src1 */ { FP32_INF(1), FP32_RAND_x7_V0 } }, 10826 10826 { /* => */ { FP32_0(0), FP32_RAND_x7_V0 } }, 10827 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,10828 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,10827 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 10828 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 10829 10829 /*256:out */ -1 }, 10830 10830 { { /*src2 */ { FP32_INF(0), FP32_RAND_x7_V3 } }, … … 10837 10837 { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V0 } }, 10838 10838 { /* => */ { FP32_INF(0), FP32_RAND_x7_V0 } }, 10839 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,10840 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,10839 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 10840 /*128:out */ X86_MXCSR_RC_ZERO, 10841 10841 /*256:out */ -1 }, 10842 10842 { { /*src2 */ { FP32_INF(1), FP32_RAND_x7_V1 } }, 10843 10843 { /*src1 */ { FP32_INF(1), FP32_RAND_x7_V2 } }, 10844 10844 { /* => */ { FP32_INF(1), FP32_RAND_x7_V2 } }, 10845 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,10846 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,10845 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 10846 /*128:out */ X86_MXCSR_RC_ZERO, 10847 10847 /*256:out */ -1 }, 10848 10848 { { /*src2 */ { FP32_INF(1), FP32_RAND_x7_V3 } }, 10849 10849 { /*src1 */ { FP32_INF(1), FP32_RAND_x7_V3 } }, 10850 10850 { /* => */ { FP32_INF(1), FP32_RAND_x7_V3 } }, 10851 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,10852 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,10851 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 10852 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 10853 10853 /*256:out */ -1 }, 10854 10854 { { /*src2 */ { FP32_INF(1), FP32_RAND_x7_V1 } }, 10855 10855 { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V1 } }, 10856 10856 { /* => */ { FP32_INF(0), FP32_RAND_x7_V1 } }, 10857 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,10858 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,10857 /*mxcsr:in */ X86_MXCSR_RC_UP, 10858 /*128:out */ X86_MXCSR_RC_UP, 10859 10859 /*256:out */ -1 }, 10860 10860 { { /*src2 */ { FP32_INF(1), FP32_RAND_x7_V0 } }, 10861 10861 { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V1 } }, 10862 10862 { /* => */ { FP32_INF(0), FP32_RAND_x7_V1 } }, 10863 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,10864 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,10863 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 10864 /*128:out */ X86_MXCSR_RC_ZERO, 10865 10865 /*256:out */ -1 }, 10866 10866 { { /*src2 */ { FP32_INF(0), FP32_RAND_x7_V3 } }, 10867 10867 { /*src1 */ { FP32_INF(1), FP32_RAND_x7_V2 } }, 10868 10868 { /* => */ { FP32_INF(0), FP32_RAND_x7_V2 } }, 10869 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,10870 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,10869 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 10870 /*128:out */ X86_MXCSR_RC_ZERO, 10871 10871 /*256:out */ -1 }, 10872 10872 { { /*src2 */ { FP32_INF(0), FP32_RAND_x7_V0 } }, 10873 10873 { /*src1 */ { FP32_INF(1), FP32_RAND_x7_V3 } }, 10874 10874 { /* => */ { FP32_INF(0), FP32_RAND_x7_V3 } }, 10875 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ,10876 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ,10875 /*mxcsr:in */ X86_MXCSR_FZ, 10876 /*128:out */ X86_MXCSR_FZ, 10877 10877 /*256:out */ -1 }, 10878 10878 { { /*src2 */ { FP32_INF(0), FP32_RAND_x7_V4 } }, 10879 10879 { /*src1 */ { FP32_NORM_V0(0), FP32_RAND_x7_V5 } }, 10880 10880 { /* => */ { FP32_INF(0), FP32_RAND_x7_V5 } }, 10881 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,10882 /*128:out */ X86_MXCSR_XCPT_MASK,10881 /*mxcsr:in */ 0, 10882 /*128:out */ 0, 10883 10883 /*256:out */ -1 }, 10884 10884 { { /*src2 */ { FP32_INF(0), FP32_RAND_x7_V6 } }, 10885 10885 { /*src1 */ { FP32_NORM_V3(0), FP32_RAND_x7_V5 } }, 10886 10886 { /* => */ { FP32_INF(0), FP32_RAND_x7_V5 } }, 10887 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,10888 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,10887 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 10888 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 10889 10889 /*256:out */ -1 }, 10890 10890 { { /*src2 */ { FP32_NORM_V7(0), FP32_RAND_x7_V7 } }, 10891 10891 { /*src1 */ { FP32_INF(1), FP32_RAND_x7_V1 } }, 10892 10892 { /* => */ { FP32_NORM_V7(0), FP32_RAND_x7_V1 } }, 10893 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,10894 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,10893 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 10894 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 10895 10895 /*256:out */ -1 }, 10896 10896 { { /*src2 */ { FP32_NORM_V7(0), FP32_RAND_x7_V4 } }, 10897 10897 { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V2 } }, 10898 10898 { /* => */ { FP32_INF(0), FP32_RAND_x7_V2 } }, 10899 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,10900 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,10899 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 10900 /*128:out */ X86_MXCSR_RC_ZERO, 10901 10901 /*256:out */ -1 }, 10902 10902 /* … … 10906 10906 { /*src1 */ { FP32_NORM_MAX(0), FP32_RAND_x7_V3 } }, 10907 10907 { /* => */ { FP32_NORM_MAX(0), FP32_RAND_x7_V3 } }, 10908 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,10909 /*128:out */ X86_MXCSR_XCPT_MASK,10908 /*mxcsr:in */ 0, 10909 /*128:out */ 0, 10910 10910 /*256:out */ -1 }, 10911 10911 { { /*src2 */ { FP32_NORM_MIN(0), FP32_RAND_x7_V3 } }, 10912 10912 { /*src1 */ { FP32_NORM_MIN(0), FP32_RAND_x7_V2 } }, 10913 10913 { /* => */ { FP32_NORM_MIN(0), FP32_RAND_x7_V2 } }, 10914 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,10915 /*128:out */ X86_MXCSR_XCPT_MASK,10914 /*mxcsr:in */ 0, 10915 /*128:out */ 0, 10916 10916 /*256:out */ -1 }, 10917 10917 { { /*src2 */ { FP32_NORM_MIN(0), FP32_RAND_x7_V3 } }, 10918 10918 { /*src1 */ { FP32_NORM_MAX(0), FP32_RAND_x7_V1 } }, 10919 10919 { /* => */ { FP32_NORM_MAX(0), FP32_RAND_x7_V1 } }, 10920 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,10921 /*128:out */ X86_MXCSR_XCPT_MASK,10920 /*mxcsr:in */ 0, 10921 /*128:out */ 0, 10922 10922 /*256:out */ -1 }, 10923 10923 { { /*src2 */ { FP32_NORM_MAX(0), FP32_RAND_x7_V2 } }, 10924 10924 { /*src1 */ { FP32_NORM_MAX(0), FP32_RAND_x7_V0 } }, 10925 10925 { /* => */ { FP32_NORM_MAX(0), FP32_RAND_x7_V0 } }, 10926 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,10927 /*128:out */ X86_MXCSR_XCPT_MASK,10926 /*mxcsr:in */ 0, 10927 /*128:out */ 0, 10928 10928 /*256:out */ -1 }, 10929 10929 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_x7_V2 } }, 10930 10930 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V1 } }, 10931 10931 { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V1 } }, 10932 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,10933 /*128:out */ X86_MXCSR_XCPT_MASK,10932 /*mxcsr:in */ 0, 10933 /*128:out */ 0, 10934 10934 /*256:out */ -1 }, 10935 10935 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V6 } }, 10936 10936 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V1 } }, 10937 10937 { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V1 } }, 10938 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,10939 /*128:out */ X86_MXCSR_XCPT_MASK,10938 /*mxcsr:in */ 0, 10939 /*128:out */ 0, 10940 10940 /*256:out */ -1 }, 10941 10941 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V0 } }, 10942 10942 { /*src1 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_x7_V1 } }, 10943 10943 { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V1 } }, 10944 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,10945 /*128:out */ X86_MXCSR_XCPT_MASK,10944 /*mxcsr:in */ 0, 10945 /*128:out */ 0, 10946 10946 /*256:out */ -1 }, 10947 10947 { { /*src2 */ { FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_RAND_x7_V1 } }, 10948 10948 { /*src1 */ { FP32_V(1, 0, 0x7d)/*-0.25*/, FP32_RAND_x7_V2 } }, 10949 10949 { /* => */ { FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_RAND_x7_V2 } }, 10950 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,10951 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,10950 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 10951 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 10952 10952 /*256:out */ -1 }, 10953 10953 { { /*src2 */ { FP32_V(0, 0, 0x7d)/*0.25*/, FP32_RAND_x7_V3 } }, 10954 10954 { /*src1 */ { FP32_V(0, 0, 0x7e)/*0.50*/, FP32_RAND_x7_V1 } }, 10955 10955 { /* => */ { FP32_V(0, 0, 0x7e)/*0.50*/, FP32_RAND_x7_V1 } }, 10956 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,10957 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,10956 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 10957 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 10958 10958 /*256:out */ -1 }, 10959 10959 { { /*src2 */ { FP32_NORM_MAX(0), FP32_RAND_x7_V1 } }, 10960 10960 { /*src1 */ { FP32_NORM_V1(0), FP32_RAND_x7_V0 } }, 10961 10961 { /* => */ { FP32_NORM_MAX(0), FP32_RAND_x7_V0 } }, 10962 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,10963 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,10962 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 10963 /*128:out */ X86_MXCSR_RC_DOWN, 10964 10964 /*256:out */ -1 }, 10965 10965 { { /*src2 */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_RAND_x7_V3 } }, 10966 10966 { /*src1 */ { FP32_V(0, 0x1ea980, 0x8f)/* 81235*/, FP32_RAND_x7_V1 } }, 10967 10967 { /* => */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_RAND_x7_V1 } }, 10968 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,10969 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,10968 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 10969 /*128:out */ X86_MXCSR_RC_ZERO, 10970 10970 /*256:out */ -1 }, 10971 10971 { { /*src2 */ { FP32_V(1, 0x2514d6, 0x93)/*-1352346.75*/, FP32_RAND_x7_V2 } }, 10972 10972 { /*src1 */ { FP32_V(0, 0x7c9000, 0x88)/* 1010.25*/, FP32_RAND_x7_V0 } }, 10973 10973 { /* => */ { FP32_V(0, 0x7c9000, 0x88)/* 1010.25*/, FP32_RAND_x7_V0 } }, 10974 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,10975 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,10974 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 10975 /*128:out */ X86_MXCSR_RC_ZERO, 10976 10976 /*256:out */ -1 }, 10977 10977 { { /*src2 */ { FP32_V(1, 0x2514d6, 0x93)/*-1352346.75*/, FP32_RAND_x7_V4 } }, 10978 10978 { /*src1 */ { FP32_V(0, 0x253468, 0x93)/* 1353357.00*/, FP32_RAND_x7_V4 } }, 10979 10979 { /* => */ { FP32_V(0, 0x253468, 0x93)/* 1353357.00*/, FP32_RAND_x7_V4 } }, 10980 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,10981 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,10980 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 10981 /*128:out */ X86_MXCSR_RC_ZERO, 10982 10982 /*256:out */ -1 }, 10983 10983 { { /*src2 */ { FP32_V(1, 0x40e6b6, 0x8c)/*-12345.678*/, FP32_RAND_x7_V3 } }, 10984 10984 { /*src1 */ { FP32_V(1, 0x40e6b7, 0x8c)/*-12345.679*/, FP32_RAND_x7_V1 } }, 10985 10985 { /* => */ { FP32_V(1, 0x40e6b6, 0x8c)/*-12345.678*/, FP32_RAND_x7_V1 } }, 10986 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,10987 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,10986 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 10987 /*128:out */ X86_MXCSR_RC_ZERO, 10988 10988 /*256:out */ -1 }, 10989 10989 { { /*src2 */ { FP32_V(0, 0x620b2e, 0x92)/*925874.9*/, FP32_RAND_x7_V2 } }, 10990 10990 { /*src1 */ { FP32_V(0, 0x620b2d, 0x92)/*925874.8*/, FP32_RAND_x7_V4 } }, 10991 10991 { /* => */ { FP32_V(0, 0x620b2e, 0x92)/*925874.9*/, FP32_RAND_x7_V4 } }, 10992 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,10993 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,10992 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 10993 /*128:out */ X86_MXCSR_RC_ZERO, 10994 10994 /*256:out */ -1 }, 10995 10995 { { /*src2 */ { FP32_V(0, 0x490fda, 0x80)/*3.1415926*/, FP32_RAND_x7_V3 } }, 10996 10996 { /*src1 */ { FP32_V(0, 0x490fdb, 0x80)/*3.1415927*/, FP32_RAND_x7_V1 } }, 10997 10997 { /* => */ { FP32_V(0, 0x490fdb, 0x80)/*3.1415927*/, FP32_RAND_x7_V1 } }, 10998 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,10999 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,10998 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 10999 /*128:out */ X86_MXCSR_RC_ZERO, 11000 11000 /*256:out */ -1 }, 11001 11001 { { /*src2 */ { FP32_V(1, 0x40e6b6, 0x8c)/*-12345.678*/, FP32_RAND_x7_V0 } }, 11002 11002 { /*src1 */ { FP32_V(1, 0x40e6b7, 0x8c)/*-12345.679*/, FP32_RAND_x7_V0 } }, 11003 11003 { /* => */ { FP32_V(1, 0x40e6b6, 0x8c)/*-12345.678*/, FP32_RAND_x7_V0 } }, 11004 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,11005 /*128:out */ X86_MXCSR_XCPT_MASK,11004 /*mxcsr:in */ 0, 11005 /*128:out */ 0, 11006 11006 /*256:out */ -1 }, 11007 11007 { { /*src2 */ { FP32_V(0, 0x5dd520, 0x8e)/* 56789.125*/, FP32_RAND_x7_V6 } }, 11008 11008 { /*src1 */ { FP32_V(1, 0x5dd521, 0x8e)/*-56789.127*/, FP32_RAND_x7_V4 } }, 11009 11009 { /* => */ { FP32_V(0, 0x5dd520, 0x8e)/* 56789.125*/, FP32_RAND_x7_V4 } }, 11010 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,11011 /*128:out */ X86_MXCSR_XCPT_MASK,11010 /*mxcsr:in */ 0, 11011 /*128:out */ 0, 11012 11012 /*256:out */ -1 }, 11013 11013 { { /*src2 */ { FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_RAND_x7_V7 } }, 11014 11014 { /*src1 */ { FP32_V(1, 0, 0x7d)/*-0.250*/, FP32_RAND_x7_V1 } }, 11015 11015 { /* => */ { FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_RAND_x7_V1 } }, 11016 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,11017 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,11016 /*mxcsr:in */ X86_MXCSR_RC_UP, 11017 /*128:out */ X86_MXCSR_RC_UP, 11018 11018 /*256:out */ -1 }, 11019 11019 /** @todo More Normals. */ … … 11030 11030 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V1 } }, 11031 11031 { /* => */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V1 } }, 11032 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,11033 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE,11032 /*mxcsr:in */ 0, 11033 /*128:out */ X86_MXCSR_DE, 11034 11034 /*256:out */ -1 }, 11035 11035 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_RAND_x7_V4 } }, 11036 11036 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V3 } }, 11037 11037 { /* => */ { FP32_0(0), FP32_RAND_x7_V3 } }, 11038 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,11039 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,11038 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 11039 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 11040 11040 /*256:out */ -1 }, 11041 11041 { { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V7 } }, 11042 11042 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V4 } }, 11043 11043 { /* => */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V4 } }, 11044 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,11045 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE,11044 /*mxcsr:in */ 0, 11045 /*128:out */ X86_MXCSR_DE, 11046 11046 /*256:out */ -1 }, 11047 11047 { { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V6 } }, 11048 11048 { /*src1 */ { FP32_DENORM_MAX(1), FP32_RAND_x7_V4 } }, 11049 11049 { /* => */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V4 } }, 11050 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,11051 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE,11050 /*mxcsr:in */ 0, 11051 /*128:out */ X86_MXCSR_DE, 11052 11052 /*256:out */ -1 }, 11053 11053 { { /*src2 */ { FP32_DENORM_MAX(1), FP32_RAND_x7_V3 } }, 11054 11054 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V2 } }, 11055 11055 { /* => */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V2 } }, 11056 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,11057 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE,11056 /*mxcsr:in */ 0, 11057 /*128:out */ X86_MXCSR_DE, 11058 11058 /*256:out */ -1 }, 11059 11059 { { /*src2 */ { FP32_DENORM_MIN(1), FP32_RAND_x7_V7 } }, 11060 11060 { /*src1 */ { FP32_DENORM_MIN(0), FP32_RAND_x7_V2 } }, 11061 11061 { /* => */ { FP32_DENORM_MIN(0), FP32_RAND_x7_V2 } }, 11062 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,11063 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE,11062 /*mxcsr:in */ 0, 11063 /*128:out */ X86_MXCSR_DE, 11064 11064 /*256:out */ -1 }, 11065 11065 { { /*src2 */ { FP32_DENORM_MIN(1), FP32_RAND_x7_V5 } }, 11066 11066 { /*src1 */ { FP32_DENORM_MIN(1), FP32_RAND_x7_V1 } }, 11067 11067 { /* => */ { FP32_DENORM_MIN(1), FP32_RAND_x7_V1 } }, 11068 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,11069 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE,11068 /*mxcsr:in */ 0, 11069 /*128:out */ X86_MXCSR_DE, 11070 11070 /*256:out */ -1 }, 11071 11071 { { /*src2 */ { FP32_DENORM_MIN(1), FP32_RAND_x7_V2 } }, 11072 11072 { /*src1 */ { FP32_DENORM_MIN(1), FP32_RAND_x7_V3 } }, 11073 11073 { /* => */ { FP32_0(1), FP32_RAND_x7_V3 } }, 11074 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,11075 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,11074 /*mxcsr:in */ X86_MXCSR_DAZ, 11075 /*128:out */ X86_MXCSR_DAZ, 11076 11076 /*256:out */ -1 }, 11077 11077 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_RAND_x7_V0 } }, 11078 11078 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V0 } }, 11079 11079 { /* => */ { FP32_DENORM_MIN(0), FP32_RAND_x7_V0 } }, 11080 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,11081 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE,11080 /*mxcsr:in */ 0, 11081 /*128:out */ X86_MXCSR_DE, 11082 11082 /*256:out */ -1 }, 11083 11083 /** @todo More Denormals. */ … … 11139 11139 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 11140 11140 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 11141 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,11142 /*128:out */ X86_MXCSR_XCPT_MASK,11141 /*mxcsr:in */ 0, 11142 /*128:out */ 0, 11143 11143 /*256:out */ -1 }, 11144 11144 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, … … 11151 11151 { /*src1 */ { FP64_0(0), FP64_INF(1), FP64_QNAN(0), FP64_SNAN(1) } }, 11152 11152 { /* => */ { FP64_0(0), FP64_INF(1), FP64_QNAN(0), FP64_SNAN(1) } }, 11153 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,11154 /*128:out */ X86_MXCSR_XCPT_MASK,11153 /*mxcsr:in */ 0, 11154 /*128:out */ 0, 11155 11155 /*256:out */ -1 }, 11156 11156 { { /*src2 */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V0(0), FP64_RAND_V0(0) } }, 11157 11157 { /*src1 */ { FP64_0(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(0) } }, 11158 11158 { /* => */ { FP64_0(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(0) } }, 11159 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,11160 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,11159 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 11160 /*128:out */ X86_MXCSR_RC_ZERO, 11161 11161 /*256:out */ -1 }, 11162 11162 { { /*src2 */ { FP64_0(0), FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V1(0) } }, 11163 11163 { /*src1 */ { FP64_0(0), FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V2(1) } }, 11164 11164 { /* => */ { FP64_0(0), FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V2(1) } }, 11165 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,11166 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,11165 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 11166 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 11167 11167 /*256:out */ -1 }, 11168 11168 { { /*src2 */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V3(0) } }, 11169 11169 { /*src1 */ { FP64_0(1), FP64_RAND_V1(0), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, 11170 11170 { /* => */ { FP64_0(0), FP64_RAND_V1(0), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, 11171 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,11172 /*128:out */ X86_MXCSR_XCPT_MASK,11171 /*mxcsr:in */ 0, 11172 /*128:out */ 0, 11173 11173 /*256:out */ -1 }, 11174 11174 { { /*src2 */ { FP64_0(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(0) } }, 11175 11175 { /*src1 */ { FP64_0(1), FP64_RAND_V2(1), FP64_RAND_V3(0), FP64_RAND_V0(1) } }, 11176 11176 { /* => */ { FP64_0(0), FP64_RAND_V2(1), FP64_RAND_V3(0), FP64_RAND_V0(1) } }, 11177 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,11178 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,11177 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 11178 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 11179 11179 /*256:out */ -1 }, 11180 11180 { { /*src2 */ { FP64_0(1), FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V3(1) } }, 11181 11181 { /*src1 */ { FP64_0(0), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V3(0) } }, 11182 11182 { /* => */ { FP64_0(1), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V3(0) } }, 11183 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,11184 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,11183 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 11184 /*128:out */ X86_MXCSR_RC_ZERO, 11185 11185 /*256:out */ -1 }, 11186 11186 { { /*src2 */ { FP64_0(1), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V1(0) } }, 11187 11187 { /*src1 */ { FP64_0(0), FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 11188 11188 { /* => */ { FP64_0(1), FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 11189 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,11190 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,11189 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 11190 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 11191 11191 /*256:out */ -1 }, 11192 11192 { { /*src2 */ { FP64_0(1), FP64_RAND_V1(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } }, … … 11199 11199 { /*src1 */ { FP64_0(1), FP64_RAND_V1(0), FP64_RAND_V0(1), FP64_RAND_V2(1) } }, 11200 11200 { /* => */ { FP64_0(1), FP64_RAND_V1(0), FP64_RAND_V0(1), FP64_RAND_V2(1) } }, 11201 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,11202 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,11201 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 11202 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 11203 11203 /*256:out */ -1 }, 11204 11204 /* … … 11208 11208 { /*src1 */ { FP64_0(0), FP64_RAND_V1(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } }, 11209 11209 { /* => */ { FP64_INF(0), FP64_RAND_V1(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } }, 11210 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,11211 /*128:out */ X86_MXCSR_XCPT_MASK,11210 /*mxcsr:in */ 0, 11211 /*128:out */ 0, 11212 11212 /*256:out */ -1 }, 11213 11213 { { /*src2 */ { FP64_0(0), FP64_RAND_V1(1), FP64_RAND_V1(1), FP64_RAND_V3(1) } }, 11214 11214 { /*src1 */ { FP64_INF(0), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } }, 11215 11215 { /* => */ { FP64_INF(0), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } }, 11216 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,11217 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,11216 /*mxcsr:in */ X86_MXCSR_RC_UP, 11217 /*128:out */ X86_MXCSR_RC_UP, 11218 11218 /*256:out */ -1 }, 11219 11219 { { /*src2 */ { FP64_INF(0), FP64_INF(1), FP64_SNAN(1), FP64_QNAN(1) } }, 11220 11220 { /*src1 */ { FP64_0(0), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } }, 11221 11221 { /* => */ { FP64_INF(0), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } }, 11222 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,11223 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,11222 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 11223 /*128:out */ X86_MXCSR_RC_ZERO, 11224 11224 /*256:out */ -1 }, 11225 11225 { { /*src2 */ { FP64_0(0), FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V3(0) } }, 11226 11226 { /*src1 */ { FP64_INF(1), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V0(1) } }, 11227 11227 { /* => */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V0(1) } }, 11228 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,11229 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,11228 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 11229 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 11230 11230 /*256:out */ -1 }, 11231 11231 { { /*src2 */ { FP64_INF(0), FP64_RAND_V3(1), FP64_RAND_V3(1), FP64_RAND_V0(1) } }, … … 11238 11238 { /*src1 */ { FP64_INF(0), FP64_RAND_V0(1), FP64_RAND_V0(1), FP64_RAND_V3(1) } }, 11239 11239 { /* => */ { FP64_INF(0), FP64_RAND_V0(1), FP64_RAND_V0(1), FP64_RAND_V3(1) } }, 11240 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,11241 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,11240 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 11241 /*128:out */ X86_MXCSR_RC_ZERO, 11242 11242 /*256:out */ -1 }, 11243 11243 { { /*src2 */ { FP64_INF(1), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V3(0) } }, 11244 11244 { /*src1 */ { FP64_INF(1), FP64_QNAN_V(1, 1), FP64_RAND_V1(1), FP64_RAND_V2(0) } }, 11245 11245 { /* => */ { FP64_INF(1), FP64_QNAN_V(1, 1), FP64_RAND_V1(1), FP64_RAND_V2(0) } }, 11246 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,11247 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,11246 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 11247 /*128:out */ X86_MXCSR_RC_ZERO, 11248 11248 /*256:out */ -1 }, 11249 11249 { { /*src2 */ { FP64_INF(1), FP64_RAND_V2(1), FP64_RAND_V1(1), FP64_RAND_V0(1) } }, 11250 11250 { /*src1 */ { FP64_INF(1), FP64_RAND_V0(0), FP64_RAND_V3(1), FP64_RAND_V0(1) } }, 11251 11251 { /* => */ { FP64_INF(1), FP64_RAND_V0(0), FP64_RAND_V3(1), FP64_RAND_V0(1) } }, 11252 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,11253 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,11252 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 11253 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 11254 11254 /*256:out */ -1 }, 11255 11255 { { /*src2 */ { FP64_INF(1), FP64_RAND_V1(1), FP64_RAND_V3(1), FP64_RAND_V0(1) } }, 11256 11256 { /*src1 */ { FP64_INF(0), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V1(1) } }, 11257 11257 { /* => */ { FP64_INF(0), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V1(1) } }, 11258 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,11259 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,11258 /*mxcsr:in */ X86_MXCSR_RC_UP, 11259 /*128:out */ X86_MXCSR_RC_UP, 11260 11260 /*256:out */ -1 }, 11261 11261 { { /*src2 */ { FP64_INF(1), FP64_RAND_V0(1), FP64_RAND_V2(1), FP64_RAND_V0(1) } }, 11262 11262 { /*src1 */ { FP64_INF(0), FP64_RAND_V0(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, 11263 11263 { /* => */ { FP64_INF(0), FP64_RAND_V0(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, 11264 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,11265 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,11264 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 11265 /*128:out */ X86_MXCSR_RC_ZERO, 11266 11266 /*256:out */ -1 }, 11267 11267 { { /*src2 */ { FP64_INF(0), FP64_RAND_V2(1), FP64_RAND_V3(1), FP64_RAND_V0(1) } }, 11268 11268 { /*src1 */ { FP64_INF(1), FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, 11269 11269 { /* => */ { FP64_INF(0), FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, 11270 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,11271 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,11270 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 11271 /*128:out */ X86_MXCSR_RC_ZERO, 11272 11272 /*256:out */ -1 }, 11273 11273 { { /*src2 */ { FP64_INF(0), FP64_RAND_V0(1), FP64_RAND_V2(1), FP64_RAND_V0(1) } }, 11274 11274 { /*src1 */ { FP64_INF(1), FP64_RAND_V0(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, 11275 11275 { /* => */ { FP64_INF(0), FP64_RAND_V0(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, 11276 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ,11277 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ,11276 /*mxcsr:in */ X86_MXCSR_FZ, 11277 /*128:out */ X86_MXCSR_FZ, 11278 11278 /*256:out */ -1 }, 11279 11279 { { /*src2 */ { FP64_INF(0), FP64_RAND_V0(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } }, 11280 11280 { /*src1 */ { FP64_NORM_V0(0), FP64_RAND_V1(1), FP64_RAND_V3(1), FP64_RAND_V1(1) } }, 11281 11281 { /* => */ { FP64_INF(0), FP64_RAND_V1(1), FP64_RAND_V3(1), FP64_RAND_V1(1) } }, 11282 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,11283 /*128:out */ X86_MXCSR_XCPT_MASK,11282 /*mxcsr:in */ 0, 11283 /*128:out */ 0, 11284 11284 /*256:out */ -1 }, 11285 11285 { { /*src2 */ { FP64_INF(0), FP64_INF(0), FP64_SNAN(1), FP64_INF(1) } }, 11286 11286 { /*src1 */ { FP64_NORM_V3(0), FP64_INF(1), FP64_QNAN(1), FP64_SNAN(1) } }, 11287 11287 { /* => */ { FP64_INF(0), FP64_INF(1), FP64_QNAN(1), FP64_SNAN(1) } }, 11288 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,11289 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,11288 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 11289 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 11290 11290 /*256:out */ -1 }, 11291 11291 { { /*src2 */ { FP64_NORM_V2(0), FP64_RAND_V3(1), FP64_QNAN(1), FP64_SNAN(1) } }, 11292 11292 { /*src1 */ { FP64_INF(1), FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V1(1) } }, 11293 11293 { /* => */ { FP64_NORM_V2(0), FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V1(1) } }, 11294 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,11295 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,11294 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 11295 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 11296 11296 /*256:out */ -1 }, 11297 11297 { { /*src2 */ { FP64_NORM_V2(0), FP64_SNAN(0), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, 11298 11298 { /*src1 */ { FP64_INF(0), FP64_RAND_V2(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, 11299 11299 { /* => */ { FP64_INF(0), FP64_RAND_V2(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, 11300 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,11301 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,11300 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 11301 /*128:out */ X86_MXCSR_RC_ZERO, 11302 11302 /*256:out */ -1 }, 11303 11303 /* … … 11307 11307 { /*src1 */ { FP64_NORM_MAX(0), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V2(1) } }, 11308 11308 { /* => */ { FP64_NORM_MAX(0), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V2(1) } }, 11309 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,11310 /*128:out */ X86_MXCSR_XCPT_MASK,11309 /*mxcsr:in */ 0, 11310 /*128:out */ 0, 11311 11311 /*256:out */ -1 }, 11312 11312 { { /*src2 */ { FP64_NORM_MIN(0), FP64_RAND_V3(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } }, 11313 11313 { /*src1 */ { FP64_NORM_MIN(0), FP64_RAND_V2(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } }, 11314 11314 { /* => */ { FP64_NORM_MIN(0), FP64_RAND_V2(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } }, 11315 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,11316 /*128:out */ X86_MXCSR_XCPT_MASK,11315 /*mxcsr:in */ 0, 11316 /*128:out */ 0, 11317 11317 /*256:out */ -1 }, 11318 11318 { { /*src2 */ { FP64_NORM_MIN(0), FP64_RAND_V3(1), FP64_RAND_V0(1), FP64_RAND_V3(0) } }, 11319 11319 { /*src1 */ { FP64_NORM_MAX(0), FP64_RAND_V1(0), FP64_RAND_V3(0), FP64_RAND_V1(0) } }, 11320 11320 { /* => */ { FP64_NORM_MAX(0), FP64_RAND_V1(0), FP64_RAND_V3(0), FP64_RAND_V1(0) } }, 11321 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,11322 /*128:out */ X86_MXCSR_XCPT_MASK,11321 /*mxcsr:in */ 0, 11322 /*128:out */ 0, 11323 11323 /*256:out */ -1 }, 11324 11324 { { /*src2 */ { FP64_NORM_MAX(0), FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V3(0) } }, 11325 11325 { /*src1 */ { FP64_NORM_MAX(0), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V1(1) } }, 11326 11326 { /* => */ { FP64_NORM_MAX(0), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V1(1) } }, 11327 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,11328 /*128:out */ X86_MXCSR_XCPT_MASK,11327 /*mxcsr:in */ 0, 11328 /*128:out */ 0, 11329 11329 /*256:out */ -1 }, 11330 11330 { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V3(0) } }, 11331 11331 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_RAND_V1(0), FP64_RAND_V1(0), FP64_RAND_V3(1) } }, 11332 11332 { /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_RAND_V1(0), FP64_RAND_V1(0), FP64_RAND_V3(1) } }, 11333 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,11334 /*128:out */ X86_MXCSR_XCPT_MASK,11333 /*mxcsr:in */ 0, 11334 /*128:out */ 0, 11335 11335 /*256:out */ -1 }, 11336 11336 { { /*src2 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, 11337 11337 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_RAND_V1(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } }, 11338 11338 { /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_RAND_V1(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } }, 11339 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,11340 /*128:out */ X86_MXCSR_XCPT_MASK,11339 /*mxcsr:in */ 0, 11340 /*128:out */ 0, 11341 11341 /*256:out */ -1 }, 11342 11342 { { /*src2 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_INF(0), FP64_QNAN(1), FP64_QNAN(0) } }, 11343 11343 { /*src1 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } }, 11344 11344 { /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } }, 11345 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,11346 /*128:out */ X86_MXCSR_XCPT_MASK,11345 /*mxcsr:in */ 0, 11346 /*128:out */ 0, 11347 11347 /*256:out */ -1 }, 11348 11348 { { /*src2 */ { FP64_V(0, 0, 0x409)/*1024*/, FP64_RAND_V1(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } }, 11349 11349 { /*src1 */ { FP64_V(0, 0, 0x408)/* 512*/, FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V3(1) } }, 11350 11350 { /* => */ { FP64_V(0, 0, 0x409)/*1024*/, FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V3(1) } }, 11351 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,11352 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,11351 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 11352 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 11353 11353 /*256:out */ -1 }, 11354 11354 { { /*src2 */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_RAND_V2(1), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, 11355 11355 { /*src1 */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_RAND_V0(0), FP64_RAND_V2(0), FP64_RAND_V0(0) } }, 11356 11356 { /* => */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_RAND_V0(0), FP64_RAND_V2(0), FP64_RAND_V0(0) } }, 11357 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,11358 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,11357 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 11358 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 11359 11359 /*256:out */ -1 }, 11360 11360 { { /*src2 */ { FP64_NORM_MAX(0), FP64_RAND_V0(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } }, 11361 11361 { /*src1 */ { FP64_NORM_V1(0), FP64_RAND_V0(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, 11362 11362 { /* => */ { FP64_NORM_MAX(0), FP64_RAND_V0(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, 11363 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,11364 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,11363 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 11364 /*128:out */ X86_MXCSR_RC_DOWN, 11365 11365 /*256:out */ -1 }, 11366 11366 { { /*src2 */ { FP64_V(0, 0xc000000000000, 0x3ff)/*1.75*/, FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V3(0) } }, 11367 11367 { /*src1 */ { FP64_V(0, 0, 0x3fd)/*0.25*/, FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V1(0) } }, 11368 11368 { /* => */ { FP64_V(0, 0xc000000000000, 0x3ff)/*1.75*/, FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V1(0) } }, 11369 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,11370 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,11369 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 11370 /*128:out */ X86_MXCSR_RC_ZERO, 11371 11371 /*256:out */ -1 }, 11372 11372 { { /*src2 */ { FP64_V(1, 0, 0x3fd)/*-0.25*/, FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V3(0) } }, 11373 11373 { /*src1 */ { FP64_V(1, 0, 0x3fe)/*-0.50*/, FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V1(1) } }, 11374 11374 { /* => */ { FP64_V(1, 0, 0x3fd)/*-0.25*/, FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V1(1) } }, 11375 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,11376 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,11375 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 11376 /*128:out */ X86_MXCSR_RC_ZERO, 11377 11377 /*256:out */ -1 }, 11378 11378 { { /*src2 */ { FP64_V(0, 0x26580b4c7e6b7, 0x41d)/*1234567891.1234567*/, FP64_RAND_V2(1), FP64_RAND_V3(1), FP64_RAND_V3(1) } }, 11379 11379 { /*src1 */ { FP64_V(0, 0x26580b4c7e6bc, 0x41d)/*1234567891.1234580*/, FP64_RAND_V3(0), FP64_RAND_V1(0), FP64_RAND_V0(1) } }, 11380 11380 { /* => */ { FP64_V(0, 0x26580b4c7e6bc, 0x41d)/*1234567891.1234580*/, FP64_RAND_V3(0), FP64_RAND_V1(0), FP64_RAND_V0(1) } }, 11381 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,11382 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,11381 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 11382 /*128:out */ X86_MXCSR_RC_ZERO, 11383 11383 /*256:out */ -1 }, 11384 11384 { { /*src2 */ { FP64_V(0, 0xf9b0207d06184, 0x3fb)/*0.1234589833333129*/, FP64_RAND_V3(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } }, 11385 11385 { /*src1 */ { FP64_V(0, 0xf9b0207d0617d, 0x3fb)/*0.1234589833333128*/, FP64_RAND_V1(1), FP64_RAND_V0(0), FP64_RAND_V0(1) } }, 11386 11386 { /* => */ { FP64_V(0, 0xf9b0207d06184, 0x3fb)/*0.1234589833333129*/, FP64_RAND_V1(1), FP64_RAND_V0(0), FP64_RAND_V0(1) } }, 11387 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,11388 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,11387 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 11388 /*128:out */ X86_MXCSR_RC_ZERO, 11389 11389 /*256:out */ -1 }, 11390 11390 { { /*src2 */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/* 121098765432102.75*/, FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } }, 11391 11391 { /*src1 */ { FP64_V(1, 0xbcd80e0108cc0, 0x42e)/*-244555555308646.00*/, FP64_RAND_V3(0), FP64_RAND_V3(1), FP64_RAND_V0(1) } }, 11392 11392 { /* => */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/* 121098765432102.75*/, FP64_RAND_V3(0), FP64_RAND_V3(1), FP64_RAND_V0(1) } }, 11393 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,11394 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,11393 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 11394 /*128:out */ X86_MXCSR_RC_ZERO, 11395 11395 /*256:out */ -1 }, 11396 11396 { { /*src2 */ { FP64_V(0, 0xcf0033a34f337, 0x432)/*4072598000007579.5*/, FP64_RAND_V3(1), FP64_RAND_V2(1), FP64_RAND_V1(1) } }, 11397 11397 { /*src1 */ { FP64_V(0, 0xd6eca42000000, 0x419)/* 123450000.5*/, FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, 11398 11398 { /* => */ { FP64_V(0, 0xcf0033a34f337, 0x432)/*4072598000007579.5*/, FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, 11399 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,11400 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,11399 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 11400 /*128:out */ X86_MXCSR_RC_ZERO, 11401 11401 /*256:out */ -1 }, 11402 11402 { { /*src2 */ { FP64_V(1, 0xbcd80e0108cc0, 0x42e)/*-244555555308646.00*/, FP64_INF(1), FP64_SNAN(1), FP64_INF(1) } }, 11403 11403 { /*src1 */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/* 121098765432102.75*/, FP64_INF(1), FP64_QNAN(0), FP64_SNAN(0) } }, 11404 11404 { /* => */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/* 121098765432102.75*/, FP64_INF(1), FP64_QNAN(0), FP64_SNAN(0) } }, 11405 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,11406 /*128:out */ X86_MXCSR_XCPT_MASK,11405 /*mxcsr:in */ 0, 11406 /*128:out */ 0, 11407 11407 /*256:out */ -1 }, 11408 11408 { { /*src2 */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/* 244555555308646.00*/, FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, 11409 11409 { /*src1 */ { FP64_V(1, 0xb88e0395d49b0, 0x42d)/*-121098765432102.75*/, FP64_RAND_V0(0), FP64_RAND_V0(0), FP64_RAND_V2(1) } }, 11410 11410 { /* => */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/* 244555555308646.00*/, FP64_RAND_V0(0), FP64_RAND_V0(0), FP64_RAND_V2(1) } }, 11411 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,11412 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,11411 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 11412 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 11413 11413 /*256:out */ -1 }, 11414 11414 { { /*src2 */ { FP64_V(1, 0xcf0033a34f337, 0x432)/*-4072598000007579.5*/, FP64_RAND_V1(0), FP64_RAND_V2(0), FP64_RAND_V1(0) } }, 11415 11415 { /*src1 */ { FP64_V(0, 0xd6eca42000000, 0x419)/* 123450000.5*/, FP64_RAND_V2(0), FP64_RAND_V2(1), FP64_RAND_V3(0) } }, 11416 11416 { /* => */ { FP64_V(0, 0xd6eca42000000, 0x419)/* 123450000.5*/, FP64_RAND_V2(0), FP64_RAND_V2(1), FP64_RAND_V3(0) } }, 11417 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,11418 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,11417 /*mxcsr:in */ X86_MXCSR_RC_UP, 11418 /*128:out */ X86_MXCSR_RC_UP, 11419 11419 /*256:out */ -1 }, 11420 11420 /** @todo More Normals. */ … … 11431 11431 { /*src1 */ { FP64_DENORM_MAX(0), FP64_RAND_V2(0), FP64_RAND_V3(1), FP64_RAND_V2(0) } }, 11432 11432 { /* => */ { FP64_DENORM_MAX(0), FP64_RAND_V2(0), FP64_RAND_V3(1), FP64_RAND_V2(0) } }, 11433 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,11434 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE,11433 /*mxcsr:in */ 0, 11434 /*128:out */ X86_MXCSR_DE, 11435 11435 /*256:out */ -1 }, 11436 11436 { { /*src2 */ { FP64_DENORM_MIN(0), FP64_INF(1), FP64_SNAN(0), FP64_INF(1) } }, 11437 11437 { /*src1 */ { FP64_DENORM_MAX(0), FP64_INF(0), FP64_QNAN(1), FP64_SNAN(1) } }, 11438 11438 { /* => */ { FP64_0(0), FP64_INF(0), FP64_QNAN(1), FP64_SNAN(1) } }, 11439 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,11440 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,11439 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 11440 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 11441 11441 /*256:out */ -1 }, 11442 11442 { { /*src2 */ { FP64_DENORM_MAX(0), FP64_RAND_V2(1), FP64_RAND_V0(1), FP64_RAND_V3(0) } }, 11443 11443 { /*src1 */ { FP64_DENORM_MAX(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, 11444 11444 { /* => */ { FP64_DENORM_MAX(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, 11445 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,11446 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE,11445 /*mxcsr:in */ 0, 11446 /*128:out */ X86_MXCSR_DE, 11447 11447 /*256:out */ -1 }, 11448 11448 { { /*src2 */ { FP64_DENORM_MAX(0), FP64_RAND_V1(1), FP64_RAND_V2(1), FP64_RAND_V2(0) } }, 11449 11449 { /*src1 */ { FP64_DENORM_MAX(1), FP64_RAND_V0(0), FP64_RAND_V3(0), FP64_RAND_V0(0) } }, 11450 11450 { /* => */ { FP64_DENORM_MAX(0), FP64_RAND_V0(0), FP64_RAND_V3(0), FP64_RAND_V0(0) } }, 11451 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,11452 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE,11451 /*mxcsr:in */ 0, 11452 /*128:out */ X86_MXCSR_DE, 11453 11453 /*256:out */ -1 }, 11454 11454 { { /*src2 */ { FP64_DENORM_MAX(1), FP64_RAND_V3(1), FP64_RAND_V0(0), FP64_RAND_V3(1) } }, 11455 11455 { /*src1 */ { FP64_DENORM_MAX(0), FP64_RAND_V2(1), FP64_RAND_V3(1), FP64_RAND_V2(1) } }, 11456 11456 { /* => */ { FP64_DENORM_MAX(0), FP64_RAND_V2(1), FP64_RAND_V3(1), FP64_RAND_V2(1) } }, 11457 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,11458 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE,11457 /*mxcsr:in */ 0, 11458 /*128:out */ X86_MXCSR_DE, 11459 11459 /*256:out */ -1 }, 11460 11460 { { /*src2 */ { FP64_DENORM_MIN(1), FP64_RAND_V0(1), FP64_RAND_V3(1), FP64_RAND_V2(1) } }, 11461 11461 { /*src1 */ { FP64_DENORM_MIN(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, 11462 11462 { /* => */ { FP64_DENORM_MIN(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, 11463 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,11464 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE,11463 /*mxcsr:in */ 0, 11464 /*128:out */ X86_MXCSR_DE, 11465 11465 /*256:out */ -1 }, 11466 11466 { { /*src2 */ { FP64_DENORM_MIN(1), FP64_INF(0), FP64_QNAN(1), FP64_SNAN(1) } }, 11467 11467 { /*src1 */ { FP64_DENORM_MIN(1), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } }, 11468 11468 { /* => */ { FP64_DENORM_MIN(1), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } }, 11469 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,11470 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE,11469 /*mxcsr:in */ 0, 11470 /*128:out */ X86_MXCSR_DE, 11471 11471 /*256:out */ -1 }, 11472 11472 { { /*src2 */ { FP64_DENORM_MIN(1), FP64_SNAN(1), FP64_SNAN(0), FP64_QNAN(0) } }, 11473 11473 { /*src1 */ { FP64_DENORM_MIN(1), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } }, 11474 11474 { /* => */ { FP64_0(1), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } }, 11475 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,11476 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,11475 /*mxcsr:in */ X86_MXCSR_DAZ, 11476 /*128:out */ X86_MXCSR_DAZ, 11477 11477 /*256:out */ -1 }, 11478 11478 { { /*src2 */ { FP64_DENORM_MIN(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, 11479 11479 { /*src1 */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(0) } }, 11480 11480 { /* => */ { FP64_DENORM_MIN(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(0) } }, 11481 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,11482 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE,11481 /*mxcsr:in */ 0, 11482 /*128:out */ X86_MXCSR_DE, 11483 11483 /*256:out */ -1 }, 11484 11484 /** @todo More Denormals. */ … … 11542 11542 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 11543 11543 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 11544 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,11545 /*128:out */ X86_MXCSR_XCPT_MASK,11546 /*256:out */ X86_MXCSR_XCPT_MASK},11544 /*mxcsr:in */ 0, 11545 /*128:out */ 0, 11546 /*256:out */ 0 }, 11547 11547 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 11548 11548 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 11549 11549 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 11550 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,11551 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,11552 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO },11550 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 11551 /*128:out */ X86_MXCSR_RC_ZERO, 11552 /*256:out */ X86_MXCSR_RC_ZERO }, 11553 11553 { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 11554 11554 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 11555 11555 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 11556 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,11557 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,11558 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },11556 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 11557 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 11558 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO }, 11559 11559 { { /*src2 */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1) } }, 11560 11560 { /*src1 */ { FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0) } }, 11561 11561 { /* => */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1) } }, 11562 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,11563 /*128:out */ X86_MXCSR_XCPT_MASK,11564 /*256:out */ X86_MXCSR_XCPT_MASK},11562 /*mxcsr:in */ 0, 11563 /*128:out */ 0, 11564 /*256:out */ 0 }, 11565 11565 { { /*src2 */ { FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0) } }, 11566 11566 { /*src1 */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0) } }, … … 11572 11572 { /*src1 */ { FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0) } }, 11573 11573 { /* => */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1) } }, 11574 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,11575 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,11576 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN },11574 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 11575 /*128:out */ X86_MXCSR_RC_DOWN, 11576 /*256:out */ X86_MXCSR_RC_DOWN }, 11577 11577 { { /*src2 */ { FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0) } }, 11578 11578 { /*src1 */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0) } }, 11579 11579 { /* => */ { FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0) } }, 11580 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,11581 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,11582 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP },11580 /*mxcsr:in */ X86_MXCSR_RC_UP, 11581 /*128:out */ X86_MXCSR_RC_UP, 11582 /*256:out */ X86_MXCSR_RC_UP }, 11583 11583 { { /*src2 */ { FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0) } }, 11584 11584 { /*src1 */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0) } }, 11585 11585 { /* => */ { FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0) } }, 11586 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,11587 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,11588 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },11586 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 11587 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 11588 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO }, 11589 11589 { { /*src2 */ { FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1) } }, 11590 11590 { /*src1 */ { FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(0) } }, 11591 11591 { /* => */ { FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1) } }, 11592 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,11593 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,11594 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },11592 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 11593 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 11594 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN }, 11595 11595 /* 11596 11596 * Infinity. … … 11599 11599 { /*src1 */ { FP32_0(0), FP32_INF(0), FP32_0(0), FP32_INF(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_INF(1) } }, 11600 11600 { /* => */ { FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(1), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1) } }, 11601 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,11602 /*128:out */ X86_MXCSR_XCPT_MASK,11603 /*256:out */ X86_MXCSR_XCPT_MASK},11601 /*mxcsr:in */ 0, 11602 /*128:out */ 0, 11603 /*256:out */ 0 }, 11604 11604 { { /*src2 */ { FP32_INF(0), FP32_0(0), FP32_INF(0), FP32_0(1), FP32_INF(1), FP32_0(0), FP32_INF(1), FP32_0(0) } }, 11605 11605 { /*src1 */ { FP32_0(0), FP32_INF(1), FP32_0(1), FP32_INF(1), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_INF(1) } }, 11606 11606 { /* => */ { FP32_0(0), FP32_INF(1), FP32_0(1), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1) } }, 11607 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,11608 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,11609 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP },11607 /*mxcsr:in */ X86_MXCSR_RC_UP, 11608 /*128:out */ X86_MXCSR_RC_UP, 11609 /*256:out */ X86_MXCSR_RC_UP }, 11610 11610 { { /*src2 */ { FP32_INF(0), FP32_0(0), FP32_INF(0), FP32_0(1), FP32_INF(1), FP32_0(0), FP32_INF(1), FP32_0(0) } }, 11611 11611 { /*src1 */ { FP32_0(0), FP32_INF(0), FP32_0(1), FP32_INF(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_INF(1) } }, 11612 11612 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1) } }, 11613 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,11614 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,11615 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN },11613 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 11614 /*128:out */ X86_MXCSR_RC_DOWN, 11615 /*256:out */ X86_MXCSR_RC_DOWN }, 11616 11616 { { /*src2 */ { FP32_INF(0), FP32_0(0), FP32_INF(0), FP32_0(1), FP32_INF(1), FP32_0(0), FP32_INF(1), FP32_0(0) } }, 11617 11617 { /*src1 */ { FP32_0(0), FP32_INF(0), FP32_0(1), FP32_INF(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_INF(1) } }, 11618 11618 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1) } }, 11619 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,11620 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,11621 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO },11619 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 11620 /*128:out */ X86_MXCSR_RC_ZERO, 11621 /*256:out */ X86_MXCSR_RC_ZERO }, 11622 11622 { { /*src2 */ { FP32_INF(0), FP32_0(0), FP32_INF(0), FP32_0(1), FP32_INF(1), FP32_0(0), FP32_INF(1), FP32_0(0) } }, 11623 11623 { /*src1 */ { FP32_0(0), FP32_INF(0), FP32_0(1), FP32_INF(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_INF(1) } }, 11624 11624 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1) } }, 11625 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,11626 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,11627 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },11625 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 11626 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 11627 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO }, 11628 11628 { { /*src2 */ { FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(0) } }, 11629 11629 { /*src1 */ { FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_INF(0) } }, … … 11635 11635 { /*src1 */ { FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_INF(0) } }, 11636 11636 { /* => */ { FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(0) } }, 11637 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,11638 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,11639 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO },11637 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 11638 /*128:out */ X86_MXCSR_RC_ZERO, 11639 /*256:out */ X86_MXCSR_RC_ZERO }, 11640 11640 { { /*src2 */ { FP32_INF(0), FP32_NORM_V1(0), FP32_INF(1), FP32_NORM_V3(1), FP32_INF(1), FP32_NORM_V5(0), FP32_INF(1), FP32_NORM_V7(0) } }, 11641 11641 { /*src1 */ { FP32_NORM_V0(0), FP32_INF(1), FP32_NORM_V2(0), FP32_INF(1), FP32_NORM_V4(1), FP32_INF(1), FP32_NORM_V6(0), FP32_INF(0) } }, 11642 11642 { /* => */ { FP32_NORM_V0(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_NORM_V7(0) } }, 11643 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,11644 /*128:out */ X86_MXCSR_XCPT_MASK,11645 /*256:out */ X86_MXCSR_XCPT_MASK},11643 /*mxcsr:in */ 0, 11644 /*128:out */ 0, 11645 /*256:out */ 0 }, 11646 11646 { { /*src2 */ { FP32_INF(0), FP32_NORM_V1(0), FP32_INF(1), FP32_NORM_V3(1), FP32_INF(0), FP32_NORM_V5(0), FP32_INF(1), FP32_NORM_V7(0) } }, 11647 11647 { /*src1 */ { FP32_NORM_V0(0), FP32_INF(1), FP32_NORM_V2(0), FP32_INF(0), FP32_NORM_V4(1), FP32_INF(1), FP32_NORM_V6(0), FP32_INF(0) } }, 11648 11648 { /* => */ { FP32_NORM_V0(0), FP32_INF(1), FP32_INF(1), FP32_NORM_V3(1), FP32_NORM_V4(1), FP32_INF(1), FP32_INF(1), FP32_NORM_V7(0) } }, 11649 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,11650 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,11651 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },11649 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 11650 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 11651 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN }, 11652 11652 { { /*src2 */ { FP32_NORM_V7(0), FP32_INF(0), FP32_NORM_V5(0), FP32_INF(0), FP32_NORM_V3(0), FP32_INF(0), FP32_NORM_V1(0), FP32_INF(0) } }, 11653 11653 { /*src1 */ { FP32_INF(1), FP32_NORM_V6(1), FP32_INF(0), FP32_NORM_V4(0), FP32_INF(0), FP32_NORM_V2(1), FP32_INF(1), FP32_NORM_V0(1) } }, 11654 11654 { /* => */ { FP32_INF(1), FP32_NORM_V6(1), FP32_NORM_V5(0), FP32_NORM_V4(0), FP32_NORM_V3(0), FP32_NORM_V2(1), FP32_INF(1), FP32_NORM_V0(1) } }, 11655 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,11656 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,11657 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP },11655 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 11656 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 11657 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP }, 11658 11658 { { /*src2 */ { FP32_NORM_V7(0), FP32_INF(0), FP32_NORM_V5(1), FP32_INF(0), FP32_NORM_V3(1), FP32_INF(0), FP32_NORM_V1(1), FP32_INF(0) } }, 11659 11659 { /*src1 */ { FP32_INF(0), FP32_NORM_V6(1), FP32_INF(0), FP32_NORM_V4(1), FP32_INF(0), FP32_NORM_V2(1), FP32_INF(0), FP32_NORM_V0(1) } }, 11660 11660 { /* => */ { FP32_NORM_V7(0), FP32_NORM_V6(1), FP32_NORM_V5(1), FP32_NORM_V4(1), FP32_NORM_V3(1), FP32_NORM_V2(1), FP32_NORM_V1(1), FP32_NORM_V0(1) } }, 11661 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,11662 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,11663 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO },11661 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 11662 /*128:out */ X86_MXCSR_RC_ZERO, 11663 /*256:out */ X86_MXCSR_RC_ZERO }, 11664 11664 /* 11665 11665 * Normals. … … 11668 11668 { /*src1 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_0(1), FP32_NORM_MAX(0) } }, 11669 11669 { /* => */ { FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(1) } }, 11670 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,11671 /*128:out */ X86_MXCSR_XCPT_MASK,11672 /*256:out */ X86_MXCSR_XCPT_MASK},11670 /*mxcsr:in */ 0, 11671 /*128:out */ 0, 11672 /*256:out */ 0 }, 11673 11673 { { /*src2 */ { FP32_NORM_MIN(0), FP32_0(0), FP32_NORM_MIN(0), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_0(1), FP32_NORM_MIN(1), FP32_NORM_MIN(1) } }, 11674 11674 { /*src1 */ { FP32_NORM_MIN(0), FP32_NORM_MIN(0), FP32_0(0), FP32_0(0), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_0(1), FP32_NORM_MIN(0) } }, 11675 11675 { /* => */ { FP32_NORM_MIN(0), FP32_0(0), FP32_0(0), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MIN(1) } }, 11676 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,11677 /*128:out */ X86_MXCSR_XCPT_MASK,11678 /*256:out */ X86_MXCSR_XCPT_MASK},11676 /*mxcsr:in */ 0, 11677 /*128:out */ 0, 11678 /*256:out */ 0 }, 11679 11679 { { /*src2 */ { FP32_NORM_MIN(0), FP32_NORM_MIN(0), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1) } }, 11680 11680 { /*src1 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MIN(0), FP32_NORM_MIN(1), FP32_NORM_MIN(0), FP32_NORM_MIN(1) } }, 11681 11681 { /* => */ { FP32_NORM_MIN(0), FP32_NORM_MAX(1), FP32_NORM_MIN(1), FP32_NORM_MAX(1), FP32_NORM_MIN(0), FP32_NORM_MIN(1), FP32_NORM_MAX(1), FP32_NORM_MAX(1) } }, 11682 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,11683 /*128:out */ X86_MXCSR_XCPT_MASK,11684 /*256:out */ X86_MXCSR_XCPT_MASK},11682 /*mxcsr:in */ 0, 11683 /*128:out */ 0, 11684 /*256:out */ 0 }, 11685 11685 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(1) } }, 11686 11686 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1) } }, 11687 11687 { /* => */ { FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(1) } }, 11688 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,11689 /*128:out */ X86_MXCSR_XCPT_MASK,11690 /*256:out */ X86_MXCSR_XCPT_MASK},11688 /*mxcsr:in */ 0, 11689 /*128:out */ 0, 11690 /*256:out */ 0 }, 11691 11691 { { /*src2 */ { FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_V(0, 0, 0x7d)/*0.25*/, FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_V(0, 0, 0x7d)/*0.25*/, FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_V(0, 0, 0x7d)/* 0.25*/, FP32_V(0, 0x600000, 0x7f)/*1.75*/, FP32_V(1, 0, 0x7d)/*-0.25*/ } }, 11692 11692 { /*src1 */ { FP32_V(1, 0, 0x7d)/*-0.25*/, FP32_V(0, 0, 0x7e)/*0.50*/, FP32_V(1, 0, 0x7d)/*-0.25*/, FP32_V(0, 0, 0x7e)/*0.50*/, FP32_V(1, 0x600000, 0x7f)/*-1.75*/, FP32_V(1, 0, 0x7e)/*-0.50*/, FP32_V(1, 0, 0x7d)/*0.25*/, FP32_V(1, 0, 0x7e)/*-0.50*/ } }, 11693 11693 { /* => */ { FP32_V(1, 0, 0x7d)/*-0.25*/, FP32_V(0, 0, 0x7d)/*0.25*/, FP32_V(1, 0, 0x7d)/*-0.25*/, FP32_V(0, 0, 0x7d)/*0.25*/, FP32_V(1, 0x600000, 0x7f)/*-1.75*/, FP32_V(1, 0, 0x7e)/*-0.50*/, FP32_V(1, 0, 0x7d)/*0.25*/, FP32_V(1, 0, 0x7e)/*-0.50*/ } }, 11694 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,11695 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,11696 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },11694 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 11695 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 11696 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN }, 11697 11697 { { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_V1(0), FP32_NORM_V2(1), FP32_NORM_V3(1), FP32_NORM_V5(0), FP32_0(1), FP32_NORM_V5(1), FP32_0(0) } }, 11698 11698 { /*src1 */ { FP32_NORM_V1(0), FP32_NORM_V1(1), FP32_NORM_V2(0), FP32_NORM_V3(1), FP32_0(1), FP32_NORM_V6(0), FP32_0(1), FP32_NORM_V7(1) } }, 11699 11699 { /* => */ { FP32_NORM_V1(0), FP32_NORM_V1(1), FP32_NORM_V2(1), FP32_NORM_V3(1), FP32_0(1), FP32_0(1), FP32_NORM_V5(1), FP32_NORM_V7(1) } }, 11700 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,11701 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,11702 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN },11700 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 11701 /*128:out */ X86_MXCSR_RC_DOWN, 11702 /*256:out */ X86_MXCSR_RC_DOWN }, 11703 11703 { { /*src2 */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_V(0, 0x600000, 0x81)/* 7*/, FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_V(0, 0x5c0000, 0x84)/* 55*/, FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_V(1, 0x534000, 0x86)/*-211.25*/, FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_1(1) } }, 11704 11704 { /*src1 */ { FP32_V(0, 0x1ea980, 0x8f)/* 81235*/, FP32_V(0, 0x5c0000, 0x84)/*55*/, FP32_V(0, 0x7c9000, 0x88)/* 1010.25*/, FP32_V(1, 0x600000, 0x81)/* -7*/, FP32_V(0, 0x253468, 0x93)/*1353357.00*/, FP32_1(1), FP32_V(0, 0x712060, 0x92)/* 987654*/, FP32_1(0) } }, 11705 11705 { /* => */ { FP32_V(0, 0x1ea980, 0x8f)/* 81235*/, FP32_V(0, 0x600000, 0x81)/* 7*/, FP32_V(0, 0x7c9000, 0x88)/* 1010.25*/, FP32_V(1, 0x600000, 0x81)/* -7*/, FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_V(1, 0x534000, 0x86)/*-211.25*/, FP32_V(0, 0x712060, 0x92)/* 987654*/, FP32_1(1) } }, 11706 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,11707 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,11708 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO },11706 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 11707 /*128:out */ X86_MXCSR_RC_ZERO, 11708 /*256:out */ X86_MXCSR_RC_ZERO }, 11709 11709 { { /*src2 */ { FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_V(0, 0x3ce348, 0x90)/*193421.125*/, FP32_V(0, 0x6423f2, 0x92)/*934463.125*/, FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0x16b43a, 0x93)/*1234567.25*/, FP32_V(0, 0x792318, 0x91)/*510232.75*/, FP32_V(0, 0x600000, 0x7e)/* 0.875*/ } }, 11710 11710 { /*src1 */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_V(0, 0x430ebc, 0x91)/*399477.875*/, FP32_V(0, 0x52e0b4, 0x92)/*863755.250*/, FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MAX(1), FP32_V(0, 0x00c6d3, 0x94)/*2109876.75*/, FP32_V(1, 0x316740, 0x8e)/*-45415.25*/, FP32_V(1, 0, 0x7d)/*-0.250*/ } }, 11711 11711 { /* => */ { FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_V(0, 0x3ce348, 0x90)/*193421.125*/, FP32_V(0, 0x52e0b4, 0x92)/*863755.250*/, FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MAX(1), FP32_V(0, 0x16b43a, 0x93)/*1234567.25*/, FP32_V(1, 0x316740, 0x8e)/*-45415.25*/, FP32_V(1, 0, 0x7d)/*-0.250*/ } }, 11712 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,11713 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,11714 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN },11712 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 11713 /*128:out */ X86_MXCSR_RC_DOWN, 11714 /*256:out */ X86_MXCSR_RC_DOWN }, 11715 11715 { { /*src2 */ { FP32_V(0, 0x490fda, 0x80)/*3.1415926*/, FP32_V(0, 0x620b2e, 0x92)/*925874.9*/, FP32_V(0, 0x5dd520, 0x8e)/* 56789.125*/, FP32_V(1, 0x40e6b6, 0x8c)/*-12345.678*/, FP32_V(1, 0x490fda, 0x80)/*-3.1415926*/, FP32_V(1, 0x620b2e, 0x92)/*-925874.8*/, FP32_V(0, 0x5dd520, 0x8e)/*56789.125*/, FP32_V(0, 0x40e6b6, 0x8c)/*12345.678*/ } }, 11716 11716 { /*src1 */ { FP32_V(0, 0x490fdb, 0x80)/*3.1415927*/, FP32_V(0, 0x620b2d, 0x92)/*925874.8*/, FP32_V(1, 0x5dd521, 0x8e)/*-56789.127*/, FP32_V(1, 0x40e6b7, 0x8c)/*-12345.679*/, FP32_V(1, 0x490fdb, 0x80)/*-3.1415927*/, FP32_V(0, 0x620b2d, 0x92)/* 925874.9*/, FP32_V(0, 0x5dd521, 0x8e)/*56789.127*/, FP32_V(0, 0x40e6b7, 0x8c)/*12345.679*/ } }, 11717 11717 { /* => */ { FP32_V(0, 0x490fda, 0x80)/*3.1415926*/, FP32_V(0, 0x620b2d, 0x92)/*925874.8*/, FP32_V(1, 0x5dd521, 0x8e)/*-56789.127*/, FP32_V(1, 0x40e6b7, 0x8c)/*-12345.679*/, FP32_V(1, 0x490fdb, 0x80)/*-3.1415927*/, FP32_V(1, 0x620b2e, 0x92)/*-925874.8*/, FP32_V(0, 0x5dd520, 0x8e)/*56789.125*/, FP32_V(0, 0x40e6b6, 0x8c)/*12345.678*/ } }, 11718 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,11719 /*128:out */ X86_MXCSR_XCPT_MASK,11720 /*256:out */ X86_MXCSR_XCPT_MASK},11718 /*mxcsr:in */ 0, 11719 /*128:out */ 0, 11720 /*256:out */ 0 }, 11721 11721 /** @todo More Normals. */ 11722 11722 /* … … 11732 11732 { /*src1 */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0) } }, 11733 11733 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 11734 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,11735 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE,11736 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE },11734 /*mxcsr:in */ 0, 11735 /*128:out */ X86_MXCSR_DE, 11736 /*256:out */ X86_MXCSR_DE }, 11737 11737 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } }, 11738 11738 { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0) } }, 11739 11739 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 11740 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,11741 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,11742 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP },11740 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 11741 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 11742 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP }, 11743 11743 { { /*src2 */ { FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 11744 11744 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, … … 11750 11750 { /*src1 */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 11751 11751 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } }, 11752 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,11753 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,11754 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ },11752 /*mxcsr:in */ X86_MXCSR_DAZ, 11753 /*128:out */ X86_MXCSR_DAZ, 11754 /*256:out */ X86_MXCSR_DAZ }, 11755 11755 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } }, 11756 11756 { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0) } }, 11757 11757 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 11758 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,11759 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,11760 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP },11758 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 11759 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 11760 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP }, 11761 11761 /** @todo More Denormals. */ 11762 11762 /*35*/ FP32_TABLE_D9_PS_INVALIDS … … 11827 11827 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 11828 11828 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 11829 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,11830 /*128:out */ X86_MXCSR_XCPT_MASK,11831 /*256:out */ X86_MXCSR_XCPT_MASK},11829 /*mxcsr:in */ 0, 11830 /*128:out */ 0, 11831 /*256:out */ 0 }, 11832 11832 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 11833 11833 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 11834 11834 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 11835 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,11836 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,11837 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO },11835 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 11836 /*128:out */ X86_MXCSR_RC_ZERO, 11837 /*256:out */ X86_MXCSR_RC_ZERO }, 11838 11838 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 11839 11839 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 11840 11840 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 11841 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,11842 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,11843 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },11841 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 11842 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 11843 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO }, 11844 11844 { { /*src2 */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } }, 11845 11845 { /*src1 */ { FP64_0(1), FP64_0(0), FP64_0(1), FP64_0(1) } }, 11846 11846 { /* => */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } }, 11847 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,11848 /*128:out */ X86_MXCSR_XCPT_MASK,11849 /*256:out */ X86_MXCSR_XCPT_MASK},11847 /*mxcsr:in */ 0, 11848 /*128:out */ 0, 11849 /*256:out */ 0 }, 11850 11850 { { /*src2 */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_0(0) } }, 11851 11851 { /*src1 */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, … … 11857 11857 { /*src1 */ { FP64_0(1), FP64_0(0), FP64_0(1), FP64_0(1) } }, 11858 11858 { /* => */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } }, 11859 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,11860 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,11861 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN },11859 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 11860 /*128:out */ X86_MXCSR_RC_DOWN, 11861 /*256:out */ X86_MXCSR_RC_DOWN }, 11862 11862 { { /*src2 */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_0(0) } }, 11863 11863 { /*src1 */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, 11864 11864 { /* => */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_0(0) } }, 11865 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,11866 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,11867 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP },11865 /*mxcsr:in */ X86_MXCSR_RC_UP, 11866 /*128:out */ X86_MXCSR_RC_UP, 11867 /*256:out */ X86_MXCSR_RC_UP }, 11868 11868 { { /*src2 */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_0(0) } }, 11869 11869 { /*src1 */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, 11870 11870 { /* => */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_0(0) } }, 11871 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,11872 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,11873 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },11871 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 11872 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 11873 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO }, 11874 11874 { { /*src2 */ { FP64_0(1), FP64_0(1), FP64_0(0), FP64_0(0) } }, 11875 11875 { /*src1 */ { FP64_0(1), FP64_0(1), FP64_0(0), FP64_0(0) } }, 11876 11876 { /* => */ { FP64_0(1), FP64_0(1), FP64_0(0), FP64_0(0) } }, 11877 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,11878 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,11879 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },11877 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 11878 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 11879 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN }, 11880 11880 /* 11881 11881 * Infinity. … … 11884 11884 { /*src1 */ { FP64_0(0), FP64_INF(0), FP64_0(1), FP64_INF(1) } }, 11885 11885 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_INF(1) } }, 11886 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,11887 /*128:out */ X86_MXCSR_XCPT_MASK,11888 /*256:out */ X86_MXCSR_XCPT_MASK},11886 /*mxcsr:in */ 0, 11887 /*128:out */ 0, 11888 /*256:out */ 0 }, 11889 11889 { { /*src2 */ { FP64_INF(0), FP64_0(0), FP64_INF(0), FP64_0(1) } }, 11890 11890 { /*src1 */ { FP64_0(0), FP64_INF(1), FP64_0(1), FP64_INF(1) } }, 11891 11891 { /* => */ { FP64_0(0), FP64_INF(1), FP64_0(1), FP64_INF(1) } }, 11892 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,11893 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,11894 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP },11892 /*mxcsr:in */ X86_MXCSR_RC_UP, 11893 /*128:out */ X86_MXCSR_RC_UP, 11894 /*256:out */ X86_MXCSR_RC_UP }, 11895 11895 { { /*src2 */ { FP64_INF(0), FP64_0(0), FP64_INF(0), FP64_0(1) } }, 11896 11896 { /*src1 */ { FP64_0(0), FP64_INF(1), FP64_0(1), FP64_INF(1) } }, 11897 11897 { /* => */ { FP64_0(0), FP64_INF(1), FP64_0(1), FP64_INF(1) } }, 11898 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,11899 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,11900 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN },11898 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 11899 /*128:out */ X86_MXCSR_RC_DOWN, 11900 /*256:out */ X86_MXCSR_RC_DOWN }, 11901 11901 { { /*src2 */ { FP64_INF(0), FP64_0(0), FP64_INF(0), FP64_0(1) } }, 11902 11902 { /*src1 */ { FP64_0(0), FP64_INF(1), FP64_0(1), FP64_INF(1) } }, 11903 11903 { /* => */ { FP64_0(0), FP64_INF(1), FP64_0(1), FP64_INF(1) } }, 11904 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,11905 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,11906 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO },11904 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 11905 /*128:out */ X86_MXCSR_RC_ZERO, 11906 /*256:out */ X86_MXCSR_RC_ZERO }, 11907 11907 { { /*src2 */ { FP64_INF(0), FP64_0(0), FP64_INF(0), FP64_0(1) } }, 11908 11908 { /*src1 */ { FP64_0(0), FP64_INF(0), FP64_0(1), FP64_INF(1) } }, 11909 11909 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_INF(1) } }, 11910 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,11911 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,11912 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },11910 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 11911 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 11912 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO }, 11913 11913 { { /*src2 */ { FP64_INF(0), FP64_INF(0), FP64_INF(1), FP64_INF(1) } }, 11914 11914 { /*src1 */ { FP64_INF(0), FP64_INF(1), FP64_INF(0), FP64_INF(1) } }, … … 11920 11920 { /*src1 */ { FP64_INF(0), FP64_INF(1), FP64_INF(0), FP64_INF(1) } }, 11921 11921 { /* => */ { FP64_INF(0), FP64_INF(1), FP64_INF(1), FP64_INF(1) } }, 11922 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,11923 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,11924 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO },11922 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 11923 /*128:out */ X86_MXCSR_RC_ZERO, 11924 /*256:out */ X86_MXCSR_RC_ZERO }, 11925 11925 { { /*src2 */ { FP64_INF(0), FP64_NORM_V1(0), FP64_INF(1), FP64_NORM_V3(1) } }, 11926 11926 { /*src1 */ { FP64_NORM_V0(0), FP64_INF(1), FP64_NORM_V2(0), FP64_INF(1) } }, 11927 11927 { /* => */ { FP64_NORM_V0(0), FP64_INF(1), FP64_INF(1), FP64_INF(1) } }, 11928 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,11929 /*128:out */ X86_MXCSR_XCPT_MASK,11930 /*256:out */ X86_MXCSR_XCPT_MASK},11928 /*mxcsr:in */ 0, 11929 /*128:out */ 0, 11930 /*256:out */ 0 }, 11931 11931 { { /*src2 */ { FP64_INF(0), FP64_NORM_V1(0), FP64_INF(1), FP64_NORM_V3(1) } }, 11932 11932 { /*src1 */ { FP64_NORM_V0(0), FP64_INF(1), FP64_NORM_V2(0), FP64_INF(1) } }, 11933 11933 { /* => */ { FP64_NORM_V0(0), FP64_INF(1), FP64_INF(1), FP64_INF(1) } }, 11934 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,11935 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,11936 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },11934 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 11935 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 11936 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN }, 11937 11937 { { /*src2 */ { FP64_INF(0), FP64_NORM_V1(0), FP64_INF(1), FP64_NORM_V3(1) } }, 11938 11938 { /*src1 */ { FP64_NORM_V0(0), FP64_INF(1), FP64_NORM_V2(0), FP64_INF(1) } }, 11939 11939 { /* => */ { FP64_NORM_V0(0), FP64_INF(1), FP64_INF(1), FP64_INF(1) } }, 11940 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,11941 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,11942 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP },11940 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 11941 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 11942 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP }, 11943 11943 { { /*src2 */ { FP64_INF(0), FP64_NORM_V1(0), FP64_INF(1), FP64_NORM_V3(1) } }, 11944 11944 { /*src1 */ { FP64_NORM_V0(0), FP64_INF(1), FP64_NORM_V2(0), FP64_INF(1) } }, 11945 11945 { /* => */ { FP64_NORM_V0(0), FP64_INF(1), FP64_INF(1), FP64_INF(1) } }, 11946 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,11947 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,11948 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO },11946 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 11947 /*128:out */ X86_MXCSR_RC_ZERO, 11948 /*256:out */ X86_MXCSR_RC_ZERO }, 11949 11949 /* 11950 11950 * Normals. … … 11953 11953 { /*src1 */ { FP64_NORM_V3(1), FP64_NORM_V1(0), FP64_NORM_V2(1), FP64_NORM_V1(0) } }, 11954 11954 { /* => */ { FP64_NORM_V3(1), FP64_NORM_V1(1), FP64_NORM_V2(1), FP64_NORM_V1(1) } }, 11955 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,11956 /*128:out */ X86_MXCSR_XCPT_MASK,11957 /*256:out */ X86_MXCSR_XCPT_MASK},11955 /*mxcsr:in */ 0, 11956 /*128:out */ 0, 11957 /*256:out */ 0 }, 11958 11958 { { /*src2 */ { FP64_NORM_V0(0), FP64_0(1), FP64_NORM_V2(0), FP64_0(1) } }, 11959 11959 { /*src1 */ { FP64_0(0), FP64_NORM_V1(1), FP64_0(0), FP64_NORM_V1(0) } }, 11960 11960 { /* => */ { FP64_0(0), FP64_NORM_V1(1), FP64_0(0), FP64_0(1) } }, 11961 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,11962 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,11963 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO },11961 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 11962 /*128:out */ X86_MXCSR_RC_ZERO, 11963 /*256:out */ X86_MXCSR_RC_ZERO }, 11964 11964 { { /*src2 */ { FP64_V(0, 0, 0x409)/*1024*/, FP64_V(0, 0xb800000000000, 0x404)/*55*/, FP64_V(1, 0x8000000000000, 0x409)/*-1536*/, FP64_V(0, 0xf000000000000, 0x404)/* 62*/ } }, 11965 11965 { /*src1 */ { FP64_V(0, 0, 0x408)/* 512*/, FP64_V(0, 0xc000000000000, 0x401)/* 7*/, FP64_1(1), FP64_V(1, 0xf000000000000, 0x404)/*-62*/ } }, 11966 11966 { /* => */ { FP64_V(0, 0, 0x408)/* 512*/, FP64_V(0, 0xc000000000000, 0x401)/* 7*/, FP64_V(1, 0x8000000000000, 0x409)/*-1536*/, FP64_V(1, 0xf000000000000, 0x404)/*-62*/ } }, 11967 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ,11968 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ,11969 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ },11967 /*mxcsr:in */ X86_MXCSR_FZ, 11968 /*128:out */ X86_MXCSR_FZ, 11969 /*256:out */ X86_MXCSR_FZ }, 11970 11970 { { /*src2 */ { FP64_V(0, 0x26580b4800000, 0x41d)/* 1234567890*/, FP64_V(0, 0xd6f3458800000, 0x41c)/*987654321*/, FP64_V(1, 0xd6f3426800000, 0x41c)/*-987654221*/, FP64_V(0, 0xcf0033a34f337, 0x432)/*4072598000007579.5*/ } }, 11971 11971 { /*src1 */ { FP64_V(1, 0x26580b4800000, 0x41d)/*-1234567890*/, FP64_V(0, 0x9000000000000, 0x405)/* 100*/, FP64_1(0), FP64_V(0, 0xd6eca42000000, 0x419)/* 123450000.5*/ } }, 11972 11972 { /* => */ { FP64_V(1, 0x26580b4800000, 0x41d)/*-1234567890*/, FP64_V(0, 0x9000000000000, 0x405)/* 100*/, FP64_V(1, 0xd6f3426800000, 0x41c)/*-987654221*/, FP64_V(0, 0xd6eca42000000, 0x419)/* 123450000.5*/ } }, 11973 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,11974 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,11975 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ },11973 /*mxcsr:in */ X86_MXCSR_DAZ, 11974 /*128:out */ X86_MXCSR_DAZ, 11975 /*256:out */ X86_MXCSR_DAZ }, 11976 11976 { { /*src2 */ { FP64_V(0, 0x26580b4800000, 0x41d)/* 1234567890*/, FP64_V(0, 0xd6f3458800000, 0x41c)/*987654321*/, FP64_V(0, 0xd6f3426800000, 0x41c)/*987654221*/, FP64_V(0, 0xcf0033a34f337, 0x432)/*4072598000007579.5*/ } }, 11977 11977 { /*src1 */ { FP64_V(1, 0x26580b4800000, 0x41d)/*-1234567890*/, FP64_V(0, 0x9000000000000, 0x405)/* -100*/, FP64_1(0), FP64_V(0, 0xd6eca42000000, 0x419)/* 123450000.5*/ } }, … … 11983 11983 { /*src1 */ { FP64_1(0), FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(0), FP64_0(0) } }, 11984 11984 { /* => */ { FP64_1(0), FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(0), FP64_0(0) } }, 11985 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,11986 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,11987 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },11985 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 11986 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 11987 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO }, 11988 11988 { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_0(0), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(1) } }, 11989 11989 { /*src1 */ { FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(1), FP64_0(0), FP64_NORM_SAFE_INT_MIN(0) } }, … … 11995 11995 { /*src1 */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_V(0, 0xb88e0395d49b0, 0x42d)/* 121098765432102.75*/ } }, 11996 11996 { /* => */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_V(1, 0xbcd80e0108cc0, 0x42e)/*-244555555308646.00*/ } }, 11997 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,11998 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,11999 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP },11997 /*mxcsr:in */ X86_MXCSR_RC_UP, 11998 /*128:out */ X86_MXCSR_RC_UP, 11999 /*256:out */ X86_MXCSR_RC_UP }, 12000 12000 { { /*src2 */ { FP64_V(0, 0xc000000000000, 0x3ff)/*1.75*/, FP64_V(0, 0, 0x3fd)/*0.25*/, FP64_V(0, 0x26580b4c7e6b7, 0x41d)/*1234567891.1234567*/, FP64_V(0, 0xf9b0207d06184, 0x3fb)/*0.1234589833333129*/ } }, 12001 12001 { /*src1 */ { FP64_V(0, 0, 0x3fd)/*0.25*/, FP64_V(0, 0, 0x3fe)/*0.50*/, FP64_V(0, 0x26580b4c7e6bc, 0x41d)/*1234567891.1234580*/, FP64_V(0, 0xf9b0207d0617d, 0x3fb)/*0.1234589833333128*/ } }, 12002 12002 { /* => */ { FP64_V(0, 0, 0x3fd)/*0.25*/, FP64_V(0, 0, 0x3fd)/*0.25*/, FP64_V(0, 0x26580b4c7e6b7, 0x41d)/*1234567891.1234567*/, FP64_V(0, 0xf9b0207d0617d, 0x3fb)/*0.1234589833333128*/ } }, 12003 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,12004 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,12005 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },12003 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 12004 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 12005 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN }, 12006 12006 /* 12007 12007 * Denormals. … … 12016 12016 { /*src1 */ { FP64_0(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_0(0) } }, 12017 12017 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 12018 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,12019 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE,12020 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE },12018 /*mxcsr:in */ 0, 12019 /*128:out */ X86_MXCSR_DE, 12020 /*256:out */ X86_MXCSR_DE }, 12021 12021 { { /*src2 */ { FP64_DENORM_MIN(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } }, 12022 12022 { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } }, 12023 12023 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 12024 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,12025 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,12026 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP },12024 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 12025 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 12026 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP }, 12027 12027 { { /*src2 */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_DENORM_MAX(0), FP64_0(0) } }, 12028 12028 { /*src1 */ { FP64_0(0), FP64_DENORM_MAX(0), FP64_0(0), FP64_DENORM_MAX(0) } }, … … 12034 12034 { /*src1 */ { FP64_0(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_0(0) } }, 12035 12035 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(1) } }, 12036 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,12037 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,12038 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ },12036 /*mxcsr:in */ X86_MXCSR_DAZ, 12037 /*128:out */ X86_MXCSR_DAZ, 12038 /*256:out */ X86_MXCSR_DAZ }, 12039 12039 { { /*src2 */ { FP64_DENORM_MIN(0), FP64_DENORM_MIN(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0) } }, 12040 12040 { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } }, 12041 12041 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 12042 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,12043 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,12044 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP },12042 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 12043 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 12044 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP }, 12045 12045 /** @todo Denormals. */ 12046 12046 /* … … 12114 12114 { /*src1 */ { FP32_0(0), FP32_0_x7(0) } }, 12115 12115 { /* => */ { FP32_0(0), FP32_0_x7(0) } }, 12116 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,12117 /*128:out */ X86_MXCSR_XCPT_MASK,12116 /*mxcsr:in */ 0, 12117 /*128:out */ 0, 12118 12118 /*256:out */ -1 }, 12119 12119 { { /*src2 */ { FP32_0(0), FP32_0_x7(0) } }, … … 12126 12126 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V1 } }, 12127 12127 { /* => */ { FP32_0(0), FP32_RAND_x7_V1 } }, 12128 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,12129 /*128:out */ X86_MXCSR_XCPT_MASK,12128 /*mxcsr:in */ 0, 12129 /*128:out */ 0, 12130 12130 /*256:out */ -1 }, 12131 12131 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V0 } }, 12132 12132 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V6 } }, 12133 12133 { /* => */ { FP32_0(0), FP32_RAND_x7_V6 } }, 12134 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12135 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12134 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 12135 /*128:out */ X86_MXCSR_RC_ZERO, 12136 12136 /*256:out */ -1 }, 12137 12137 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V6 } }, 12138 12138 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V0 } }, 12139 12139 { /* => */ { FP32_0(0), FP32_RAND_x7_V0 } }, 12140 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,12141 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,12140 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 12141 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 12142 12142 /*256:out */ -1 }, 12143 12143 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V0 } }, 12144 12144 { /*src1 */ { FP32_0(1), FP32_RAND_x7_V6 } }, 12145 12145 { /* => */ { FP32_0(0), FP32_RAND_x7_V6 } }, 12146 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,12147 /*128:out */ X86_MXCSR_XCPT_MASK,12146 /*mxcsr:in */ 0, 12147 /*128:out */ 0, 12148 12148 /*256:out */ -1 }, 12149 12149 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V2 } }, 12150 12150 { /*src1 */ { FP32_0(1), FP32_RAND_x7_V3 } }, 12151 12151 { /* => */ { FP32_0(0), FP32_RAND_x7_V3 } }, 12152 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_XCPT_FLAGS | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,12153 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,12152 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 12153 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 12154 12154 /*256:out */ -1 }, 12155 12155 { { /*src2 */ { FP32_0(1), FP32_RAND_x7_V6 } }, 12156 12156 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V0 } }, 12157 12157 { /* => */ { FP32_0(1), FP32_RAND_x7_V0 } }, 12158 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12159 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12158 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 12159 /*128:out */ X86_MXCSR_RC_ZERO, 12160 12160 /*256:out */ -1 }, 12161 12161 { { /*src2 */ { FP32_0(1), FP32_RAND_x7_V5 } }, 12162 12162 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V0 } }, 12163 12163 { /* => */ { FP32_0(1), FP32_RAND_x7_V0 } }, 12164 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_XCPT_FLAGS | X86_MXCSR_FZ | X86_MXCSR_RC_UP,12165 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,12164 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 12165 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 12166 12166 /*256:out */ -1 }, 12167 12167 { { /*src2 */ { FP32_0(1), FP32_RAND_x7_V6 } }, … … 12174 12174 { /*src1 */ { FP32_0(1), FP32_RAND_x7_V7 } }, 12175 12175 { /* => */ { FP32_0(1), FP32_RAND_x7_V7 } }, 12176 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,12177 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,12176 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 12177 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 12178 12178 /*256:out */ -1 }, 12179 12179 /* … … 12183 12183 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V7 } }, 12184 12184 { /* => */ { FP32_0(0), FP32_RAND_x7_V7 } }, 12185 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,12186 /*128:out */ X86_MXCSR_XCPT_MASK,12185 /*mxcsr:in */ 0, 12186 /*128:out */ 0, 12187 12187 /*256:out */ -1 }, 12188 12188 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V2 } }, 12189 12189 { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V6 } }, 12190 12190 { /* => */ { FP32_0(0), FP32_RAND_x7_V6 } }, 12191 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,12192 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,12191 /*mxcsr:in */ X86_MXCSR_RC_UP, 12192 /*128:out */ X86_MXCSR_RC_UP, 12193 12193 /*256:out */ -1 }, 12194 12194 { { /*src2 */ { FP32_INF(0), FP32_RAND_x7_V2 } }, 12195 12195 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V4 } }, 12196 12196 { /* => */ { FP32_0(0), FP32_RAND_x7_V4 } }, 12197 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12198 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12197 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 12198 /*128:out */ X86_MXCSR_RC_ZERO, 12199 12199 /*256:out */ -1 }, 12200 12200 { { /*src2 */ { FP32_0(0), FP32_RAND_x7_V2 } }, 12201 12201 { /*src1 */ { FP32_INF(1), FP32_RAND_x7_V0 } }, 12202 12202 { /* => */ { FP32_INF(1), FP32_RAND_x7_V0 } }, 12203 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,12204 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,12203 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 12204 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 12205 12205 /*256:out */ -1 }, 12206 12206 { { /*src2 */ { FP32_INF(0), FP32_RAND_x7_V3 } }, … … 12213 12213 { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V6 } }, 12214 12214 { /* => */ { FP32_INF(0), FP32_RAND_x7_V6 } }, 12215 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12216 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12215 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 12216 /*128:out */ X86_MXCSR_RC_ZERO, 12217 12217 /*256:out */ -1 }, 12218 12218 { { /*src2 */ { FP32_INF(1), FP32_RAND_x7_V3 } }, 12219 12219 { /*src1 */ { FP32_INF(1), FP32_RAND_x7_V5 } }, 12220 12220 { /* => */ { FP32_INF(1), FP32_RAND_x7_V5 } }, 12221 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12222 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12221 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 12222 /*128:out */ X86_MXCSR_RC_ZERO, 12223 12223 /*256:out */ -1 }, 12224 12224 { { /*src2 */ { FP32_INF(1), FP32_RAND_x7_V3 } }, 12225 12225 { /*src1 */ { FP32_INF(1), FP32_RAND_x7_V0 } }, 12226 12226 { /* => */ { FP32_INF(1), FP32_RAND_x7_V0 } }, 12227 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,12228 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,12227 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 12228 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 12229 12229 /*256:out */ -1 }, 12230 12230 { { /*src2 */ { FP32_INF(1), FP32_RAND_x7_V3 } }, 12231 12231 { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V1 } }, 12232 12232 { /* => */ { FP32_INF(1), FP32_RAND_x7_V1 } }, 12233 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,12234 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,12233 /*mxcsr:in */ X86_MXCSR_RC_UP, 12234 /*128:out */ X86_MXCSR_RC_UP, 12235 12235 /*256:out */ -1 }, 12236 12236 { { /*src2 */ { FP32_INF(1), FP32_RAND_x7_V1 } }, 12237 12237 { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V1 } }, 12238 12238 { /* => */ { FP32_INF(1), FP32_RAND_x7_V1 } }, 12239 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12240 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12239 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 12240 /*128:out */ X86_MXCSR_RC_ZERO, 12241 12241 /*256:out */ -1 }, 12242 12242 { { /*src2 */ { FP32_INF(0), FP32_RAND_x7_V0 } }, 12243 12243 { /*src1 */ { FP32_INF(1), FP32_RAND_x7_V1 } }, 12244 12244 { /* => */ { FP32_INF(1), FP32_RAND_x7_V1 } }, 12245 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12246 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12245 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 12246 /*128:out */ X86_MXCSR_RC_ZERO, 12247 12247 /*256:out */ -1 }, 12248 12248 { { /*src2 */ { FP32_INF(0), FP32_RAND_x7_V1 } }, 12249 12249 { /*src1 */ { FP32_INF(1), FP32_RAND_x7_V5 } }, 12250 12250 { /* => */ { FP32_INF(1), FP32_RAND_x7_V5 } }, 12251 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ,12252 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ,12251 /*mxcsr:in */ X86_MXCSR_FZ, 12252 /*128:out */ X86_MXCSR_FZ, 12253 12253 /*256:out */ -1 }, 12254 12254 { { /*src2 */ { FP32_INF(0), FP32_RAND_x7_V0 } }, 12255 12255 { /*src1 */ { FP32_NORM_V0(0), FP32_RAND_x7_V4 } }, 12256 12256 { /* => */ { FP32_NORM_V0(0), FP32_RAND_x7_V4 } }, 12257 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,12258 /*128:out */ X86_MXCSR_XCPT_MASK,12257 /*mxcsr:in */ 0, 12258 /*128:out */ 0, 12259 12259 /*256:out */ -1 }, 12260 12260 { { /*src2 */ { FP32_INF(0), FP32_RAND_x7_V0 } }, 12261 12261 { /*src1 */ { FP32_NORM_V3(0), FP32_RAND_x7_V3 } }, 12262 12262 { /* => */ { FP32_NORM_V3(0), FP32_RAND_x7_V3 } }, 12263 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,12264 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,12263 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 12264 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 12265 12265 /*256:out */ -1 }, 12266 12266 { { /*src2 */ { FP32_NORM_V7(0), FP32_RAND_x7_V2 } }, 12267 12267 { /*src1 */ { FP32_INF(1), FP32_RAND_x7_V3 } }, 12268 12268 { /* => */ { FP32_INF(1), FP32_RAND_x7_V3 } }, 12269 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,12270 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,12269 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 12270 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 12271 12271 /*256:out */ -1 }, 12272 12272 { { /*src2 */ { FP32_NORM_V7(0), FP32_RAND_x7_V5 } }, 12273 12273 { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V5 } }, 12274 12274 { /* => */ { FP32_NORM_V7(0), FP32_RAND_x7_V5 } }, 12275 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12276 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12275 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 12276 /*128:out */ X86_MXCSR_RC_ZERO, 12277 12277 /*256:out */ -1 }, 12278 12278 /* … … 12282 12282 { /*src1 */ { FP32_NORM_MAX(0), FP32_RAND_x7_V1 } }, 12283 12283 { /* => */ { FP32_NORM_MAX(0), FP32_RAND_x7_V1 } }, 12284 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,12285 /*128:out */ X86_MXCSR_XCPT_MASK,12284 /*mxcsr:in */ 0, 12285 /*128:out */ 0, 12286 12286 /*256:out */ -1 }, 12287 12287 { { /*src2 */ { FP32_NORM_MIN(0), FP32_RAND_x7_V3 } }, 12288 12288 { /*src1 */ { FP32_NORM_MIN(0), FP32_RAND_x7_V2 } }, 12289 12289 { /* => */ { FP32_NORM_MIN(0), FP32_RAND_x7_V2 } }, 12290 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,12291 /*128:out */ X86_MXCSR_XCPT_MASK,12290 /*mxcsr:in */ 0, 12291 /*128:out */ 0, 12292 12292 /*256:out */ -1 }, 12293 12293 { { /*src2 */ { FP32_NORM_MIN(0), FP32_RAND_x7_V3 } }, 12294 12294 { /*src1 */ { FP32_NORM_MAX(0), FP32_RAND_x7_V1 } }, 12295 12295 { /* => */ { FP32_NORM_MIN(0), FP32_RAND_x7_V1 } }, 12296 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,12297 /*128:out */ X86_MXCSR_XCPT_MASK,12296 /*mxcsr:in */ 0, 12297 /*128:out */ 0, 12298 12298 /*256:out */ -1 }, 12299 12299 { { /*src2 */ { FP32_NORM_MAX(0), FP32_RAND_x7_V2 } }, 12300 12300 { /*src1 */ { FP32_NORM_MAX(0), FP32_RAND_x7_V0 } }, 12301 12301 { /* => */ { FP32_NORM_MAX(0), FP32_RAND_x7_V0 } }, 12302 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,12303 /*128:out */ X86_MXCSR_XCPT_MASK,12302 /*mxcsr:in */ 0, 12303 /*128:out */ 0, 12304 12304 /*256:out */ -1 }, 12305 12305 { { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_x7_V2 } }, 12306 12306 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V5 } }, 12307 12307 { /* => */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_x7_V5 } }, 12308 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,12309 /*128:out */ X86_MXCSR_XCPT_MASK,12308 /*mxcsr:in */ 0, 12309 /*128:out */ 0, 12310 12310 /*256:out */ -1 }, 12311 12311 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V6 } }, 12312 12312 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V1 } }, 12313 12313 { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V1 } }, 12314 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,12315 /*128:out */ X86_MXCSR_XCPT_MASK,12314 /*mxcsr:in */ 0, 12315 /*128:out */ 0, 12316 12316 /*256:out */ -1 }, 12317 12317 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V6 } }, 12318 12318 { /*src1 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_x7_V3 } }, 12319 12319 { /* => */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_x7_V3 } }, 12320 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,12321 /*128:out */ X86_MXCSR_XCPT_MASK,12320 /*mxcsr:in */ 0, 12321 /*128:out */ 0, 12322 12322 /*256:out */ -1 }, 12323 12323 { { /*src2 */ { FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_RAND_x7_V1 } }, 12324 12324 { /*src1 */ { FP32_V(1, 0, 0x7d)/*-0.25*/, FP32_RAND_x7_V1 } }, 12325 12325 { /* => */ { FP32_V(1, 0, 0x7d)/*-0.25*/, FP32_RAND_x7_V1 } }, 12326 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,12327 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,12326 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 12327 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 12328 12328 /*256:out */ -1 }, 12329 12329 { { /*src2 */ { FP32_V(0, 0, 0x7d)/*0.25*/, FP32_RAND_x7_V2 } }, 12330 12330 { /*src1 */ { FP32_V(0, 0, 0x7e)/*0.50*/, FP32_RAND_x7_V1 } }, 12331 12331 { /* => */ { FP32_V(0, 0, 0x7d)/*0.25*/, FP32_RAND_x7_V1 } }, 12332 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,12333 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,12332 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 12333 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 12334 12334 /*256:out */ -1 }, 12335 12335 { { /*src2 */ { FP32_NORM_MAX(0), FP32_RAND_x7_V0 } }, 12336 12336 { /*src1 */ { FP32_NORM_V1(0), FP32_RAND_x7_V0 } }, 12337 12337 { /* => */ { FP32_NORM_V1(0), FP32_RAND_x7_V0 } }, 12338 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,12339 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,12338 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 12339 /*128:out */ X86_MXCSR_RC_DOWN, 12340 12340 /*256:out */ -1 }, 12341 12341 { { /*src2 */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_RAND_x7_V3 } }, 12342 12342 { /*src1 */ { FP32_V(0, 0x1ea980, 0x8f)/* 81235*/, FP32_RAND_x7_V0 } }, 12343 12343 { /* => */ { FP32_V(0, 0x1ea980, 0x8f)/* 81235*/, FP32_RAND_x7_V0 } }, 12344 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12345 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12344 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 12345 /*128:out */ X86_MXCSR_RC_ZERO, 12346 12346 /*256:out */ -1 }, 12347 12347 { { /*src2 */ { FP32_V(1, 0x2514d6, 0x93)/*-1352346.75*/, FP32_RAND_x7_V2 } }, 12348 12348 { /*src1 */ { FP32_V(0, 0x7c9000, 0x88)/* 1010.25*/, FP32_RAND_x7_V0 } }, 12349 12349 { /* => */ { FP32_V(1, 0x2514d6, 0x93)/*-1352346.75*/, FP32_RAND_x7_V0 } }, 12350 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12351 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12350 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 12351 /*128:out */ X86_MXCSR_RC_ZERO, 12352 12352 /*256:out */ -1 }, 12353 12353 { { /*src2 */ { FP32_V(1, 0x2514d6, 0x93)/*-1352346.75*/, FP32_RAND_x7_V2 } }, 12354 12354 { /*src1 */ { FP32_V(0, 0x253468, 0x93)/* 1353357.00*/, FP32_RAND_x7_V3 } }, 12355 12355 { /* => */ { FP32_V(1, 0x2514d6, 0x93)/*-1352346.75*/, FP32_RAND_x7_V3 } }, 12356 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12357 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12356 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 12357 /*128:out */ X86_MXCSR_RC_ZERO, 12358 12358 /*256:out */ -1 }, 12359 12359 { { /*src2 */ { FP32_V(1, 0x40e6b6, 0x8c)/*-12345.678*/, FP32_RAND_x7_V4 } }, 12360 12360 { /*src1 */ { FP32_V(1, 0x40e6b7, 0x8c)/*-12345.679*/, FP32_RAND_x7_V6 } }, 12361 12361 { /* => */ { FP32_V(1, 0x40e6b7, 0x8c)/*-12345.679*/, FP32_RAND_x7_V6 } }, 12362 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12363 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12362 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 12363 /*128:out */ X86_MXCSR_RC_ZERO, 12364 12364 /*256:out */ -1 }, 12365 12365 { { /*src2 */ { FP32_V(0, 0x620b2e, 0x92)/*925874.9*/, FP32_RAND_x7_V5 } }, 12366 12366 { /*src1 */ { FP32_V(0, 0x620b2d, 0x92)/*925874.8*/, FP32_RAND_x7_V0 } }, 12367 12367 { /* => */ { FP32_V(0, 0x620b2d, 0x92)/*925874.8*/, FP32_RAND_x7_V0 } }, 12368 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12369 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12368 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 12369 /*128:out */ X86_MXCSR_RC_ZERO, 12370 12370 /*256:out */ -1 }, 12371 12371 { { /*src2 */ { FP32_V(0, 0x490fda, 0x80)/*3.1415926*/, FP32_RAND_x7_V6 } }, 12372 12372 { /*src1 */ { FP32_V(0, 0x490fdb, 0x80)/*3.1415927*/, FP32_RAND_x7_V0 } }, 12373 12373 { /* => */ { FP32_V(0, 0x490fda, 0x80)/*3.1415926*/, FP32_RAND_x7_V0 } }, 12374 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12375 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12374 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 12375 /*128:out */ X86_MXCSR_RC_ZERO, 12376 12376 /*256:out */ -1 }, 12377 12377 { { /*src2 */ { FP32_V(1, 0x40e6b6, 0x8c)/*-12345.678*/, FP32_RAND_x7_V5 } }, 12378 12378 { /*src1 */ { FP32_V(1, 0x40e6b7, 0x8c)/*-12345.679*/, FP32_RAND_x7_V0 } }, 12379 12379 { /* => */ { FP32_V(1, 0x40e6b7, 0x8c)/*-12345.679*/, FP32_RAND_x7_V0 } }, 12380 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,12381 /*128:out */ X86_MXCSR_XCPT_MASK,12380 /*mxcsr:in */ 0, 12381 /*128:out */ 0, 12382 12382 /*256:out */ -1 }, 12383 12383 { { /*src2 */ { FP32_V(0, 0x5dd520, 0x8e)/* 56789.125*/, FP32_RAND_x7_V4 } }, 12384 12384 { /*src1 */ { FP32_V(1, 0x5dd521, 0x8e)/*-56789.127*/, FP32_RAND_x7_V0 } }, 12385 12385 { /* => */ { FP32_V(1, 0x5dd521, 0x8e)/*-56789.127*/, FP32_RAND_x7_V0 } }, 12386 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,12387 /*128:out */ X86_MXCSR_XCPT_MASK,12386 /*mxcsr:in */ 0, 12387 /*128:out */ 0, 12388 12388 /*256:out */ -1 }, 12389 12389 { { /*src2 */ { FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_RAND_x7_V3 } }, 12390 12390 { /*src1 */ { FP32_V(1, 0, 0x7d)/*-0.250*/, FP32_RAND_x7_V6 } }, 12391 12391 { /* => */ { FP32_V(1, 0, 0x7d)/*-0.250*/, FP32_RAND_x7_V6 } }, 12392 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,12393 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,12392 /*mxcsr:in */ X86_MXCSR_RC_UP, 12393 /*128:out */ X86_MXCSR_RC_UP, 12394 12394 /*256:out */ -1 }, 12395 12395 /** @todo More Normals. */ … … 12406 12406 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V4 } }, 12407 12407 { /* => */ { FP32_0(0), FP32_RAND_x7_V4 } }, 12408 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,12409 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE,12408 /*mxcsr:in */ 0, 12409 /*128:out */ X86_MXCSR_DE, 12410 12410 /*256:out */ -1 }, 12411 12411 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_RAND_x7_V6 } }, 12412 12412 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V3 } }, 12413 12413 { /* => */ { FP32_0(0), FP32_RAND_x7_V3 } }, 12414 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,12415 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,12414 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 12415 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 12416 12416 /*256:out */ -1 }, 12417 12417 { { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V5 } }, 12418 12418 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V4 } }, 12419 12419 { /* => */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V4 } }, 12420 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,12421 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE,12420 /*mxcsr:in */ 0, 12421 /*128:out */ X86_MXCSR_DE, 12422 12422 /*256:out */ -1 }, 12423 12423 { { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V1 } }, 12424 12424 { /*src1 */ { FP32_DENORM_MAX(1), FP32_RAND_x7_V3 } }, 12425 12425 { /* => */ { FP32_DENORM_MAX(1), FP32_RAND_x7_V3 } }, 12426 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,12427 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE,12426 /*mxcsr:in */ 0, 12427 /*128:out */ X86_MXCSR_DE, 12428 12428 /*256:out */ -1 }, 12429 12429 { { /*src2 */ { FP32_DENORM_MAX(1), FP32_RAND_x7_V3 } }, 12430 12430 { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V0 } }, 12431 12431 { /* => */ { FP32_DENORM_MAX(1), FP32_RAND_x7_V0 } }, 12432 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,12433 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE,12432 /*mxcsr:in */ 0, 12433 /*128:out */ X86_MXCSR_DE, 12434 12434 /*256:out */ -1 }, 12435 12435 { { /*src2 */ { FP32_DENORM_MIN(1), FP32_RAND_x7_V7 } }, 12436 12436 { /*src1 */ { FP32_DENORM_MIN(0), FP32_RAND_x7_V0 } }, 12437 12437 { /* => */ { FP32_DENORM_MIN(1), FP32_RAND_x7_V0 } }, 12438 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,12439 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE,12438 /*mxcsr:in */ 0, 12439 /*128:out */ X86_MXCSR_DE, 12440 12440 /*256:out */ -1 }, 12441 12441 { { /*src2 */ { FP32_DENORM_MIN(1), FP32_RAND_x7_V6 } }, 12442 12442 { /*src1 */ { FP32_DENORM_MIN(1), FP32_RAND_x7_V3 } }, 12443 12443 { /* => */ { FP32_DENORM_MIN(1), FP32_RAND_x7_V3 } }, 12444 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,12445 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE,12444 /*mxcsr:in */ 0, 12445 /*128:out */ X86_MXCSR_DE, 12446 12446 /*256:out */ -1 }, 12447 12447 { { /*src2 */ { FP32_DENORM_MIN(1), FP32_RAND_x7_V6 } }, 12448 12448 { /*src1 */ { FP32_DENORM_MIN(1), FP32_RAND_x7_V1 } }, 12449 12449 { /* => */ { FP32_0(1), FP32_RAND_x7_V1 } }, 12450 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,12451 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,12450 /*mxcsr:in */ X86_MXCSR_DAZ, 12451 /*128:out */ X86_MXCSR_DAZ, 12452 12452 /*256:out */ -1 }, 12453 12453 { { /*src2 */ { FP32_DENORM_MIN(0), FP32_RAND_x7_V6 } }, 12454 12454 { /*src1 */ { FP32_0(0), FP32_RAND_x7_V2 } }, 12455 12455 { /* => */ { FP32_0(0), FP32_RAND_x7_V2 } }, 12456 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,12457 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE,12456 /*mxcsr:in */ 0, 12457 /*128:out */ X86_MXCSR_DE, 12458 12458 /*256:out */ -1 }, 12459 12459 /** @todo More Denormals. */ … … 12515 12515 { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 12516 12516 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 12517 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,12518 /*128:out */ X86_MXCSR_XCPT_MASK,12517 /*mxcsr:in */ 0, 12518 /*128:out */ 0, 12519 12519 /*256:out */ -1 }, 12520 12520 { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, … … 12527 12527 { /*src1 */ { FP64_0(0), FP64_INF(1), FP64_QNAN(0), FP64_SNAN(1) } }, 12528 12528 { /* => */ { FP64_0(0), FP64_INF(1), FP64_QNAN(0), FP64_SNAN(1) } }, 12529 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,12530 /*128:out */ X86_MXCSR_XCPT_MASK,12529 /*mxcsr:in */ 0, 12530 /*128:out */ 0, 12531 12531 /*256:out */ -1 }, 12532 12532 { { /*src2 */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V0(0), FP64_RAND_V0(0) } }, 12533 12533 { /*src1 */ { FP64_0(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(0) } }, 12534 12534 { /* => */ { FP64_0(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(0) } }, 12535 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12536 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12535 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 12536 /*128:out */ X86_MXCSR_RC_ZERO, 12537 12537 /*256:out */ -1 }, 12538 12538 { { /*src2 */ { FP64_0(0), FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V1(0) } }, 12539 12539 { /*src1 */ { FP64_0(0), FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V2(1) } }, 12540 12540 { /* => */ { FP64_0(0), FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V2(1) } }, 12541 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,12542 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,12541 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 12542 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 12543 12543 /*256:out */ -1 }, 12544 12544 { { /*src2 */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V3(0) } }, 12545 12545 { /*src1 */ { FP64_0(1), FP64_RAND_V1(0), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, 12546 12546 { /* => */ { FP64_0(0), FP64_RAND_V1(0), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, 12547 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,12548 /*128:out */ X86_MXCSR_XCPT_MASK,12547 /*mxcsr:in */ 0, 12548 /*128:out */ 0, 12549 12549 /*256:out */ -1 }, 12550 12550 { { /*src2 */ { FP64_0(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(0) } }, 12551 12551 { /*src1 */ { FP64_0(1), FP64_RAND_V2(1), FP64_RAND_V3(0), FP64_RAND_V0(1) } }, 12552 12552 { /* => */ { FP64_0(0), FP64_RAND_V2(1), FP64_RAND_V3(0), FP64_RAND_V0(1) } }, 12553 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,12554 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,12553 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 12554 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 12555 12555 /*256:out */ -1 }, 12556 12556 { { /*src2 */ { FP64_0(1), FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V3(1) } }, 12557 12557 { /*src1 */ { FP64_0(0), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V3(0) } }, 12558 12558 { /* => */ { FP64_0(1), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V3(0) } }, 12559 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12560 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12559 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 12560 /*128:out */ X86_MXCSR_RC_ZERO, 12561 12561 /*256:out */ -1 }, 12562 12562 { { /*src2 */ { FP64_0(1), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V1(0) } }, 12563 12563 { /*src1 */ { FP64_0(0), FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 12564 12564 { /* => */ { FP64_0(1), FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, 12565 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,12566 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,12565 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 12566 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 12567 12567 /*256:out */ -1 }, 12568 12568 { { /*src2 */ { FP64_0(1), FP64_RAND_V1(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } }, … … 12575 12575 { /*src1 */ { FP64_0(1), FP64_RAND_V1(0), FP64_RAND_V0(1), FP64_RAND_V2(1) } }, 12576 12576 { /* => */ { FP64_0(1), FP64_RAND_V1(0), FP64_RAND_V0(1), FP64_RAND_V2(1) } }, 12577 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,12578 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,12577 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 12578 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 12579 12579 /*256:out */ -1 }, 12580 12580 /* … … 12584 12584 { /*src1 */ { FP64_0(0), FP64_RAND_V1(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } }, 12585 12585 { /* => */ { FP64_0(0), FP64_RAND_V1(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } }, 12586 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,12587 /*128:out */ X86_MXCSR_XCPT_MASK,12586 /*mxcsr:in */ 0, 12587 /*128:out */ 0, 12588 12588 /*256:out */ -1 }, 12589 12589 { { /*src2 */ { FP64_0(0), FP64_RAND_V1(1), FP64_RAND_V1(1), FP64_RAND_V3(1) } }, 12590 12590 { /*src1 */ { FP64_INF(0), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } }, 12591 12591 { /* => */ { FP64_0(0), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } }, 12592 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,12593 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,12592 /*mxcsr:in */ X86_MXCSR_RC_UP, 12593 /*128:out */ X86_MXCSR_RC_UP, 12594 12594 /*256:out */ -1 }, 12595 12595 { { /*src2 */ { FP64_INF(0), FP64_INF(1), FP64_SNAN(1), FP64_QNAN(1) } }, 12596 12596 { /*src1 */ { FP64_0(0), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } }, 12597 12597 { /* => */ { FP64_0(0), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } }, 12598 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12599 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12598 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 12599 /*128:out */ X86_MXCSR_RC_ZERO, 12600 12600 /*256:out */ -1 }, 12601 12601 { { /*src2 */ { FP64_0(0), FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V3(0) } }, 12602 12602 { /*src1 */ { FP64_INF(1), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V0(1) } }, 12603 12603 { /* => */ { FP64_INF(1), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V0(1) } }, 12604 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,12605 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,12604 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 12605 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 12606 12606 /*256:out */ -1 }, 12607 12607 { { /*src2 */ { FP64_INF(0), FP64_RAND_V3(1), FP64_RAND_V3(1), FP64_RAND_V0(1) } }, … … 12614 12614 { /*src1 */ { FP64_INF(0), FP64_RAND_V0(1), FP64_RAND_V0(1), FP64_RAND_V3(1) } }, 12615 12615 { /* => */ { FP64_INF(0), FP64_RAND_V0(1), FP64_RAND_V0(1), FP64_RAND_V3(1) } }, 12616 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12617 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12616 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 12617 /*128:out */ X86_MXCSR_RC_ZERO, 12618 12618 /*256:out */ -1 }, 12619 12619 { { /*src2 */ { FP64_INF(1), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V3(0) } }, 12620 12620 { /*src1 */ { FP64_INF(1), FP64_QNAN_V(1, 1), FP64_RAND_V1(1), FP64_RAND_V2(0) } }, 12621 12621 { /* => */ { FP64_INF(1), FP64_QNAN_V(1, 1), FP64_RAND_V1(1), FP64_RAND_V2(0) } }, 12622 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12623 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12622 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 12623 /*128:out */ X86_MXCSR_RC_ZERO, 12624 12624 /*256:out */ -1 }, 12625 12625 { { /*src2 */ { FP64_INF(1), FP64_RAND_V2(1), FP64_RAND_V1(1), FP64_RAND_V0(1) } }, 12626 12626 { /*src1 */ { FP64_INF(1), FP64_RAND_V0(0), FP64_RAND_V3(1), FP64_RAND_V0(1) } }, 12627 12627 { /* => */ { FP64_INF(1), FP64_RAND_V0(0), FP64_RAND_V3(1), FP64_RAND_V0(1) } }, 12628 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,12629 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,12628 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 12629 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 12630 12630 /*256:out */ -1 }, 12631 12631 { { /*src2 */ { FP64_INF(1), FP64_RAND_V1(1), FP64_RAND_V3(1), FP64_RAND_V0(1) } }, 12632 12632 { /*src1 */ { FP64_INF(0), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V1(1) } }, 12633 12633 { /* => */ { FP64_INF(1), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V1(1) } }, 12634 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,12635 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,12634 /*mxcsr:in */ X86_MXCSR_RC_UP, 12635 /*128:out */ X86_MXCSR_RC_UP, 12636 12636 /*256:out */ -1 }, 12637 12637 { { /*src2 */ { FP64_INF(1), FP64_RAND_V0(1), FP64_RAND_V2(1), FP64_RAND_V0(1) } }, 12638 12638 { /*src1 */ { FP64_INF(0), FP64_RAND_V0(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, 12639 12639 { /* => */ { FP64_INF(1), FP64_RAND_V0(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, 12640 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12641 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12640 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 12641 /*128:out */ X86_MXCSR_RC_ZERO, 12642 12642 /*256:out */ -1 }, 12643 12643 { { /*src2 */ { FP64_INF(0), FP64_RAND_V2(1), FP64_RAND_V3(1), FP64_RAND_V0(1) } }, 12644 12644 { /*src1 */ { FP64_INF(1), FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, 12645 12645 { /* => */ { FP64_INF(1), FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, 12646 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12647 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12646 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 12647 /*128:out */ X86_MXCSR_RC_ZERO, 12648 12648 /*256:out */ -1 }, 12649 12649 { { /*src2 */ { FP64_INF(0), FP64_RAND_V0(1), FP64_RAND_V2(1), FP64_RAND_V0(1) } }, 12650 12650 { /*src1 */ { FP64_INF(1), FP64_RAND_V0(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, 12651 12651 { /* => */ { FP64_INF(1), FP64_RAND_V0(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, 12652 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ,12653 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ,12652 /*mxcsr:in */ X86_MXCSR_FZ, 12653 /*128:out */ X86_MXCSR_FZ, 12654 12654 /*256:out */ -1 }, 12655 12655 { { /*src2 */ { FP64_INF(0), FP64_RAND_V0(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } }, 12656 12656 { /*src1 */ { FP64_NORM_V0(0), FP64_RAND_V1(1), FP64_RAND_V3(1), FP64_RAND_V1(1) } }, 12657 12657 { /* => */ { FP64_NORM_V0(0), FP64_RAND_V1(1), FP64_RAND_V3(1), FP64_RAND_V1(1) } }, 12658 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,12659 /*128:out */ X86_MXCSR_XCPT_MASK,12658 /*mxcsr:in */ 0, 12659 /*128:out */ 0, 12660 12660 /*256:out */ -1 }, 12661 12661 { { /*src2 */ { FP64_INF(0), FP64_INF(0), FP64_SNAN(1), FP64_INF(1) } }, 12662 12662 { /*src1 */ { FP64_NORM_V3(0), FP64_INF(1), FP64_QNAN(1), FP64_SNAN(1) } }, 12663 12663 { /* => */ { FP64_NORM_V3(0), FP64_INF(1), FP64_QNAN(1), FP64_SNAN(1) } }, 12664 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,12665 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,12664 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 12665 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 12666 12666 /*256:out */ -1 }, 12667 12667 { { /*src2 */ { FP64_NORM_V2(0), FP64_RAND_V3(1), FP64_QNAN(1), FP64_SNAN(1) } }, 12668 12668 { /*src1 */ { FP64_INF(1), FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V1(1) } }, 12669 12669 { /* => */ { FP64_INF(1), FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V1(1) } }, 12670 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,12671 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,12670 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 12671 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 12672 12672 /*256:out */ -1 }, 12673 12673 { { /*src2 */ { FP64_NORM_V2(0), FP64_SNAN(0), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, 12674 12674 { /*src1 */ { FP64_INF(0), FP64_RAND_V2(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, 12675 12675 { /* => */ { FP64_NORM_V2(0), FP64_RAND_V2(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, 12676 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12677 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12676 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 12677 /*128:out */ X86_MXCSR_RC_ZERO, 12678 12678 /*256:out */ -1 }, 12679 12679 /* … … 12683 12683 { /*src1 */ { FP64_NORM_MAX(0), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V2(1) } }, 12684 12684 { /* => */ { FP64_NORM_MAX(0), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V2(1) } }, 12685 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,12686 /*128:out */ X86_MXCSR_XCPT_MASK,12685 /*mxcsr:in */ 0, 12686 /*128:out */ 0, 12687 12687 /*256:out */ -1 }, 12688 12688 { { /*src2 */ { FP64_NORM_MIN(0), FP64_RAND_V3(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } }, 12689 12689 { /*src1 */ { FP64_NORM_MIN(0), FP64_RAND_V2(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } }, 12690 12690 { /* => */ { FP64_NORM_MIN(0), FP64_RAND_V2(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } }, 12691 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,12692 /*128:out */ X86_MXCSR_XCPT_MASK,12691 /*mxcsr:in */ 0, 12692 /*128:out */ 0, 12693 12693 /*256:out */ -1 }, 12694 12694 { { /*src2 */ { FP64_NORM_MIN(0), FP64_RAND_V3(1), FP64_RAND_V0(1), FP64_RAND_V3(0) } }, 12695 12695 { /*src1 */ { FP64_NORM_MAX(0), FP64_RAND_V1(0), FP64_RAND_V3(0), FP64_RAND_V1(0) } }, 12696 12696 { /* => */ { FP64_NORM_MIN(0), FP64_RAND_V1(0), FP64_RAND_V3(0), FP64_RAND_V1(0) } }, 12697 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,12698 /*128:out */ X86_MXCSR_XCPT_MASK,12697 /*mxcsr:in */ 0, 12698 /*128:out */ 0, 12699 12699 /*256:out */ -1 }, 12700 12700 { { /*src2 */ { FP64_NORM_MAX(0), FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V3(0) } }, 12701 12701 { /*src1 */ { FP64_NORM_MAX(0), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V1(1) } }, 12702 12702 { /* => */ { FP64_NORM_MAX(0), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V1(1) } }, 12703 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,12704 /*128:out */ X86_MXCSR_XCPT_MASK,12703 /*mxcsr:in */ 0, 12704 /*128:out */ 0, 12705 12705 /*256:out */ -1 }, 12706 12706 { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V3(0) } }, 12707 12707 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_RAND_V1(0), FP64_RAND_V1(0), FP64_RAND_V3(1) } }, 12708 12708 { /* => */ { FP64_NORM_SAFE_INT_MIN(0), FP64_RAND_V1(0), FP64_RAND_V1(0), FP64_RAND_V3(1) } }, 12709 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,12710 /*128:out */ X86_MXCSR_XCPT_MASK,12709 /*mxcsr:in */ 0, 12710 /*128:out */ 0, 12711 12711 /*256:out */ -1 }, 12712 12712 { { /*src2 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, 12713 12713 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_RAND_V1(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } }, 12714 12714 { /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_RAND_V1(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } }, 12715 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,12716 /*128:out */ X86_MXCSR_XCPT_MASK,12715 /*mxcsr:in */ 0, 12716 /*128:out */ 0, 12717 12717 /*256:out */ -1 }, 12718 12718 { { /*src2 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_INF(0), FP64_QNAN(1), FP64_QNAN(0) } }, 12719 12719 { /*src1 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } }, 12720 12720 { /* => */ { FP64_NORM_SAFE_INT_MIN(0), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } }, 12721 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,12722 /*128:out */ X86_MXCSR_XCPT_MASK,12721 /*mxcsr:in */ 0, 12722 /*128:out */ 0, 12723 12723 /*256:out */ -1 }, 12724 12724 { { /*src2 */ { FP64_V(0, 0, 0x409)/*1024*/, FP64_RAND_V1(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } }, 12725 12725 { /*src1 */ { FP64_V(0, 0, 0x408)/* 512*/, FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V3(1) } }, 12726 12726 { /* => */ { FP64_V(0, 0, 0x408)/* 512*/, FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V3(1) } }, 12727 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,12728 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,12727 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 12728 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 12729 12729 /*256:out */ -1 }, 12730 12730 { { /*src2 */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_RAND_V2(1), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, 12731 12731 { /*src1 */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_RAND_V0(0), FP64_RAND_V2(0), FP64_RAND_V0(0) } }, 12732 12732 { /* => */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_RAND_V0(0), FP64_RAND_V2(0), FP64_RAND_V0(0) } }, 12733 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,12734 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,12733 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 12734 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 12735 12735 /*256:out */ -1 }, 12736 12736 { { /*src2 */ { FP64_NORM_MAX(0), FP64_RAND_V0(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } }, 12737 12737 { /*src1 */ { FP64_NORM_V1(0), FP64_RAND_V0(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, 12738 12738 { /* => */ { FP64_NORM_V1(0), FP64_RAND_V0(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, 12739 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,12740 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,12739 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 12740 /*128:out */ X86_MXCSR_RC_DOWN, 12741 12741 /*256:out */ -1 }, 12742 12742 { { /*src2 */ { FP64_V(0, 0xc000000000000, 0x3ff)/*1.75*/, FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V3(0) } }, 12743 12743 { /*src1 */ { FP64_V(0, 0, 0x3fd)/*0.25*/, FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V1(0) } }, 12744 12744 { /* => */ { FP64_V(0, 0, 0x3fd)/*0.25*/, FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V1(0) } }, 12745 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12746 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12745 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 12746 /*128:out */ X86_MXCSR_RC_ZERO, 12747 12747 /*256:out */ -1 }, 12748 12748 { { /*src2 */ { FP64_V(1, 0, 0x3fd)/*-0.25*/, FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V3(0) } }, 12749 12749 { /*src1 */ { FP64_V(1, 0, 0x3fe)/*-0.50*/, FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V1(1) } }, 12750 12750 { /* => */ { FP64_V(1, 0, 0x3fe)/*-0.50*/, FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V1(1) } }, 12751 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12752 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12751 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 12752 /*128:out */ X86_MXCSR_RC_ZERO, 12753 12753 /*256:out */ -1 }, 12754 12754 { { /*src2 */ { FP64_V(0, 0x26580b4c7e6b7, 0x41d)/*1234567891.1234567*/, FP64_RAND_V2(1), FP64_RAND_V3(1), FP64_RAND_V3(1) } }, 12755 12755 { /*src1 */ { FP64_V(0, 0x26580b4c7e6bc, 0x41d)/*1234567891.1234580*/, FP64_RAND_V3(0), FP64_RAND_V1(0), FP64_RAND_V0(1) } }, 12756 12756 { /* => */ { FP64_V(0, 0x26580b4c7e6b7, 0x41d)/*1234567891.1234567*/, FP64_RAND_V3(0), FP64_RAND_V1(0), FP64_RAND_V0(1) } }, 12757 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12758 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12757 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 12758 /*128:out */ X86_MXCSR_RC_ZERO, 12759 12759 /*256:out */ -1 }, 12760 12760 { { /*src2 */ { FP64_V(0, 0xf9b0207d06184, 0x3fb)/*0.1234589833333129*/, FP64_RAND_V3(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } }, 12761 12761 { /*src1 */ { FP64_V(0, 0xf9b0207d0617d, 0x3fb)/*0.1234589833333128*/, FP64_RAND_V1(1), FP64_RAND_V0(0), FP64_RAND_V0(1) } }, 12762 12762 { /* => */ { FP64_V(0, 0xf9b0207d0617d, 0x3fb)/*0.1234589833333128*/, FP64_RAND_V1(1), FP64_RAND_V0(0), FP64_RAND_V0(1) } }, 12763 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12764 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12763 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 12764 /*128:out */ X86_MXCSR_RC_ZERO, 12765 12765 /*256:out */ -1 }, 12766 12766 { { /*src2 */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/* 121098765432102.75*/, FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } }, 12767 12767 { /*src1 */ { FP64_V(1, 0xbcd80e0108cc0, 0x42e)/*-244555555308646.00*/, FP64_RAND_V3(0), FP64_RAND_V3(1), FP64_RAND_V0(1) } }, 12768 12768 { /* => */ { FP64_V(1, 0xbcd80e0108cc0, 0x42e)/*-244555555308646.00*/, FP64_RAND_V3(0), FP64_RAND_V3(1), FP64_RAND_V0(1) } }, 12769 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12770 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12769 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 12770 /*128:out */ X86_MXCSR_RC_ZERO, 12771 12771 /*256:out */ -1 }, 12772 12772 { { /*src2 */ { FP64_V(0, 0xcf0033a34f337, 0x432)/*4072598000007579.5*/, FP64_RAND_V3(1), FP64_RAND_V2(1), FP64_RAND_V1(1) } }, 12773 12773 { /*src1 */ { FP64_V(0, 0xd6eca42000000, 0x419)/* 123450000.5*/, FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, 12774 12774 { /* => */ { FP64_V(0, 0xd6eca42000000, 0x419)/* 123450000.5*/, FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, 12775 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12776 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,12775 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 12776 /*128:out */ X86_MXCSR_RC_ZERO, 12777 12777 /*256:out */ -1 }, 12778 12778 { { /*src2 */ { FP64_V(1, 0xbcd80e0108cc0, 0x42e)/*-244555555308646.00*/, FP64_INF(1), FP64_SNAN(1), FP64_INF(1) } }, 12779 12779 { /*src1 */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/* 121098765432102.75*/, FP64_INF(1), FP64_QNAN(0), FP64_SNAN(0) } }, 12780 12780 { /* => */ { FP64_V(1, 0xbcd80e0108cc0, 0x42e)/*-244555555308646.00*/, FP64_INF(1), FP64_QNAN(0), FP64_SNAN(0) } }, 12781 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,12782 /*128:out */ X86_MXCSR_XCPT_MASK,12781 /*mxcsr:in */ 0, 12782 /*128:out */ 0, 12783 12783 /*256:out */ -1 }, 12784 12784 { { /*src2 */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/* 244555555308646.00*/, FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, 12785 12785 { /*src1 */ { FP64_V(1, 0xb88e0395d49b0, 0x42d)/*-121098765432102.75*/, FP64_RAND_V0(0), FP64_RAND_V0(0), FP64_RAND_V2(1) } }, 12786 12786 { /* => */ { FP64_V(1, 0xb88e0395d49b0, 0x42d)/*-121098765432102.75*/, FP64_RAND_V0(0), FP64_RAND_V0(0), FP64_RAND_V2(1) } }, 12787 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,12788 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,12787 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 12788 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 12789 12789 /*256:out */ -1 }, 12790 12790 { { /*src2 */ { FP64_V(1, 0xcf0033a34f337, 0x432)/*-4072598000007579.5*/, FP64_RAND_V1(0), FP64_RAND_V2(0), FP64_RAND_V1(0) } }, 12791 12791 { /*src1 */ { FP64_V(0, 0xd6eca42000000, 0x419)/* 123450000.5*/, FP64_RAND_V2(0), FP64_RAND_V2(1), FP64_RAND_V3(0) } }, 12792 12792 { /* => */ { FP64_V(1, 0xcf0033a34f337, 0x432)/*-4072598000007579.5*/, FP64_RAND_V2(0), FP64_RAND_V2(1), FP64_RAND_V3(0) } }, 12793 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,12794 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,12793 /*mxcsr:in */ X86_MXCSR_RC_UP, 12794 /*128:out */ X86_MXCSR_RC_UP, 12795 12795 /*256:out */ -1 }, 12796 12796 /** @todo More Normals. */ … … 12807 12807 { /*src1 */ { FP64_DENORM_MAX(0), FP64_RAND_V2(0), FP64_RAND_V3(1), FP64_RAND_V2(0) } }, 12808 12808 { /* => */ { FP64_0(0), FP64_RAND_V2(0), FP64_RAND_V3(1), FP64_RAND_V2(0) } }, 12809 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,12810 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE,12809 /*mxcsr:in */ 0, 12810 /*128:out */ X86_MXCSR_DE, 12811 12811 /*256:out */ -1 }, 12812 12812 { { /*src2 */ { FP64_DENORM_MIN(0), FP64_INF(1), FP64_SNAN(0), FP64_INF(1) } }, 12813 12813 { /*src1 */ { FP64_DENORM_MAX(0), FP64_INF(0), FP64_QNAN(1), FP64_SNAN(1) } }, 12814 12814 { /* => */ { FP64_0(0), FP64_INF(0), FP64_QNAN(1), FP64_SNAN(1) } }, 12815 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,12816 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,12815 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 12816 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 12817 12817 /*256:out */ -1 }, 12818 12818 { { /*src2 */ { FP64_DENORM_MAX(0), FP64_RAND_V2(1), FP64_RAND_V0(1), FP64_RAND_V3(0) } }, 12819 12819 { /*src1 */ { FP64_DENORM_MAX(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, 12820 12820 { /* => */ { FP64_DENORM_MAX(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, 12821 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,12822 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE,12821 /*mxcsr:in */ 0, 12822 /*128:out */ X86_MXCSR_DE, 12823 12823 /*256:out */ -1 }, 12824 12824 { { /*src2 */ { FP64_DENORM_MAX(0), FP64_RAND_V1(1), FP64_RAND_V2(1), FP64_RAND_V2(0) } }, 12825 12825 { /*src1 */ { FP64_DENORM_MAX(1), FP64_RAND_V0(0), FP64_RAND_V3(0), FP64_RAND_V0(0) } }, 12826 12826 { /* => */ { FP64_DENORM_MAX(1), FP64_RAND_V0(0), FP64_RAND_V3(0), FP64_RAND_V0(0) } }, 12827 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,12828 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE,12827 /*mxcsr:in */ 0, 12828 /*128:out */ X86_MXCSR_DE, 12829 12829 /*256:out */ -1 }, 12830 12830 { { /*src2 */ { FP64_DENORM_MAX(1), FP64_RAND_V3(1), FP64_RAND_V0(0), FP64_RAND_V3(1) } }, 12831 12831 { /*src1 */ { FP64_DENORM_MAX(0), FP64_RAND_V2(1), FP64_RAND_V3(1), FP64_RAND_V2(1) } }, 12832 12832 { /* => */ { FP64_DENORM_MAX(1), FP64_RAND_V2(1), FP64_RAND_V3(1), FP64_RAND_V2(1) } }, 12833 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,12834 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE,12833 /*mxcsr:in */ 0, 12834 /*128:out */ X86_MXCSR_DE, 12835 12835 /*256:out */ -1 }, 12836 12836 { { /*src2 */ { FP64_DENORM_MIN(1), FP64_RAND_V0(1), FP64_RAND_V3(1), FP64_RAND_V2(1) } }, 12837 12837 { /*src1 */ { FP64_DENORM_MIN(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, 12838 12838 { /* => */ { FP64_DENORM_MIN(1), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, 12839 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,12840 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE,12839 /*mxcsr:in */ 0, 12840 /*128:out */ X86_MXCSR_DE, 12841 12841 /*256:out */ -1 }, 12842 12842 { { /*src2 */ { FP64_DENORM_MIN(1), FP64_INF(0), FP64_QNAN(1), FP64_SNAN(1) } }, 12843 12843 { /*src1 */ { FP64_DENORM_MIN(1), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } }, 12844 12844 { /* => */ { FP64_DENORM_MIN(1), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } }, 12845 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,12846 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE,12845 /*mxcsr:in */ 0, 12846 /*128:out */ X86_MXCSR_DE, 12847 12847 /*256:out */ -1 }, 12848 12848 { { /*src2 */ { FP64_DENORM_MIN(1), FP64_SNAN(1), FP64_SNAN(0), FP64_QNAN(0) } }, 12849 12849 { /*src1 */ { FP64_DENORM_MIN(1), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } }, 12850 12850 { /* => */ { FP64_0(1), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } }, 12851 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,12852 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,12851 /*mxcsr:in */ X86_MXCSR_DAZ, 12852 /*128:out */ X86_MXCSR_DAZ, 12853 12853 /*256:out */ -1 }, 12854 12854 { { /*src2 */ { FP64_DENORM_MIN(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, 12855 12855 { /*src1 */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(0) } }, 12856 12856 { /* => */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(0) } }, 12857 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,12858 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE,12857 /*mxcsr:in */ 0, 12858 /*128:out */ X86_MXCSR_DE, 12859 12859 /*256:out */ -1 }, 12860 12860 /** @todo More Denormals. */ … … 12918 12918 { /*unused */ { FP32_ROW_UNUSED } }, 12919 12919 { /* => */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0) } }, 12920 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,12921 /*128:out */ X86_MXCSR_XCPT_MASK,12922 /*256:out */ X86_MXCSR_XCPT_MASK},12920 /*mxcsr:in */ 0, 12921 /*128:out */ 0, 12922 /*256:out */ 0 }, 12923 12923 { { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 12924 12924 { /*unused */ { FP32_ROW_UNUSED } }, … … 12945 12945 { /*unused */ { FP32_ROW_UNUSED } }, 12946 12946 { /* => */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0) } }, 12947 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,12948 /*128:out */ X86_MXCSR_XCPT_MASK,12949 /*256:out */ X86_MXCSR_XCPT_MASK},12947 /*mxcsr:in */ 0, 12948 /*128:out */ 0, 12949 /*256:out */ 0 }, 12950 12950 { { /*src1 */ { FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(0) } }, 12951 12951 { /*unused */ { FP32_ROW_UNUSED } }, … … 13087 13087 { /*unused */ { FP32_ROW_UNUSED } }, 13088 13088 { /* => */ { FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(0) } }, 13089 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,13090 /*128:out */ X86_MXCSR_XCPT_MASK,13091 /*256:out */ X86_MXCSR_XCPT_MASK},13089 /*mxcsr:in */ 0, 13090 /*128:out */ 0, 13091 /*256:out */ 0 }, 13092 13092 { { /*src1 */ { FP32_DENORM_MAX(1), FP32_DENORM_MAX(1), FP32_DENORM_MIN(1), FP32_DENORM_MIN(1), FP32_DENORM_MIN(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } }, 13093 13093 { /*unused */ { FP32_ROW_UNUSED } }, … … 13139 13139 { /*unused */ { FP32_ROW_UNUSED } }, 13140 13140 { /* => */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(1, 1), FP32_QNAN(0), FP32_QNAN(1), FP32_QNAN_V(1, 1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN_V(1, 1) } }, 13141 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,13142 /*128:out */ X86_MXCSR_XCPT_MASK,13143 /*256:out */ X86_MXCSR_XCPT_MASK},13141 /*mxcsr:in */ 0, 13142 /*128:out */ 0, 13143 /*256:out */ 0 }, 13144 13144 { { /*src1 */ { FP32_SNAN(0), FP32_SNAN(1), FP32_QNAN(0), FP32_QNAN(1), FP32_SNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_SNAN(1) } }, 13145 13145 { /*unused */ { FP32_ROW_UNUSED } }, … … 13250 13250 { /*src2 */ { FP32_RAND_V2(0), FP32_RAND_x7_V2 } }, 13251 13251 { /* => */ { FP32_INF(0), FP32_RAND_x7_V2 } }, 13252 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,13253 /*128:out */ X86_MXCSR_XCPT_MASK,13252 /*mxcsr:in */ 0, 13253 /*128:out */ 0, 13254 13254 /*256:out */ -1 }, 13255 13255 { { /*src1 */ { FP32_0(1), FP32_RAND_x7_V0 } }, 13256 13256 { /*src2 */ { FP32_RAND_V3(1), FP32_RAND_x7_V1 } }, 13257 13257 { /* => */ { FP32_INF(1), FP32_RAND_x7_V1 } }, 13258 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,13259 /*128:out */ X86_MXCSR_XCPT_MASK,13258 /*mxcsr:in */ 0, 13259 /*128:out */ 0, 13260 13260 /*256:out */ -1 }, 13261 13261 { { /*src1 */ { FP32_0(1), FP32_RAND_x7_V2 } }, … … 13289 13289 { /*unused */ { FP32_RAND_V2(0), FP32_RAND_x7_V0 } }, 13290 13290 { /* => */ { FP32_0(0), FP32_RAND_x7_V0 } }, 13291 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,13292 /*128:out */ X86_MXCSR_XCPT_MASK,13291 /*mxcsr:in */ 0, 13292 /*128:out */ 0, 13293 13293 /*256:out */ -1 }, 13294 13294 { { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V3 } }, … … 13508 13508 { /*unused */ { FP32_RAND_V2(0), FP32_RAND_x7_V3 } }, 13509 13509 { /* => */ { FP32_V(0, 1112064, 107), FP32_RAND_x7_V3 } }, 13510 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,13511 /*128:out */ X86_MXCSR_XCPT_MASK,13510 /*mxcsr:in */ 0, 13511 /*128:out */ 0, 13512 13512 /*256:out */ -1 }, 13513 13513 { { /*src1 */ { FP32_V(0, 0x620b2d, 0x92)/*925874.8*/, FP32_RAND_x7_V4 } }, 13514 13514 { /*unused */ { FP32_RAND_V2(0), FP32_RAND_x7_V3 } }, 13515 13515 { /* => */ { FP32_V(0, 1112064, 107), FP32_RAND_x7_V3 } }, 13516 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,13517 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,13516 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 13517 /*128:out */ X86_MXCSR_RC_ZERO, 13518 13518 /*256:out */ -1 }, 13519 13519 { { /*src1 */ { FP32_V(0, 0x600000, 0x7e)/*0.875*/, FP32_RAND_x7_V4 } }, … … 13526 13526 { /*unused */ { FP32_RAND_V1(0), FP32_RAND_x7_V3 } }, 13527 13527 { /* => */ { FP32_V(0, 2293760, 125), FP32_RAND_x7_V3 } }, 13528 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,13529 /*128:out */ X86_MXCSR_XCPT_MASK,13528 /*mxcsr:in */ 0, 13529 /*128:out */ 0, 13530 13530 /*256:out */ -1 }, 13531 13531 { { /*src1 */ { FP32_V(0, 0x490fda, 0x80)/*3.1415926*/, FP32_RAND_x7_V2 } }, … … 13620 13620 { /*unused */ { FP32_ROW_UNUSED } }, 13621 13621 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1) } }, 13622 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,13623 /*128:out */ X86_MXCSR_XCPT_MASK,13624 /*256:out */ X86_MXCSR_XCPT_MASK},13622 /*mxcsr:in */ 0, 13623 /*128:out */ 0, 13624 /*256:out */ 0 }, 13625 13625 { { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1) } }, 13626 13626 { /*unused */ { FP32_ROW_UNUSED } }, … … 13638 13638 { /*unused */ { FP32_ROW_UNUSED } }, 13639 13639 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1) } }, 13640 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,13641 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,13642 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },13640 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 13641 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 13642 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN }, 13643 13643 /* 13644 13644 * Infinity. … … 13662 13662 { /*unused */ { FP32_ROW_UNUSED } }, 13663 13663 { /* => */ { FP32_0(0), FP32_1(0), FP32_1(0), FP32_0(1), FP32_1(0), FP32_0(0), FP32_1(0), FP32_V(0, 0x3504f3, 0x7f)/*sqrt(2)*/ } }, 13664 /*mxcsr:in */ X86_MXCSR_ PM | X86_MXCSR_RC_DOWN,13665 /*128:out */ X86_MXCSR_ PM | X86_MXCSR_RC_DOWN,13666 /*256:out */ X86_MXCSR_ PM | X86_MXCSR_RC_DOWN | X86_MXCSR_PE },13664 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 13665 /*128:out */ X86_MXCSR_RC_DOWN, 13666 /*256:out */ X86_MXCSR_RC_DOWN | X86_MXCSR_PE }, 13667 13667 { { /*src1 */ { FP32_0(0), FP32_1(0), FP32_1(0), FP32_0(1), FP32_1(0), FP32_0(0), FP32_1(0), FP32_2(0) } }, 13668 13668 { /*unused */ { FP32_ROW_UNUSED } }, 13669 13669 { /* => */ { FP32_0(0), FP32_1(0), FP32_1(0), FP32_0(1), FP32_1(0), FP32_0(0), FP32_1(0), FP32_V(0, 0x3504f4, 0x7f)/*sqrt^(2)*/ } }, 13670 /*mxcsr:in */ X86_MXCSR_ PM | X86_MXCSR_RC_UP,13671 /*128:out */ X86_MXCSR_ PM | X86_MXCSR_RC_UP,13672 /*256:out */ X86_MXCSR_ PM | X86_MXCSR_RC_UP | X86_MXCSR_PE },13670 /*mxcsr:in */ X86_MXCSR_RC_UP, 13671 /*128:out */ X86_MXCSR_RC_UP, 13672 /*256:out */ X86_MXCSR_RC_UP | X86_MXCSR_PE }, 13673 13673 { { /*src1 */ { FP32_0(0), FP32_1(0), FP32_1(0), FP32_0(1), FP32_1(0), FP32_0(0), FP32_1(0), FP32_2(0) } }, 13674 13674 { /*unused */ { FP32_ROW_UNUSED } }, 13675 13675 { /* => */ { FP32_0(0), FP32_1(0), FP32_1(0), FP32_0(1), FP32_1(0), FP32_0(0), FP32_1(0), FP32_V(0, 0x3504f3, 0x7f)/*sqrt(2)*/ } }, 13676 /*mxcsr:in */ X86_MXCSR_ PM | X86_MXCSR_RC_ZERO,13677 /*128:out */ X86_MXCSR_ PM | X86_MXCSR_RC_ZERO,13678 /*256:out */ X86_MXCSR_ PM | X86_MXCSR_RC_ZERO | X86_MXCSR_PE },13676 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 13677 /*128:out */ X86_MXCSR_RC_ZERO, 13678 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE }, 13679 13679 { { /*src1 */ { FP32_0(0), FP32_1(0), FP32_1(0), FP32_0(1), FP32_1(0), FP32_0(0), FP32_1(0), FP32_2(0) } }, 13680 13680 { /*unused */ { FP32_ROW_UNUSED } }, 13681 13681 { /* => */ { FP32_0(0), FP32_1(0), FP32_1(0), FP32_0(1), FP32_1(0), FP32_0(0), FP32_1(0), FP32_V(0, 0x3504f3, 0x7f)/*sqrt(2)*/ } }, 13682 /*mxcsr:in */ X86_MXCSR_ PM | X86_MXCSR_FZ | X86_MXCSR_DAZ,13683 /*128:out */ X86_MXCSR_ PM | X86_MXCSR_FZ | X86_MXCSR_DAZ,13684 /*256:out */ X86_MXCSR_ PM | X86_MXCSR_FZ | X86_MXCSR_DAZ | X86_MXCSR_PE },13682 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_DAZ, 13683 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_DAZ, 13684 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_DAZ | X86_MXCSR_PE }, 13685 13685 /* 13686 13686 * Normals. … … 13696 13696 FP32_V(0,0x561776,0x5d)/*sqrt(FP32_NORM_V6)*/, 13697 13697 FP32_V(0,0x3504f3,0x68)/*sqrt(FP32_NORM_V7)*/ } }, 13698 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,13699 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_PE,13700 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_PE },13698 /*mxcsr:in */ 0, 13699 /*128:out */ X86_MXCSR_PE, 13700 /*256:out */ X86_MXCSR_PE }, 13701 13701 { { /*src1 */ { FP32_V(0,0x44000,0x88)/*529.0*/, 13702 13702 FP32_V(0,0x0,0x87)/*256.0*/, … … 13716 13716 FP32_V(0,0x5fffff,0x7d)/*7/16-*/, 13717 13717 FP32_V(0,0x778001,0x85)/*123.75+*/ } }, 13718 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,13719 /*128:out */ X86_MXCSR_XCPT_MASK,13720 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_PE },13718 /*mxcsr:in */ 0, 13719 /*128:out */ 0, 13720 /*256:out */ X86_MXCSR_PE }, 13721 13721 { { /*src1 */ { FP32_V(0,0x44000,0x88)/*529.0*/, 13722 13722 FP32_V(0,0x0,0x87)/*256.0*/, … … 13736 13736 FP32_V(0,0x5fffff,0x7d)/*7/16-*/, 13737 13737 FP32_V(0,0x778000,0x85)/*123.75[DOWN]*/ } }, 13738 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,13739 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,13740 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_PE | X86_MXCSR_RC_DOWN },13738 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 13739 /*128:out */ X86_MXCSR_RC_DOWN, 13740 /*256:out */ X86_MXCSR_PE | X86_MXCSR_RC_DOWN }, 13741 13741 { { /*src1 */ { FP32_V(0,0x44000,0x88)/*529.0*/, 13742 13742 FP32_V(0,0x0,0x87)/*256.0*/, … … 13756 13756 FP32_V(0,0x600000,0x7d)/*7/16[UP]*/, 13757 13757 FP32_V(0,0x778001,0x85)/*123.75+*/ } }, 13758 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,13759 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,13760 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_PE | X86_MXCSR_RC_UP },13758 /*mxcsr:in */ X86_MXCSR_RC_UP, 13759 /*128:out */ X86_MXCSR_RC_UP, 13760 /*256:out */ X86_MXCSR_PE | X86_MXCSR_RC_UP }, 13761 13761 { { /*src1 */ { FP32_V(0,0x44000,0x88)/*529.0*/, 13762 13762 FP32_V(0,0x0,0x87)/*256.0*/, … … 13776 13776 FP32_V(0,0x5fffff,0x7d)/*7/16-*/, 13777 13777 FP32_V(0,0x778000,0x85)/*123.75[ZERO=DOWN]*/ } }, 13778 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,13779 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,13780 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_PE | X86_MXCSR_RC_ZERO },13778 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 13779 /*128:out */ X86_MXCSR_RC_ZERO, 13780 /*256:out */ X86_MXCSR_PE | X86_MXCSR_RC_ZERO }, 13781 13781 { { /*src1 */ { FP32_NORM_MAX(0), 13782 13782 FP32_NORM_MIN(0), … … 13796 13796 FP32_QNAN(1), 13797 13797 FP32_QNAN(1) } }, 13798 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ,13799 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_PE,13800 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_PE | X86_MXCSR_IE | BS3_MXCSR_PE_FUZZY /* IEM */ },13798 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 13799 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_PE, 13800 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_PE | X86_MXCSR_IE | BS3_MXCSR_PE_FUZZY /* IEM */ }, 13801 13801 /** @todo More Normals. */ 13802 13802 /* … … 13818 13818 { /*unused */ { FP32_ROW_UNUSED } }, 13819 13819 { /* => */ { FP32_V(0,0x3504f3+1,0x34), FP32_V(0,0x7fffff,0x3f), FP32_0(0), FP32_0(1), FP32_QNAN(1), FP32_QNAN(1), FP32_0(1), FP32_0(0) } }, 13820 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,13821 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_RC_UP,13822 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_IE | X86_MXCSR_PE | X86_MXCSR_RC_UP | BS3_MXCSR_PE_FUZZY /* IEM */ },13820 /*mxcsr:in */ X86_MXCSR_RC_UP, 13821 /*128:out */ X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_RC_UP, 13822 /*256:out */ X86_MXCSR_DE | X86_MXCSR_IE | X86_MXCSR_PE | X86_MXCSR_RC_UP | BS3_MXCSR_PE_FUZZY /* IEM */ }, 13823 13823 { { /*src1 */ { FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(1), FP32_DENORM_MIN(1), FP32_DENORM_MAX(1), FP32_0(1), FP32_0(0) } }, 13824 13824 { /*unused */ { FP32_ROW_UNUSED } }, 13825 13825 { /* => */ { FP32_V(0,0x3504f3,0x34), FP32_V(0,0x7fffff-1,0x3f), FP32_0(0), FP32_0(1), FP32_QNAN(1), FP32_QNAN(1), FP32_0(1), FP32_0(0) } }, 13826 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,13827 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_RC_DOWN,13828 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_IE | X86_MXCSR_PE | X86_MXCSR_RC_DOWN | BS3_MXCSR_PE_FUZZY /* IEM */ },13826 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 13827 /*128:out */ X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_RC_DOWN, 13828 /*256:out */ X86_MXCSR_DE | X86_MXCSR_IE | X86_MXCSR_PE | X86_MXCSR_RC_DOWN | BS3_MXCSR_PE_FUZZY /* IEM */ }, 13829 13829 { { /*src1 */ { FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(1), FP32_DENORM_MIN(1), FP32_DENORM_MAX(1), FP32_0(1), FP32_0(0) } }, 13830 13830 { /*unused */ { FP32_ROW_UNUSED } }, 13831 13831 { /* => */ { FP32_V(0,0x3504f3,0x34), FP32_V(0,0x7fffff-1,0x3f), FP32_0(0), FP32_0(1), FP32_QNAN(1), FP32_QNAN(1), FP32_0(1), FP32_0(0) } }, 13832 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,13833 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_RC_ZERO,13834 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_IE | X86_MXCSR_PE | X86_MXCSR_RC_ZERO | BS3_MXCSR_PE_FUZZY /* IEM */ },13832 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 13833 /*128:out */ X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_RC_ZERO, 13834 /*256:out */ X86_MXCSR_DE | X86_MXCSR_IE | X86_MXCSR_PE | X86_MXCSR_RC_ZERO | BS3_MXCSR_PE_FUZZY /* IEM */ }, 13835 13835 { { /*src1 */ { FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(1), FP32_DENORM_MIN(1), FP32_DENORM_MAX(1), FP32_0(1), FP32_0(0) } }, 13836 13836 { /*unused */ { FP32_ROW_UNUSED } }, 13837 13837 { /* => */ { FP32_V(0,0x3504f3,0x34), FP32_V(0,0x7fffff,0x3f), FP32_0(0), FP32_0(1), FP32_QNAN(1), FP32_QNAN(1), FP32_0(1), FP32_0(0) } }, 13838 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ,13839 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_FZ,13840 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_IE | X86_MXCSR_PE | X86_MXCSR_FZ | BS3_MXCSR_PE_FUZZY /* IEM */ },13838 /*mxcsr:in */ X86_MXCSR_FZ, 13839 /*128:out */ X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_FZ, 13840 /*256:out */ X86_MXCSR_DE | X86_MXCSR_IE | X86_MXCSR_PE | X86_MXCSR_FZ | BS3_MXCSR_PE_FUZZY /* IEM */ }, 13841 13841 { { /*src1 */ { FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(1), FP32_DENORM_MIN(1), FP32_DENORM_MAX(1), FP32_0(1), FP32_0(0) } }, 13842 13842 { /*unused */ { FP32_ROW_UNUSED } }, 13843 13843 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0) } }, 13844 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,13845 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,13846 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ },13844 /*mxcsr:in */ X86_MXCSR_DAZ, 13845 /*128:out */ X86_MXCSR_DAZ, 13846 /*256:out */ X86_MXCSR_DAZ }, 13847 13847 /** @todo More Denormals. */ 13848 13848 /* … … 13918 13918 { /*unused */ { FP64_ROW_UNUSED } }, 13919 13919 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(1) } }, 13920 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,13921 /*128:out */ X86_MXCSR_XCPT_MASK,13922 /*256:out */ X86_MXCSR_XCPT_MASK},13920 /*mxcsr:in */ 0, 13921 /*128:out */ 0, 13922 /*256:out */ 0 }, 13923 13923 { { /*src1 */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } }, 13924 13924 { /*unused */ { FP64_ROW_UNUSED } }, … … 13936 13936 { /*unused */ { FP64_ROW_UNUSED } }, 13937 13937 { /* => */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(1) } }, 13938 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,13939 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,13940 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },13938 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 13939 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 13940 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN }, 13941 13941 /* 13942 13942 * Infinity. … … 13960 13960 { /*unused */ { FP64_ROW_UNUSED } }, 13961 13961 { /* => */ { FP64_0(0), FP64_1(0), FP64_0(1), FP64_V(0,0x6a09e667f3bcc,0x3ff)/*sqrt(2)v*/ } }, 13962 /*mxcsr:in */ X86_MXCSR_ PM | X86_MXCSR_RC_DOWN,13963 /*128:out */ X86_MXCSR_ PM | X86_MXCSR_RC_DOWN,13964 /*256:out */ X86_MXCSR_ PM | X86_MXCSR_RC_DOWN | X86_MXCSR_PE },13962 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 13963 /*128:out */ X86_MXCSR_RC_DOWN, 13964 /*256:out */ X86_MXCSR_RC_DOWN | X86_MXCSR_PE }, 13965 13965 { { /*src1 */ { FP64_0(0), FP64_1(0), FP64_0(1), FP64_2(0) } }, 13966 13966 { /*unused */ { FP64_ROW_UNUSED } }, 13967 13967 { /* => */ { FP64_0(0), FP64_1(0), FP64_0(1), FP64_V(0,0x6a09e667f3bcd,0x3ff)/*sqrt(2)*/ } }, 13968 /*mxcsr:in */ X86_MXCSR_ PM | X86_MXCSR_RC_UP,13969 /*128:out */ X86_MXCSR_ PM | X86_MXCSR_RC_UP,13970 /*256:out */ X86_MXCSR_ PM | X86_MXCSR_RC_UP | X86_MXCSR_PE },13968 /*mxcsr:in */ X86_MXCSR_RC_UP, 13969 /*128:out */ X86_MXCSR_RC_UP, 13970 /*256:out */ X86_MXCSR_RC_UP | X86_MXCSR_PE }, 13971 13971 { { /*src1 */ { FP64_0(0), FP64_1(0), FP64_0(1), FP64_2(0) } }, 13972 13972 { /*unused */ { FP64_ROW_UNUSED } }, 13973 13973 { /* => */ { FP64_0(0), FP64_1(0), FP64_0(1), FP64_V(0,0x6a09e667f3bcc,0x3ff)/*sqrt(2)v*/ } }, 13974 /*mxcsr:in */ X86_MXCSR_ PM | X86_MXCSR_RC_ZERO,13975 /*128:out */ X86_MXCSR_ PM | X86_MXCSR_RC_ZERO,13976 /*256:out */ X86_MXCSR_ PM | X86_MXCSR_RC_ZERO | X86_MXCSR_PE },13974 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 13975 /*128:out */ X86_MXCSR_RC_ZERO, 13976 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE }, 13977 13977 { { /*src1 */ { FP64_0(0), FP64_1(0), FP64_0(1), FP64_2(0) } }, 13978 13978 { /*unused */ { FP64_ROW_UNUSED } }, 13979 13979 { /* => */ { FP64_0(0), FP64_1(0), FP64_0(1), FP64_V(0,0x6a09e667f3bcd,0x3ff)/*sqrt(2)*/ } }, 13980 /*mxcsr:in */ X86_MXCSR_ PM | X86_MXCSR_FZ | X86_MXCSR_DAZ,13981 /*128:out */ X86_MXCSR_ PM | X86_MXCSR_FZ | X86_MXCSR_DAZ,13982 /*256:out */ X86_MXCSR_ PM | X86_MXCSR_FZ | X86_MXCSR_DAZ | X86_MXCSR_PE },13980 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_DAZ, 13981 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_DAZ, 13982 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_DAZ | X86_MXCSR_PE }, 13983 13983 /* 13984 13984 * Normals. … … 13990 13990 FP64_V(0,0x568cddb7b5f47,0x5fe)/*sqrt(FP64_NORM_V2)*/, 13991 13991 FP64_V(0,0x4ebe86dd38102,0x440)/*sqrt(FP64_NORM_V3)*/ } }, 13992 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,13993 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_PE,13994 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_PE },13992 /*mxcsr:in */ 0, 13993 /*128:out */ X86_MXCSR_PE, 13994 /*256:out */ X86_MXCSR_PE }, 13995 13995 { { /*src1 */ { FP64_V(0,0xf46c4c48b9b90,0x42f)/*23456789^2*/, 13996 13996 FP64_V(0,0x153e1f1867880,0x408)/*(12345678/524288)^2*/, … … 14002 14002 FP64_V(0,0x65ec150000006,0x417)/*23456789+*/, 14003 14003 FP64_V(0,0x78c29bfffffff,0x403)/*12345678/524288-*/ } }, 14004 /*mxcsr:in */ X86_MXCSR_XCPT_MASK,14005 /*128:out */ X86_MXCSR_XCPT_MASK,14006 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_PE },14004 /*mxcsr:in */ 0, 14005 /*128:out */ 0, 14006 /*256:out */ X86_MXCSR_PE }, 14007 14007 { { /*src1 */ { FP64_V(0,0xf46c4c48b9b90,0x42f)/*23456789^2*/, 14008 14008 FP64_V(0,0x153e1f1867880,0x408)/*(12345678/524288)^2*/, … … 14014 14014 FP64_V(0,0x65ec150000005,0x417)/*23456789+[DOWN]*/, 14015 14015 FP64_V(0,0x78c29bfffffff,0x403)/*12345678/524288-*/ } }, 14016 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,14017 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,14018 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_PE | X86_MXCSR_RC_DOWN },14016 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 14017 /*128:out */ X86_MXCSR_RC_DOWN, 14018 /*256:out */ X86_MXCSR_PE | X86_MXCSR_RC_DOWN }, 14019 14019 { { /*src1 */ { FP64_V(0,0xf46c4c48b9b90,0x42f)/*23456789^2*/, 14020 14020 FP64_V(0,0x153e1f1867880,0x408)/*(12345678/524288)^2*/, … … 14026 14026 FP64_V(0,0x65ec150000006,0x417)/*23456789+*/, 14027 14027 FP64_V(0,0x78c29c0000000,0x403)/*12345678/524288[UP]*/ } }, 14028 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,14029 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,14030 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_PE | X86_MXCSR_RC_UP },14028 /*mxcsr:in */ X86_MXCSR_RC_UP, 14029 /*128:out */ X86_MXCSR_RC_UP, 14030 /*256:out */ X86_MXCSR_PE | X86_MXCSR_RC_UP }, 14031 14031 { { /*src1 */ { FP64_V(0,0xf46c4c48b9b90,0x42f)/*23456789^2*/, 14032 14032 FP64_V(0,0x153e1f1867880,0x408)/*(12345678/524288)^2*/, … … 14038 14038 FP64_V(0,0x65ec150000005,0x417)/*23456789+[ZERO]*/, 14039 14039 FP64_V(0,0x78c29bfffffff,0x403)/*12345678/524288-*/ } }, 14040 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,14041 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,14042 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_PE | X86_MXCSR_RC_ZERO },14040 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 14041 /*128:out */ X86_MXCSR_RC_ZERO, 14042 /*256:out */ X86_MXCSR_PE | X86_MXCSR_RC_ZERO }, 14043 14043 { { /*src1 */ { FP64_NORM_MAX(0), 14044 14044 FP64_NORM_MIN(0), … … 14050 14050 FP64_QNAN(1), 14051 14051 FP64_QNAN(1) } }, 14052 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ,14053 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_PE,14054 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_PE | X86_MXCSR_IE | BS3_MXCSR_PE_FUZZY /* IEM */ },14052 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 14053 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_PE, 14054 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_PE | X86_MXCSR_IE | BS3_MXCSR_PE_FUZZY /* IEM */ }, 14055 14055 /** @todo More Normals. */ 14056 14056 /* … … 14072 14072 { /*unused */ { FP64_ROW_UNUSED } }, 14073 14073 { /* => */ { FP64_V(0,0x0,0x1e6), FP64_V(0,0xfffffffffffff,0x1ff), FP64_QNAN(1), FP64_QNAN(1) } }, 14074 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_UP,14075 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_RC_UP,14076 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_IE | X86_MXCSR_PE | X86_MXCSR_RC_UP | BS3_MXCSR_PE_FUZZY /* IEM */ },14074 /*mxcsr:in */ X86_MXCSR_RC_UP, 14075 /*128:out */ X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_RC_UP, 14076 /*256:out */ X86_MXCSR_DE | X86_MXCSR_IE | X86_MXCSR_PE | X86_MXCSR_RC_UP | BS3_MXCSR_PE_FUZZY /* IEM */ }, 14077 14077 { { /*src1 */ { FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(1), FP64_DENORM_MAX(1) } }, 14078 14078 { /*unused */ { FP64_ROW_UNUSED } }, 14079 14079 { /* => */ { FP64_V(0,0x0,0x1e6), FP64_V(0,0xffffffffffffe,0x1ff), FP64_QNAN(1), FP64_QNAN(1) } }, 14080 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_DOWN,14081 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_RC_DOWN,14082 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_IE | X86_MXCSR_PE | X86_MXCSR_RC_DOWN | BS3_MXCSR_PE_FUZZY /* IEM */ },14080 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 14081 /*128:out */ X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_RC_DOWN, 14082 /*256:out */ X86_MXCSR_DE | X86_MXCSR_IE | X86_MXCSR_PE | X86_MXCSR_RC_DOWN | BS3_MXCSR_PE_FUZZY /* IEM */ }, 14083 14083 { { /*src1 */ { FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(1), FP64_DENORM_MAX(1) } }, 14084 14084 { /*unused */ { FP64_ROW_UNUSED } }, 14085 14085 { /* => */ { FP64_V(0,0x0,0x1e6), FP64_V(0,0xffffffffffffe,0x1ff), FP64_QNAN(1), FP64_QNAN(1) } }, 14086 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_RC_ZERO,14087 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_RC_ZERO,14088 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_IE | X86_MXCSR_PE | X86_MXCSR_RC_ZERO | BS3_MXCSR_PE_FUZZY /* IEM */ },14086 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 14087 /*128:out */ X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_RC_ZERO, 14088 /*256:out */ X86_MXCSR_DE | X86_MXCSR_IE | X86_MXCSR_PE | X86_MXCSR_RC_ZERO | BS3_MXCSR_PE_FUZZY /* IEM */ }, 14089 14089 { { /*src1 */ { FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(1), FP64_DENORM_MAX(1) } }, 14090 14090 { /*unused */ { FP64_ROW_UNUSED } }, 14091 14091 { /* => */ { FP64_V(0,0x0,0x1e6), FP64_V(0,0xfffffffffffff,0x1ff), FP64_QNAN(1), FP64_QNAN(1) } }, 14092 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_FZ,14093 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_FZ,14094 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_IE | X86_MXCSR_PE | X86_MXCSR_FZ | BS3_MXCSR_PE_FUZZY /* IEM */ },14092 /*mxcsr:in */ X86_MXCSR_FZ, 14093 /*128:out */ X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_FZ, 14094 /*256:out */ X86_MXCSR_DE | X86_MXCSR_IE | X86_MXCSR_PE | X86_MXCSR_FZ | BS3_MXCSR_PE_FUZZY /* IEM */ }, 14095 14095 { { /*src1 */ { FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(1), FP64_DENORM_MAX(1) } }, 14096 14096 { /*unused */ { FP64_ROW_UNUSED } }, 14097 14097 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(1), } }, 14098 /*mxcsr:in */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,14099 /*128:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ,14100 /*256:out */ X86_MXCSR_ XCPT_MASK | X86_MXCSR_DAZ },14098 /*mxcsr:in */ X86_MXCSR_DAZ, 14099 /*128:out */ X86_MXCSR_DAZ, 14100 /*256:out */ X86_MXCSR_DAZ }, 14101 14101 /** @todo More Denormals. */ 14102 14102 /*
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