Index: /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32
===================================================================
--- /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32	(revision 106297)
+++ /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32	(revision 106298)
@@ -729,37 +729,37 @@
             { /*src1     */ { FP32_QNAN(0), FP32_QNAN(0),     FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } },       \
             { /* =>      */ { FP32_QNAN(0), FP32_QNAN(0),     FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } },       \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                               \
-              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                               \
-              /*256:out  */ X86_MXCSR_XCPT_MASK },                                                                                                                             \
+              /*mxcsr:in */ 0,                                                                                                                                                 \
+              /*128:out  */ 0,                                                                                                                                                 \
+              /*256:out  */ 0 },                                                                                                                                               \
           { { /*src2     */ { FP32_QNAN(0),      FP32_QNAN_MAX(0),  FP32_QNAN_V0(0),  FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \
             { /*src1     */ { FP32_SNAN(0),      FP32_SNAN(0),      FP32_SNAN_MAX(0), FP32_SNAN_V2(0), FP32_SNAN_V6(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V4(0) } }, \
             { /* =>      */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } }, \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                               \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE },                                                                                                              \
+              /*mxcsr:in */ 0,                                                                                                                                                 \
+              /*128:out  */ X86_MXCSR_IE,                                                                                                                                      \
+              /*256:out  */ X86_MXCSR_IE },                                                                                                                                    \
           { { /*src2     */ { FP32_SNAN(0), FP32_SNAN(0),     FP32_SNAN_V1(0), FP32_SNAN_V1(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V5(0), FP32_SNAN_V6(0) } },        \
             { /*src1     */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } },        \
             { /* =>      */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } },        \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,                                                                                                                \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,                                                                                                 \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE },                                                                                               \
+              /*mxcsr:in */ X86_MXCSR_FZ,                                                                                                                                      \
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_IE,                                                                                                                       \
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_IE },                                                                                                                     \
           { { /*src2     */ { FP32_SNAN(0),      FP32_SNAN(0),     FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V7(0), FP32_SNAN_V1(0), FP32_SNAN_V6(0), FP32_SNAN_V1(0) } },   \
             { /*src1     */ { FP32_SNAN(0),      FP32_SNAN_MAX(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } },   \
             { /* =>      */ { FP32_QNAN_V(0, 1), FP32_QNAN_MAX(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V5(0), FP32_QNAN_V3(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0) } },   \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                               \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE },                                                                                                              \
+              /*mxcsr:in */ 0,                                                                                                                                                 \
+              /*128:out  */ X86_MXCSR_IE,                                                                                                                                      \
+              /*256:out  */ X86_MXCSR_IE },                                                                                                                                    \
           { { /*src2     */ { FP32_QNAN(0), FP32_QNAN_MAX(1), FP32_NORM_V0(1),  FP32_QNAN_V1(0), FP32_NORM_V3(0), FP32_QNAN_V3(1), FP32_NORM_V5(0), FP32_QNAN_V5(1) } },       \
             { /*src1     */ { FP32_1(0),    FP32_1(1),        FP32_QNAN_V0(1),  FP32_NORM_V2(1), FP32_QNAN_V2(0), FP32_NORM_V4(0), FP32_QNAN_V4(1), FP32_NORM_V6(1) } },       \
             { /* =>      */ { FP32_QNAN(0), FP32_QNAN_MAX(1), FP32_QNAN_MAX(1), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(1), FP32_QNAN_V4(1), FP32_QNAN_V5(1) } },       \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                               \
-              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                               \
-              /*256:out  */ X86_MXCSR_XCPT_MASK },                                                                                                                             \
+              /*mxcsr:in */ 0,                                                                                                                                                 \
+              /*128:out  */ 0,                                                                                                                                                 \
+              /*256:out  */ 0 },                                                                                                                                               \
           { { /*src2     */ { FP32_SNAN(1),      FP32_SNAN_MAX(1), FP32_NORM_V0(1), FP32_SNAN_V1(0), FP32_NORM_V3(0), FP32_SNAN_V3(1), FP32_NORM_V5(0), FP32_SNAN_V5(1) } },   \
             { /*src1     */ { FP32_1(0),         FP32_1(0),        FP32_SNAN_V0(1), FP32_NORM_V2(1), FP32_SNAN_V2(1), FP32_NORM_V4(0), FP32_SNAN_V4(1), FP32_NORM_V6(1) } },   \
             { /* =>      */ { FP32_QNAN_V(1, 1), FP32_QNAN_MAX(1), FP32_QNAN_V0(1), FP32_QNAN_V1(0), FP32_QNAN_V2(1), FP32_QNAN_V3(1), FP32_QNAN_V4(1), FP32_QNAN_V5(1) } },   \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                               \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE },                                                                                                              \
+              /*mxcsr:in */ 0,                                                                                                                                                 \
+              /*128:out  */ X86_MXCSR_IE,                                                                                                                                      \
+              /*256:out  */ X86_MXCSR_IE },                                                                                                                                    \
           { { /*src2     */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0),  FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } },       \
             { /*src1     */ { FP32_QNAN(0), FP32_QNAN(0),     FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } },       \
@@ -807,37 +807,37 @@
             { /*src1     */ { FP64_QNAN(0), FP64_QNAN(0),     FP64_QNAN_MAX(0), FP64_QNAN_V2(0) } },       \
             { /* =>      */ { FP64_QNAN(0), FP64_QNAN(0),     FP64_QNAN_MAX(0), FP64_QNAN_V2(0) } },       \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                           \
-              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                           \
-              /*256:out  */ X86_MXCSR_XCPT_MASK },                                                         \
+              /*mxcsr:in */ 0,                                                                             \
+              /*128:out  */ 0,                                                                             \
+              /*256:out  */ 0 },                                                                           \
           { { /*src2     */ { FP64_QNAN(0),      FP64_QNAN_MAX(0),  FP64_QNAN_V0(0),  FP64_QNAN_V2(0) } }, \
             { /*src1     */ { FP64_SNAN(0),      FP64_SNAN(0),      FP64_SNAN_MAX(0), FP64_SNAN_V1(0) } }, \
             { /* =>      */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_MAX(0), FP64_QNAN_V1(0) } }, \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                           \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                            \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE },                                          \
+              /*mxcsr:in */ 0,                                                                             \
+              /*128:out  */ X86_MXCSR_IE,                                                                  \
+              /*256:out  */ X86_MXCSR_IE },                                                                \
           { { /*src2     */ { FP64_SNAN(0), FP64_SNAN(0),     FP64_SNAN_V0(0), FP64_SNAN_V1(0) } },        \
             { /*src1     */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V2(0), FP64_QNAN_V3(0) } },        \
             { /* =>      */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V2(0), FP64_QNAN_V3(0) } },        \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                           \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                            \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE },                                          \
+              /*mxcsr:in */ 0,                                                                             \
+              /*128:out  */ X86_MXCSR_IE,                                                                  \
+              /*256:out  */ X86_MXCSR_IE },                                                                \
           { { /*src2     */ { FP64_SNAN(0),      FP64_SNAN(0),     FP64_SNAN_V1(0), FP64_SNAN_V2(0) } },   \
             { /*src1     */ { FP64_SNAN(0),      FP64_SNAN_MAX(0), FP64_SNAN_V3(0), FP64_SNAN_V0(0) } },   \
             { /* =>      */ { FP64_QNAN_V(0, 1), FP64_QNAN_MAX(0), FP64_QNAN_V3(0), FP64_QNAN_V0(0) } },   \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                           \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                            \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE },                                          \
+              /*mxcsr:in */ 0,                                                                             \
+              /*128:out  */ X86_MXCSR_IE,                                                                  \
+              /*256:out  */ X86_MXCSR_IE },                                                                \
           { { /*src2     */ { FP64_QNAN(0), FP64_QNAN_MAX(1), FP64_NORM_V0(1), FP64_QNAN_V1(0) } },        \
             { /*src1     */ { FP64_1(0),    FP64_1(1),        FP64_QNAN_V0(1), FP64_NORM_V2(1) } },        \
             { /* =>      */ { FP64_QNAN(0), FP64_QNAN_MAX(1), FP64_QNAN_V0(1), FP64_QNAN_V1(0) } },        \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                           \
-              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                           \
-              /*256:out  */ X86_MXCSR_XCPT_MASK },                                                         \
+              /*mxcsr:in */ 0,                                                                             \
+              /*128:out  */ 0,                                                                             \
+              /*256:out  */ 0 },                                                                           \
           { { /*src2     */ { FP64_SNAN(1),      FP64_SNAN_MAX(1), FP64_NORM_V0(1), FP64_SNAN_V1(0) } },   \
             { /*src1     */ { FP64_1(0),         FP64_1(0),        FP64_SNAN_V0(1), FP64_NORM_V2(1) } },   \
             { /* =>      */ { FP64_QNAN_V(1, 1), FP64_QNAN_MAX(1), FP64_QNAN_V0(1), FP64_QNAN_V1(0) } },   \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                           \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                            \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE },                                          \
+              /*mxcsr:in */ 0,                                                                             \
+              /*128:out  */ X86_MXCSR_IE,                                                                  \
+              /*256:out  */ X86_MXCSR_IE },                                                                \
           { { /*src2     */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V0(0),  FP64_QNAN_V2(0) } },       \
             { /*src1     */ { FP64_QNAN(0), FP64_QNAN(0),     FP64_QNAN_MAX(0), FP64_QNAN_V3(0) } },       \
@@ -982,18 +982,18 @@
             { /*src1     */ { FP64_QNAN(0), FP64_QNAN(1),     FP64_QNAN_MAX(1), FP64_QNAN_V2(0) } },      \
             { /* =>      */ { FP64_QNAN(0), FP64_QNAN(1),     FP64_QNAN_MAX(1), FP64_QNAN_V2(0) } },      \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                          \
-              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                          \
+              /*mxcsr:in */ 0,                                                                            \
+              /*128:out  */ 0,                                                                            \
               /*256:out  */ -1 },                                                                         \
           { { /*src2     */ { FP64_QNAN_MAX(0), FP64_QNAN_V1(1), FP64_QNAN_V2(0), FP64_INF(0)  } },       \
             { /*src1     */ { FP64_QNAN(0),     FP64_QNAN_V2(1), FP64_QNAN_V3(1), FP64_SNAN(1) } },       \
             { /* =>      */ { FP64_QNAN(0),     FP64_QNAN_V2(1), FP64_QNAN_V3(1), FP64_SNAN(1) } },       \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                          \
-              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                          \
+              /*mxcsr:in */ 0,                                                                            \
+              /*128:out  */ 0,                                                                            \
               /*256:out  */ -1 },                                                                         \
           { { /*src2     */ { FP64_QNAN_V1(0), FP64_QNAN_V1(0), FP64_QNAN_V2(0), FP64_INF(1)  } },        \
             { /*src1     */ { FP64_QNAN_V0(0), FP64_QNAN_V2(0), FP64_QNAN_V3(1), FP64_QNAN(0) } },        \
             { /* =>      */ { FP64_QNAN_V0(0), FP64_QNAN_V2(0), FP64_QNAN_V3(1), FP64_QNAN(0) } },        \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                          \
-              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                          \
+              /*mxcsr:in */ 0,                                                                            \
+              /*128:out  */ 0,                                                                            \
               /*256:out  */ -1 },                                                                         \
     /* QNan, SNan (Masked). */                                                                            \
@@ -1001,18 +1001,18 @@
             { /*src1     */ { FP64_SNAN(0),      FP64_SNAN_V2(1), FP64_SNAN_V1(0), FP64_SNAN_V2(1) } },   \
             { /* =>      */ { FP64_QNAN_V(0, 1), FP64_SNAN_V2(1), FP64_SNAN_V1(0), FP64_SNAN_V2(1) } },   \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                          \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                           \
+              /*mxcsr:in */ 0,                                                                            \
+              /*128:out  */ X86_MXCSR_IE,                                                                 \
               /*256:out  */ -1 },                                                                         \
           { { /*src2     */ { FP64_QNAN_MAX(0),  FP64_QNAN_MAX(0), FP64_QNAN_V0(0),  FP64_QNAN_V1(0) } }, \
             { /*src1     */ { FP64_SNAN(0),      FP64_SNAN(1),     FP64_SNAN_MAX(1), FP64_SNAN_V2(0) } }, \
             { /* =>      */ { FP64_QNAN_V(0, 1), FP64_SNAN(1),     FP64_SNAN_MAX(1), FP64_SNAN_V2(0) } }, \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                          \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                           \
+              /*mxcsr:in */ 0,                                                                            \
+              /*128:out  */ X86_MXCSR_IE,                                                                 \
               /*256:out  */ -1 },                                                                         \
           { { /*src2     */ { FP64_QNAN_V1(0), FP64_QNAN_MAX(0), FP64_QNAN_V0(0),  FP64_INF(0)  } },      \
             { /*src1     */ { FP64_SNAN_V2(0), FP64_QNAN(0),     FP64_QNAN_MAX(1), FP64_QNAN(1) } },      \
             { /* =>      */ { FP64_QNAN_V2(0), FP64_QNAN(0),     FP64_QNAN_MAX(1), FP64_QNAN(1) } },      \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                          \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                           \
+              /*mxcsr:in */ 0,                                                                            \
+              /*128:out  */ X86_MXCSR_IE,                                                                 \
               /*256:out  */ -1 },                                                                         \
     /* SNan, QNan (Masked). */                                                                            \
@@ -1020,18 +1020,18 @@
             { /*src1     */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V3(1), FP64_QNAN_V2(1) } },       \
             { /* =>      */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V3(1), FP64_QNAN_V2(1) } },       \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                          \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                           \
+              /*mxcsr:in */ 0,                                                                            \
+              /*128:out  */ X86_MXCSR_IE,                                                                 \
               /*256:out  */ -1 },                                                                         \
           { { /*src2     */ { FP64_SNAN_MAX(0), FP64_SNAN_MAX(1), FP64_SNAN_V1(0), FP64_SNAN_V1(0) } },   \
             { /*src1     */ { FP64_QNAN(0),     FP64_QNAN(1),     FP64_QNAN_V3(1), FP64_QNAN_V2(0) } },   \
             { /* =>      */ { FP64_QNAN(0),     FP64_QNAN(1),     FP64_QNAN_V3(1), FP64_QNAN_V2(0) } },   \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                          \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                           \
+              /*mxcsr:in */ 0,                                                                            \
+              /*128:out  */ X86_MXCSR_IE,                                                                 \
               /*256:out  */ -1 },                                                                         \
           { { /*src2     */ { FP64_SNAN_V0(0), FP64_SNAN_MAX(0), FP64_SNAN_V1(0), FP64_SNAN_V1(0) } },    \
             { /*src1     */ { FP64_QNAN_V1(0), FP64_QNAN(1),     FP64_QNAN_V2(1), FP64_QNAN_V3(1) } },    \
             { /* =>      */ { FP64_QNAN_V1(0), FP64_QNAN(1),     FP64_QNAN_V2(1), FP64_QNAN_V3(1) } },    \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                          \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                           \
+              /*mxcsr:in */ 0,                                                                            \
+              /*128:out  */ X86_MXCSR_IE,                                                                 \
               /*256:out  */ -1 },                                                                         \
     /* SNan, SNan (Masked). */                                                                            \
@@ -1039,18 +1039,18 @@
             { /*src1     */ { FP64_SNAN(0),      FP64_SNAN_MAX(0), FP64_SNAN_V0(0), FP64_SNAN_V3(0) } },  \
             { /* =>      */ { FP64_QNAN_V(0, 1), FP64_SNAN_MAX(0), FP64_SNAN_V0(0), FP64_SNAN_V3(0) } },  \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                          \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                           \
+              /*mxcsr:in */ 0,                                                                            \
+              /*128:out  */ X86_MXCSR_IE,                                                                 \
               /*256:out  */ -1 },                                                                         \
           { { /*src2     */ { FP64_SNAN(0),     FP64_SNAN_V2(0), FP64_SNAN_V1(0), FP64_SNAN_V2(0) } },    \
             { /*src1     */ { FP64_SNAN_MAX(0), FP64_SNAN_V0(0), FP64_SNAN_V2(0), FP64_SNAN_V3(1) } },    \
             { /* =>      */ { FP64_QNAN_MAX(0), FP64_SNAN_V0(0), FP64_SNAN_V2(0), FP64_SNAN_V3(1) } },    \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                          \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                           \
+              /*mxcsr:in */ 0,                                                                            \
+              /*128:out  */ X86_MXCSR_IE,                                                                 \
               /*256:out  */ -1 },                                                                         \
           { { /*src2     */ { FP64_SNAN_V1(0), FP64_SNAN_V2(0), FP64_SNAN_V1(0), FP64_SNAN_V2(0) } },     \
             { /*src1     */ { FP64_SNAN_V0(0), FP64_SNAN_V3(0), FP64_SNAN_V0(0), FP64_SNAN_V3(0) } },     \
             { /* =>      */ { FP64_QNAN_V0(0), FP64_SNAN_V3(0), FP64_SNAN_V0(0), FP64_SNAN_V3(0) } },     \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                          \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                           \
+              /*mxcsr:in */ 0,                                                                            \
+              /*128:out  */ X86_MXCSR_IE,                                                                 \
               /*256:out  */ -1 },                                                                         \
     /* QNan, Norm FP (Masked). */                                                                         \
@@ -1058,6 +1058,6 @@
             { /*src1     */ { FP64_1(0),    FP64_1(1),        FP64_QNAN_V0(1), FP64_NORM_V2(1) } },       \
             { /* =>      */ { FP64_QNAN(0), FP64_1(1),        FP64_QNAN_V0(1), FP64_NORM_V2(1) } },       \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                          \
-              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                          \
+              /*mxcsr:in */ 0,                                                                            \
+              /*128:out  */ 0,                                                                            \
               /*256:out  */ -1 },                                                                         \
     /* SNan, Norm FP (Masked). */                                                                         \
@@ -1065,6 +1065,6 @@
             { /*src1     */ { FP64_1(0),         FP64_1(0),        FP64_SNAN_V0(1), FP64_NORM_V2(1) } },  \
             { /* =>      */ { FP64_QNAN_V(1, 1), FP64_1(0),        FP64_SNAN_V0(1), FP64_NORM_V2(1) } },  \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                          \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                           \
+              /*mxcsr:in */ 0,                                                                            \
+              /*128:out  */ X86_MXCSR_IE,                                                                 \
               /*256:out  */ -1 },                                                                         \
     /* QNan, QNan (Unmasked). */                                                                          \
@@ -1167,37 +1167,37 @@
             { /*src1     */ { FP32_QNAN(0),     FP32_QNAN(0), FP32_QNAN(0),     FP32_QNAN_MAX(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } },        \
             { /* =>      */ { FP32_QNAN(0),     FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0),  FP32_QNAN_V6(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0) } },        \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                 \
-              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                                 \
-              /*256:out  */ X86_MXCSR_XCPT_MASK },                                                                                                                               \
+              /*mxcsr:in */ 0,                                                                                                                                                   \
+              /*128:out  */ 0,                                                                                                                                                   \
+              /*256:out  */ 0 },                                                                                                                                                 \
           { { /*src2     */ { FP32_QNAN(0), FP32_SNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V1(0),  FP32_QNAN_V2(0), FP32_SNAN_V3(0), FP32_QNAN_V4(0), FP32_SNAN_V5(0) } },            \
             { /*src1     */ { FP32_QNAN(0), FP32_SNAN(0), FP32_QNAN(0),     FP32_SNAN_V2(0),  FP32_QNAN_V6(0), FP32_SNAN_V2(0), FP32_QNAN_V1(0), FP32_SNAN_V4(0) } },            \
             { /* =>      */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN(0),     FP32_QNAN_MAX(0), FP32_QNAN_V6(0), FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V4(0) } },            \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                 \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                  \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE },                                                                                                                \
+              /*mxcsr:in */ 0,                                                                                                                                                   \
+              /*128:out  */ X86_MXCSR_IE,                                                                                                                                        \
+              /*256:out  */ X86_MXCSR_IE },                                                                                                                                      \
           { { /*src2     */ { FP32_SNAN_MAX(0),  FP32_QNAN_V2(0),   FP32_SNAN_V1(0),  FP32_QNAN_V2(0), FP32_SNAN_V3(0), FP32_QNAN_V4(0), FP32_SNAN_V5(0), FP32_QNAN_V6(0) } },   \
             { /*src1     */ { FP32_SNAN(0),      FP32_QNAN(0),      FP32_SNAN(0),     FP32_QNAN_V5(0), FP32_SNAN_V4(0), FP32_QNAN_V3(0), FP32_SNAN_V2(0), FP32_QNAN_V1(0) } },   \
             { /* =>      */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_MAX(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V5(0) } },   \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                 \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                  \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE },                                                                                                                \
+              /*mxcsr:in */ 0,                                                                                                                                                   \
+              /*128:out  */ X86_MXCSR_IE,                                                                                                                                        \
+              /*256:out  */ X86_MXCSR_IE },                                                                                                                                      \
           { { /*src2     */ { FP32_SNAN(0),      FP32_SNAN_MAX(0),  FP32_SNAN_MAX(0),  FP32_SNAN(0),     FP32_SNAN_V7(0), FP32_SNAN_V1(0), FP32_SNAN_V6(0), FP32_SNAN_V1(0) } }, \
             { /*src1     */ { FP32_SNAN(0),      FP32_SNAN(0),      FP32_SNAN(0),      FP32_SNAN_MAX(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } }, \
             { /* =>      */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_V(0, 1), FP32_QNAN_MAX(0), FP32_QNAN_V5(0), FP32_QNAN_V1(0), FP32_QNAN_V7(0), FP32_QNAN_V6(0) } }, \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                 \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                  \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE },                                                                                                                \
+              /*mxcsr:in */ 0,                                                                                                                                                   \
+              /*128:out  */ X86_MXCSR_IE,                                                                                                                                        \
+              /*256:out  */ X86_MXCSR_IE },                                                                                                                                      \
           { { /*src2     */ { FP32_QNAN(0), FP32_NORM_V1(0),  FP32_QNAN_MAX(0), FP32_QNAN_V1(0),  FP32_QNAN_V1(0), FP32_NORM_V3(1), FP32_QNAN_V5(0), FP32_NORM_V5(1) } },        \
             { /*src1     */ { FP32_QNAN(0), FP32_1(1),        FP32_QNAN_MAX(1), FP32_NORM_V2(1),  FP32_QNAN_V2(0), FP32_NORM_V4(0), FP32_QNAN_V4(1), FP32_NORM_V6(1) } },        \
             { /* =>      */ { FP32_QNAN(0), FP32_QNAN_MAX(1), FP32_QNAN(0),     FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V4(1), FP32_QNAN_V1(0), FP32_QNAN_V5(0) } },        \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                 \
-              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                                                                                                 \
-              /*256:out  */ X86_MXCSR_XCPT_MASK },                                                                                                                               \
+              /*mxcsr:in */ 0,                                                                                                                                                   \
+              /*128:out  */ 0,                                                                                                                                                   \
+              /*256:out  */ 0 },                                                                                                                                                 \
           { { /*src2     */ { FP32_SNAN_MAX(1),  FP32_1(0),        FP32_SNAN_V1(0),  FP32_NORM_V3(0), FP32_SNAN_V0(0), FP32_NORM_V3(1), FP32_SNAN_V6(0), FP32_NORM_V7(1) } },    \
             { /*src1     */ { FP32_SNAN(0),      FP32_1(1),        FP32_SNAN_MAX(0), FP32_NORM_V2(1), FP32_SNAN_V2(1), FP32_NORM_V4(0), FP32_SNAN_V4(1), FP32_NORM_V6(1) } },    \
             { /* =>      */ { FP32_QNAN_V(0, 1), FP32_QNAN_MAX(0), FP32_QNAN_MAX(1), FP32_QNAN_V1(0), FP32_QNAN_V2(1), FP32_QNAN_V4(1), FP32_QNAN_V0(0), FP32_QNAN_V6(0) } },    \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                                 \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                                  \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE },                                                                                                                \
+              /*mxcsr:in */ 0,                                                                                                                                                   \
+              /*128:out  */ X86_MXCSR_IE,                                                                                                                                        \
+              /*256:out  */ X86_MXCSR_IE },                                                                                                                                      \
           { { /*src2     */ { FP32_QNAN_MAX(0), FP32_QNAN(0), FP32_QNAN_V0(0),  FP32_QNAN_V1(0),  FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V3(0), FP32_QNAN_V5(0) } },        \
             { /*src1     */ { FP32_QNAN(0),     FP32_QNAN(0), FP32_QNAN(0),     FP32_QNAN_MAX(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } },        \
@@ -1245,37 +1245,37 @@
             { /*src1     */ { FP64_QNAN(0),     FP64_QNAN(0),     FP64_QNAN(0),    FP64_QNAN_MAX(0) } },     \
             { /* =>      */ { FP64_QNAN(0),     FP64_QNAN_MAX(0), FP64_QNAN(0),    FP64_QNAN_V0(0)  } },     \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                             \
-              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                             \
-              /*256:out  */ X86_MXCSR_XCPT_MASK },                                                           \
+              /*mxcsr:in */ 0,                                                                               \
+              /*128:out  */ 0,                                                                               \
+              /*256:out  */ 0 },                                                                             \
           { { /*src2     */ { FP64_QNAN(0), FP64_SNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V1(0)  } },            \
             { /*src1     */ { FP64_QNAN(0), FP64_SNAN(0), FP64_QNAN(0),     FP64_SNAN_V2(0)  } },            \
             { /* =>      */ { FP64_QNAN(0), FP64_QNAN(0), FP64_QNAN(0),     FP64_QNAN_MAX(0) } },            \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                             \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                              \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE },                                            \
+              /*mxcsr:in */ 0,                                                                               \
+              /*128:out  */ X86_MXCSR_IE,                                                                    \
+              /*256:out  */ X86_MXCSR_IE },                                                                  \
           { { /*src2     */ { FP64_SNAN_MAX(0),  FP64_QNAN_V2(0),  FP64_SNAN_V1(0),   FP64_QNAN_V2(0) } },   \
             { /*src1     */ { FP64_SNAN(0),      FP64_QNAN(0),     FP64_SNAN(0),      FP64_QNAN_V3(0) } },   \
             { /* =>      */ { FP64_QNAN_V(0, 1), FP64_QNAN_MAX(0), FP64_QNAN_V(0, 1), FP64_QNAN_V1(0) } },   \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                             \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                              \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE },                                            \
+              /*mxcsr:in */ 0,                                                                               \
+              /*128:out  */ X86_MXCSR_IE,                                                                    \
+              /*256:out  */ X86_MXCSR_IE },                                                                  \
           { { /*src2     */ { FP64_SNAN(0),      FP64_SNAN_MAX(0),  FP64_SNAN_MAX(0),  FP64_SNAN(0)     } }, \
             { /*src1     */ { FP64_SNAN(0),      FP64_SNAN(0),      FP64_SNAN(0),      FP64_SNAN_MAX(0) } }, \
             { /* =>      */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1), FP64_QNAN_MAX(0) } }, \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                             \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                              \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE },                                            \
+              /*mxcsr:in */ 0,                                                                               \
+              /*128:out  */ X86_MXCSR_IE,                                                                    \
+              /*256:out  */ X86_MXCSR_IE },                                                                  \
           { { /*src2     */ { FP64_QNAN(0), FP64_NORM_V1(0), FP64_QNAN_MAX(0), FP64_QNAN_V1(0)  } },         \
             { /*src1     */ { FP64_QNAN(0), FP64_1(1),       FP64_QNAN_MAX(1), FP64_NORM_V2(1)  } },         \
             { /* =>      */ { FP64_QNAN(0), FP64_QNAN(0),    FP64_QNAN_MAX(1), FP64_QNAN_MAX(0) } },         \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                             \
-              /*128:out  */ X86_MXCSR_XCPT_MASK,                                                             \
-              /*256:out  */ X86_MXCSR_XCPT_MASK },                                                           \
+              /*mxcsr:in */ 0,                                                                               \
+              /*128:out  */ 0,                                                                               \
+              /*256:out  */ 0 },                                                                             \
           { { /*src2     */ { FP64_SNAN_MAX(1),  FP64_1(0),        FP64_SNAN_V1(0),  FP64_NORM_V3(0) } },    \
             { /*src1     */ { FP64_SNAN(0),      FP64_1(1),        FP64_SNAN_MAX(0), FP64_NORM_V2(1) } },    \
             { /* =>      */ { FP64_QNAN_V(0, 1), FP64_QNAN_MAX(1), FP64_QNAN_MAX(0), FP64_QNAN_V1(0) } },    \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                             \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                              \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE },                                            \
+              /*mxcsr:in */ 0,                                                                               \
+              /*128:out  */ X86_MXCSR_IE,                                                                    \
+              /*256:out  */ X86_MXCSR_IE },                                                                  \
           { { /*src2     */ { FP64_QNAN_MAX(0), FP64_QNAN(0),     FP64_QNAN_V0(0), FP64_QNAN_V1(0)  } },     \
             { /*src1     */ { FP64_QNAN(0),     FP64_QNAN(0),     FP64_QNAN(0),    FP64_QNAN_MAX(0) } },     \
@@ -1323,37 +1323,37 @@
             { /*src1     */ { FP32_QNAN(0), FP32_QNAN(0),     FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } }, \
             { /* =>      */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0),  FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                         \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                          \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE },                                                                                                        \
+              /*mxcsr:in */ 0,                                                                                                                                           \
+              /*128:out  */ X86_MXCSR_IE,                                                                                                                                \
+              /*256:out  */ X86_MXCSR_IE },                                                                                                                              \
           { { /*src2     */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0),  FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \
             { /*src1     */ { FP32_SNAN(0), FP32_SNAN(0),     FP32_SNAN_MAX(0), FP32_SNAN_V2(0), FP32_SNAN_V6(0), FP32_SNAN_V2(0), FP32_SNAN_V1(0), FP32_SNAN_V4(0) } }, \
             { /* =>      */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0),  FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                         \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                          \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE },                                                                                                        \
+              /*mxcsr:in */ 0,                                                                                                                                           \
+              /*128:out  */ X86_MXCSR_IE,                                                                                                                                \
+              /*256:out  */ X86_MXCSR_IE },                                                                                                                              \
           { { /*src2     */ { FP32_SNAN(0), FP32_SNAN(0),     FP32_SNAN_V1(0), FP32_SNAN_V1(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V5(0), FP32_SNAN_V6(0) } },  \
             { /*src1     */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V6(0), FP32_QNAN_V5(0), FP32_QNAN_V4(0), FP32_QNAN_V3(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0) } },  \
             { /* =>      */ { FP32_SNAN(0), FP32_SNAN(0),     FP32_SNAN_V1(0), FP32_SNAN_V1(0), FP32_SNAN_V3(0), FP32_SNAN_V4(0), FP32_SNAN_V5(0), FP32_SNAN_V6(0) } },  \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,                                                                                                          \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,                                                                                           \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE },                                                                                         \
+              /*mxcsr:in */ X86_MXCSR_FZ,                                                                                                                                \
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_IE,                                                                                                                 \
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_IE },                                                                                                               \
           { { /*src2     */ { FP32_SNAN(0), FP32_SNAN(0),     FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V7(0), FP32_SNAN_V1(0), FP32_SNAN_V6(0), FP32_SNAN_V1(0) } },  \
             { /*src1     */ { FP32_SNAN(0), FP32_SNAN_MAX(0), FP32_SNAN_V4(0), FP32_SNAN_V3(0), FP32_SNAN_V5(0), FP32_SNAN_V3(0), FP32_SNAN_V1(0), FP32_SNAN_V2(0) } },  \
             { /* =>      */ { FP32_SNAN(0), FP32_SNAN(0),     FP32_SNAN_V1(0), FP32_SNAN_V2(0), FP32_SNAN_V7(0), FP32_SNAN_V1(0), FP32_SNAN_V6(0), FP32_SNAN_V1(0) } },  \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                         \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                          \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE },                                                                                                        \
+              /*mxcsr:in */ 0,                                                                                                                                           \
+              /*128:out  */ X86_MXCSR_IE,                                                                                                                                \
+              /*256:out  */ X86_MXCSR_IE },                                                                                                                              \
           { { /*src2     */ { FP32_QNAN(0), FP32_QNAN_MAX(1), FP32_NORM_V0(1), FP32_QNAN_V1(0), FP32_NORM_V3(0), FP32_QNAN_V3(1), FP32_NORM_V5(0), FP32_QNAN_V5(1) } },  \
             { /*src1     */ { FP32_1(0),    FP32_1(1),        FP32_QNAN_V0(1), FP32_NORM_V2(1), FP32_QNAN_V2(0), FP32_NORM_V4(0), FP32_QNAN_V4(1), FP32_NORM_V6(1) } },  \
             { /* =>      */ { FP32_QNAN(0), FP32_QNAN_MAX(1), FP32_NORM_V0(1), FP32_QNAN_V1(0), FP32_NORM_V3(0), FP32_QNAN_V3(1), FP32_NORM_V5(0), FP32_QNAN_V5(1) } },  \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                         \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                          \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE },                                                                                                        \
+              /*mxcsr:in */ 0,                                                                                                                                           \
+              /*128:out  */ X86_MXCSR_IE,                                                                                                                                \
+              /*256:out  */ X86_MXCSR_IE },                                                                                                                              \
           { { /*src2     */ { FP32_SNAN(1), FP32_SNAN_MAX(1), FP32_NORM_V0(1), FP32_SNAN_V1(0), FP32_NORM_V3(0), FP32_SNAN_V3(1), FP32_NORM_V5(0), FP32_SNAN_V5(1) } },  \
             { /*src1     */ { FP32_1(0),    FP32_1(0),        FP32_SNAN_V0(1), FP32_NORM_V2(1), FP32_SNAN_V2(1), FP32_NORM_V4(0), FP32_SNAN_V4(1), FP32_NORM_V6(1) } },  \
             { /* =>      */ { FP32_SNAN(1), FP32_SNAN_MAX(1), FP32_NORM_V0(1), FP32_SNAN_V1(0), FP32_NORM_V3(0), FP32_SNAN_V3(1), FP32_NORM_V5(0), FP32_SNAN_V5(1) } },  \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                         \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                          \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE },                                                                                                        \
+              /*mxcsr:in */ 0,                                                                                                                                           \
+              /*128:out  */ X86_MXCSR_IE,                                                                                                                                \
+              /*256:out  */ X86_MXCSR_IE },                                                                                                                              \
           { { /*src2     */ { FP32_QNAN(0), FP32_QNAN_MAX(0), FP32_QNAN_V0(0),  FP32_QNAN_V1(0), FP32_QNAN_V2(0), FP32_QNAN_V3(0), FP32_QNAN_V4(0), FP32_QNAN_V5(0) } }, \
             { /*src1     */ { FP32_QNAN(0), FP32_QNAN(0),     FP32_QNAN_MAX(0), FP32_QNAN_V2(0), FP32_QNAN_V6(0), FP32_QNAN_V2(0), FP32_QNAN_V1(0), FP32_QNAN_V4(0) } }, \
@@ -1389,37 +1389,37 @@
             { /*src1     */ { FP64_QNAN(0), FP64_QNAN(0),     FP64_QNAN_MAX(0), FP64_QNAN_V2(0) } }, \
             { /* =>      */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V0(0),  FP64_QNAN_V1(0) } }, \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                     \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                      \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE },                                    \
+              /*mxcsr:in */ 0,                                                                       \
+              /*128:out  */ X86_MXCSR_IE,                                                            \
+              /*256:out  */ X86_MXCSR_IE },                                                          \
           { { /*src2     */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V0(0),  FP64_QNAN_V1(0) } }, \
             { /*src1     */ { FP64_SNAN(0), FP64_SNAN(0),     FP64_SNAN_MAX(0), FP64_SNAN_V2(0) } }, \
             { /* =>      */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V0(0),  FP64_QNAN_V1(0) } }, \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                     \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                      \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE },                                    \
+              /*mxcsr:in */ 0,                                                                       \
+              /*128:out  */ X86_MXCSR_IE,                                                            \
+              /*256:out  */ X86_MXCSR_IE },                                                          \
           { { /*src2     */ { FP64_SNAN(0), FP64_SNAN(0),     FP64_SNAN_V1(0), FP64_SNAN_V1(0) } },  \
             { /*src1     */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V2(0), FP64_QNAN_V3(0) } },  \
             { /* =>      */ { FP64_SNAN(0), FP64_SNAN(0),     FP64_SNAN_V1(0), FP64_SNAN_V1(0) } },  \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,                                      \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,                       \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE },                     \
+              /*mxcsr:in */ X86_MXCSR_FZ,                                                            \
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_IE,                                             \
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_IE },                                           \
           { { /*src2     */ { FP64_SNAN(0), FP64_SNAN(0),     FP64_SNAN_V1(0), FP64_SNAN_V2(0) } },  \
             { /*src1     */ { FP64_SNAN(0), FP64_SNAN_MAX(0), FP64_SNAN_V2(0), FP64_SNAN_V3(0) } },  \
             { /* =>      */ { FP64_SNAN(0), FP64_SNAN(0),     FP64_SNAN_V1(0), FP64_SNAN_V2(0) } },  \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                     \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                      \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE },                                    \
+              /*mxcsr:in */ 0,                                                                       \
+              /*128:out  */ X86_MXCSR_IE,                                                            \
+              /*256:out  */ X86_MXCSR_IE },                                                          \
           { { /*src2     */ { FP64_QNAN(0), FP64_QNAN_MAX(1), FP64_NORM_V0(1), FP64_QNAN_V1(0) } },  \
             { /*src1     */ { FP64_1(0),    FP64_1(1),        FP64_QNAN_V0(1), FP64_NORM_V2(1) } },  \
             { /* =>      */ { FP64_QNAN(0), FP64_QNAN_MAX(1), FP64_NORM_V0(1), FP64_QNAN_V1(0) } },  \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                     \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                      \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE },                                    \
+              /*mxcsr:in */ 0,                                                                       \
+              /*128:out  */ X86_MXCSR_IE,                                                            \
+              /*256:out  */ X86_MXCSR_IE },                                                          \
           { { /*src2     */ { FP64_SNAN(1), FP64_SNAN_MAX(1), FP64_NORM_V0(1), FP64_SNAN_V1(0) } },  \
             { /*src1     */ { FP64_1(0),    FP64_1(0),        FP64_SNAN_V0(1), FP64_NORM_V2(1) } },  \
             { /* =>      */ { FP64_SNAN(1), FP64_SNAN_MAX(1), FP64_NORM_V0(1), FP64_SNAN_V1(0) } },  \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                     \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                      \
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE },                                    \
+              /*mxcsr:in */ 0,                                                                       \
+              /*128:out  */ X86_MXCSR_IE,                                                            \
+              /*256:out  */ X86_MXCSR_IE },                                                          \
           { { /*src2     */ { FP64_QNAN(0), FP64_QNAN_MAX(0), FP64_QNAN_V0(0),  FP64_QNAN_V1(0) } }, \
             { /*src1     */ { FP64_QNAN(0), FP64_QNAN(0),     FP64_QNAN_MAX(0), FP64_QNAN_V2(0) } }, \
@@ -1456,18 +1456,18 @@
             { /*src1     */ { FP32_QNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V5(1), FP32_RAND_V6(1), FP32_RAND_V7(1), FP32_RAND_V1(1) } },     \
             { /* =>      */ { FP32_QNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V5(1), FP32_RAND_V6(1), FP32_RAND_V7(1), FP32_RAND_V1(1) } },     \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                           \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                            \
+              /*mxcsr:in */ 0,                                                                                                                                             \
+              /*128:out  */ X86_MXCSR_IE,                                                                                                                                  \
               /*256:out  */ -1 },                                                                                                                                          \
           { { /*src2     */ { FP32_QNAN_MAX(0), FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(0), FP32_RAND_V6(1) } }, \
             { /*src1     */ { FP32_QNAN(0),     FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V1(0) } }, \
             { /* =>      */ { FP32_QNAN_MAX(0), FP32_RAND_V7(1), FP32_RAND_V6(0), FP32_RAND_V5(1), FP32_RAND_V4(1), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V1(0) } }, \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                           \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                            \
+              /*mxcsr:in */ 0,                                                                                                                                             \
+              /*128:out  */ X86_MXCSR_IE,                                                                                                                                  \
               /*256:out  */ -1 },                                                                                                                                          \
           { { /*src2     */ { FP32_QNAN_V0(0),  FP32_RAND_V0(1), FP32_RAND_V7(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } }, \
             { /*src1     */ { FP32_QNAN_MAX(0), FP32_RAND_V1(0), FP32_RAND_V7(0), FP32_RAND_V2(1), FP32_RAND_V6(1), FP32_RAND_V3(1), FP32_RAND_V5(0), FP32_RAND_V4(1) } }, \
             { /* =>      */ { FP32_QNAN_V0(0),  FP32_RAND_V1(0), FP32_RAND_V7(0), FP32_RAND_V2(1), FP32_RAND_V6(1), FP32_RAND_V3(1), FP32_RAND_V5(0), FP32_RAND_V4(1) } }, \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                           \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                            \
+              /*mxcsr:in */ 0,                                                                                                                                             \
+              /*128:out  */ X86_MXCSR_IE,                                                                                                                                  \
               /*256:out  */ -1 },                                                                                                                                          \
     /* QNan, SNan (Masked). */                                                                                                                                             \
@@ -1475,18 +1475,18 @@
             { /*src1     */ { FP32_SNAN(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },     \
             { /* =>      */ { FP32_QNAN(0), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V6(0) } },     \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                           \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                            \
+              /*mxcsr:in */ 0,                                                                                                                                             \
+              /*128:out  */ X86_MXCSR_IE,                                                                                                                                  \
               /*256:out  */ -1 },                                                                                                                                          \
           { { /*src2     */ { FP32_QNAN_MAX(0), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V1(1), FP32_RAND_V0(1), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, \
             { /*src1     */ { FP32_SNAN(0),     FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V3(0) } }, \
             { /* =>      */ { FP32_QNAN_MAX(0), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V3(0) } }, \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                           \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                            \
+              /*mxcsr:in */ 0,                                                                                                                                             \
+              /*128:out  */ X86_MXCSR_IE,                                                                                                                                  \
               /*256:out  */ -1 },                                                                                                                                          \
           { { /*src2     */ { FP32_QNAN_V0(0),  FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V1(1), FP32_RAND_V0(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V6(1) } }, \
             { /*src1     */ { FP32_SNAN_MAX(0), FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V1(0) } }, \
             { /* =>      */ { FP32_QNAN_V0(0),  FP32_RAND_V3(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V1(0) } }, \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                           \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                            \
+              /*mxcsr:in */ 0,                                                                                                                                             \
+              /*128:out  */ X86_MXCSR_IE,                                                                                                                                  \
               /*256:out  */ -1 },                                                                                                                                          \
     /* SNan, QNan (Masked). */                                                                                                                                             \
@@ -1494,18 +1494,18 @@
             { /*src1     */ { FP32_QNAN(0), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V3(0) } },     \
             { /* =>      */ { FP32_SNAN(0), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V5(0), FP32_RAND_V2(1), FP32_RAND_V0(0), FP32_RAND_V1(0), FP32_RAND_V3(0) } },     \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,                                                                                                            \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,                                                                                             \
+              /*mxcsr:in */ X86_MXCSR_FZ,                                                                                                                                  \
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_IE,                                                                                                                   \
               /*256:out  */ -1 },                                                                                                                                          \
           { { /*src2     */ { FP32_SNAN(0),     FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V1(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V7(1) } }, \
             { /*src1     */ { FP32_QNAN_MAX(0), FP32_RAND_V2(0), FP32_RAND_V4(0), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V2(0) } }, \
             { /* =>      */ { FP32_SNAN(0),     FP32_RAND_V2(0), FP32_RAND_V4(0), FP32_RAND_V3(1), FP32_RAND_V2(0), FP32_RAND_V6(0), FP32_RAND_V7(1), FP32_RAND_V2(0) } }, \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                           \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                            \
+              /*mxcsr:in */ 0,                                                                                                                                             \
+              /*128:out  */ X86_MXCSR_IE,                                                                                                                                  \
               /*256:out  */ -1 },                                                                                                                                          \
           { { /*src2     */ { FP32_SNAN_V1(0), FP32_RAND_V1(1), FP32_RAND_V7(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } },  \
             { /*src1     */ { FP32_QNAN_V6(0), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V0(1), FP32_RAND_V2(0), FP32_RAND_V3(1) } },  \
             { /* =>      */ { FP32_SNAN_V1(0), FP32_RAND_V2(0), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V5(1), FP32_RAND_V0(1), FP32_RAND_V2(0), FP32_RAND_V3(1) } },  \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                           \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                            \
+              /*mxcsr:in */ 0,                                                                                                                                             \
+              /*128:out  */ X86_MXCSR_IE,                                                                                                                                  \
               /*256:out  */ -1 },                                                                                                                                          \
     /* SNan, SNan (Masked). */                                                                                                                                             \
@@ -1513,18 +1513,18 @@
             { /*src1     */ { FP32_SNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V7(0) } },     \
             { /* =>      */ { FP32_SNAN(0), FP32_RAND_V3(0), FP32_RAND_V4(0), FP32_RAND_V5(1), FP32_RAND_V2(1), FP32_RAND_V0(1), FP32_RAND_V1(0), FP32_RAND_V7(0) } },     \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                           \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                            \
+              /*mxcsr:in */ 0,                                                                                                                                             \
+              /*128:out  */ X86_MXCSR_IE,                                                                                                                                  \
               /*256:out  */ -1 },                                                                                                                                          \
           { { /*src2     */ { FP32_SNAN(0),     FP32_RAND_V1(0), FP32_RAND_V7(1), FP32_RAND_V2(1), FP32_RAND_V3(0), FP32_RAND_V4(1), FP32_RAND_V1(1), FP32_RAND_V2(1) } }, \
             { /*src1     */ { FP32_SNAN_MAX(0), FP32_RAND_V7(0), FP32_RAND_V5(0), FP32_RAND_V7(1), FP32_RAND_V6(1), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V2(1) } }, \
             { /* =>      */ { FP32_SNAN(0),     FP32_RAND_V7(0), FP32_RAND_V5(0), FP32_RAND_V7(1), FP32_RAND_V6(1), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V2(1) } }, \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                           \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                            \
+              /*mxcsr:in */ 0,                                                                                                                                             \
+              /*128:out  */ X86_MXCSR_IE,                                                                                                                                  \
               /*256:out  */ -1 },                                                                                                                                          \
           { { /*src2     */ { FP32_SNAN_V1(0), FP32_RAND_V1(1), FP32_RAND_V6(1), FP32_RAND_V2(0), FP32_RAND_V3(1), FP32_RAND_V4(0), FP32_RAND_V1(0), FP32_RAND_V2(0) } },  \
             { /*src1     */ { FP32_SNAN_V4(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V0(1) } },  \
             { /* =>      */ { FP32_SNAN_V1(0), FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V0(1) } },  \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                           \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                            \
+              /*mxcsr:in */ 0,                                                                                                                                             \
+              /*128:out  */ X86_MXCSR_IE,                                                                                                                                  \
               /*256:out  */ -1 },                                                                                                                                          \
     /* QNan, Normal (Masked). */                                                                                                                                           \
@@ -1532,6 +1532,6 @@
             { /*src1     */ { FP32_1(0),    FP32_RAND_V2(1), FP32_RAND_V4(1), FP32_RAND_V6(1), FP32_RAND_V2(1), FP32_RAND_V7(0), FP32_RAND_V3(0), FP32_RAND_V4(1) } },     \
             { /* =>      */ { FP32_QNAN(0), FP32_RAND_V2(1), FP32_RAND_V4(1), FP32_RAND_V6(1), FP32_RAND_V2(1), FP32_RAND_V7(0), FP32_RAND_V3(0), FP32_RAND_V4(1) } },     \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                           \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                            \
+              /*mxcsr:in */ 0,                                                                                                                                             \
+              /*128:out  */ X86_MXCSR_IE,                                                                                                                                  \
               /*256:out  */ -1 },                                                                                                                                          \
     /* SNan, Normal (Masked). */                                                                                                                                           \
@@ -1539,6 +1539,6 @@
             { /*src1     */ { FP32_1(0),    FP32_RAND_V0(1), FP32_RAND_V1(1), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V6(0), FP32_RAND_V7(0), FP32_RAND_V1(1) } },     \
             { /* =>      */ { FP32_SNAN(1), FP32_RAND_V0(1), FP32_RAND_V1(1), FP32_RAND_V3(1), FP32_RAND_V4(1), FP32_RAND_V6(0), FP32_RAND_V7(0), FP32_RAND_V1(1) } },     \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                                                                                           \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                                                                                            \
+              /*mxcsr:in */ 0,                                                                                                                                             \
+              /*128:out  */ X86_MXCSR_IE,                                                                                                                                  \
               /*256:out  */ -1 },                                                                                                                                          \
     /* QNan, QNan (Unmasked). */                                                                                                                                           \
@@ -1642,18 +1642,18 @@
             { /*src1     */ { FP64_QNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },     \
             { /* =>      */ { FP64_QNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },     \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                       \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                        \
+              /*mxcsr:in */ 0,                                                                         \
+              /*128:out  */ X86_MXCSR_IE,                                                              \
               /*256:out  */ -1 },                                                                      \
           { { /*src2     */ { FP64_QNAN_MAX(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(0) } }, \
             { /*src1     */ { FP64_QNAN(0),     FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V3(1) } }, \
             { /* =>      */ { FP64_QNAN_MAX(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V3(1) } }, \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                       \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                        \
+              /*mxcsr:in */ 0,                                                                         \
+              /*128:out  */ X86_MXCSR_IE,                                                              \
               /*256:out  */ -1 },                                                                      \
           { { /*src2     */ { FP64_QNAN_V0(0),  FP64_RAND_V0(1), FP64_RAND_V0(1), FP64_RAND_V2(0) } }, \
             { /*src1     */ { FP64_QNAN_MAX(0), FP64_RAND_V1(0), FP64_RAND_V0(0), FP64_RAND_V2(1) } }, \
             { /* =>      */ { FP64_QNAN_V0(0),  FP64_RAND_V1(0), FP64_RAND_V0(0), FP64_RAND_V2(1) } }, \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                       \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                        \
+              /*mxcsr:in */ 0,                                                                         \
+              /*128:out  */ X86_MXCSR_IE,                                                              \
               /*256:out  */ -1 },                                                                      \
     /* QNan, SNan (Masked). */                                                                         \
@@ -1661,18 +1661,18 @@
             { /*src1     */ { FP64_SNAN(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(0) } },     \
             { /* =>      */ { FP64_QNAN(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(0) } },     \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                       \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                        \
+              /*mxcsr:in */ 0,                                                                         \
+              /*128:out  */ X86_MXCSR_IE,                                                              \
               /*256:out  */ -1 },                                                                      \
           { { /*src2     */ { FP64_QNAN_MAX(0), FP64_RAND_V2(1), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, \
             { /*src1     */ { FP64_SNAN(0),     FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, \
             { /* =>      */ { FP64_QNAN_MAX(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                       \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                        \
+              /*mxcsr:in */ 0,                                                                         \
+              /*128:out  */ X86_MXCSR_IE,                                                              \
               /*256:out  */ -1 },                                                                      \
           { { /*src2     */ { FP64_QNAN_V0(0),  FP64_RAND_V1(1), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, \
             { /*src1     */ { FP64_SNAN_MAX(0), FP64_RAND_V3(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } }, \
             { /* =>      */ { FP64_QNAN_V0(0),  FP64_RAND_V3(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } }, \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                       \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                        \
+              /*mxcsr:in */ 0,                                                                         \
+              /*128:out  */ X86_MXCSR_IE,                                                              \
               /*256:out  */ -1 },                                                                      \
     /* SNan, QNan (Masked). */                                                                         \
@@ -1680,18 +1680,18 @@
             { /*src1     */ { FP64_QNAN(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } },     \
             { /* =>      */ { FP64_SNAN(0), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } },     \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,                                        \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,                         \
+              /*mxcsr:in */ X86_MXCSR_FZ,                                                              \
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_IE,                                               \
               /*256:out  */ -1 },                                                                      \
           { { /*src2     */ { FP64_SNAN(0),     FP64_RAND_V1(1), FP64_RAND_V3(0), FP64_RAND_V1(1) } }, \
             { /*src1     */ { FP64_QNAN_MAX(0), FP64_RAND_V2(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, \
             { /* =>      */ { FP64_SNAN(0),     FP64_RAND_V2(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                       \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                        \
+              /*mxcsr:in */ 0,                                                                         \
+              /*128:out  */ X86_MXCSR_IE,                                                              \
               /*256:out  */ -1 },                                                                      \
           { { /*src2     */ { FP64_SNAN_V1(0), FP64_RAND_V1(1), FP64_RAND_V0(1), FP64_RAND_V2(0) } },  \
             { /*src1     */ { FP64_QNAN_V1(0), FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } },  \
             { /* =>      */ { FP64_SNAN_V1(0), FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } },  \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                       \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                        \
+              /*mxcsr:in */ 0,                                                                         \
+              /*128:out  */ X86_MXCSR_IE,                                                              \
               /*256:out  */ -1 },                                                                      \
     /* SNan, SNan (Masked). */                                                                         \
@@ -1699,18 +1699,18 @@
             { /*src1     */ { FP64_SNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },     \
             { /* =>      */ { FP64_SNAN(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },     \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                       \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                        \
+              /*mxcsr:in */ 0,                                                                         \
+              /*128:out  */ X86_MXCSR_IE,                                                              \
               /*256:out  */ -1 },                                                                      \
           { { /*src2     */ { FP64_SNAN(0),     FP64_RAND_V1(0), FP64_RAND_V0(1), FP64_RAND_V2(1) } }, \
             { /*src1     */ { FP64_SNAN_MAX(0), FP64_RAND_V0(0), FP64_RAND_V3(0), FP64_RAND_V0(1) } }, \
             { /* =>      */ { FP64_SNAN(0),     FP64_RAND_V0(0), FP64_RAND_V3(0), FP64_RAND_V0(1) } }, \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                       \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                        \
+              /*mxcsr:in */ 0,                                                                         \
+              /*128:out  */ X86_MXCSR_IE,                                                              \
               /*256:out  */ -1 },                                                                      \
           { { /*src2     */ { FP64_SNAN_V1(0), FP64_RAND_V1(1), FP64_RAND_V1(1), FP64_RAND_V2(0) } },  \
             { /*src1     */ { FP64_SNAN_V2(0), FP64_RAND_V2(1), FP64_RAND_V3(1), FP64_RAND_V1(1) } },  \
             { /* =>      */ { FP64_SNAN_V1(0), FP64_RAND_V2(1), FP64_RAND_V3(1), FP64_RAND_V1(1) } },  \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                       \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                        \
+              /*mxcsr:in */ 0,                                                                         \
+              /*128:out  */ X86_MXCSR_IE,                                                              \
               /*256:out  */ -1 },                                                                      \
     /* QNan, Normal (Masked). */                                                                       \
@@ -1718,6 +1718,6 @@
             { /*src1     */ { FP64_1(0),    FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V1(1) } },     \
             { /* =>      */ { FP64_QNAN(0), FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V1(1) } },     \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                       \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                        \
+              /*mxcsr:in */ 0,                                                                         \
+              /*128:out  */ X86_MXCSR_IE,                                                              \
               /*256:out  */ -1 },                                                                      \
     /* SNan, Normal (Masked). */                                                                       \
@@ -1725,6 +1725,6 @@
             { /*src1     */ { FP64_1(0),    FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V3(1) } },     \
             { /* =>      */ { FP64_SNAN(1), FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V3(1) } },     \
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,                                                       \
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,                                        \
+              /*mxcsr:in */ 0,                                                                         \
+              /*128:out  */ X86_MXCSR_IE,                                                              \
               /*256:out  */ -1 },                                                                      \
     /* QNan, QNan (Unmasked). */                                                                       \
@@ -3111,7 +3111,7 @@
             { /*src1     */ { FP32_INF(1),  FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
             { /* =>      */ { FP32_QNAN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_IM,
-              /*128:out  */ X86_MXCSR_IM | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_IM | X86_MXCSR_IE },
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_IE },
           { { /*src2     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1),  FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
             { /*src1     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0),  FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
@@ -3225,7 +3225,7 @@
             { /*src1     */ { FP32_V(1, 0,        0x7d)/*-0.25*/, FP32_NORM_MAX(1), FP32_0(0), FP32_V(0, 0,        0x7e)/*0.50*/, FP32_V(1, 0,        0x7d)/*-0.25*/, FP32_NORM_MAX(1), FP32_0(0), FP32_V(0, 0,        0x7e)/*0.50*/ } },
             { /* =>      */ { FP32_V(0, 0x400000, 0x7f)/* 1.50*/, FP32_0(1),        FP32_0(0), FP32_V(0, 0x400000, 0x7e)/*0.75*/, FP32_V(0, 0x400000, 0x7f)/* 1.50*/, FP32_0(1),        FP32_0(0), FP32_V(0, 0x400000, 0x7e)/*0.75*/ } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
           { { /*src2     */ { FP32_NORM_MAX(0), FP32_NORM_V1(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_V1(0), FP32_0(0), FP32_0(0) } },
             { /*src1     */ { FP32_NORM_MAX(1), FP32_NORM_V1(1), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_V1(1), FP32_0(0), FP32_0(0) } },
@@ -3237,7 +3237,7 @@
             { /*src1     */ { FP32_V(0, 0x1ea980, 0x8f)/*  81235*/, FP32_V(0, 0x600000, 0x81)/* 7*/, FP32_V(0, 0x7c9000, 0x88)/*   1010.25*/, FP32_0(0), FP32_V(0, 0x600000, 0x81)/* 7*/, FP32_V(0, 0x7c9000, 0x88)/*   1010.25*/, FP32_1(1)                /*- 1.00*/, FP32_0(0) } },
             { /* =>      */ { FP32_V(0, 0x669050, 0x93)/*1888778*/, FP32_V(0, 0x780000, 0x84)/*62*/, FP32_V(0, 0x253468, 0x93)/*1353357.00*/, FP32_0(0), FP32_V(0, 0x780000, 0x84)/*62*/, FP32_V(0, 0x253468, 0x93)/*1353357.00*/, FP32_V(0, 0x524000, 0x86)/*210.25*/, FP32_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_RC_ZERO },
           { { /*src2     */ { FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_V(0, 0x3c614e, 0x96)/*12345678*/, FP32_0(0), FP32_0(0), FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_V(0, 0x3c614e, 0x96)/*12345678*/, FP32_1(1), FP32_0(0) } },
             { /*src1     */ { FP32_V(1, 0x712060, 0x92)/*- 987654*/, FP32_V(0, 0x3c614e, 0x96)/*12345678*/, FP32_0(0), FP32_1(0), FP32_V(1, 0x712060, 0x92)/*- 987654*/, FP32_V(0, 0x3c614e, 0x96)/*12345678*/, FP32_1(0), FP32_1(0) } },
@@ -3317,7 +3317,7 @@
             { /*src1     */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0) } },
             { /* =>      */ { FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0)          } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP },
           { { /*src2     */ { FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0),          FP32_0(0), FP32_0(0), FP32_0(0) } },
             { /*src1     */ { FP32_0(0),          FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
@@ -3344,13 +3344,13 @@
             { /*src1     */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0)          } },
             { /* =>      */ { FP32_0(0), FP32_0(0),          FP32_0(0), FP32_0(0), FP32_0(0),          FP32_0(0), FP32_0(0), FP32_0(0)          } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ },
+              /*mxcsr:in */ X86_MXCSR_DAZ,
+              /*128:out  */ X86_MXCSR_DAZ,
+              /*256:out  */ X86_MXCSR_DAZ },
           { { /*src2     */ { FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } },
             { /*src1     */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0) } },
             { /* =>      */ { FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0)          } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP },
     /** @todo More Denormals. */
     /*
@@ -3425,7 +3425,7 @@
             { /*src1     */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
             { /* =>      */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
             { /*src1     */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
@@ -3437,7 +3437,7 @@
             { /*src1     */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(0) } },
             { /* =>      */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN },
           { { /*src2     */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(1) } },
             { /*src1     */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(1) } },
@@ -3449,7 +3449,7 @@
             { /*src1     */ { FP64_0(1), FP64_0(0), FP64_0(1), FP64_0(0) } },
             { /* =>      */ { FP64_0(1), FP64_0(0), FP64_0(1), FP64_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
     /*
      * Infinity.
@@ -3458,31 +3458,31 @@
             { /*src1     */ { FP64_INF(1),  FP64_0(0), FP64_0(0), FP64_0(0) } },
             { /* =>      */ { FP64_QNAN(1), FP64_0(0), FP64_0(0), FP64_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM,
-              /*128:out  */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_IE },
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_IE },
           { { /*src2     */ { FP64_0(0), FP64_INF(1),  FP64_0(0), FP64_0(0) } },
             { /*src1     */ { FP64_0(0), FP64_INF(0),  FP64_0(0), FP64_0(0) } },
             { /* =>      */ { FP64_0(0), FP64_QNAN(1), FP64_0(0), FP64_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE },
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE },
           { { /*src2     */ { FP64_0(0), FP64_INF(1),  FP64_0(0), FP64_0(0) } },
             { /*src1     */ { FP64_0(0), FP64_INF(0),  FP64_0(0), FP64_0(0) } },
             { /* =>      */ { FP64_0(0), FP64_QNAN(1), FP64_0(0), FP64_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE },
           { { /*src2     */ { FP64_INF(0),  FP64_INF(1),  FP64_0(0), FP64_INF(1) } },
             { /*src1     */ { FP64_INF(1),  FP64_INF(0),  FP64_0(0), FP64_INF(0) } },
             { /* =>      */ { FP64_QNAN(1), FP64_QNAN(1), FP64_0(0), FP64_QNAN(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE },
           { { /*src2     */ { FP64_V(0, 0,               0x3fd)/*0.25*/, FP64_0(1), FP64_0(0), FP64_INF(1) } },
             { /*src1     */ { FP64_V(0, 0,               0x3fe)/*0.50*/, FP64_0(1), FP64_0(0), FP64_INF(0) } },
             { /* =>      */ { FP64_V(0, 0x8000000000000, 0x3fe)/*0.75*/, FP64_0(1), FP64_0(0), FP64_QNAN(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_IE },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE },
     /*
      * Overflow, Precision.
@@ -3503,19 +3503,19 @@
             { /*src1     */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1),                     FP64_0(0), FP64_NORM_MAX(0) } },
             { /* =>      */ { FP64_INF(0),      FP64_V(1, 0, FP32_EXP_NORM_MIN + 1),  FP64_0(0), FP64_INF(0)      } },
-              /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ,
-              /*128:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* i7-10700, IEM */,
-              /*256:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* i7-10700, IEM */ },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* i7-10700, IEM */,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* i7-10700, IEM */ },
           { { /*src2     */ { FP64_NORM_MIN(1),                     FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_0(0) } },
             { /*src1     */ { FP64_NORM_MIN(1),                     FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_0(0) } },
             { /* =>      */ { FP64_V(1, 0, FP32_EXP_NORM_MIN + 1),  FP64_INF(0),      FP64_0(0),        FP64_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_FZ,
-              /*128:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* i7-10700, IEM */,
-              /*256:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* i7-10700, IEM */ },
+              /*mxcsr:in */ X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* i7-10700, IEM */,
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* i7-10700, IEM */ },
           { { /*src2     */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } },
             { /*src1     */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } },
             { /* =>      */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* i7-10700, IEM */,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* i7-10700, IEM */ },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* i7-10700, IEM */,
+              /*256:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* i7-10700, IEM */ },
           { { /*src2     */ { FP64_NORM_SAFE_INT_MIN(0),                            FP64_NORM_MAX(0), FP64_0(0), FP64_NORM_SAFE_INT_MAX(1)                                } },
             { /*src1     */ { FP64_NORM_SAFE_INT_MAX(0),                            FP64_NORM_MAX(1), FP64_0(0), FP64_NORM_SAFE_INT_MAX(1)                                } },
@@ -3536,7 +3536,7 @@
             { /*src1     */ { FP64_V(0, 0,               0x408)/* 512*/, FP64_V(0, 0xc000000000000, 0x401)/* 7*/, FP64_0(0), FP64_0(0) } },
             { /* =>      */ { FP64_V(0, 0x8000000000000, 0x409)/*1536*/, FP64_V(0, 0xf000000000000, 0x404)/*62*/, FP64_0(0), FP64_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP64_V(0, 0x26580b4800000, 0x41d)/* 1234567890*/, FP64_V(0, 0xd6f3458800000, 0x41c)/*987654321*/, FP64_0(0), FP64_V(0, 0xcf0033a34f337, 0x432)/*4072598000007579.5*/ } },
             { /*src1     */ { FP64_V(1, 0x26580b4800000, 0x41d)/*-1234567890*/, FP64_V(1, 0x9000000000000, 0x405)/*     -100*/, FP64_0(0), FP64_V(0, 0xd6eca42000000, 0x419)/*       123450000.5*/ } },
@@ -3548,7 +3548,7 @@
             { /*src1     */ { FP64_1(0),                                                FP64_1(1),                                                FP64_0(0), FP64_0(0) } },
             { /* =>      */ { FP64_NORM_SAFE_INT_MAX(0),                                FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_0(0), FP64_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
           { { /*src2     */ { FP64_NORM_SAFE_INT_MAX(0),               FP64_1(1),                               FP64_0(0), FP64_0(0) } },
             { /*src1     */ { FP64_1(0),                               FP64_NORM_SAFE_INT_MAX(1),               FP64_0(0), FP64_0(0) } },
@@ -3572,7 +3572,7 @@
             { /*src1     */ { FP64_V(1, 0,               0x3fd)/*-0.25*/, FP64_NORM_MAX(1), FP64_0(0), FP64_V(0, 0,               0x3fe)/*0.50*/ } },
             { /* =>      */ { FP64_V(0, 0x8000000000000, 0x3ff)/* 1.50*/, FP64_0(1),        FP64_0(0), FP64_V(0, 0x8000000000000, 0x3fe)/*0.75*/ } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
     /*
      * Denormals.
@@ -3621,7 +3621,7 @@
             { /*src1     */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } },
             { /* =>      */ { FP64_0(0),          FP64_0(0),          FP64_0(0),          FP64_0(0)          } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP },
     /** @todo More denormals. */
     /*
@@ -3696,6 +3696,6 @@
             { /*src1     */ { FP32_0(0), FP32_0_x7(0) } },
             { /* =>      */ { FP32_0(0), FP32_0_x7(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_0(0), FP32_RAND_x7_V7 } },
@@ -3735,24 +3735,24 @@
             { /*src1     */ { FP32_INF(1),  FP32_0_x7(0) } },
             { /* =>      */ { FP32_QNAN(1), FP32_0_x7(0) } },
-              /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM,
-              /*128:out  */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_IE,
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_IE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_INF(0),  FP32_RAND_x7_V1 } },
             { /*src1     */ { FP32_INF(1),  FP32_RAND_x7_V2 } },
             { /* =>      */ { FP32_QNAN(1), FP32_RAND_x7_V2 } },
-              /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_INF(1),  FP32_RAND_x7_V4 } },
             { /*src1     */ { FP32_INF(0),  FP32_RAND_x7_V5 } },
             { /* =>      */ { FP32_QNAN(1), FP32_RAND_x7_V5 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
+              /*mxcsr:in */ X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_INF(0),  FP32_RAND_x7_V6 } },
             { /*src1     */ { FP32_INF(1),  FP32_RAND_x7_V3 } },
             { /* =>      */ { FP32_QNAN(1), FP32_RAND_x7_V3 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,
+              /*mxcsr:in */ X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_IE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_INF(0),  FP32_RAND_x7_V5 } },
@@ -3798,6 +3798,6 @@
             { /*src1     */ { FP32_NORM_MAX(1), FP32_RAND_x7_V1 } },
             { /* =>      */ { FP32_NORM_MAX(1), FP32_RAND_x7_V1 } },
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM,
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_PE,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_PE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_NORM_MAX(1), FP32_RAND_x7_V5 } },
@@ -3831,18 +3831,18 @@
             { /*src1     */ { FP32_V(1, 0,        0x7d)/*-0.25*/, FP32_RAND_x7_V2 } },
             { /* =>      */ { FP32_V(0, 0x400000, 0x7f)/* 1.50*/, FP32_RAND_x7_V2 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_NORM_MAX(0), FP32_RAND_x7_V3 } },
             { /*src1     */ { FP32_NORM_MAX(1), FP32_RAND_x7_V3 } },
             { /* =>      */ { FP32_0(0),        FP32_RAND_x7_V3 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_RAND_x7_V2 } },
             { /*src1     */ { FP32_V(0, 0x1ea980, 0x8f)/*  81235*/, FP32_RAND_x7_V1 } },
             { /* =>      */ { FP32_V(0, 0x669050, 0x93)/*1888778*/, FP32_RAND_x7_V1 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_RAND_x7_V1 } },
@@ -3861,12 +3861,12 @@
             { /*src1     */ { FP32_1(0),                                                FP32_RAND_x7_V2 } },
             { /* =>      */ { FP32_NORM_SAFE_INT_MAX(0),                                FP32_RAND_x7_V2 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_NORM_SAFE_INT_MAX(0),                                FP32_RAND_x7_V4 } },
             { /*src1     */ { FP32_1(1),                                                FP32_RAND_x7_V3 } },
             { /* =>      */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_RAND_x7_V3 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_V(0, 0x600000, 0x7e)/*      0.875*/, FP32_RAND_x7_V1 } },
@@ -3991,6 +3991,6 @@
             { /*src1     */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
             { /* =>      */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_0(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } },
@@ -4030,24 +4030,24 @@
             { /*src1     */ { FP64_INF(1),  FP64_0(0), FP64_0(0), FP64_0(0) } },
             { /* =>      */ { FP64_QNAN(1), FP64_0(0), FP64_0(0), FP64_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM,
-              /*128:out  */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_IE,
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_IE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_INF(0),  FP64_RAND_V1(0), FP64_RAND_V2(0), FP32_RAND_V3(1) } },
             { /*src1     */ { FP64_INF(1),  FP64_RAND_V0(0), FP64_RAND_V1(1), FP32_RAND_V1(1) } },
             { /* =>      */ { FP64_QNAN(1), FP64_RAND_V0(0), FP64_RAND_V1(1), FP32_RAND_V1(1) } },
-              /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_INF(1),  FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V1(1) } },
             { /*src1     */ { FP64_INF(0),  FP64_RAND_V1(1), FP64_RAND_V1(0), FP64_RAND_V0(1) } },
             { /* =>      */ { FP64_QNAN(1), FP64_RAND_V1(1), FP64_RAND_V1(0), FP64_RAND_V0(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
+              /*mxcsr:in */ X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_INF(0),  FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
             { /*src1     */ { FP64_INF(1),  FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V1(0) } },
             { /* =>      */ { FP64_QNAN(1), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V1(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,
+              /*mxcsr:in */ X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_IE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_INF(0),  FP64_RAND_V0(0), FP64_RAND_V0(0), FP64_RAND_V0(1) } },
@@ -4093,6 +4093,6 @@
             { /*src1     */ { FP64_NORM_MAX(1), FP64_RAND_V2(0), FP64_RAND_V0(1), FP64_RAND_V1(0) } },
             { /* =>      */ { FP64_NORM_MAX(1), FP64_RAND_V2(0), FP64_RAND_V0(1), FP64_RAND_V1(0) } },
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM,
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_PE,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_PE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_NORM_MAX(1), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V0(1) } },
@@ -4132,12 +4132,12 @@
             { /*src1     */ { FP64_V(0, 0,               0x408)/* 512*/, FP64_RAND_V2(1), FP64_RAND_V1(1), FP64_RAND_V3(0) } },
             { /* =>      */ { FP64_V(0, 0x8000000000000, 0x409)/*1536*/, FP64_RAND_V2(1), FP64_RAND_V1(1), FP64_RAND_V3(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_V(0, 0xb800000000000, 0x404)/*55*/, FP64_RAND_V2(1), FP64_RAND_V1(0), FP64_RAND_V0(1) } },
             { /*src1     */ { FP64_V(0, 0xc000000000000, 0x401)/* 7*/, FP64_RAND_V1(1), FP64_RAND_V3(1), FP64_RAND_V2(0) } },
             { /* =>      */ { FP64_V(0, 0xf000000000000, 0x404)/*62*/, FP64_RAND_V1(1), FP64_RAND_V3(1), FP64_RAND_V2(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_V(0, 0x26580b4800000, 0x41d)/* 1234567890*/, FP64_RAND_V0(1), FP64_RAND_V2(0), FP64_RAND_V1(1) } },
@@ -4162,6 +4162,6 @@
             { /*src1     */ { FP64_1(0),                                                FP64_RAND_V2(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
             { /* =>      */ { FP64_NORM_SAFE_INT_MAX(0),                                FP64_RAND_V2(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_NORM_SAFE_INT_MAX(0),               FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(0) } },
@@ -4236,6 +4236,6 @@
             { /*src1     */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } },
             { /* =>      */ { FP64_0(0),          FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
               /*256:out  */ -1 },
           /** @todo More Denormals. */
@@ -4324,7 +4324,7 @@
             { /*src1     */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } },
             { /* =>      */ { FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
     /*
      * Infinity.
@@ -4333,13 +4333,13 @@
             { /*src1     */ { FP32_INF(1),  FP32_INF(0),  FP32_0(0),    FP32_0(0),    FP32_INF(0),  FP32_INF(1), FP32_0(0),    FP32_0(0)    } },
             { /* =>      */ { FP32_QNAN(1), FP32_0(0),    FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_0(0),   FP32_QNAN(1), FP32_QNAN(1) } },
-              /*mxcsr:in */ X86_MXCSR_IM,
-              /*128:out  */ X86_MXCSR_IM | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_IM | X86_MXCSR_IE },
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_IE },
           { { /*src2     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1),  FP32_INF(1), FP32_0(0),   FP32_0(0)   } },
             { /*src1     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1),  FP32_INF(0), FP32_INF(0), FP32_INF(0) } },
             { /* =>      */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN(1), FP32_INF(0), FP32_INF(1), FP32_0(0)   } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ X86_MXCSR_IE },
           { { /*src2     */ { FP32_INF(0),  FP32_INF(1), FP32_INF(0),  FP32_INF(1),  FP32_INF(1),  FP32_INF(1), FP32_0(0),   FP32_0(0)   } },
             { /*src1     */ { FP32_INF(1),  FP32_INF(0), FP32_0(0),    FP32_0(0),    FP32_INF(1),  FP32_INF(0), FP32_INF(0), FP32_INF(0) } },
@@ -4357,7 +4357,7 @@
             { /*src1     */ { FP32_INF(0),  FP32_QNAN(0), FP32_INF(1),  FP32_QNAN(0), FP32_INF(1),  FP32_QNAN(1), FP32_INF(0), FP32_INF(0) } },
             { /* =>      */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN(1), FP32_QNAN(0), FP32_QNAN(1), FP32_INF(0),  FP32_INF(1), FP32_0(0)   } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_RC_ZERO },
     /*
      * Overflow, Precision.
@@ -4438,7 +4438,7 @@
             { /*src1     */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MIN(0),                                FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MAX(0),          FP32_0(0),        FP32_NORM_SAFE_INT_MAX(1) } },
             { /* =>      */ { FP32_NORM_SAFE_INT_MAX(0), FP32_V(1, FP32_FRAC_NORM_MAX, FP32_EXP_SAFE_INT_MAX + 1), FP32_NORM_MAX(0),          FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_MAX(0),          FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_MAX(0), FP32_NORM_SAFE_INT_MAX(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_PE },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE },
     /*
      * Normals.
@@ -4447,7 +4447,7 @@
             { /*src1     */ { FP32_V(1, 0,        0x7d)/*-0.25*/, FP32_V(0, 0x600000, 0x7f)/*1.75*/, FP32_NORM_MAX(1),                  FP32_0(0),        FP32_V(0, 0,        0x7e)/*0.50*/, FP32_V(0, 0, 0x7d)/*0.25*/, FP32_0(0),                         FP32_0(0)                         } },
             { /* =>      */ { FP32_V(0, 0x400000, 0x7f)/* 1.50*/, FP32_NORM_MAX(1),                  FP32_V(0, 0x400000, 0x7e)/*0.75*/, FP32_NORM_MAX(0), FP32_V(0, 0x400000, 0x7e)/*0.75*/, FP32_0(0),                  FP32_NORM_MAX(0),                  FP32_V(0, 0x600000, 0x7f)/*1.75*/ } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
           { { /*src2     */ { FP32_NORM_V1(1),  FP32_NORM_V1(0),  FP32_NORM_V4(1),  FP32_NORM_V4(0),  FP32_NORM_V1(1),  FP32_NORM_V1(0),  FP32_NORM_V2(1), FP32_NORM_V2(0) } },
             { /*src1     */ { FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_NORM_MIN(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_V3(0), FP32_NORM_V3(1) } },
@@ -4459,19 +4459,19 @@
             { /*src1     */ { FP32_V(0, 0x669050, 0x93)/*1888778*/, FP32_V(1, 0x1ea980, 0x8f)/* -81235.00*/, FP32_V(0, 0x253468, 0x93)/*1353357*/, FP32_V(1, 0x7c9000, 0x88)/*-1010.25*/, FP32_V(0, 0x5c0000, 0x84)/*     55*/, FP32_V(0, 0x600000, 0x81)/*7*/,        FP32_V(0, 0x534000, 0x86)/*    211.25*/, FP32_1(1)                           } },
             { /* =>      */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_V(0, 0x780000, 0x84)/*     62*/, FP32_V(0, 0x5c0000, 0x84)/*   55.00*/, FP32_V(0, 0x780000, 0x84)/*     62*/, FP32_V(0, 0x524000, 0x86)/*210.25*/,   FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_V(0, 0x534000, 0x86)/*211.25*/ } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP32_V(0, 0x3c614e, 0x96)/*12345678*/, FP32_V(0, 0x3c614e, 0x96)/*12345678*/, FP32_0(0),                             FP32_NORM_V1(0), FP32_V(0, 0x3c614e, 0x97)/*24691356*/, FP32_V(1, 0x3c614e, 0x96)/*-12345678*/, FP32_0(0),                             FP32_1(1) } },
             { /*src1     */ { FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_V(1, 0x712060, 0x92)/* -987654*/, FP32_NORM_V3(1),                       FP32_0(0),       FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_V(1, 0x712060, 0x92)/*  -987654*/, FP32_0(0),                             FP32_1(0) } },
             { /* =>      */ { FP32_V(0, 0x6cb99c, 0x97)/*31028024*/, FP32_NORM_V3(1),                       FP32_V(0, 0x3c614e, 0x97)/*24691356*/, FP32_NORM_V1(0), FP32_V(0, 0x6cb99c, 0x97)/*31028024*/, FP32_1(0),                              FP32_V(0, 0x3c614e, 0x96)/*12345678*/, FP32_1(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP32_1(0),                                                FP32_1(1),                                                FP32_1(1),                 FP32_0(0), FP32_1(0),                                                FP32_1(1),                                                FP32_1(1),                 FP32_0(0) } },
             { /*src1     */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_1(0),                                                FP32_NORM_SAFE_INT_MAX(0), FP32_1(1), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_1(0),                                                FP32_NORM_SAFE_INT_MAX(0), FP32_1(1) } },
             { /* =>      */ { FP32_NORM_SAFE_INT_MAX(0),                                FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_0(0),                 FP32_1(1), FP32_NORM_SAFE_INT_MAX(0),                                FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_0(0),                 FP32_1(1) } },
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
           { { /*src2     */ { FP32_NORM_SAFE_INT_MAX(0),               FP32_1(0),                               FP32_1(1),                               FP32_0(0), FP32_NORM_SAFE_INT_MAX(0),               FP32_1(0),                               FP32_1(1),                               FP32_0(0) } },
             { /*src1     */ { FP32_NORM_SAFE_INT_MAX(0),               FP32_1(0),                               FP32_NORM_SAFE_INT_MAX(1),               FP32_1(1), FP32_NORM_SAFE_INT_MAX(0),               FP32_1(0),                               FP32_NORM_SAFE_INT_MAX(1),               FP32_1(1) } },
@@ -4489,7 +4489,7 @@
             { /*src1     */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_V(0, 0x600000, 0x7e)/*     0.875*/, FP32_V(0, 0x430ebc, 0x91)/*399477.875*/, FP32_V(0, 0x3ce348, 0x90)/*193421.125*/, FP32_V(0, 0x16b43a, 0x93)/*1234567.25*/, FP32_V(0, 0x00c6d3, 0x94)/*2109876.75*/, FP32_V(0, 0x792318, 0x91)/*510232.750*/, FP32_V(1, 0x316740, 0x8e)/* -45415.250*/ } },
             { /* =>      */ { FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/, FP32_V(0, 0x10c030, 0x92)/*592899.000*/, FP32_V(0, 0x52e0b4, 0x92)/*863755.250*/, FP32_V(1, 0, FP32_EXP_SAFE_INT_MIN + 1), FP32_V(0, 0x4c20f0, 0x94)/*3344444.00*/, FP32_V(0, 0x62f630, 0x91)/*464817.50*/,  FP32_V(0, 0, FP32_EXP_SAFE_INT_MIN + 1), FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/ } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
     /*
      * Denormals.
@@ -4519,7 +4519,7 @@
             { /*src1     */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0) } },
             { /* =>      */ { FP32_0(0), FP32_0(0),          FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0),          FP32_0(0), FP32_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ X86_MXCSR_DAZ,
+              /*128:out  */ X86_MXCSR_DAZ,
+              /*256:out  */ X86_MXCSR_DAZ },
           { { /*src2     */ { FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } },
             { /*src1     */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0) } },
@@ -4552,13 +4552,13 @@
             { /*src1     */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0)          } },
             { /* =>      */ { FP32_0(0), FP32_0(0),          FP32_0(0), FP32_0(0), FP32_0(0),          FP32_0(0), FP32_0(0), FP32_0(0)          } },
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ X86_MXCSR_DAZ,
+              /*128:out  */ X86_MXCSR_DAZ,
+              /*256:out  */ X86_MXCSR_DAZ },
           { { /*src2     */ { FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } },
             { /*src1     */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0) } },
             { /* =>      */ { FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0)          } },
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP },
           /** @todo More Denormals. */
     /*
@@ -4657,7 +4657,7 @@
             { /*src1     */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } },
             { /* =>      */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_0(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
     /*
      * Infinity.
@@ -4666,13 +4666,13 @@
             { /*src1     */ { FP64_INF(1),  FP64_INF(0),  FP64_0(0),   FP64_0(0)    } },
             { /* =>      */ { FP64_QNAN(1), FP64_QNAN(1), FP64_0(0),   FP64_QNAN(1) } },
-              /*mxcsr:in */ X86_MXCSR_IM,
-              /*128:out  */ X86_MXCSR_IM | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_IM | X86_MXCSR_IE },
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_IE },
           { { /*src2     */ { FP64_0(0), FP64_0(0), FP64_INF(1),  FP64_INF(1) } },
             { /*src1     */ { FP64_0(0), FP64_0(0), FP64_INF(1),  FP64_INF(0) } },
             { /* =>      */ { FP64_0(0), FP64_0(0), FP64_QNAN(1), FP64_INF(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ X86_MXCSR_IE },
           { { /*src2     */ { FP64_INF(0),  FP64_INF(1),  FP64_INF(0), FP64_INF(1)  } },
             { /*src1     */ { FP64_INF(1),  FP64_INF(0),  FP64_0(0),   FP64_0(0)    } },
@@ -4690,7 +4690,7 @@
             { /*src1     */ { FP64_INF(0),  FP64_QNAN(0), FP64_INF(1),  FP64_QNAN(0) } },
             { /* =>      */ { FP64_QNAN(0), FP64_QNAN(1), FP64_QNAN(0), FP64_QNAN(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_RC_ZERO },
     /*
      * Overflow, Precision.
@@ -4705,37 +4705,37 @@
             { /*src1     */ { FP64_NORM_MAX(1), FP64_NORM_MAX(1),                                     FP64_NORM_MAX(1), FP64_NORM_MAX(1) } },
             { /* =>      */ { FP64_INF(1),      FP64_V(1, FP32_FRAC_NORM_MIN, FP32_EXP_NORM_MIN + 1), FP64_INF(1),      FP64_INF(0)      } },
-              /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM,
-              /*128:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY,
-              /*256:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY },
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY,
+              /*256:out  */ X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY },
           { { /*src2     */ { FP64_NORM_MAX(1), FP64_NORM_MAX(0), FP64_0(0),        FP64_0(0)        } },
             { /*src1     */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1) } },
             { /* =>      */ { FP64_NORM_MAX(0), FP64_0(0),        FP64_NORM_MAX(1), FP64_0(0)        } },
-              /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY,
-              /*256:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY,
+              /*256:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY },
           { { /*src2     */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_0(0),                            FP64_NORM_MIN(1) } },
             { /*src1     */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MIN(1),                     FP64_NORM_MIN(1) } },
             { /* =>      */ { FP64_INF(0),      FP64_0(0),        FP64_V(1, 0, FP32_EXP_NORM_MIN + 1),  FP64_NORM_MIN(1) } },
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY },
           { { /*src2     */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_0(0),                                            FP64_NORM_MAX(0) } },
             { /*src1     */ { FP64_NORM_MIN(1), FP64_NORM_MAX(0), FP64_NORM_MIN(0),                                     FP64_NORM_MAX(1) } },
             { /* =>      */ { FP64_NORM_MAX(0), FP64_INF(0),      FP64_V(1, FP64_FRAC_NORM_MAX - 1, FP64_EXP_NORM_MAX), FP64_NORM_MAX(0) } },
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE },
           { { /*src2     */ { FP64_NORM_MAX(0),                     FP64_NORM_MAX(0), FP64_NORM_MAX(0),                     FP64_0(0)        } },
             { /*src1     */ { FP64_NORM_MIN(1),                     FP64_NORM_MIN(1), FP64_NORM_MIN(0),                     FP64_NORM_MIN(0) } },
             { /* =>      */ { FP64_V(1, 0, FP32_EXP_NORM_MIN + 1),  FP64_NORM_MAX(0), FP64_V(0, 0, FP32_EXP_NORM_MIN + 1),  FP64_NORM_MAX(0) } },
-              /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY,
-              /*256:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY,
+              /*256:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY },
           { { /*src2     */ { FP64_0(0),                                        FP64_NORM_MAX(0), FP64_NORM_MIN(1),                     FP64_NORM_MIN(0) } },
             { /*src1     */ { FP64_NORM_MAX(1),                                 FP64_NORM_MAX(1), FP64_NORM_MIN(1),                     FP64_NORM_MIN(1) } },
             { /* =>      */ { FP64_V(1, FP64_FRAC_NORM_MAX, FP64_EXP_NORM_MAX), FP64_NORM_MAX(0), FP64_V(1, 0, FP32_EXP_NORM_MIN + 1),  FP64_0(0)        } },
-              /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY,
-              /*256:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY,
+              /*256:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY },
           { { /*src2     */ { FP64_0(0), FP64_0(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1) } },
             { /*src1     */ { FP64_0(0), FP64_0(0), FP64_NORM_MAX(0), FP64_NORM_MAX(0) } },
@@ -4747,7 +4747,7 @@
             { /*src1     */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MIN(0) } },
             { /* =>      */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0), FP64_0(0)                 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_PE },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE },
     /*
      * Normals.
@@ -4756,13 +4756,13 @@
             { /*src1     */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_V1(0), FP64_NORM_V1(1) } },
             { /* =>      */ { FP64_0(1),        FP64_0(1),        FP64_0(1),       FP64_0(1)       } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
           { { /*src2     */ { FP64_V(0, 0xb800000000000, 0x404)/*  55*/, FP64_V(0, 0xc000000000000, 0x401)/*  7*/, FP64_V(0, 0x26580b4800000, 0x41d)/*1234567890*/, FP64_V(1, 0x26580b4800000, 0x41d)/*-1234567890*/ } },
             { /*src1     */ { FP64_V(0, 0,               0x409)/*1024*/, FP64_V(0, 0,               0x408)/*512*/, FP64_V(0, 0xd6f3458800000, 0x41c)/* 987654321*/, FP64_V(1, 0x9000000000000, 0x405)/*       -100*/ } },
             { /* =>      */ { FP64_V(0, 0x8000000000000, 0x409)/*1536*/, FP64_V(0, 0xf000000000000, 0x404)/* 62*/, FP64_V(0, 0xd6f3426800000, 0x41c)/* 987654221*/, FP64_0(0)                                        } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_NORM_V2(1), FP64_NORM_V2(0) } },
             { /*src1     */ { FP64_V(0, 0xcf0033a34f337, 0x432)/*4072598000007579.5*/, FP64_V(0, 0xd6eca42000000, 0x419)/*      123450000.50*/, FP64_NORM_V0(1), FP64_NORM_V0(0) } },
@@ -4774,7 +4774,7 @@
             { /*src1     */ { FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_1(0),                                                FP64_NORM_V1(0), FP64_NORM_V1(1) } },
             { /* =>      */ { FP64_NORM_SAFE_INT_MAX(0),                                FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_0(0),       FP64_0(0)       } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
           { { /*src2     */ { FP64_NORM_SAFE_INT_MIN(0), FP64_0(0),                 FP64_NORM_SAFE_INT_MIN(1),               FP64_NORM_SAFE_INT_MIN(1)               } },
             { /*src1     */ { FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(0),               FP64_NORM_SAFE_INT_MIN(0)               } },
@@ -4815,7 +4815,7 @@
             { /*src1     */ { FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(1), FP64_DENORM_MAX(1) } },
             { /* =>      */ { FP64_0(0),          FP64_0(0),          FP64_0(1),          FP64_0(1)          } },
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ X86_MXCSR_DAZ,
+              /*128:out  */ X86_MXCSR_DAZ,
+              /*256:out  */ X86_MXCSR_DAZ },
           { { /*src2     */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0),          FP64_0(0) } },
             { /*src1     */ { FP64_0(0),          FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0) } },
@@ -4842,7 +4842,7 @@
             { /*src1     */ { FP64_0(1), FP64_DENORM_MAX(0), FP64_DENORM_MAX(1), FP64_0(0)          } },
             { /* =>      */ { FP64_0(0), FP64_0(0),          FP64_0(0),          FP64_0(1)          } },
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
           { { /*src2     */ { FP64_0(0), FP64_0(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } },
             { /*src1     */ { FP64_0(0), FP64_0(0), FP64_DENORM_MIN(1), FP64_DENORM_MIN(1) } },
@@ -4954,13 +4954,13 @@
             { /*src1     */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } },
             { /* =>      */ { FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_RC_DOWN },
           { { /*src2     */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } },
             { /*src1     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } },
             { /* =>      */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ },
+              /*mxcsr:in */ X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_FZ,
+              /*256:out  */ X86_MXCSR_FZ },
     /*
      * Infinity.
@@ -4969,25 +4969,25 @@
             { /*src1     */ { FP32_INF(1),  FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0) } },
             { /* =>      */ { FP32_INF(1),  FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
-              /*128:out  */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
-              /*256:out  */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP32_INF(0),  FP32_0(0), FP32_0(0), FP32_INF(1),  FP32_INF(1), FP32_0(0), FP32_0(0), FP32_INF(1)  } },
             { /*src1     */ { FP32_INF(0),  FP32_0(0), FP32_0(0), FP32_INF(1),  FP32_INF(0), FP32_0(0), FP32_0(0), FP32_INF(1)  } },
             { /* =>      */ { FP32_QNAN(1), FP32_0(0), FP32_0(0), FP32_QNAN(1), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_QNAN(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE },
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_IE },
           { { /*src2     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0),  FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1)  } },
             { /*src1     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0),  FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1)  } },
             { /* =>      */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE },
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_IE },
           { { /*src2     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1),  FP32_0(1), FP32_0(1), FP32_0(0) } },
             { /*src1     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1),  FP32_0(1), FP32_0(1), FP32_0(0) } },
             { /* =>      */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN(1), FP32_0(0), FP32_0(0), FP32_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE },
+              /*mxcsr:in */ X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_FZ,
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_IE },
           { { /*src2     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0)  } },
             { /*src1     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0)  } },
@@ -5123,7 +5123,7 @@
             { /*src1     */ { FP32_NORM_SAFE_INT_MAX(0),                                FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_1(0), FP32_1(1), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_1(0),                                                FP32_0(1), FP32_0(0) } },
             { /* =>      */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_NORM_SAFE_INT_MAX(0),                                FP32_0(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(0),                                FP32_V(1, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_0(0), FP32_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ },
+              /*mxcsr:in */ X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_FZ,
+              /*256:out  */ X86_MXCSR_FZ },
           { { /*src2     */ { FP32_1(0),                                                FP32_1(0),                               FP32_0(1), FP32_1(1), FP32_0(1), FP32_1(1), FP32_1(1),                               FP32_NORM_SAFE_INT_MAX(0)               } },
             { /*src1     */ { FP32_NORM_SAFE_INT_MAX(0),                                FP32_NORM_SAFE_INT_MAX(1),               FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_NORM_SAFE_INT_MAX(0),               FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1) } },
@@ -5141,7 +5141,7 @@
             { /*src1     */ { FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/, FP32_V(0, 0x10c030, 0x92)/*592899.000*/, FP32_V(0, 0x52e0b4, 0x92)/*863755.250*/, FP32_NORM_SAFE_INT_MIN(0),               FP32_NORM_SAFE_INT_MIN(1),               FP32_V(0, 0x4c20f0, 0x94)/*3344444.00*/, FP32_V(0, 0x792318, 0x91)/*510232.75*/, FP32_V(1, 0x769b50, 0x92)/*-1010101.000*/ } },
             { /* =>      */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_V(0, 0x430ebc, 0x91)/*399477.875*/, FP32_V(0, 0x6423f2, 0x92)/*934463.125*/, FP32_V(0, 0, FP32_EXP_SAFE_INT_MIN + 1), FP32_V(1, 0, FP32_EXP_SAFE_INT_MIN + 1), FP32_V(0, 0x16b43a, 0x93)/*1234567.25*/, FP32_V(0, 0x62f630, 0x91)/*464817.50*/, FP32_V(1, 0x769b5e, 0x92)/*-1010101.875*/ } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
     /*
      * Denormals.
@@ -5191,7 +5191,7 @@
             { /*src1     */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0) } },
             { /* =>      */ { FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0)          } },
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP },
           { { /*src2     */ { FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0),          FP32_0(0), FP32_0(0), FP32_0(0) } },
             { /*src1     */ { FP32_0(0),          FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
@@ -5238,7 +5238,7 @@
             { /*src1     */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(1), FP32_DENORM_MIN(0) } },
             { /* =>      */ { FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0)          } },
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP },
           /** @todo More denormals. */
     /*
@@ -5313,7 +5313,7 @@
             { /*src1     */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
             { /* =>      */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
             { /*src1     */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
@@ -5352,25 +5352,25 @@
             { /*src1     */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_INF(0) } },
             { /* =>      */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_INF(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
-              /*128:out  */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
-              /*256:out  */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP64_INF(0),  FP64_INF(1),  FP64_INF(1), FP64_INF(1)  } },
             { /*src1     */ { FP64_INF(0),  FP64_INF(1),  FP64_INF(0), FP64_INF(1)  } },
             { /* =>      */ { FP64_QNAN(1), FP64_QNAN(1), FP64_INF(0), FP64_QNAN(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE },
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_IE },
           { { /*src2     */ { FP64_INF(0),  FP64_INF(0), FP64_INF(1), FP64_INF(1)  } },
             { /*src1     */ { FP64_INF(0),  FP64_INF(1), FP64_INF(0), FP64_INF(1)  } },
             { /* =>      */ { FP64_QNAN(1), FP64_INF(1), FP64_INF(0), FP64_QNAN(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE },
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_IE },
           { { /*src2     */ { FP64_0(0), FP64_0(0), FP64_INF(1), FP64_INF(1)  } },
             { /*src1     */ { FP64_0(0), FP64_0(0), FP64_INF(0), FP64_INF(1)  } },
             { /* =>      */ { FP64_0(0), FP64_0(0), FP64_INF(0), FP64_QNAN(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE },
+              /*mxcsr:in */ X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_FZ,
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_IE },
           { { /*src2     */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_INF(0)  } },
             { /*src1     */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_INF(0)  } },
@@ -5415,31 +5415,31 @@
             { /*src1     */ { FP64_NORM_MAX(1), FP64_0(0), FP64_0(0), FP64_NORM_MAX(1) } },
             { /* =>      */ { FP64_INF(1),      FP64_0(0), FP64_0(0), FP64_INF(1)      } },
-              /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_FZ,
-              /*128:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY,
-              /*256:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY },
+              /*mxcsr:in */ X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY,
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY },
           { { /*src2     */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_V(1, 0, FP32_EXP_NORM_MIN + 1),  FP64_NORM_MIN(1) } },
             { /*src1     */ { FP64_NORM_MAX(1), FP64_NORM_MAX(0), FP64_NORM_MIN(1),                     FP64_NORM_MIN(1) } },
             { /* =>      */ { FP64_INF(1),      FP64_NORM_MAX(0), FP64_NORM_MIN(0),                     FP64_0(0)        } },
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM,
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_PE },
           { { /*src2     */ { FP64_V(1, 0, FP32_EXP_NORM_MIN + 1),  FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_V(1, 0, 2)  } },
             { /*src1     */ { FP64_NORM_MIN(1),                     FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MIN(1) } },
             { /* =>      */ { FP64_NORM_MIN(0),                     FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MIN(0) } },
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM,
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY },
           { { /*src2     */ { FP64_0(0), FP64_0(0), FP64_NORM_MIN(0), FP64_NORM_MAX(0) } },
             { /*src1     */ { FP64_0(0), FP64_0(0), FP64_NORM_MIN(0), FP64_NORM_MAX(1) } },
             { /* =>      */ { FP64_0(0), FP64_0(0), FP64_0(0),        FP64_NORM_MAX(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY },
           { { /*src2     */ { FP64_NORM_MIN(0),                FP64_NORM_MIN(0),                FP64_NORM_MIN(1),                FP64_NORM_MIN(0)                } },
             { /*src1     */ { FP64_NORM_MAX(0),                FP64_NORM_MAX(0),                FP64_NORM_MAX(1),                FP64_NORM_MAX(0)                } },
             { /* =>      */ { FP64_V(0,0xffffffffffffe,0x7fe), FP64_V(0,0xffffffffffffe,0x7fe), FP64_V(1,0xffffffffffffe,0x7fe), FP64_V(0,0xffffffffffffe,0x7fe) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM) | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM) | X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM) | X86_MXCSR_RC_ZERO | X86_MXCSR_PE },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE },
           { { /*src2     */ { FP64_NORM_SAFE_INT_MIN(0),       FP64_NORM_MAX(0), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MAX(1) } },
             { /*src1     */ { FP64_NORM_SAFE_INT_MAX(0),       FP64_NORM_MAX(1), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MAX(1) } },
@@ -5460,37 +5460,37 @@
             { /*src1     */ { FP64_V(0, 0x8000000000000, 0x409)/*1536*/, FP64_V(1, 0xc000000000000, 0x401)/* 7*/, FP64_V(0, 0xb800000000000, 0x404)/*55*/, FP64_V(0, 0,               0x409)/*1024*/ } },
             { /* =>      */ { FP64_V(0, 0,               0x408)/* 512*/, FP64_V(1, 0xf000000000000, 0x404)/*62*/, FP64_V(0, 0xf000000000000, 0x404)/*62*/, FP64_V(1, 0,               0x408)/* 512*/ } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP64_V(0, 0x26580b4800000, 0x41d)/*1234567890*/, FP64_V(0, 0x9000000000000, 0x405)/*      100*/, FP64_0(0), FP64_V(0, 0xd6eca42000000, 0x419)/*       123450000.5*/ } },
             { /*src1     */ { FP64_V(0, 0x26580b4800000, 0x41d)/*1234567890*/, FP64_V(0, 0xd6f3458800000, 0x41c)/*987654321*/, FP64_0(0), FP64_V(0, 0xcf00348ec5858, 0x432)/*4072598123457580.0*/ } },
             { /* =>      */ { FP64_0(0),                                       FP64_V(0, 0xd6f3426800000, 0x41c)/*987654221*/, FP64_0(0), FP64_V(0, 0xcf0033a34f337, 0x432)/*4072598000007579.5*/ } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_NORM_SAFE_INT_MAX(0),                                FP64_0(0), FP64_0(0) } },
             { /*src1     */ { FP64_NORM_SAFE_INT_MAX(0),                                FP64_1(0),                                                FP64_0(0), FP64_0(0) } },
             { /* =>      */ { FP64_1(0),                                                FP64_V(1, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_0(0), FP64_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP64_1(0),                                                FP64_1(1),                                                FP64_1(1),                                                FP64_NORM_SAFE_INT_MAX(0)                                } },
             { /*src1     */ { FP64_NORM_SAFE_INT_MAX(0),                                FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_1(0)                                                } },
             { /* =>      */ { FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_NORM_SAFE_INT_MAX(0),                                FP64_NORM_SAFE_INT_MAX(0),                                FP64_V(1, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX) } },
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
           { { /*src2     */ { FP64_NORM_SAFE_INT_MAX(1), FP64_0(0),                 FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(1)               } },
             { /*src1     */ { FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MIN(1), FP64_0(0),                 FP64_NORM_SAFE_INT_MIN(0)               } },
             { /* =>      */ { FP64_0(0),                 FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(1), FP64_V(0, 0, FP32_EXP_SAFE_INT_MIN + 1) } },
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP },
           { { /*src2     */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_0(0), FP64_0(1), FP64_NORM_SAFE_INT_MIN(0)               } },
             { /*src1     */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_0(0), FP64_0(1), FP64_NORM_SAFE_INT_MIN(1)               } },
             { /* =>      */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_0(1), FP64_0(1), FP64_V(1, 0, FP32_EXP_SAFE_INT_MIN + 1) } },
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
     /*
      * Denormals.
@@ -5519,13 +5519,13 @@
             { /*src1     */ { FP64_0(0), FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0) } },
             { /* =>      */ { FP64_0(0), FP64_0(0),          FP64_0(0), FP64_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ X86_MXCSR_DAZ,
+              /*128:out  */ X86_MXCSR_DAZ,
+              /*256:out  */ X86_MXCSR_DAZ },
           { { /*src2     */ { FP64_DENORM_MIN(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } },
             { /*src1     */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } },
             { /* =>      */ { FP64_0(0),          FP64_0(0),          FP64_0(0),          FP64_0(0)          } },
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP },
     /** @todo More denormals. */
     /*
@@ -5600,6 +5600,6 @@
             { /*src1     */ { FP32_0(0), FP32_0_x7(0) } },
             { /* =>      */ { FP32_0(0), FP32_0_x7(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_0(0), FP32_RAND_x7_V0 } },
@@ -5639,24 +5639,24 @@
             { /*src1     */ { FP32_INF(1), FP32_0_x7(0) } },
             { /* =>      */ { FP32_INF(1), FP32_0_x7(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
-              /*128:out  */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_INF(0),  FP32_RAND_x7_V6 } },
             { /*src1     */ { FP32_INF(0),  FP32_RAND_x7_V7 } },
             { /* =>      */ { FP32_QNAN(1), FP32_RAND_x7_V7 } },
-              /*mxcsr:in */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM),
-              /*128:out  */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_IE,
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_IE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_INF(1), FP32_RAND_x7_V0 } },
             { /*src1     */ { FP32_INF(0), FP32_RAND_x7_V1 } },
             { /* =>      */ { FP32_INF(0), FP32_RAND_x7_V1 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_INF(1),  FP32_RAND_x7_V4 } },
             { /*src1     */ { FP32_INF(1),  FP32_RAND_x7_V3 } },
             { /* =>      */ { FP32_QNAN(1), FP32_RAND_x7_V3 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,
+              /*mxcsr:in */ X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_IE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_INF(0), FP32_RAND_x7_V5 } },
@@ -5669,6 +5669,6 @@
             { /*src1     */ { FP32_INF(0), FP32_RAND_x7_V2 } },
             { /* =>      */ { FP32_INF(0), FP32_RAND_x7_V2 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
     /*
@@ -5720,6 +5720,6 @@
             { /*src1     */ { FP32_NORM_MAX(0), FP32_0_x7(0) } },
             { /* =>      */ { FP32_NORM_MAX(0), FP32_0_x7(0) } },
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM,
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_PE,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_NORM_MAX(0), FP32_0_x7(0) } },
@@ -5759,24 +5759,24 @@
             { /*src1     */ { FP32_V(0, 0,        0x7d)/*0.25*/, FP32_RAND_x7_V2 } },
             { /* =>      */ { FP32_V(1, 0x400000, 0x7f)/*1.50*/, FP32_RAND_x7_V2 } },
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_NORM_MAX(1), FP32_RAND_x7_V3 } },
             { /*src1     */ { FP32_NORM_MAX(1), FP32_RAND_x7_V4 } },
             { /* =>      */ { FP32_0(0),        FP32_RAND_x7_V4 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
+              /*mxcsr:in */ X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_RC_UP,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_RAND_x7_V5 } },
             { /*src1     */ { FP32_V(0, 0x669050, 0x93)/*1888778*/, FP32_RAND_x7_V6 } },
             { /* =>      */ { FP32_V(0, 0x1ea980, 0x8f)/*  81235*/, FP32_RAND_x7_V6 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_RAND_x7_V7 } },
             { /*src1     */ { FP32_V(0, 0x253468, 0x93)/*1353357.00*/, FP32_RAND_x7_V0 } },
             { /* =>      */ { FP32_V(0, 0x7c9000, 0x88)/*   1010.25*/, FP32_RAND_x7_V0 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_V(0, 0x712060, 0x92)/*  987654*/, FP32_RAND_x7_V0 } },
@@ -5789,12 +5789,12 @@
             { /*src1     */ { FP32_NORM_SAFE_INT_MAX(0),                                FP32_RAND_x7_V4 } },
             { /* =>      */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_RAND_x7_V4 } },
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_V(1, 0x600000, 0x7e)/*      -0.875*/, FP32_RAND_x7_V5 } },
             { /*src1     */ { FP32_V(0, 0x769b50, 0x92)/* 1010101.000*/, FP32_RAND_x7_V6 } },
             { /* =>      */ { FP32_V(0, 0x769b5e, 0x92)/* 1010101.875*/, FP32_RAND_x7_V6 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_x7_V1 } },
@@ -5831,12 +5831,12 @@
             { /*src1     */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V3 } },
             { /* =>      */ { FP32_0(0),          FP32_RAND_x7_V3 } },
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ X86_MXCSR_DAZ,
+              /*128:out  */ X86_MXCSR_DAZ,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_DENORM_MIN(0), FP32_RAND_x7_V6 } },
             { /*src1     */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V6 } },
             { /* =>      */ { FP32_0(0),          FP32_RAND_x7_V6 } },
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
               /*256:out  */ -1 },
     /** @todo More denormals. */
@@ -5901,6 +5901,6 @@
             { /*src1     */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
             { /* =>      */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_0(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } },
@@ -5940,24 +5940,24 @@
             { /*src1     */ { FP64_INF(1),  FP64_0(0), FP64_0(0), FP64_0(0) } },
             { /* =>      */ { FP64_QNAN(1), FP64_0(0), FP64_0(0), FP64_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM,
-              /*128:out  */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_IE,
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_IE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_INF(1),  FP64_RAND_V1(0), FP64_RAND_V2(0), FP32_RAND_V3(1) } },
             { /*src1     */ { FP64_INF(1),  FP64_RAND_V0(0), FP64_RAND_V1(1), FP32_RAND_V1(1) } },
             { /* =>      */ { FP64_QNAN(1), FP64_RAND_V0(0), FP64_RAND_V1(1), FP32_RAND_V1(1) } },
-              /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_DM | X86_MXCSR_ZM | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_INF(1),  FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V1(1) } },
             { /*src1     */ { FP64_INF(1),  FP64_RAND_V1(1), FP64_RAND_V1(0), FP64_RAND_V0(1) } },
             { /* =>      */ { FP64_QNAN(1), FP64_RAND_V1(1), FP64_RAND_V1(0), FP64_RAND_V0(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
+              /*mxcsr:in */ X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_INF(1),  FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
             { /*src1     */ { FP64_INF(1),  FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V1(0) } },
             { /* =>      */ { FP64_QNAN(1), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V1(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_IE,
+              /*mxcsr:in */ X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_IE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_INF(1),  FP64_RAND_V0(0), FP64_RAND_V0(0), FP64_RAND_V0(1) } },
@@ -5976,12 +5976,12 @@
             { /*src1     */ { FP64_INF(1), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V1(0) } },
             { /* =>      */ { FP64_INF(1), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V1(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_INF(1), FP64_RAND_V1(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } },
             { /*src1     */ { FP64_INF(0), FP64_RAND_V0(1), FP64_RAND_V2(1), FP64_RAND_V1(0) } },
             { /* =>      */ { FP64_INF(0), FP64_RAND_V0(1), FP64_RAND_V2(1), FP64_RAND_V1(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
     /*
@@ -6051,6 +6051,6 @@
             { /*src1     */ { FP64_0(0), FP64_0(0), FP64_NORM_MIN(0), FP64_NORM_MAX(1) } },
             { /* =>      */ { FP64_0(0), FP64_0(0), FP64_0(0),        FP64_NORM_MAX(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_NORM_MIN(0),                                     FP64_NORM_MIN(0), FP64_NORM_MIN(1), FP64_NORM_MIN(0) } },
@@ -6084,54 +6084,54 @@
             { /*src1     */ { FP64_V(0, 0x8000000000000, 0x409)/*1536*/, FP64_RAND_V2(1), FP64_RAND_V3(0), FP64_RAND_V1(0) } },
             { /* =>      */ { FP64_V(0, 0,               0x408)/* 512*/, FP64_RAND_V2(1), FP64_RAND_V3(0), FP64_RAND_V1(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_V(0, 0xc000000000000, 0x401)/* 7*/, FP64_RAND_V2(0), FP64_RAND_V2(0), FP64_RAND_V0(1) } },
             { /*src1     */ { FP64_V(0, 0xf000000000000, 0x404)/*62*/, FP64_RAND_V0(1), FP64_RAND_V2(1), FP64_RAND_V1(1) } },
             { /* =>      */ { FP64_V(0, 0xb800000000000, 0x404)/*55*/, FP64_RAND_V0(1), FP64_RAND_V2(1), FP64_RAND_V1(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_V(0, 0x26580b4800000, 0x41d)/*1234567890*/, FP64_RAND_V3(0), FP64_RAND_V0(0), FP64_RAND_V1(1) } },
             { /*src1     */ { FP64_V(0, 0x26580b4800000, 0x41d)/*1234567890*/, FP64_RAND_V3(1), FP64_RAND_V1(0), FP64_RAND_V2(0) } },
             { /* =>      */ { FP64_0(0),                                       FP64_RAND_V3(1), FP64_RAND_V1(0), FP64_RAND_V2(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_V(0, 0x9000000000000, 0x405)/*       100*/, FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
             { /*src1     */ { FP64_V(1, 0xd6f3426800000, 0x41c)/*-987654221*/, FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(0) } },
             { /* =>      */ { FP64_V(1, 0xd6f3458800000, 0x41c)/*-987654321*/, FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_V(0, 0xd6eca42000000, 0x419)/*       123450000.5*/, FP64_RAND_V0(0), FP64_RAND_V0(1), FP64_RAND_V0(1) } },
             { /*src1     */ { FP64_V(0, 0xcf00348ec5858, 0x432)/*4072598123457580.0*/, FP64_RAND_V1(1), FP64_RAND_V1(0), FP64_RAND_V1(0) } },
             { /* =>      */ { FP64_V(0, 0xcf0033a34f337, 0x432)/*4072598000007579.5*/, FP64_RAND_V1(1), FP64_RAND_V1(0), FP64_RAND_V1(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V1(1) } },
             { /*src1     */ { FP64_NORM_SAFE_INT_MAX(0),                                FP64_RAND_V0(1), FP64_RAND_V3(1), FP64_RAND_V2(0) } },
             { /* =>      */ { FP64_1(0),                                                FP64_RAND_V0(1), FP64_RAND_V3(1), FP64_RAND_V2(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_1(0),                                                FP64_RAND_V3(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } },
             { /*src1     */ { FP64_NORM_SAFE_INT_MAX(0),                                FP64_RAND_V1(0), FP64_RAND_V0(0), FP64_RAND_V1(0) } },
             { /* =>      */ { FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_RAND_V1(0), FP64_RAND_V0(0), FP64_RAND_V1(0) } },
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_NORM_SAFE_INT_MAX(1), FP64_RAND_V0(0), FP64_RAND_V0(1), FP64_RAND_V0(1) } },
             { /*src1     */ { FP64_NORM_SAFE_INT_MAX(1), FP64_RAND_V1(1), FP64_RAND_V1(0), FP64_RAND_V1(0) } },
             { /* =>      */ { FP64_0(0),                 FP64_RAND_V1(1), FP64_RAND_V1(0), FP64_RAND_V1(0) } },
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_RAND_V0(0), FP64_RAND_V0(1), FP64_RAND_V0(1) } },
             { /*src1     */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_RAND_V1(1), FP64_RAND_V1(0), FP64_RAND_V1(0) } },
             { /* =>      */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_RAND_V1(1), FP64_RAND_V1(0), FP64_RAND_V1(0) } },
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*256:out  */ -1 },
     /*
@@ -6161,12 +6161,12 @@
             { /*src1     */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_0(1), FP64_0(0) } },
             { /* =>      */ { FP64_0(0),          FP64_0(0), FP64_0(1), FP64_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ X86_MXCSR_DAZ,
+              /*128:out  */ X86_MXCSR_DAZ,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_DENORM_MIN(0), FP64_RAND_V1(0), FP64_RAND_V0(0), FP64_RAND_V0(1) } },
             { /*src1     */ { FP64_DENORM_MAX(0), FP64_RAND_V2(1), FP64_RAND_V3(0), FP64_RAND_V1(0) } },
             { /* =>      */ { FP64_0(0),          FP64_RAND_V2(1), FP64_RAND_V3(0), FP64_RAND_V1(0) } },
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
               /*256:out  */ -1 },
           /** @todo More Denormals. */
@@ -6255,7 +6255,7 @@
             { /*src1     */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } },
             { /* =>      */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
     /*
      * Infinity.
@@ -6264,13 +6264,13 @@
             { /*src1     */ { FP32_INF(0),  FP32_INF(1), FP32_0(0),   FP32_0(0),   FP32_INF(0),  FP32_INF(1), FP32_0(0),   FP32_0(0)    } },
             { /* =>      */ { FP32_INF(0),  FP32_0(0),   FP32_INF(1), FP32_INF(0), FP32_INF(0),  FP32_0(0),   FP32_INF(0), FP32_INF(0)  } },
-              /*mxcsr:in */ X86_MXCSR_IM,
-              /*128:out  */ X86_MXCSR_IM,
-              /*256:out  */ X86_MXCSR_IM },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_INF(1),  FP32_0(0),    FP32_0(0)   } },
             { /*src1     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_INF(0),  FP32_INF(0),  FP32_INF(0) } },
             { /* =>      */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_QNAN(1), FP32_QNAN(1), FP32_0(0)   } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ X86_MXCSR_IE },
           { { /*src2     */ { FP32_INF(0),  FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1),  FP32_0(0),    FP32_0(0)   } },
             { /*src1     */ { FP32_INF(1),  FP32_INF(0), FP32_0(0),   FP32_0(0),   FP32_INF(1), FP32_INF(0),  FP32_INF(0),  FP32_INF(0) } },
@@ -6288,7 +6288,7 @@
             { /*src1     */ { FP32_INF(0),  FP32_QNAN(0), FP32_INF(1),  FP32_QNAN(0), FP32_INF(1),  FP32_QNAN(1), FP32_INF(0),  FP32_INF(0) } },
             { /* =>      */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN(1), FP32_QNAN(0), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_0(0)   } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_IE },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE },
     /*
      * Overflow, Precision.
@@ -6303,13 +6303,13 @@
             { /*src1     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MIN(1), FP32_NORM_MAX(1), FP32_NORM_MIN(1) } },
             { /* =>      */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_PE },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ X86_MXCSR_PE },
           { { /*src2     */ { FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
             { /*src1     */ { FP32_NORM_MAX(1), FP32_NORM_MIN(1), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
             { /* =>      */ { FP32_NORM_MAX(1), FP32_0(0),        FP32_0(0),        FP32_0(0),        FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_PM,
-              /*128:out  */ X86_MXCSR_PM | X86_MXCSR_PE,
-              /*256:out  */ X86_MXCSR_PM | X86_MXCSR_PE },
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_PE },
           { { /*src2     */ { FP32_0(0),        FP32_0(0),        FP32_0(0),        FP32_0(0),        FP32_0(0),        FP32_0(0),        FP32_0(0), FP32_NORM_MAX(1) } },
             { /*src1     */ { FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_0(1),        FP32_0(0), FP32_NORM_MAX(0) } },
@@ -6366,13 +6366,13 @@
             { /*src1     */ { FP32_V(0, 0x600000, 0x7f)/*1.75*/, FP32_V(0, 0,        0x7d)/*0.25*/, FP32_NORM_MAX(1),            FP32_0(0),        FP32_V(1, 0,        0x7e)/*-0.50*/, FP32_V(0, 0, 0x7d)/*-0.25*/, FP32_0(0),                         FP32_0(0)                         } },
             { /* =>      */ { FP32_V(0, 0x400000, 0x7f)/*1.50*/, FP32_NORM_MAX(1),                  FP32_V(1, 0, 0x7e)/*-0.50*/, FP32_NORM_MAX(0), FP32_V(1, 0x400000, 0x7e)/*-0.75*/, FP32_0(0),                   FP32_NORM_MAX(1),                  FP32_V(0, 0x400000, 0x7f)/*1.50*/ } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
           { { /*src2     */ { FP32_V(0, 0,        0x7d)/*0.25*/, FP32_V(0, 0x400000, 0x7e)/*0.75*/, FP32_NORM_MAX(0),            FP32_0(0),        FP32_0(0),                          FP32_NORM_MAX(0),            FP32_V(0, 0x600000, 0x7f)/*1.75*/, FP32_V(0, 0,        0x7d)/*0.25*/ } },
             { /*src1     */ { FP32_V(0, 0x600000, 0x7f)/*1.75*/, FP32_V(0, 0,        0x7d)/*0.25*/, FP32_NORM_MAX(1),            FP32_0(0),        FP32_V(1, 0,        0x7e)/*-0.50*/, FP32_V(0, 0, 0x7d)/*-0.25*/, FP32_0(0),                         FP32_0(0)                         } },
             { /* =>      */ { FP32_V(0, 0x400000, 0x7f)/*1.50*/, FP32_NORM_MAX(1),                  FP32_V(1, 0, 0x7e)/*-0.50*/, FP32_NORM_MAX(0), FP32_V(1, 0x400000, 0x7e)/*-0.75*/, FP32_0(1),                   FP32_NORM_MAX(1),                  FP32_V(0, 0x400000, 0x7f)/*1.50*/ } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_RC_DOWN },
           { { /*src2     */ { FP32_NORM_V1(0),  FP32_NORM_V1(0),  FP32_NORM_V4(0),  FP32_NORM_V4(0),  FP32_NORM_V1(0),  FP32_NORM_V1(0),  FP32_NORM_V2(0), FP32_NORM_V2(0) } },
             { /*src1     */ { FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MIN(0), FP32_NORM_MIN(0), FP32_NORM_MIN(0), FP32_NORM_MIN(0), FP32_NORM_V3(0), FP32_NORM_V3(0) } },
@@ -6390,25 +6390,25 @@
             { /*src1     */ { FP32_V(0, 0x669050, 0x93)/*1888778*/, FP32_V(0, 0x1ea980, 0x8f)/*  81235.00*/, FP32_V(0, 0x253468, 0x93)/*1353357*/, FP32_V(0, 0x7c9000, 0x88)/*1010.25*/, FP32_V(0, 0x780000, 0x84)/*     62*/, FP32_V(0, 0x600000, 0x81)/*7*/,       FP32_V(0, 0x534000, 0x86)/*    211.25*/, FP32_1(0)                            } },
             { /* =>      */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_V(1, 0x780000, 0x84)/*    -62*/, FP32_V(1, 0x5c0000, 0x84)/* -55.00*/, FP32_V(0, 0x5c0000, 0x84)/*     55*/, FP32_V(0, 0x524000, 0x86)/*210.25*/,  FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_V(1, 0x534000, 0x86)/*-211.25*/ } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP32_V(0, 0x3c614e, 0x97)/*24691356*/, FP32_V(0, 0x3c614e, 0x96)/*12345678*/, FP32_0(0),                             FP32_NORM_V1(0), FP32_V(0, 0x3c614e, 0x97)/*24691356*/, FP32_V(0, 0x3c614e, 0x96)/*12345678*/, FP32_2(0),                             FP32_1(0) } },
             { /*src1     */ { FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_V(0, 0x712060, 0x92)/*  987654*/, FP32_NORM_V5(0),                       FP32_0(0),       FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_V(0, 0x712060, 0x92)/*  987654*/, FP32_0(0),                             FP32_1(0) } },
             { /* =>      */ { FP32_V(0, 0x6cb99c, 0x97)/*31028024*/, FP32_NORM_V5(0),                       FP32_V(0, 0x3c614e, 0x96)/*12345678*/, FP32_NORM_V1(1), FP32_V(0, 0x6cb99c, 0x97)/*31028024*/, FP32_1(1),                             FP32_V(0, 0x3c614e, 0x96)/*12345678*/, FP32_1(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP32_V(0, 0x6423f2, 0x92)/* 934463.125*/, FP32_V(0, 0x0a19f0, 0x8f)/* 70707.875*/, FP32_NORM_SAFE_INT_MIN(1),               FP32_NORM_SAFE_INT_MIN(1),               FP32_1(1),                                FP32_1(0),                               FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/, FP32_V(0, 0x600000, 0x7e)/*     0.875*/ } },
             { /*src1     */ { FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/, FP32_V(0, 0x600000, 0x7e)/*     0.875*/, FP32_V(0, 0x10c030, 0x92)/*592899.000*/, FP32_V(0, 0x3ce348, 0x90)/*193421.125*/, FP32_V(1, 0x16b43a, 0x93)/*-1234567.25*/, FP32_V(0, 0x00c6d3, 0x94)/*2109876.75*/, FP32_V(0, 0x792318, 0x91)/*510232.750*/,  FP32_V(0, 0x316740, 0x8e)/*  45415.250*/ } },
             { /* =>      */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_V(0, 0x430ebc, 0x91)/*399477.875*/, FP32_V(0, 0x52e0b4, 0x92)/*863755.250*/, FP32_0(0),                               FP32_V(1, 0x4c20f0, 0x94)/*-3344444.00*/, FP32_V(0, 0x62f630, 0x91)/* 464817.50*/, FP32_2(1),                                FP32_V(0, 0x769b50, 0x92)/*1010101.000*/ } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP32_2(0),                                                FP32_1(0),                                                FP32_1(1),                 FP32_1(0), FP32_2(0),                                                FP32_1(0),                                                FP32_1(0),                 FP32_1(0) } },
             { /*src1     */ { FP32_V(1, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_1(0),                                                FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_V(1, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_1(0),                                                FP32_NORM_SAFE_INT_MAX(0), FP32_1(0) } },
             { /* =>      */ { FP32_NORM_SAFE_INT_MAX(1),                                FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_1(0),                 FP32_2(1), FP32_NORM_SAFE_INT_MAX(1),                                FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_1(0),                 FP32_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
           { { /*src2     */ { FP32_2(0),                                                FP32_1(0),                                                FP32_1(1),                 FP32_1(0), FP32_2(0),                                                FP32_1(0),                                                FP32_1(0),                 FP32_1(0) } },
             { /*src1     */ { FP32_V(1, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_1(0),                                                FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_V(1, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_1(0),                                                FP32_NORM_SAFE_INT_MAX(0), FP32_1(0) } },
@@ -6450,7 +6450,7 @@
             { /*src1     */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0) } },
             { /* =>      */ { FP32_0(0), FP32_0(0),          FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0),          FP32_0(0), FP32_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ X86_MXCSR_DAZ,
+              /*128:out  */ X86_MXCSR_DAZ,
+              /*256:out  */ X86_MXCSR_DAZ },
           { { /*src2     */ { FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } },
             { /*src1     */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0) } },
@@ -6483,13 +6483,13 @@
             { /*src1     */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0)          } },
             { /* =>      */ { FP32_0(0), FP32_0(0),          FP32_0(0), FP32_0(0), FP32_0(0),          FP32_0(0), FP32_0(0), FP32_0(0)          } },
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ X86_MXCSR_DAZ,
+              /*128:out  */ X86_MXCSR_DAZ,
+              /*256:out  */ X86_MXCSR_DAZ },
           { { /*src2     */ { FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } },
             { /*src1     */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0) } },
             { /* =>      */ { FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0)          } },
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP },
           /** @todo More Denormals. */
     /*
@@ -6588,13 +6588,13 @@
             { /*src1     */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } },
             { /* =>      */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
           { { /*src2     */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(1) } },
             { /*src1     */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(0) } },
             { /* =>      */ { FP64_0(1), FP64_0(0), FP64_0(1), FP64_0(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_RC_DOWN },
     /*
      * Infinity.
@@ -6603,19 +6603,19 @@
             { /*src1     */ { FP64_INF(1), FP64_INF(0), FP64_0(0),   FP64_0(0)   } },
             { /* =>      */ { FP64_INF(1), FP64_INF(0), FP64_0(0),   FP64_INF(0) } },
-              /*mxcsr:in */ X86_MXCSR_IM,
-              /*128:out  */ X86_MXCSR_IM,
-              /*256:out  */ X86_MXCSR_IM },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP64_0(0), FP64_0(0), FP64_INF(1), FP64_INF(1)  } },
             { /*src1     */ { FP64_0(0), FP64_0(0), FP64_INF(1), FP64_INF(0)  } },
             { /* =>      */ { FP64_0(0), FP64_0(0), FP64_INF(1), FP64_QNAN(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ X86_MXCSR_IE },
           { { /*src2     */ { FP64_INF(0), FP64_INF(1), FP64_INF(0), FP64_INF(1) } },
             { /*src1     */ { FP64_INF(1), FP64_INF(0), FP64_0(0),   FP64_0(0)   } },
             { /* =>      */ { FP64_INF(1), FP64_INF(0), FP64_0(0),   FP64_INF(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ },
+              /*mxcsr:in */ X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_FZ,
+              /*256:out  */ X86_MXCSR_FZ },
           { { /*src2     */ { FP64_INF(1),  FP64_INF(1),  FP64_INF(0), FP64_0(0)   } },
             { /*src1     */ { FP64_INF(0),  FP64_INF(0),  FP64_INF(1), FP64_0(0)   } },
@@ -6627,7 +6627,7 @@
             { /*src1     */ { FP64_INF(0),  FP64_QNAN(0), FP64_INF(1),  FP64_QNAN(0) } },
             { /* =>      */ { FP64_QNAN(0), FP64_QNAN(1), FP64_QNAN(0), FP64_QNAN(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP },
+              /*mxcsr:in */ X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_RC_UP },
     /*
      * Overflow, Precision.
@@ -6642,7 +6642,7 @@
             { /*src1     */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MIN(0), FP64_NORM_MAX(0) } },
             { /* =>      */ { FP64_INF(0),      FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_0(0)       } },
-              /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM,
-              /*128:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
-              /*256:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE },
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_OE | X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_OE | X86_MXCSR_PE },
           { { /*src2     */ { FP64_NORM_MAX(1), FP64_NORM_MAX(0), FP64_2(0),        FP64_1(0)        } },
             { /*src1     */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } },
@@ -6672,7 +6672,7 @@
             { /*src1     */ { FP64_NORM_MIN(1), FP64_NORM_MAX(0), FP64_NORM_MIN(0), FP64_NORM_MAX(1) } },
             { /* =>      */ { FP64_NORM_MAX(1), FP64_0(0),        FP64_INF(0),      FP64_NORM_MAX(1) } },
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_PE,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE },
           { { /*src2     */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MIN(1),                                     FP64_NORM_MAX(0) } },
             { /*src1     */ { FP64_NORM_MIN(1), FP64_NORM_MIN(1), FP64_NORM_MIN(0),                                     FP64_NORM_MAX(0) } },
@@ -6690,13 +6690,13 @@
             { /*src1     */ { FP64_NORM_SAFE_INT_MIN(0),                                FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0),                                FP64_NORM_SAFE_INT_MIN(0) } },
             { /* =>      */ { FP64_V(1, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_NORM_SAFE_INT_MAX(1), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_0(0)                 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_PE },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE },
           { { /*src2     */ { FP64_NORM_SAFE_INT_MIN(1),                                FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0) } },
             { /*src1     */ { FP64_NORM_SAFE_INT_MIN(0),                                FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MIN(0) } },
             { /* =>      */ { FP64_V(1, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MAX(0), FP64_0(0)                 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_PE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_PE },
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_PE },
     /*
      * Denormals.
@@ -6726,7 +6726,7 @@
             { /*src1     */ { FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(1), FP64_DENORM_MAX(1) } },
             { /* =>      */ { FP64_0(0),          FP64_0(0),          FP64_0(0),          FP64_0(0)          } },
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ X86_MXCSR_DAZ,
+              /*128:out  */ X86_MXCSR_DAZ,
+              /*256:out  */ X86_MXCSR_DAZ },
  /*26|27*/{ { /*src2     */ { FP64_DENORM_MAX(0), FP64_0(0), FP64_0(0),          FP64_0(0) } },
             { /*src1     */ { FP64_0(0),          FP64_0(0), FP64_DENORM_MIN(0), FP64_0(0) } },
@@ -6753,7 +6753,7 @@
             { /*src1     */ { FP64_0(1), FP64_DENORM_MAX(0), FP64_DENORM_MAX(1), FP64_0(0)          } },
             { /* =>      */ { FP64_0(1), FP64_0(0),          FP64_0(1),          FP64_0(0)          } },
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
           { { /*src2     */ { FP64_0(0), FP64_0(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } },
             { /*src1     */ { FP64_0(0), FP64_0(0), FP64_DENORM_MIN(1), FP64_DENORM_MIN(1) } },
@@ -6863,13 +6863,13 @@
             { /*src1     */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1) } },
             { /* =>      */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO },
           { { /*src2     */ { FP32_NORM_V0(0), FP32_NORM_V1(1), FP32_0(0),       FP32_NORM_V3(1), FP32_0(0), FP32_NORM_V1(1), FP32_NORM_V4(0), FP32_NORM_V3(0) } },
             { /*src1     */ { FP32_0(0),       FP32_0(0),       FP32_NORM_V2(1), FP32_0(1),       FP32_0(0), FP32_0(1),       FP32_0(0),       FP32_0(1)       } },
             { /* =>      */ { FP32_0(0),       FP32_0(1),       FP32_0(1),       FP32_0(0),       FP32_0(0), FP32_0(0),       FP32_0(0),       FP32_0(1)       } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
     /*
      * Infinity.
@@ -6878,19 +6878,19 @@
             { /*src1     */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
             { /* =>      */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
-              /*128:out  */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
-              /*256:out  */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
             { /*src1     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
             { /* =>      */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0), FP32_0(1), FP32_0(1), FP32_0(0) } },
             { /*src1     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(1), FP32_0(1), FP32_0(0) } },
             { /* =>      */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_FZ,
+              /*256:out  */ X86_MXCSR_FZ },
           { { /*src2     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0) } },
             { /*src1     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1) } },
@@ -6908,7 +6908,7 @@
             { /*src1     */ { FP32_0(0),    FP32_INF(1),  FP32_0(1),    FP32_INF(1),  FP32_0(0),    FP32_INF(0),  FP32_0(0),    FP32_INF(1)  } },
             { /* =>      */ { FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE },
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_IE },
           { { /*src2     */ { FP32_INF(0),  FP32_0(0),    FP32_INF(0),  FP32_0(1),    FP32_INF(0),  FP32_0(1),    FP32_INF(1),  FP32_0(1)    } },
             { /*src1     */ { FP32_0(0),    FP32_INF(1),  FP32_0(1),    FP32_INF(1),  FP32_0(0),    FP32_INF(0),  FP32_0(0),    FP32_INF(1)  } },
@@ -7043,19 +7043,19 @@
             { /*src1     */ { FP32_V(0, 0,        0x7d)/*0.2500*/, FP32_1(0),       FP32_1(1),       FP32_0(0),       FP32_NORM_V0(1), FP32_NORM_V3(0), FP32_NORM_V4(0), FP32_1(0)       } },
             { /* =>      */ { FP32_V(0, 0x600000, 0x7d)/*0.4375*/, FP32_NORM_V0(0), FP32_NORM_V1(1), FP32_0(1),       FP32_NORM_V0(0), FP32_NORM_V3(0), FP32_NORM_V4(1), FP32_NORM_V6(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
           { { /*src2     */ { FP32_V(0, 0x61e000, 0x89)/*   1807*/, FP32_V(0, 0x61e000, 0x89)/*   1807*/, FP32_V(0, 0x4a30b8, 0x8f)/* 103521.4375*/, FP32_V(0, 0x1a5200, 0x8c)/*     9876.5*/, FP32_V(0, 0x23b6a0, 0x8e)/*41910.625000*/, FP32_V(0, 0x23b6a0, 0x8e)/*41910.625000*/, FP32_V(0, 0,        0x7d)/*0.2500*/, FP32_V(0, 0x504000, 0x8a)/*    3332*/ } },
             { /*src1     */ { FP32_V(0, 0x504000, 0x8a)/*   3332*/, FP32_V(0, 0x504000, 0x8a)/*   3332*/, FP32_V(0, 0x600000, 0x82)/*     14.0000*/, FP32_V(1, 0x1a4000, 0x89)/*    -1234.0*/, FP32_V(0, 0,        0x7c)/*    0.125000*/, FP32_V(0, 0,        0x7c)/*    0.125000*/, FP32_V(0, 0x600000, 0x7f)/*1.7500*/, FP32_V(1, 0x61e000, 0x89)/*   -1807*/ } },
             { /* =>      */ { FP32_V(0, 0x37be78, 0x95)/*6020924*/, FP32_V(0, 0x37be78, 0x95)/*6020924*/, FP32_V(0, 0x30eaa1, 0x93)/*1449300.1250*/, FP32_V(1, 0x39f7d1, 0x96)/*-12187601.0*/, FP32_V(0, 0x23b6a0, 0x8b)/* 5238.828125*/, FP32_V(0, 0x23b6a0, 0x8b)/* 5238.828125*/, FP32_V(0, 0x600000, 0x7d)/*0.4375*/, FP32_V(1, 0x37be78, 0x95)/*-6020924*/ } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP32_NORM_SAFE_INT_MAX(0), FP32_1(0),                 FP32_NORM_SAFE_INT_MAX(1), FP32_1(1),                 FP32_NORM_SAFE_INT_MIN(1), FP32_1(1),                 FP32_NORM_SAFE_INT_MIN(0), FP32_0(1)                 } },
             { /*src1     */ { FP32_1(0),                 FP32_NORM_SAFE_INT_MIN(0), FP32_1(0),                 FP32_NORM_SAFE_INT_MAX(1), FP32_1(0),                 FP32_NORM_SAFE_INT_MIN(1), FP32_0(0),                 FP32_NORM_SAFE_INT_MAX(0) } },
             { /* =>      */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_0(0),                 FP32_0(1)                 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
           { { /*src2     */ { FP32_NORM_MAX(0), FP32_1(0),        FP32_NORM_MAX(1), FP32_1(1),        FP32_NORM_MIN(0), FP32_NORM_MIN(0), FP32_1(0),        FP32_1(1)        } },
             { /*src1     */ { FP32_1(0),        FP32_NORM_MAX(1), FP32_1(0),        FP32_NORM_MAX(1), FP32_1(0),        FP32_1(1),        FP32_NORM_MIN(1), FP32_NORM_MIN(1) } },
@@ -7097,13 +7097,13 @@
             { /*src1     */ { FP32_0(0),          FP32_0(1),          FP32_0(0),          FP32_0(1),          FP32_DENORM_MAX(0), FP32_DENORM_MAX(1), FP32_DENORM_MAX(0), FP32_DENORM_MAX(1) } },
             { /* =>      */ { FP32_0(0),          FP32_0(1),          FP32_0(1),          FP32_0(0),          FP32_0(0),          FP32_0(1),          FP32_0(1),          FP32_0(0)          } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ },
+              /*mxcsr:in */ X86_MXCSR_DAZ,
+              /*128:out  */ X86_MXCSR_DAZ,
+              /*256:out  */ X86_MXCSR_DAZ },
           { { /*src2     */ { FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(1), FP32_DENORM_MAX(1), FP32_1(0),          FP32_1(0),          FP32_1(1),          FP32_1(1)          } },
             { /*src1     */ { FP32_1(0),          FP32_1(1),          FP32_1(0),          FP32_1(1),          FP32_DENORM_MAX(0), FP32_DENORM_MAX(1), FP32_DENORM_MAX(0), FP32_DENORM_MAX(1) } },
             { /* =>      */ { FP32_0(0),          FP32_0(1),          FP32_0(1),          FP32_0(0),          FP32_0(0),          FP32_0(1),          FP32_0(1),          FP32_0(0)          } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ },
+              /*mxcsr:in */ X86_MXCSR_DAZ,
+              /*128:out  */ X86_MXCSR_DAZ,
+              /*256:out  */ X86_MXCSR_DAZ },
           { { /*src2     */ { FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(1), FP32_DENORM_MIN(1), FP32_0(0),          FP32_0(0),          FP32_0(1),          FP32_0(1)          } },
             { /*src1     */ { FP32_0(0),          FP32_0(1),          FP32_0(0),          FP32_0(1),          FP32_DENORM_MIN(0), FP32_DENORM_MIN(1), FP32_DENORM_MIN(0), FP32_DENORM_MIN(1) } },
@@ -7135,37 +7135,37 @@
             { /*src1     */ { FP32_0(0),          FP32_0(1),          FP32_0(0),          FP32_0(1),          FP32_DENORM_MIN(0), FP32_DENORM_MIN(1), FP32_DENORM_MIN(0), FP32_DENORM_MIN(1) } },
             { /* =>      */ { FP32_0(0),          FP32_0(1),          FP32_0(1),          FP32_0(0),          FP32_0(0),          FP32_0(1),          FP32_0(1),          FP32_0(0)          } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ },
+              /*mxcsr:in */ X86_MXCSR_DAZ,
+              /*128:out  */ X86_MXCSR_DAZ,
+              /*256:out  */ X86_MXCSR_DAZ },
           { { /*src2     */ { FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(1), FP32_DENORM_MIN(1), FP32_1(0),          FP32_1(0),          FP32_1(1),          FP32_1(1)          } },
             { /*src1     */ { FP32_1(0),          FP32_1(1),          FP32_1(0),          FP32_1(1),          FP32_DENORM_MIN(0), FP32_DENORM_MIN(1), FP32_DENORM_MIN(0), FP32_DENORM_MIN(1) } },
             { /* =>      */ { FP32_0(0),          FP32_0(1),          FP32_0(1),          FP32_0(0),          FP32_0(0),          FP32_0(1),          FP32_0(1),          FP32_0(0)          } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ },
+              /*mxcsr:in */ X86_MXCSR_DAZ,
+              /*128:out  */ X86_MXCSR_DAZ,
+              /*256:out  */ X86_MXCSR_DAZ },
           { { /*src2     */ { FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(1), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(1) } },
             { /*src1     */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(1), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1) } },
             { /* =>      */ { FP32_0(0),          FP32_0(1),          FP32_0(1),          FP32_0(0),          FP32_0(0),          FP32_0(1),          FP32_0(1),          FP32_0(0)          } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP },
           { { /*src2     */ { FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(1), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(1) } },
             { /*src1     */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(1), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1) } },
             { /* =>      */ { FP32_0(0),          FP32_0(1),          FP32_0(1),          FP32_0(0),          FP32_0(0),          FP32_0(1),          FP32_0(1),          FP32_0(0)          } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN },
           { { /*src2     */ { FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(1), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(1) } },
             { /*src1     */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(1), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1) } },
             { /* =>      */ { FP32_0(0),          FP32_0(1),          FP32_0(1),          FP32_0(0),          FP32_0(0),          FP32_0(1),          FP32_0(1),          FP32_0(0)          } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO },
           { { /*src2     */ { FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(1), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(1) } },
             { /*src1     */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(1), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1) } },
             { /* =>      */ { FP32_0(0),          FP32_0(1),          FP32_0(1),          FP32_0(0),          FP32_0(0),          FP32_0(1),          FP32_0(1),          FP32_0(0)          } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ },
     /** @todo More Denormals. */
     /*
@@ -7240,7 +7240,7 @@
             { /*src1     */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
             { /* =>      */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
             { /*src1     */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
@@ -7270,13 +7270,13 @@
             { /*src1     */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(1) } },
             { /* =>      */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
           { { /*src2     */ { FP64_NORM_V0(0), FP64_NORM_V1(1), FP64_0(0),       FP64_NORM_V3(1) } },
             { /*src1     */ { FP64_0(0),       FP64_0(0),       FP64_NORM_V2(1), FP64_0(1)       } },
             { /* =>      */ { FP64_0(0),       FP64_0(1),       FP64_0(1),       FP64_0(0)       } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
     /*
      * Infinity.
@@ -7285,13 +7285,13 @@
             { /*src1     */ { FP64_INF(1), FP64_0(0), FP64_INF(0), FP64_0(0) } },
             { /* =>      */ { FP64_INF(1), FP64_0(0), FP64_INF(1), FP64_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
-              /*128:out  */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
-              /*256:out  */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP64_INF(0), FP64_INF(0), FP64_INF(1), FP64_INF(1) } },
             { /*src1     */ { FP64_INF(1), FP64_INF(0), FP64_INF(1), FP64_INF(0) } },
             { /* =>      */ { FP64_INF(1), FP64_INF(0), FP64_INF(0), FP64_INF(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP64_INF(0), FP64_INF(1), FP64_0(1), FP64_INF(0) } },
             { /*src1     */ { FP64_INF(1), FP64_INF(0), FP64_0(1), FP64_INF(0) } },
@@ -7303,19 +7303,19 @@
             { /*src1     */ { FP64_INF(1), FP64_INF(0), FP64_0(1), FP64_INF(0) } },
             { /* =>      */ { FP64_INF(1), FP64_INF(1), FP64_0(0), FP64_INF(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
           { { /*src2     */ { FP64_INF(0), FP64_INF(0),     FP64_1(0),   FP64_INF(0)     } },
             { /*src1     */ { FP64_1(0),   FP64_NORM_V0(0), FP64_INF(0), FP64_NORM_V1(0) } },
             { /* =>      */ { FP64_INF(0), FP64_INF(0),     FP64_INF(0), FP64_INF(0)     } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_RC_DOWN },
           { { /*src2     */ { FP64_INF(1), FP64_INF(0),     FP64_NORM_V3(0), FP64_INF(1)     } },
             { /*src1     */ { FP64_1(1),   FP64_NORM_V3(1), FP64_INF(1),     FP64_NORM_V1(1) } },
             { /* =>      */ { FP64_INF(0), FP64_INF(1),     FP64_INF(1),     FP64_INF(0)     } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP },
     /*
      * Normals.
@@ -7324,31 +7324,31 @@
             { /*src1     */ { FP64_1(0),                                         FP64_V(0, 0x2d69a80000000, 0x413)/*  1234586.50*/, FP64_V(1, 0x4000000000000, 0x400)/*             -2.50*/, FP64_V(0, 0xb800000000000, 0x402)/*          13.75000*/ } },
             { /* =>      */ { FP64_V(0, 0xe66f500000000, 0x40d)/*31131.828125*/, FP64_V(0, 0xfb74e1d800000, 0x41a)/*266053390.75*/, FP64_V(0, 0x549270a11c760, 0x42c)/* 46807863534478.75*/, FP64_V(0, 0x3c30944926c00, 0x424)/*169753086244.84375*/ } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP64_NORM_MAX(1), FP64_NORM_V3(1), FP64_1(0),       FP64_1(1)        } },
             { /*src1     */ { FP64_1(1),        FP64_1(0),       FP64_NORM_V1(0), FP64_NORM_MIN(1) } },
             { /* =>      */ { FP64_NORM_MAX(0), FP64_NORM_V3(1), FP64_NORM_V1(0), FP64_NORM_MIN(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_RC_DOWN },
           { { /*src2     */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_V(1, 0x68b83b1ed4000, 0x41e)/*-3025935759.4140625*/, FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646*/, FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/ } },
             { /*src1     */ { FP64_V(0, 0x8000000000000, 0x3fe)/*              0.75*/, FP64_V(1, 0,               0x400)/*         -2.0000000*/, FP64_1(0),                                            FP64_V(0, 0x8000000000000, 0x400)/*              3.00*/ } },
             { /* =>      */ { FP64_V(0, 0x4da20a80c6990, 0x42e)/*183416666481484.50*/, FP64_V(0, 0x68b83b1ed4000, 0x41f)/* 6051871518.8281250*/, FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646*/, FP64_V(0, 0x4a6a82b05f744, 0x42f)/*363296296296308.25*/ } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_RC_DOWN },
           { { /*src2     */ { FP64_1(0),                 FP64_1(0),                                                FP64_NORM_SAFE_INT_MIN(0), FP64_1(0)                 } },
             { /*src1     */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_1(0),                 FP64_NORM_SAFE_INT_MIN(1) } },
             { /* =>      */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
           { { /*src2     */ { FP64_NORM_V0(0), FP64_NORM_V1(1), FP64_NORM_V2(0), FP64_NORM_V3(1) } },
             { /*src1     */ { FP64_1(0),       FP64_1(1),       FP64_1(1),       FP64_1(1)       } },
             { /* =>      */ { FP64_NORM_V0(0), FP64_NORM_V1(0), FP64_NORM_V2(1), FP64_NORM_V3(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_RC_DOWN },
           /** @todo More Normals. */
     /*
@@ -7376,19 +7376,19 @@
             { /*src1     */ { FP64_1(0),          FP64_DENORM_MAX(0), FP64_1(0),          FP64_DENORM_MIN(0) } },
             { /* =>      */ { FP64_0(0),          FP64_0(0),          FP64_0(0),          FP64_0(0)          } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ },
           { { /*src2     */ { FP64_DENORM_MIN(1), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(1) } },
             { /*src1     */ { FP64_DENORM_MAX(1), FP64_DENORM_MIN(1), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } },
             { /* =>      */ { FP64_0(0),          FP64_0(1),          FP64_0(0),          FP64_0(1)         } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP },
           { { /*src2     */ { FP64_1(0),       FP64_NORM_V1(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } },
             { /*src1     */ { FP64_NORM_V0(0), FP64_1(0),       FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } },
             { /* =>      */ { FP64_NORM_V0(0), FP64_NORM_V1(0), FP64_0(0),          FP64_0(0)          } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_DE | X86_MXCSR_UE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */ },
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_DE | X86_MXCSR_UE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */ },
           { { /*src2     */ { FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(1) } },
             { /*src1     */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(1), FP64_DENORM_MIN(1) } },
@@ -7409,43 +7409,43 @@
             { /*src1     */ { FP64_1(0),       FP64_1(0), FP64_1(0),        FP64_NORM_MAX(0) } },
             { /* =>      */ { FP64_NORM_V3(1), FP64_1(0), FP64_NORM_MAX(0), FP64_INF(0)      } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */ },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */ },
           { { /*src2     */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_V3(1), FP64_1(0) } },
             { /*src1     */ { FP64_1(0),        FP64_NORM_MAX(0), FP64_1(0),       FP64_1(0) } },
             { /* =>      */ { FP64_NORM_MAX(0), FP64_INF(0),      FP64_NORM_V3(1), FP64_1(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */ },
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */,
+              /*256:out  */ X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */ },
           { { /*src2     */ { FP64_NORM_V3(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_1(0)       } },
             { /*src1     */ { FP64_1(0),       FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_V1(0) } },
             { /* =>      */ { FP64_NORM_V3(0), FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_V1(0) } },
-              /*mxcsr:in */ (X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM)) | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ (X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM)) | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */,
-              /*256:out  */ (X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM)) | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */ },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */ },
           { { /*src2     */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MIN(1),                                       FP64_NORM_MAX(0) } },
             { /*src1     */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MAX(1),                                       FP64_NORM_MAX(0) } },
             { /* =>      */ { FP64_INF(0),      FP64_0(0),        FP64_V(0, FP64_FRAC_NORM_MAX, RTFLOAT64U_EXP_BIAS + 1), FP64_INF(0)      } },
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM,
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_UE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_UE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */ },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_UE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OE | X86_MXCSR_UE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */ },
           { { /*src2     */ { FP64_NORM_V3(0), FP64_1(1),       FP64_NORM_MAX(1), FP64_NORM_MIN(0)                                       } },
             { /*src1     */ { FP64_1(0),       FP64_NORM_V2(1), FP64_NORM_MAX(1), FP64_NORM_MAX(1)                                       } },
             { /* =>      */ { FP64_NORM_V3(0), FP64_NORM_V2(0), FP64_NORM_MAX(0), FP64_V(1, FP64_FRAC_NORM_MAX, RTFLOAT64U_EXP_BIAS + 1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM) | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM) | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM) | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */ },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */ },
           { { /*src2     */ { FP64_NORM_SAFE_INT_MIN(0),                         FP64_NORM_MAX(0), FP64_NORM_SAFE_INT_MAX(1),                FP64_NORM_SAFE_INT_MIN(0)            } },
             { /*src1     */ { FP64_NORM_SAFE_INT_MAX(0),                         FP64_NORM_MAX(1), FP64_NORM_SAFE_INT_MAX(1),                FP64_NORM_SAFE_INT_MAX(0)            } },
             { /* =>      */ { FP64_V(0, FP64_FRAC_NORM_MAX, FP64_FRAC_BITS + 1), FP64_NORM_MAX(1), FP64_V(0, FP64_FRAC_NORM_MAX - 1, 0x468), FP64_V(0, FP64_FRAC_NORM_MAX, 0x035) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */ },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */,
+              /*256:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */ },
           { { /*src2     */ { FP64_NORM_SAFE_INT_MIN(0),                         FP64_NORM_MAX(0), FP64_NORM_SAFE_INT_MAX(1),                FP64_NORM_SAFE_INT_MIN(0)            } },
             { /*src1     */ { FP64_NORM_SAFE_INT_MAX(0),                         FP64_NORM_MAX(1), FP64_NORM_SAFE_INT_MAX(1),                FP64_NORM_SAFE_INT_MAX(0)            } },
             { /* =>      */ { FP64_V(0, FP64_FRAC_NORM_MAX, FP64_FRAC_BITS + 1), FP64_INF(1),      FP64_V(0, FP64_FRAC_NORM_MAX - 1, 0x468), FP64_V(0, FP64_FRAC_NORM_MAX, 0x035) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_OE | X86_MXCSR_PE },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_OE | X86_MXCSR_PE },
     /*
      * Invalids.
@@ -7525,12 +7525,12 @@
             { /*src1     */ { FP32_0(0), FP32_0_x7(0) } },
             { /* =>      */ { FP32_0(0), FP32_0_x7(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_0(0), FP32_RAND_x7_V1 } },
             { /*src1     */ { FP32_0(0), FP32_RAND_x7_V2 } },
             { /* =>      */ { FP32_0(0), FP32_RAND_x7_V2 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_0(1), FP32_RAND_x7_V4 } },
@@ -7549,12 +7549,12 @@
             { /*src1     */ { FP32_0(1), FP32_RAND_x7_V1 } },
             { /* =>      */ { FP32_0(1), FP32_RAND_x7_V1 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
+              /*mxcsr:in */ X86_MXCSR_DAZ,
+              /*128:out  */ X86_MXCSR_DAZ,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_0(0), FP32_RAND_x7_V5 } },
             { /*src1     */ { FP32_1(0), FP32_RAND_x7_V2 } },
             { /* =>      */ { FP32_0(0), FP32_RAND_x7_V2 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*256:out  */ -1 },
     /*
@@ -7564,30 +7564,30 @@
             { /*src1     */ { FP32_1(1),   FP32_0_x7(0) } },
             { /* =>      */ { FP32_INF(1), FP32_0_x7(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
-              /*128:out  */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_INF(1), FP32_0_x7(0) } },
             { /*src1     */ { FP32_1(1),   FP32_0_x7(0) } },
             { /* =>      */ { FP32_INF(0), FP32_0_x7(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_INF(0), FP32_RAND_x7_V7 } },
             { /*src1     */ { FP32_INF(0), FP32_RAND_x7_V0 } },
             { /* =>      */ { FP32_INF(0), FP32_RAND_x7_V0 } },
-              /*mxcsr:in */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_DAZ | X86_MXCSR_FZ,
-              /*128:out  */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_DAZ | X86_MXCSR_FZ,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_INF(1), FP32_RAND_x7_V7 } },
             { /*src1     */ { FP32_INF(0), FP32_RAND_x7_V1 } },
             { /* =>      */ { FP32_INF(1), FP32_RAND_x7_V1 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_1(0),   FP32_RAND_x7_V3 } },
             { /*src1     */ { FP32_INF(0), FP32_RAND_x7_V2 } },
             { /* =>      */ { FP32_INF(0), FP32_RAND_x7_V2 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
+              /*mxcsr:in */ X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_FZ,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_INF(0), FP32_RAND_x7_V0 } },
@@ -7609,30 +7609,30 @@
             { /*src1     */ { FP32_V(0, 0,        0x7d)/*0.2500*/, FP32_RAND_x7_V4 } },
             { /* =>      */ { FP32_V(0, 0x600000, 0x7d)/*0.4375*/, FP32_RAND_x7_V4 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_V(0, 0x61e000, 0x89)/*   1807*/, FP32_RAND_x7_V4 } },
             { /*src1     */ { FP32_V(0, 0x504000, 0x8a)/*   3332*/, FP32_RAND_x7_V5 } },
             { /* =>      */ { FP32_V(0, 0x37be78, 0x95)/*6020924*/, FP32_RAND_x7_V5 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V6 } },
             { /*src1     */ { FP32_1(0),                 FP32_RAND_x7_V6 } },
             { /* =>      */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V6 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_V(0, 0x61e000, 0x89)/*   1807*/, FP32_RAND_x7_V6 } },
             { /*src1     */ { FP32_V(0, 0x504000, 0x8a)/*   3332*/, FP32_RAND_x7_V2 } },
             { /* =>      */ { FP32_V(0, 0x37be78, 0x95)/*6020924*/, FP32_RAND_x7_V2 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
+              /*mxcsr:in */ X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_RC_UP,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_V(0, 0x4a30b8, 0x8f)/* 103521.4375*/, FP32_RAND_x7_V7 } },
             { /*src1     */ { FP32_V(0, 0x600000, 0x82)/*     14.0000*/, FP32_RAND_x7_V2 } },
             { /* =>      */ { FP32_V(0, 0x30eaa1, 0x93)/*1449300.1250*/, FP32_RAND_x7_V2 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_V(0, 0x1a5200, 0x8c)/*     9876.5*/, FP32_RAND_x7_V3 } },
@@ -7679,12 +7679,12 @@
             { /*src1     */ { FP32_DENORM_MIN(1), FP32_RAND_x7_V2 } },
             { /* =>      */ { FP32_0(1),          FP32_RAND_x7_V2 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_DE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_DENORM_MIN(0), FP32_RAND_x7_V3 } },
             { /*src1     */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V3 } },
             { /* =>      */ { FP32_0(0),          FP32_RAND_x7_V3 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
               /*256:out  */ -1 },
     /** @todo More Denormals. */
@@ -7755,12 +7755,12 @@
             { /*src1     */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
             { /* =>      */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_0(0), FP64_NORM_V3(0), FP64_NORM_V2(0), FP64_0(0)       } },
             { /*src1     */ { FP64_0(0), FP64_0(1),       FP64_0(1),       FP64_NORM_V1(0) } },
             { /* =>      */ { FP64_0(0), FP64_0(1),       FP64_0(1),       FP64_NORM_V1(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_0(1), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V1(1) } },
@@ -7779,12 +7779,12 @@
             { /*src1     */ { FP64_0(1), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V0(0) } },
             { /* =>      */ { FP64_0(1), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
+              /*mxcsr:in */ X86_MXCSR_DAZ,
+              /*128:out  */ X86_MXCSR_DAZ,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
             { /*src1     */ { FP64_1(0), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V0(0) } },
             { /* =>      */ { FP64_0(0), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*256:out  */ -1 },
     /*
@@ -7794,30 +7794,30 @@
             { /*src1     */ { FP64_1(1),   FP64_0(0), FP64_0(0), FP64_0(0) } },
             { /* =>      */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
-              /*128:out  */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_0(0) } },
             { /*src1     */ { FP64_1(1),   FP64_0(0), FP64_0(0), FP64_0(0) } },
             { /* =>      */ { FP64_INF(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_INF(0), FP64_RAND_V1(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },
             { /*src1     */ { FP64_INF(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } },
             { /* =>      */ { FP64_INF(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } },
-              /*mxcsr:in */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_DAZ | X86_MXCSR_FZ,
-              /*128:out  */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_DAZ | X86_MXCSR_FZ,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_INF(1), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V1(1) } },
             { /*src1     */ { FP64_INF(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V0(0) } },
             { /* =>      */ { FP64_INF(1), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_1(0),   FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } },
             { /*src1     */ { FP64_INF(0), FP64_RAND_V1(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },
             { /* =>      */ { FP64_INF(0), FP64_RAND_V1(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
+              /*mxcsr:in */ X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_FZ,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_INF(0), FP64_INF(0), FP64_INF(1), FP64_INF(1) } },
@@ -7839,60 +7839,60 @@
             { /*src1     */ { FP64_1(0),                                         FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } },
             { /* =>      */ { FP64_V(0, 0xe66f500000000, 0x40d)/*31131.828125*/, FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_V(0, 0xaf00000000000, 0x406)/*      215.50*/, FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } },
             { /*src1     */ { FP64_V(0, 0x2d69a80000000, 0x413)/*  1234586.50*/, FP64_RAND_V1(0), FP64_RAND_V1(1), FP64_RAND_V0(1) } },
             { /* =>      */ { FP64_V(0, 0xfb74e1d800000, 0x41a)/*266053390.75*/, FP64_RAND_V1(0), FP64_RAND_V1(1), FP64_RAND_V0(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_V(1, 0x107526e749f80, 0x42b)/*-18723145413791.50*/, FP64_RAND_V3(0), FP64_RAND_V1(0), FP64_RAND_V1(1) } },
             { /*src1     */ { FP64_V(1, 0x4000000000000, 0x400)/*             -2.50*/, FP64_RAND_V0(0), FP64_RAND_V2(1), FP64_RAND_V2(1) } },
             { /* =>      */ { FP64_V(0, 0x549270a11c760, 0x42c)/* 46807863534478.75*/, FP64_RAND_V0(0), FP64_RAND_V2(1), FP64_RAND_V2(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_V(0, 0x6fee0e4bd0000, 0x420)/* 12345678999.62500*/, FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } },
             { /*src1     */ { FP64_V(0, 0xb800000000000, 0x402)/*          13.75000*/, FP64_RAND_V2(0), FP64_RAND_V1(1), FP64_RAND_V3(1) } },
             { /* =>      */ { FP64_V(0, 0x3c30944926c00, 0x424)/*169753086244.84375*/, FP64_RAND_V2(0), FP64_RAND_V1(1), FP64_RAND_V3(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_NORM_MAX(1), FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } },
             { /*src1     */ { FP64_1(1),        FP64_RAND_V1(1), FP64_RAND_V0(0), FP64_RAND_V2(0) } },
             { /* =>      */ { FP64_NORM_MAX(0), FP64_RAND_V1(1), FP64_RAND_V0(0), FP64_RAND_V2(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
+              /*mxcsr:in */ X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_RC_DOWN,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_RAND_V2(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } },
             { /*src1     */ { FP64_V(0, 0x8000000000000, 0x3fe)/*              0.75*/, FP64_RAND_V1(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } },
             { /* =>      */ { FP64_V(0, 0x4da20a80c6990, 0x42e)/*183416666481484.50*/, FP64_RAND_V1(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
+              /*mxcsr:in */ X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_RC_DOWN,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_V(1, 0x68b83b1ed4000, 0x41e)/*-3025935759.4140625*/, FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
             { /*src1     */ { FP64_V(1, 0,               0x400)/*         -2.0000000*/, FP64_RAND_V2(0), FP64_RAND_V1(1), FP64_RAND_V3(1) } },
             { /* =>      */ { FP64_V(0, 0x68b83b1ed4000, 0x41f)/* 6051871518.8281250*/, FP64_RAND_V2(0), FP64_RAND_V1(1), FP64_RAND_V3(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
+              /*mxcsr:in */ X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_RC_DOWN,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } },
             { /*src1     */ { FP64_V(0, 0x8000000000000, 0x400)/*              3.00*/, FP64_RAND_V1(1), FP64_RAND_V1(1), FP64_RAND_V3(0) } },
             { /* =>      */ { FP64_V(0, 0x4a6a82b05f744, 0x42f)/*363296296296308.25*/, FP64_RAND_V1(1), FP64_RAND_V1(1), FP64_RAND_V3(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
+              /*mxcsr:in */ X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_RC_DOWN,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_1(0),                 FP64_0(0),                                                FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_MAX(1)          } },
             { /*src1     */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_INF(1),               FP64_NORM_SAFE_INT_MIN(1) } },
             { /* =>      */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_INF(1),               FP64_NORM_SAFE_INT_MIN(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_NORM_V0(0), FP64_NORM_V1(1), FP64_NORM_V2(0), FP64_NORM_V3(1) } },
             { /*src1     */ { FP64_1(0),       FP64_SNAN(0),    FP64_SNAN(1),    FP64_QNAN(0)    } },
             { /* =>      */ { FP64_NORM_V0(0), FP64_SNAN(0),    FP64_SNAN(1),    FP64_QNAN(0)    } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
+              /*mxcsr:in */ X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_RC_DOWN,
               /*256:out  */ -1 },
     /*
@@ -7920,12 +7920,12 @@
             { /*src1     */ { FP64_1(0),          FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V3(1) } },
             { /* =>      */ { FP64_0(0),          FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V3(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_DENORM_MIN(1), FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V1(1) } },
             { /*src1     */ { FP64_DENORM_MAX(1), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V2(1) } },
             { /* =>      */ { FP64_0(0),          FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V2(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_1(1),          FP64_RAND_V3(0), FP64_RAND_V3(0), FP64_RAND_V1(1) } },
@@ -8070,13 +8070,13 @@
             { /*src1     */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0) } },
             { /* =>      */ { FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE },
           { { /*src2     */ { FP32_NORM_V0(0), FP32_NORM_V1(1), FP32_0(0),       FP32_NORM_V3(1), FP32_0(0), FP32_NORM_V1(1), FP32_NORM_V4(0), FP32_NORM_V3(0) } },
             { /*src1     */ { FP32_0(0),       FP32_0(1),       FP32_0(1),       FP32_0(0),       FP32_0(0), FP32_0(0),       FP32_0(0),       FP32_0(1)       } },
             { /* =>      */ { FP32_0(0),       FP32_0(0),       FP32_QNAN(1),    FP32_0(1),       FP32_QNAN(1), FP32_0(1),    FP32_0(0),       FP32_0(1)       } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE },
     /*
      * Infinity.
@@ -8085,19 +8085,19 @@
             { /*src1     */ { FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
             { /* =>      */ { FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
-              /*128:out  */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_IE,
-              /*256:out  */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_IE },
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_IE },
           { { /*src2     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
             { /*src1     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
             { /* =>      */ { FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE },
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_IE },
           { { /*src2     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0), FP32_0(1), FP32_0(1), FP32_0(0) } },
             { /*src1     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0) } },
             { /* =>      */ { FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1) } },
-              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_XCPT_MASK | X86_MXCSR_IE },
+              /*mxcsr:in */ X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_IE },
           { { /*src2     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0)  } },
             { /*src1     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1) } },
@@ -8115,7 +8115,7 @@
             { /*src1     */ { FP32_QNAN(0), FP32_QNAN(0), FP32_INF(1),  FP32_INF(1),  FP32_QNAN(1), FP32_INF(0),  FP32_INF(0),  FP32_QNAN(1) } },
             { /* =>      */ { FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN(0), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(0), FP32_QNAN(1)  } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP32_INF(0),  FP32_INF(1),  FP32_QNAN(0), FP32_QNAN(1), FP32_INF(0),  FP32_QNAN(1), FP32_QNAN(0), FP32_INF(1)  } },
             { /*src1     */ { FP32_QNAN(0), FP32_QNAN(0), FP32_INF(1),  FP32_INF(1),  FP32_QNAN(1), FP32_INF(0),  FP32_INF(0),  FP32_QNAN(1) } },
@@ -8184,19 +8184,19 @@
             { /*src1     */ { FP32_INF(0),      FP32_0(0),        FP32_NORM_V1(0), FP32_INF(0),      FP32_INF(0),      FP32_0(1),        FP32_0(1),        FP32_INF(1)      } },
             { /* =>      */ { FP32_INF(0),      FP32_0(1),        FP32_1(0),       FP32_INF(0),      FP32_INF(1),      FP32_0(1),        FP32_0(0),        FP32_INF(1)      } },
-              /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM,
-              /*128:out  */ X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM,
-              /*256:out  */ X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP32_NORM_MAX(0), FP32_NORM_MIN(0), FP32_NORM_V3(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MIN(0), FP32_NORM_MIN(1), FP32_NORM_MAX(0) } },
             { /*src1     */ { FP32_NORM_MAX(0), FP32_0(1),        FP32_0(0),       FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(1),        FP32_0(1),        FP32_INF(1)      } },
             { /* =>      */ { FP32_1(0),        FP32_0(1),        FP32_0(0),       FP32_1(0),        FP32_1(1),        FP32_0(1),        FP32_0(0),        FP32_INF(1)      } },
-              /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
           { { /*src2     */ { FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_2(0), FP32_1(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MIN(1) } },
             { /*src1     */ { FP32_0(0),        FP32_NORM_MAX(0), FP32_INF(1),      FP32_2(1), FP32_2(0), FP32_INF(1),      FP32_NORM_MAX(0), FP32_0(0)        } },
             { /* =>      */ { FP32_0(1),        FP32_1(0),        FP32_INF(1),      FP32_1(1), FP32_2(1), FP32_INF(1),      FP32_1(0),        FP32_0(1)        } },
-              /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
           { { /*src2     */ { FP32_1(0),       FP32_NORM_V2(1), FP32_1(1),       FP32_NORM_V6(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } },
             { /*src1     */ { FP32_NORM_V7(0), FP32_NORM_V2(0), FP32_NORM_V4(1), FP32_NORM_V6(1), FP32_INF(0),      FP32_INF(0),      FP32_INF(0),      FP32_INF(0)      } },
@@ -8212,19 +8212,19 @@
             { /*src1     */ { FP32_V(0, 0x600000, 0x7d)/*0.4375*/, FP32_NORM_V0(0), FP32_NORM_V1(1), FP32_0(1),       FP32_NORM_V0(0), FP32_NORM_V3(0), FP32_NORM_V4(1), FP32_NORM_V6(1) } },
             { /* =>      */ { FP32_V(0, 0,        0x7d)/*0.2500*/, FP32_1(0),       FP32_1(1),       FP32_0(0),       FP32_NORM_V0(1), FP32_NORM_V3(0), FP32_NORM_V4(0), FP32_1(0)       } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
           { { /*src2     */ { FP32_V(0, 0x61e000, 0x89)/*   1807*/, FP32_V(0, 0x61e000, 0x89)/*   1807*/, FP32_V(0, 0x4a30b8, 0x8f)/* 103521.4375*/, FP32_V(0, 0x1a5200, 0x8c)/*     9876.5*/, FP32_V(0, 0x23b6a0, 0x8e)/*41910.625000*/, FP32_V(0, 0x23b6a0, 0x8e)/*41910.625000*/, FP32_V(0, 0,        0x7d)/*0.2500*/, FP32_V(0, 0x504000, 0x8a)/*    3332*/ } },
             { /*src1     */ { FP32_V(0, 0x37be78, 0x95)/*6020924*/, FP32_V(0, 0x37be78, 0x95)/*6020924*/, FP32_V(0, 0x30eaa1, 0x93)/*1449300.1250*/, FP32_V(1, 0x39f7d1, 0x96)/*-12187601.0*/, FP32_V(0, 0x23b6a0, 0x8b)/* 5238.828125*/, FP32_V(0, 0x23b6a0, 0x8b)/* 5238.828125*/, FP32_V(0, 0x600000, 0x7d)/*0.4375*/, FP32_V(1, 0x37be78, 0x95)/*-6020924*/ } },
             { /* =>      */ { FP32_V(0, 0x504000, 0x8a)/*   3332*/, FP32_V(0, 0x504000, 0x8a)/*   3332*/, FP32_V(0, 0x600000, 0x82)/*     14.0000*/, FP32_V(1, 0x1a4000, 0x89)/*    -1234.0*/, FP32_V(0, 0,        0x7c)/*    0.125000*/, FP32_V(0, 0,        0x7c)/*    0.125000*/, FP32_V(0, 0x600000, 0x7f)/*1.7500*/, FP32_V(1, 0x61e000, 0x89)/*   -1807*/ } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP32_NORM_SAFE_INT_MAX(0), FP32_1(0),                 FP32_NORM_SAFE_INT_MAX(1), FP32_1(1),                 FP32_NORM_SAFE_INT_MIN(1), FP32_1(1),                 FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MAX(0) } },
             { /*src1     */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_0(0),                 FP32_0(1)                 } },
             { /* =>      */ { FP32_1(0),                 FP32_NORM_SAFE_INT_MIN(0), FP32_1(0),                 FP32_NORM_SAFE_INT_MAX(1), FP32_1(0),                 FP32_NORM_SAFE_INT_MIN(1), FP32_0(0),                 FP32_0(1)                 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
           { { /*src2     */ { FP32_NORM_MAX(0), FP32_1(0),        FP32_NORM_MAX(1), FP32_1(1),        FP32_NORM_MIN(0), FP32_NORM_MIN(0), FP32_1(0),        FP32_1(1)        } },
             { /*src1     */ { FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_MIN(0), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MIN(0) } },
@@ -8260,13 +8260,13 @@
             { /*src1     */ { FP32_0(0),          FP32_0(1),          FP32_0(1),          FP32_0(0),          FP32_DENORM_MAX(0), FP32_DENORM_MAX(1), FP32_DENORM_MAX(0), FP32_DENORM_MAX(1) } },
             { /* =>      */ { FP32_QNAN(1),       FP32_QNAN(1),       FP32_QNAN(1),       FP32_QNAN(1),       FP32_QNAN(1),       FP32_QNAN(1),       FP32_QNAN(1),       FP32_QNAN(1)       } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_IE },
+              /*mxcsr:in */ X86_MXCSR_DAZ,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_IE },
           { { /*src2     */ { FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(1), FP32_DENORM_MAX(1), FP32_1(0),          FP32_1(0),          FP32_1(1),          FP32_1(1)          } },
             { /*src1     */ { FP32_0(0),          FP32_0(1),          FP32_0(1),          FP32_0(0),          FP32_DENORM_MAX(0), FP32_DENORM_MAX(1), FP32_DENORM_MAX(0), FP32_DENORM_MAX(1) } },
             { /* =>      */ { FP32_QNAN(1),       FP32_QNAN(1),       FP32_QNAN(1),       FP32_QNAN(1),       FP32_0(0),          FP32_0(1),          FP32_0(1),          FP32_0(0)          } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_IE },
+              /*mxcsr:in */ X86_MXCSR_DAZ,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_IE },
           { { /*src2     */ { FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(1), FP32_DENORM_MIN(1), FP32_0(0),          FP32_0(0),          FP32_0(1),          FP32_0(1)          } },
             { /*src1     */ { FP32_0(0),          FP32_0(1),          FP32_0(1),          FP32_0(0),          FP32_DENORM_MIN(0), FP32_DENORM_MIN(1), FP32_DENORM_MIN(0), FP32_DENORM_MIN(1) } },
@@ -8298,37 +8298,37 @@
             { /*src1     */ { FP32_0(0),          FP32_0(1),          FP32_0(1),          FP32_0(0),          FP32_DENORM_MIN(0), FP32_DENORM_MIN(1), FP32_DENORM_MIN(0), FP32_DENORM_MIN(1) } },
             { /* =>      */ { FP32_QNAN(1),       FP32_QNAN(1),       FP32_QNAN(1),       FP32_QNAN(1),       FP32_QNAN(1),       FP32_QNAN(1),       FP32_QNAN(1),       FP32_QNAN(1)       } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_IE },
+              /*mxcsr:in */ X86_MXCSR_DAZ,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_IE },
           { { /*src2     */ { FP32_1(0),          FP32_1(0),          FP32_1(1),          FP32_1(1),          FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(1), FP32_DENORM_MIN(1) } },
             { /*src1     */ { FP32_DENORM_MIN(0), FP32_DENORM_MIN(1), FP32_DENORM_MIN(0), FP32_DENORM_MIN(1), FP32_0(0),          FP32_0(1),          FP32_0(1),          FP32_0(0)          } },
             { /* =>      */ { FP32_0(0),          FP32_0(1),          FP32_0(1),          FP32_0(0),          FP32_QNAN(1),       FP32_QNAN(1),       FP32_QNAN(1),       FP32_QNAN(1)       } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_IE },
+              /*mxcsr:in */ X86_MXCSR_DAZ,
+              /*128:out  */ X86_MXCSR_DAZ,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_IE },
           { { /*src2     */ { FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(1), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(1) } },
             { /*src1     */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(1), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1) } },
             { /* =>      */ { FP32_QNAN(1),       FP32_QNAN(1),       FP32_QNAN(1),       FP32_QNAN(1),       FP32_QNAN(1),       FP32_QNAN(1),       FP32_QNAN(1),       FP32_QNAN(1)       } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_IE },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_IE },
           { { /*src2     */ { FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(1), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(1) } },
             { /*src1     */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(1), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1) } },
             { /* =>      */ { FP32_QNAN(1),       FP32_QNAN(1),       FP32_QNAN(1),       FP32_QNAN(1),       FP32_QNAN(1),       FP32_QNAN(1),       FP32_QNAN(1),       FP32_QNAN(1)       } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE },
           { { /*src2     */ { FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(1), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(1) } },
             { /*src1     */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(1), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1) } },
             { /* =>      */ { FP32_QNAN(1),       FP32_QNAN(1),       FP32_QNAN(1),       FP32_QNAN(1),       FP32_QNAN(1),       FP32_QNAN(1),       FP32_QNAN(1),       FP32_QNAN(1)       } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE },
           { { /*src2     */ { FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(1), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(1) } },
             { /*src1     */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(1), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MIN(1) } },
             { /* =>      */ { FP32_QNAN(1),       FP32_QNAN(1),       FP32_QNAN(1),       FP32_QNAN(1),       FP32_QNAN(1),       FP32_QNAN(1),       FP32_QNAN(1),       FP32_QNAN(1)       } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE },
     /** @todo More Denormals. */
     /*
@@ -8403,7 +8403,7 @@
             { /*src1     */ { FP64_0(1),    FP64_0(0),    FP64_0(1),    FP64_0(0) } },
             { /* =>      */ { FP64_QNAN(1), FP64_QNAN(1), FP64_QNAN(1), FP64_QNAN(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE },
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_IE },
           { { /*src2     */ { FP64_0(1),    FP64_0(1),    FP64_0(0),    FP64_0(0) } },
             { /*src1     */ { FP64_0(1),    FP64_0(0),    FP64_0(1),    FP64_0(0) } },
@@ -8433,13 +8433,13 @@
             { /*src1     */ { FP64_0(1),    FP64_0(0),    FP64_0(1),    FP64_0(0) } },
             { /* =>      */ { FP64_QNAN(1), FP64_QNAN(1), FP64_QNAN(1), FP64_QNAN(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE },
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE },
           { { /*src2     */ { FP64_NORM_V0(0), FP64_NORM_V1(1), FP64_0(0),       FP64_0(1)       } },
             { /*src1     */ { FP64_0(0),       FP64_0(0),       FP64_NORM_V2(1), FP64_NORM_V3(1) } },
             { /* =>      */ { FP64_0(0),       FP64_0(1),       FP64_INF(1),     FP64_INF(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_ZE },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_ZE },
     /*
      * Infinity.
@@ -8454,7 +8454,7 @@
             { /*src1     */ { FP64_INF(0), FP64_INF(1), FP64_INF(0), FP64_INF(1) } },
             { /* =>      */ { FP64_INF(0), FP64_INF(1), FP64_INF(1), FP64_INF(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP64_INF(0),  FP64_INF(0),  FP64_INF(1),  FP64_INF(1) } },
             { /*src1     */ { FP64_INF(0),  FP64_INF(1),  FP64_INF(0),  FP64_INF(1) } },
@@ -8466,19 +8466,19 @@
             { /*src1     */ { FP64_INF(0),  FP64_INF(1),  FP64_INF(0),  FP64_INF(1) } },
             { /* =>      */ { FP64_QNAN(1), FP64_QNAN(1), FP64_QNAN(1), FP64_QNAN(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE },
           { { /*src2     */ { FP64_INF(0), FP64_INF(0),     FP64_1(1),   FP64_NORM_V1(1) } },
             { /*src1     */ { FP64_1(0),   FP64_NORM_V0(1), FP64_INF(0), FP64_INF(1)     } },
             { /* =>      */ { FP64_0(0),   FP64_0(1),       FP64_INF(1), FP64_INF(0)     } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_RC_DOWN },
           { { /*src2     */ { FP64_INF(0), FP64_INF(0),     FP64_1(1),   FP64_NORM_V2(1) } },
             { /*src1     */ { FP64_1(0),   FP64_NORM_V3(1), FP64_INF(0), FP64_INF(1)     } },
             { /* =>      */ { FP64_0(0),   FP64_0(1),       FP64_INF(1), FP64_INF(0)     } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP },
     /*
      * Normals.
@@ -8487,31 +8487,31 @@
             { /*src1     */ { FP64_V(0, 0xe66f500000000, 0x40d)/*31131.828125*/, FP64_V(0, 0xfb74e1d800000, 0x41a)/*266053390.75*/, FP64_V(0, 0x549270a11c760, 0x42c)/* 46807863534478.75*/, FP64_V(0, 0x3c30944926c00, 0x424)/*169753086244.84375*/ } },
             { /* =>      */ { FP64_1(0),                                         FP64_V(0, 0x2d69a80000000, 0x413)/*  1234586.50*/, FP64_V(1, 0x4000000000000, 0x400)/*             -2.50*/, FP64_V(0, 0xb800000000000, 0x402)/*          13.75000*/ } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP64_NORM_MAX(1), FP64_NORM_V3(1), FP64_1(0),       FP64_1(1)        } },
             { /*src1     */ { FP64_NORM_MAX(0), FP64_NORM_V3(1), FP64_NORM_V1(0), FP64_NORM_MIN(0) } },
             { /* =>      */ { FP64_1(1),        FP64_1(0),       FP64_NORM_V1(0), FP64_NORM_MIN(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_RC_DOWN },
           { { /*src2     */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_V(1, 0x68b83b1ed4000, 0x41e)/*-3025935759.4140625*/, FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646*/, FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/ } },
             { /*src1     */ { FP64_V(0, 0x4da20a80c6990, 0x42e)/*183416666481484.50*/, FP64_V(0, 0x68b83b1ed4000, 0x41f)/* 6051871518.8281250*/, FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646*/, FP64_V(0, 0x4a6a82b05f744, 0x42f)/*363296296296308.25*/ } },
             { /* =>      */ { FP64_V(0, 0x8000000000000, 0x3fe)/*              0.75*/, FP64_V(1, 0,               0x400)/*         -2.0000000*/, FP64_1(0),                                            FP64_V(0, 0x8000000000000, 0x400)/*              3.00*/ } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_RC_DOWN },
           { { /*src2     */ { FP64_1(0),                 FP64_1(0),                                                FP64_NORM_SAFE_INT_MIN(0), FP64_1(0)                 } },
             { /*src1     */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(1) } },
             { /* =>      */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_1(0),                 FP64_NORM_SAFE_INT_MIN(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
           { { /*src2     */ { FP64_NORM_V0(0), FP64_NORM_V1(1), FP64_NORM_V2(0), FP64_NORM_V3(1) } },
             { /*src1     */ { FP64_NORM_V0(0), FP64_NORM_V1(0), FP64_NORM_V2(1), FP64_NORM_V3(0) } },
             { /* =>      */ { FP64_1(0),       FP64_1(1),       FP64_1(1),       FP64_1(1)       } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_RC_DOWN },
           /** @todo More Normals. */
     /*
@@ -8573,19 +8573,19 @@
             { /*src1     */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_1(0),          FP64_1(0)          } },
             { /* =>      */ { FP64_0(0),          FP64_0(0),          FP64_INF(0),        FP64_INF(0)        } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_ZE },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_ZE },
           { { /*src2     */ { FP64_DENORM_MIN(1), FP64_DENORM_MIN(1), FP64_DENORM_MIN(0), FP64_DENORM_MAX(1) } },
             { /*src1     */ { FP64_1(0),          FP64_1(1),          FP64_DENORM_MIN(0), FP64_DENORM_MAX(1) } },
             { /* =>      */ { FP64_INF(1),        FP64_INF(0),        FP64_QNAN(1),       FP64_QNAN(1)       } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_ZE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_ZE | X86_MXCSR_IE },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_ZE,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_ZE | X86_MXCSR_IE },
           { { /*src2     */ { FP64_1(0),       FP64_NORM_V1(0), FP64_DENORM_MAX(0), FP64_1(0)          } },
             { /*src1     */ { FP64_NORM_V0(0), FP64_NORM_V1(0), FP64_0(0),          FP64_DENORM_MAX(0) } },
             { /* =>      */ { FP64_NORM_V0(0), FP64_1(0),       FP64_0(0),          FP64_0(0)          } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_DE | X86_MXCSR_UE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY },
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_DE | X86_MXCSR_UE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY },
           { { /*src2     */ { FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(1) } },
             { /*src1     */ { FP64_0(0),          FP64_0(0),          FP64_INF(1),        FP64_INF(0)        } },
@@ -8606,19 +8606,19 @@
             { /*src1     */ { FP64_NORM_V3(1), FP64_1(0), FP64_NORM_MAX(0), FP64_INF(0)      } },
             { /* =>      */ { FP64_1(0),       FP64_1(0), FP64_1(0),        FP64_INF(0)      } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP64_NORM_V3(1), FP64_1(1), FP64_NORM_MIN(0), FP64_NORM_MIN(0) } },
             { /*src1     */ { FP64_NORM_V3(0), FP64_1(1), FP64_NORM_MIN(1), FP64_NORM_MAX(0) } },
             { /* =>      */ { FP64_1(1),       FP64_1(0), FP64_1(1),        FP64_INF(0)      } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* i7-10700, IEM */ },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* i7-10700, IEM */ },
           { { /*src2     */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_V3(1), FP64_NORM_MAX(1) } },
             { /*src1     */ { FP64_NORM_MAX(0), FP64_INF(0),      FP64_NORM_V3(1), FP64_NORM_MIN(0) } },
             { /* =>      */ { FP64_1(0),        FP64_INF(0),      FP64_1(0),       FP64_0(1)        } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_UE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */ },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ X86_MXCSR_UE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */ },
           { { /*src2     */ { FP64_NORM_V3(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_V(1, 0, 0x3fe)/*-0.5*/ } },
             { /*src1     */ { FP64_NORM_V3(1), FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1)            } },
@@ -8636,37 +8636,37 @@
             { /*src1     */ { FP64_NORM_V3(1), FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1)            } },
             { /* =>      */ { FP64_1(1),       FP64_1(0),        FP64_1(1),        FP64_NORM_MAX(0)            } },
-              /*mxcsr:in */ (X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM)) | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ (X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM)) | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
-              /*256:out  */ (X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM)) | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* i7-10700, IEM */ },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* i7-10700, IEM */ },
           { { /*src2     */ { FP64_NORM_V3(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_V(1, 0, 0x3fe)/*-0.5*/ } },
             { /*src1     */ { FP64_NORM_V3(1), FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1)            } },
             { /* =>      */ { FP64_1(1),       FP64_1(0),        FP64_1(1),        FP64_INF(0)                 } },
-              /*mxcsr:in */ (X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM)) | X86_MXCSR_DAZ,
-              /*128:out  */ (X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM)) | X86_MXCSR_DAZ,
-              /*256:out  */ (X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM)) | X86_MXCSR_DAZ | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* i7-10700, IEM */ },
+              /*mxcsr:in */ X86_MXCSR_DAZ,
+              /*128:out  */ X86_MXCSR_DAZ,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* i7-10700, IEM */ },
           { { /*src2     */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MIN(1),                                       FP64_NORM_MAX(0) } },
             { /*src1     */ { FP64_INF(0),      FP64_0(0),        FP64_V(0, FP64_FRAC_NORM_MAX, RTFLOAT64U_EXP_BIAS + 1), FP64_INF(0)      } },
             { /* =>      */ { FP64_INF(0),      FP64_0(1),        FP64_NORM_MAX(1),                                       FP64_INF(0)      } },
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM,
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_UM | X86_MXCSR_PM },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ },
           { { /*src2     */ { FP64_NORM_V3(0), FP64_1(1),       FP64_V(1, 0, 0x3fe)/*-0.5*/, FP64_NORM_MIN(0)                                       } },
             { /*src1     */ { FP64_NORM_V3(0), FP64_NORM_V2(0), FP64_NORM_MAX(0),            FP64_V(1, FP64_FRAC_NORM_MAX, RTFLOAT64U_EXP_BIAS + 1) } },
             { /* =>      */ { FP64_1(0),       FP64_NORM_V2(1), FP64_NORM_MAX(1),            FP64_NORM_MAX(1)                                       } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM) | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM) | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK & ~(X86_MXCSR_OM | X86_MXCSR_PM) | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* i7-10700, IEM */ },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* i7-10700, IEM */ },
           { { /*src2     */ { FP64_NORM_SAFE_INT_MIN(0),                         FP64_NORM_MAX(0), FP64_NORM_SAFE_INT_MAX(1),                                FP64_NORM_SAFE_INT_MIN(0)            } },
             { /*src1     */ { FP64_V(0, FP64_FRAC_NORM_MAX, FP64_FRAC_BITS + 1), FP64_NORM_MAX(1), FP64_V(0, FP64_FRAC_NORM_MAX - 1, 0x468),                 FP64_V(0, FP64_FRAC_NORM_MAX, 0x035) } },
             { /* =>      */ { FP64_NORM_SAFE_INT_MAX(0),                         FP64_1(1),        FP64_V(1, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_NORM_SAFE_INT_MAX(0)            } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_PE },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE },
           { { /*src2     */ { FP64_NORM_SAFE_INT_MIN(0),                         FP64_NORM_MAX(0), FP64_V(0, 0x8000000000000, 0x400)/*3.0*/, FP64_1(1) } },
             { /*src1     */ { FP64_V(0, FP64_FRAC_NORM_MAX, FP64_FRAC_BITS + 1), FP64_INF(1),      FP64_1(1),                                FP64_1(0) } },
             { /* =>      */ { FP64_NORM_SAFE_INT_MAX(0),                         FP64_INF(1),      FP64_V(1, 0x5555555555556, 0x3fd)/*1/3*/, FP64_1(1) } },
-              /*mxcsr:in */ X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_PE },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_PE },
     /*
      * Invalids.
@@ -8746,12 +8746,12 @@
             { /*src1     */ { FP32_0(0),    FP32_0_x7(0) } },
             { /* =>      */ { FP32_QNAN(1), FP32_0_x7(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_0(0),    FP32_RAND_x7_V1 } },
             { /*src1     */ { FP32_0(0),    FP32_RAND_x7_V2 } },
             { /* =>      */ { FP32_QNAN(1), FP32_RAND_x7_V2 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_0(1),    FP32_RAND_x7_V2 } },
@@ -8770,12 +8770,12 @@
             { /*src1     */ { FP32_0(1),    FP32_RAND_x7_V5 } },
             { /* =>      */ { FP32_QNAN(1), FP32_RAND_x7_V5 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_IE,
+              /*mxcsr:in */ X86_MXCSR_DAZ,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_IE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_0(0),   FP32_RAND_x7_V5 } },
             { /*src1     */ { FP32_1(0),   FP32_RAND_x7_V6 } },
             { /* =>      */ { FP32_INF(0), FP32_RAND_x7_V6 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_FSW_ZE,
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_FSW_ZE,
               /*256:out  */ -1 },
     /*
@@ -8785,30 +8785,30 @@
             { /*src1     */ { FP32_1(1),   FP32_0_x7(0) } },
             { /* =>      */ { FP32_0(1),   FP32_0_x7(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
-              /*128:out  */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_INF(1), FP32_0_x7(0) } },
             { /*src1     */ { FP32_1(1),   FP32_0_x7(0) } },
             { /* =>      */ { FP32_0(0),   FP32_0_x7(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_INF(0),  FP32_RAND_x7_V7 } },
             { /*src1     */ { FP32_INF(0),  FP32_RAND_x7_V0 } },
             { /* =>      */ { FP32_QNAN(1), FP32_RAND_x7_V0 } },
-              /*mxcsr:in */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_DAZ | X86_MXCSR_FZ,
-              /*128:out  */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_INF(1),  FP32_RAND_x7_V7 } },
             { /*src1     */ { FP32_INF(0),  FP32_RAND_x7_V1 } },
             { /* =>      */ { FP32_QNAN(1), FP32_RAND_x7_V1 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_1(0),   FP32_RAND_x7_V7 } },
             { /*src1     */ { FP32_INF(0), FP32_RAND_x7_V6 } },
             { /* =>      */ { FP32_INF(0), FP32_RAND_x7_V6 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
+              /*mxcsr:in */ X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_FZ,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_INF(0), FP32_RAND_x7_V5 } },
@@ -8830,30 +8830,30 @@
             { /*src1     */ { FP32_V(0, 0x600000, 0x7d)/*0.4375*/, FP32_RAND_x7_V6 } },
             { /* =>      */ { FP32_V(0, 0,        0x7d)/*0.2500*/, FP32_RAND_x7_V6 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_V(0, 0x61e000, 0x89)/*   1807*/, FP32_RAND_x7_V6 } },
             { /*src1     */ { FP32_V(0, 0x37be78, 0x95)/*6020924*/, FP32_RAND_x7_V1 } },
             { /* =>      */ { FP32_V(0, 0x504000, 0x8a)/*   3332*/, FP32_RAND_x7_V1 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V4 } },
             { /*src1     */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V2 } },
             { /* =>      */ { FP32_1(0),                 FP32_RAND_x7_V2 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_V(0, 0x61e000, 0x89)/*   1807*/, FP32_RAND_x7_V0 } },
             { /*src1     */ { FP32_V(0, 0x37be78, 0x95)/*6020924*/, FP32_RAND_x7_V7 } },
             { /* =>      */ { FP32_V(0, 0x504000, 0x8a)/*   3332*/, FP32_RAND_x7_V7 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
+              /*mxcsr:in */ X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_RC_UP,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_V(0, 0x4a30b8, 0x8f)/* 103521.4375*/, FP32_RAND_x7_V1 } },
             { /*src1     */ { FP32_V(0, 0x30eaa1, 0x93)/*1449300.1250*/, FP32_RAND_x7_V3 } },
             { /* =>      */ { FP32_V(0, 0x600000, 0x82)/*     14.0000*/, FP32_RAND_x7_V3 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_V(0, 0x1a5200, 0x8c)/*     9876.5*/, FP32_RAND_x7_V6 } },
@@ -8900,12 +8900,12 @@
             { /*src1     */ { FP32_DENORM_MIN(1), FP32_RAND_x7_V2 } },
             { /* =>      */ { FP32_INF(1),        FP32_RAND_x7_V2 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_ZE,
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_ZE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_DENORM_MIN(0), FP32_RAND_x7_V1 } },
             { /*src1     */ { FP32_0(0),          FP32_RAND_x7_V4 } },
             { /* =>      */ { FP32_QNAN(1),       FP32_RAND_x7_V4 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,
               /*256:out  */ -1 },
     /** @todo More Denormals. */
@@ -8978,12 +8978,12 @@
             { /*src1     */ { FP64_0(0),    FP64_0(0), FP64_0(0), FP64_0(0) } },
             { /* =>      */ { FP64_QNAN(1), FP64_0(0), FP64_0(0), FP64_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_0(0),    FP64_NORM_V3(0), FP64_NORM_V2(0), FP64_0(0)       } },
             { /*src1     */ { FP64_0(0),    FP64_0(1),       FP64_0(1),       FP64_NORM_V1(0) } },
             { /* =>      */ { FP64_QNAN(1), FP64_0(1),       FP64_0(1),       FP64_NORM_V1(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_0(1),    FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V1(1) } },
@@ -9002,12 +9002,12 @@
             { /*src1     */ { FP64_0(1),    FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V0(0) } },
             { /* =>      */ { FP64_QNAN(1), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_IE,
+              /*mxcsr:in */ X86_MXCSR_DAZ,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_IE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_0(0),   FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
             { /*src1     */ { FP64_1(0),   FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V0(0) } },
             { /* =>      */ { FP64_INF(0), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_FSW_ZE,
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_FSW_ZE,
               /*256:out  */ -1 },
     /*
@@ -9017,30 +9017,30 @@
             { /*src1     */ { FP64_1(1),   FP64_0(0), FP64_0(0), FP64_0(0) } },
             { /* =>      */ { FP64_0(1),   FP64_0(0), FP64_0(0), FP64_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
-              /*128:out  */ X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_INF(1), FP64_0(0), FP64_0(0), FP64_0(0) } },
             { /*src1     */ { FP64_1(1),   FP64_0(0), FP64_0(0), FP64_0(0) } },
             { /* =>      */ { FP64_0(0),   FP64_0(0), FP64_0(0), FP64_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_INF(0),  FP64_RAND_V1(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },
             { /*src1     */ { FP64_INF(0),  FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } },
             { /* =>      */ { FP64_QNAN(1), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } },
-              /*mxcsr:in */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_DAZ | X86_MXCSR_FZ,
-              /*128:out  */ (X86_MXCSR_XCPT_MASK & ~X86_MXCSR_IM) | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_IE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_INF(1),  FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V1(1) } },
             { /*src1     */ { FP64_INF(0),  FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V0(0) } },
             { /* =>      */ { FP64_QNAN(1), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_1(0),   FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } },
             { /*src1     */ { FP64_INF(0), FP64_RAND_V1(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },
             { /* =>      */ { FP64_INF(0), FP64_RAND_V1(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
+              /*mxcsr:in */ X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_FZ,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_INF(0), FP64_INF(0), FP64_INF(1), FP64_INF(1) } },
@@ -9062,60 +9062,60 @@
             { /*src1     */ { FP64_V(0, 0xe66f500000000, 0x40d)/*31131.828125*/, FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } },
             { /* =>      */ { FP64_1(0),                                         FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_V(0, 0xaf00000000000, 0x406)/*      215.50*/, FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V2(1) } },
             { /*src1     */ { FP64_V(0, 0xfb74e1d800000, 0x41a)/*266053390.75*/, FP64_RAND_V1(0), FP64_RAND_V1(1), FP64_RAND_V0(1) } },
             { /* =>      */ { FP64_V(0, 0x2d69a80000000, 0x413)/*  1234586.50*/, FP64_RAND_V1(0), FP64_RAND_V1(1), FP64_RAND_V0(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_V(1, 0x107526e749f80, 0x42b)/*-18723145413791.50*/, FP64_RAND_V3(0), FP64_RAND_V1(0), FP64_RAND_V1(1) } },
             { /*src1     */ { FP64_V(0, 0x549270a11c760, 0x42c)/* 46807863534478.75*/, FP64_RAND_V0(0), FP64_RAND_V2(1), FP64_RAND_V2(1) } },
             { /* =>      */ { FP64_V(1, 0x4000000000000, 0x400)/*             -2.50*/, FP64_RAND_V0(0), FP64_RAND_V2(1), FP64_RAND_V2(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_V(0, 0x6fee0e4bd0000, 0x420)/* 12345678999.62500*/, FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } },
             { /*src1     */ { FP64_V(0, 0x3c30944926c00, 0x424)/*169753086244.84375*/, FP64_RAND_V2(0), FP64_RAND_V1(1), FP64_RAND_V3(1) } },
             { /* =>      */ { FP64_V(0, 0xb800000000000, 0x402)/*          13.75000*/, FP64_RAND_V2(0), FP64_RAND_V1(1), FP64_RAND_V3(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_NORM_MAX(1), FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } },
             { /*src1     */ { FP64_NORM_MAX(0), FP64_RAND_V1(1), FP64_RAND_V0(0), FP64_RAND_V2(0) } },
             { /* =>      */ { FP64_1(1),        FP64_RAND_V1(1), FP64_RAND_V0(0), FP64_RAND_V2(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
+              /*mxcsr:in */ X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_RC_DOWN,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_RAND_V2(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } },
             { /*src1     */ { FP64_V(0, 0x4da20a80c6990, 0x42e)/*183416666481484.50*/, FP64_RAND_V1(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } },
             { /* =>      */ { FP64_V(0, 0x8000000000000, 0x3fe)/*              0.75*/, FP64_RAND_V1(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
+              /*mxcsr:in */ X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_RC_DOWN,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_V(1, 0x68b83b1ed4000, 0x41e)/*-3025935759.4140625*/, FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
             { /*src1     */ { FP64_V(0, 0x68b83b1ed4000, 0x41f)/* 6051871518.8281250*/, FP64_RAND_V2(0), FP64_RAND_V1(1), FP64_RAND_V3(1) } },
             { /* =>      */ { FP64_V(1, 0,               0x400)/*         -2.0000000*/, FP64_RAND_V2(0), FP64_RAND_V1(1), FP64_RAND_V3(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
+              /*mxcsr:in */ X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_RC_DOWN,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(1) } },
             { /*src1     */ { FP64_V(0, 0x4a6a82b05f744, 0x42f)/*363296296296308.25*/, FP64_RAND_V1(1), FP64_RAND_V1(1), FP64_RAND_V3(0) } },
             { /* =>      */ { FP64_V(0, 0x8000000000000, 0x400)/*              3.00*/, FP64_RAND_V1(1), FP64_RAND_V1(1), FP64_RAND_V3(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
+              /*mxcsr:in */ X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_RC_DOWN,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_1(0),                 FP64_0(0),                                                FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_MAX(1)          } },
             { /*src1     */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_INF(1),               FP64_NORM_SAFE_INT_MIN(1) } },
             { /* =>      */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_INF(1),               FP64_NORM_SAFE_INT_MIN(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_NORM_V0(0), FP64_NORM_V1(1), FP64_NORM_V2(0), FP64_NORM_V3(1) } },
             { /*src1     */ { FP64_NORM_V0(0), FP64_SNAN(0),    FP64_SNAN(1),    FP64_QNAN(0)    } },
             { /* =>      */ { FP64_1(0),       FP64_SNAN(0),    FP64_SNAN(1),    FP64_QNAN(0)    } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
+              /*mxcsr:in */ X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_RC_DOWN,
               /*256:out  */ -1 },
     /*
@@ -9140,6 +9140,6 @@
             { /*src1     */ { FP64_DENORM_MAX(1), FP64_DENORM_MIN(0), FP64_0(0),          FP64_DENORM_MAX(0) } },
             { /* =>      */ { FP64_INF(0),        FP64_DENORM_MIN(0), FP64_0(0),          FP64_DENORM_MAX(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_ZE,
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_ZE,
               /*256:out  */ -1 },
           { { /*           -DENORM_MAX /  DENORM_MIN = (-huge)  &_DE */
@@ -9147,6 +9147,6 @@
             { /*src1     */ { FP64_DENORM_MAX(1),                                       FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } },
             { /* =>      */ { FP64_V(1, 0xffffffffffffe, 0x432)/*-4503599627370495.0*/, FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP | X86_MXCSR_DE,
+              /*mxcsr:in */ X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_RC_UP | X86_MXCSR_DE,
               /*256:out  */ -1 },
           { { /*           -DENORM_MAX / -DENORM_MIN = (huge)   &_DE */
@@ -9161,6 +9161,6 @@
             { /*src1     */ { FP64_DENORM_MIN(1),                                             FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } },
             { /* =>      */ { FP64_V(1, 0x0000000000001, 0x3cb)/*-22204460492503135739e-35*/, FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_PE,
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_DE | X86_MXCSR_PE,
               /*256:out  */ -1 },
           { { /*                    -0 /  DENORM_MIN = -0       &_DE */
@@ -9168,6 +9168,6 @@
             { /*src1     */ { FP64_0(1),          FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } },
             { /* =>      */ { FP64_0(1),          FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_DE,
               /*256:out  */ -1 },
           { { /*                 -0.25 /  DENORM_MAX = (-HUGE)  &_DE &_PE */
@@ -9175,6 +9175,6 @@
             { /*src1     */ { FP64_V(1, 0, 0x3fd)/*0.25*/,       FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } },
             { /* =>      */ { FP64_V(1, 1, 0x7fb)/*1.1XYZe307*/, FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_PE,
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_DE | X86_MXCSR_PE,
               /*256:out  */ -1 },
           { { /*                  42.0 /  DENORM_MIN = INF      &_DE &_PE(if OM) &_OE */
@@ -9224,6 +9224,6 @@
             { /*src1     */ { FP64_V(0, 0x5000000000000, 0x404)/*42.0*/, FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } },
             { /* =>      */ { FP64_INF(0),                               FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_ZE | X86_MXCSR_DAZ,
+              /*mxcsr:in */ X86_MXCSR_DAZ,
+              /*128:out  */ X86_MXCSR_ZE | X86_MXCSR_DAZ,
               /*256:out  */ -1 },
           { { /*            DENORM_MAX /       -42.0 = -5e-310  &_DE &_PE(if UM) &_UE */
@@ -9277,6 +9277,6 @@
             { /*src1     */ { FP64_DENORM_MAX(0),                         FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } },
             { /* =>      */ { FP64_0(1),                                  FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
+              /*mxcsr:in */ X86_MXCSR_DAZ,
+              /*128:out  */ X86_MXCSR_DAZ,
               /*256:out  */ -1 },
           { { /* DAZ+FZ:    DENORM_MAX /       -42.0 = -0       &- */
@@ -9284,6 +9284,6 @@
             { /*src1     */ { FP64_DENORM_MAX(0),                         FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } },
             { /* =>      */ { FP64_0(1),                                  FP64_DENORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
               /*256:out  */ -1 },
           /** @todo how to usefully test FZ, RC_{NEAREST,UP,DOWN,ZERO} ? */
@@ -9399,25 +9399,25 @@
             { /*src1     */ { FP32_INF(0),  FP32_INF(0), FP32_INF(1), FP32_INF(1),  FP32_INF(0), FP32_INF(0),  FP32_INF(1),  FP32_INF(1) } },
             { /* =>      */ { FP32_QNAN(1), FP32_INF(0), FP32_INF(1), FP32_QNAN(1), FP32_INF(0), FP32_QNAN(1), FP32_QNAN(1), FP32_INF(1) } },
-              /*mxcsr:in */ X86_MXCSR_IM,
-              /*128:out  */ X86_MXCSR_IM | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_IM | X86_MXCSR_IE },
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_IE },
           { { /*src2     */ { FP32_INF(0),  FP32_INF(0), FP32_INF(0), FP32_INF(0),  FP32_INF(1), FP32_INF(1),  FP32_INF(1),  FP32_INF(1) } },
             { /*src1     */ { FP32_INF(0),  FP32_INF(0), FP32_INF(1), FP32_INF(1),  FP32_INF(0), FP32_INF(0),  FP32_INF(1),  FP32_INF(1) } },
             { /* =>      */ { FP32_QNAN(1), FP32_INF(0), FP32_INF(1), FP32_QNAN(1), FP32_INF(0), FP32_QNAN(1), FP32_QNAN(1), FP32_INF(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE },
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE },
           { { /*src2     */ { FP32_INF(0),  FP32_INF(0), FP32_INF(0), FP32_INF(0),  FP32_INF(1), FP32_INF(1),  FP32_INF(1),  FP32_INF(1) } },
             { /*src1     */ { FP32_INF(0),  FP32_INF(0), FP32_INF(1), FP32_INF(1),  FP32_INF(0), FP32_INF(0),  FP32_INF(1),  FP32_INF(1) } },
             { /* =>      */ { FP32_QNAN(1), FP32_INF(0), FP32_INF(1), FP32_QNAN(1), FP32_INF(0), FP32_QNAN(1), FP32_QNAN(1), FP32_INF(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE },
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE },
           { { /*src2     */ { FP32_INF(0),  FP32_INF(0), FP32_INF(0), FP32_INF(0),  FP32_INF(1), FP32_INF(1),  FP32_INF(1),  FP32_INF(1) } },
             { /*src1     */ { FP32_INF(0),  FP32_INF(0), FP32_INF(1), FP32_INF(1),  FP32_INF(0), FP32_INF(0),  FP32_INF(1),  FP32_INF(1) } },
             { /* =>      */ { FP32_QNAN(1), FP32_INF(0), FP32_INF(1), FP32_QNAN(1), FP32_INF(0), FP32_QNAN(1), FP32_QNAN(1), FP32_INF(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE },
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE },
           { { /*src2     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_INF(1),  FP32_INF(1),  FP32_INF(1) } },
             { /*src1     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0), FP32_INF(0),  FP32_INF(1),  FP32_INF(1) } },
@@ -9429,19 +9429,19 @@
             { /*src1     */ { FP32_0(0),   FP32_INF(0), FP32_INF(1), FP32_0(1),   FP32_INF(0), FP32_INF(0), FP32_0(1),   FP32_0(1)   } },
             { /* =>      */ { FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP32_INF(0),     FP32_NORM_V1(0), FP32_NORM_V2(0), FP32_INF(0),     FP32_NORM_V3(1), FP32_NORM_V2(1), FP32_INF(1),     FP32_INF(1)     } },
             { /*src1     */ { FP32_NORM_V0(0), FP32_INF(0),     FP32_INF(1),     FP32_NORM_V3(1), FP32_INF(0),     FP32_INF(0),     FP32_NORM_V1(1), FP32_NORM_V0(1) } },
             { /* =>      */ { FP32_INF(1),     FP32_INF(0),     FP32_INF(1),     FP32_INF(0),     FP32_INF(0),     FP32_INF(0),     FP32_INF(0),     FP32_INF(1)     } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP32_NORM_V7(0), FP32_NORM_V6(0), FP32_NORM_V5(0), FP32_NORM_V4(0), FP32_NORM_V3(1), FP32_NORM_V2(1), FP32_NORM_V1(1), FP32_NORM_V0(1) } },
             { /*src1     */ { FP32_INF(0),     FP32_INF(0),     FP32_INF(1),     FP32_INF(1),     FP32_INF(0),     FP32_INF(0),     FP32_INF(1),     FP32_INF(1)     } },
             { /* =>      */ { FP32_INF(0),     FP32_INF(0),     FP32_INF(1),     FP32_INF(1),     FP32_INF(0),     FP32_INF(0),     FP32_INF(1),     FP32_INF(1)     } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO },
     /*
      * Overflow, Precision.
@@ -9462,7 +9462,7 @@
             { /*src1     */ { FP32_NORM_MAX(0),                                     FP32_NORM_MAX(0), FP32_2(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_1(0), FP32_NORM_V7(1), FP32_NORM_MAX(0) } },
             { /* =>      */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_NORM_MAX), FP32_NORM_MAX(0), FP32_1(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_2(0), FP32_NORM_V7(1), FP32_NORM_MAX(0) } },
-              /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
-              /*256:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE },
           { { /*src2     */ { FP32_NORM_MAX(0), FP32_NORM_MIN(1),                     FP32_NORM_V3(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0),                                     FP32_NORM_MIN(1),                    FP32_0(0), FP32_NORM_MAX(0) } },
             { /*src1     */ { FP32_NORM_MAX(0), FP32_NORM_MIN(1),                     FP32_NORM_V3(0), FP32_NORM_MAX(0), FP32_NORM_MIN(0),                                     FP32_NORM_MIN(1),                    FP32_0(0), FP32_NORM_MAX(0) } },
@@ -9525,7 +9525,7 @@
             { /*src1     */ { FP32_V(0, 0x600000, 0x7f)/*1.75*/, FP32_V(1, 0,        0x7d)/*-0.25*/, FP32_V(0, 0x400000, 0x7e)/*0.75*/, FP32_V(1, 0,        0x7d)/*-0.25*/, FP32_V(0, 0,        0x7e)/* 0.50*/, FP32_V(1, 0,        0x7d)/*-0.25*/, FP32_V(0, 0x400000, 0x7e)/*0.75*/, FP32_1(1)                /*- 1.00*/} },
             { /* =>      */ { FP32_V(0, 0x400000, 0x7f)/*1.50*/, FP32_V(0, 0x400000, 0x7f)/* 1.50*/, FP32_V(0, 0,        0x7e)/*0.50*/, FP32_V(1, 0x400000, 0x7e)/*-0.75*/, FP32_V(1, 0,        0x7d)/*-0.25*/, FP32_V(0, 0x400000, 0x7f)/* 1.50*/, FP32_V(0, 0,        0x7d)/*0.25*/, FP32_V(0, 0x524000, 0x86)/*210.25*/} },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_V(0, 0x600000, 0x81)/* 7*/, FP32_V(0, 0x5c0000, 0x84)/*55*/, FP32_V(0, 0x534000, 0x86)/*211.25*/, FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_V(0, 0x7c9000, 0x88)/*   1010.25*/, FP32_V(0, 0x534000, 0x86)/*211.25*/ } },
             { /*src1     */ { FP32_V(0, 0x669050, 0x93)/*1888778*/, FP32_V(0, 0x1ea980, 0x8f)/*  81235*/, FP32_V(0, 0x780000, 0x84)/*62*/, FP32_V(0, 0x600000, 0x81)/* 7*/, FP32_1(0)                /*  1.00*/, FP32_V(0, 0x7c9000, 0x88)/*   1010.25*/, FP32_V(0, 0x253468, 0x93)/*1353357.00*/, FP32_1(1)                /*- 1.00*/ } },
@@ -9617,19 +9617,19 @@
             { /*src1     */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0) } },
             { /* =>      */ { FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0)          } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP },
           { { /*src2     */ { FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } },
             { /*src1     */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0) } },
             { /* =>      */ { FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0)          } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ },
+              /*mxcsr:in */ X86_MXCSR_DAZ,
+              /*128:out  */ X86_MXCSR_DAZ,
+              /*256:out  */ X86_MXCSR_DAZ },
           { { /*src2     */ { FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } },
             { /*src1     */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0) } },
             { /* =>      */ { FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0)          } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
           { { /*src2     */ { FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } },
             { /*src1     */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0) } },
@@ -9773,49 +9773,49 @@
             { /*src1     */ { FP64_INF(0),  FP64_INF(0), FP64_INF(1), FP64_INF(1)  } },
             { /* =>      */ { FP64_QNAN(1), FP64_INF(0), FP64_INF(1), FP64_QNAN(1) } },
-              /*mxcsr:in */ X86_MXCSR_IM,
-              /*128:out  */ X86_MXCSR_IM | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_IM | X86_MXCSR_IE },
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_IE },
           { { /*src2     */ { FP64_INF(0),  FP64_QNAN(1), FP64_QNAN(1), FP64_INF(1) } },
             { /*src1     */ { FP64_INF(0),  FP64_QNAN(1), FP64_QNAN(1), FP64_INF(1) } },
             { /* =>      */ { FP64_QNAN(1), FP64_QNAN(1), FP64_QNAN(1), FP64_INF(1) } },
-              /*mxcsr:in */ X86_MXCSR_IM,
-              /*128:out  */ X86_MXCSR_IM | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_IM | X86_MXCSR_IE },
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_IE },
           { { /*src2     */ { FP64_INF(0),  FP64_INF(0), FP64_INF(0), FP64_INF(0)  } },
             { /*src1     */ { FP64_INF(0),  FP64_INF(0), FP64_INF(1), FP64_INF(1)  } },
             { /* =>      */ { FP64_QNAN(1), FP64_INF(0), FP64_INF(1), FP64_QNAN(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE },
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE },
           { { /*src2     */ { FP64_INF(1), FP64_INF(1),  FP64_INF(1),  FP64_INF(1) } },
             { /*src1     */ { FP64_INF(0), FP64_INF(0),  FP64_INF(1),  FP64_INF(1) } },
             { /* =>      */ { FP64_INF(0), FP64_QNAN(1), FP64_QNAN(1), FP64_INF(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE },
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE },
           { { /*src2     */ { FP64_INF(0),  FP64_INF(0), FP64_INF(0), FP64_INF(0)  } },
             { /*src1     */ { FP64_INF(0),  FP64_INF(0), FP64_INF(1), FP64_INF(1)  } },
             { /* =>      */ { FP64_QNAN(1), FP64_INF(0), FP64_INF(1), FP64_QNAN(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE },
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE },
           { { /*src2     */ { FP64_INF(1), FP64_INF(1),  FP64_INF(1),  FP64_INF(1) } },
             { /*src1     */ { FP64_INF(0), FP64_INF(0),  FP64_INF(1),  FP64_INF(1) } },
             { /* =>      */ { FP64_INF(0), FP64_QNAN(1), FP64_QNAN(1), FP64_INF(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE },
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE },
           { { /*src2     */ { FP64_INF(0),  FP64_INF(0), FP64_INF(0), FP64_INF(0)  } },
             { /*src1     */ { FP64_INF(0),  FP64_INF(0), FP64_INF(1), FP64_INF(1)  } },
             { /* =>      */ { FP64_QNAN(1), FP64_INF(0), FP64_INF(1), FP64_QNAN(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE },
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE },
           { { /*src2     */ { FP64_INF(1), FP64_INF(1),  FP64_INF(1),  FP64_INF(1) } },
             { /*src1     */ { FP64_INF(0), FP64_INF(0),  FP64_INF(1),  FP64_INF(1) } },
             { /* =>      */ { FP64_INF(0), FP64_QNAN(1), FP64_QNAN(1), FP64_INF(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE },
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE },
           { { /*src2     */ { FP64_0(0), FP64_0(0), FP64_INF(1), FP64_INF(1)  } },
             { /*src1     */ { FP64_0(0), FP64_0(0), FP64_INF(0), FP64_INF(0)  } },
@@ -9827,19 +9827,19 @@
             { /*src1     */ { FP64_0(0),   FP64_INF(0), FP64_INF(0), FP64_INF(0) } },
             { /* =>      */ { FP64_INF(1), FP64_INF(0), FP64_INF(0), FP64_INF(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP64_INF(0),     FP64_NORM_V1(0), FP64_INF(1),     FP64_INF(1)     } },
             { /*src1     */ { FP64_NORM_V0(0), FP64_INF(0),     FP64_NORM_V1(1), FP64_NORM_V0(1) } },
             { /* =>      */ { FP64_INF(1),     FP64_INF(0),     FP64_INF(0),     FP64_INF(1)     } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP64_NORM_V3(0), FP64_NORM_V3(0), FP64_NORM_V1(1), FP64_NORM_V0(1) } },
             { /*src1     */ { FP64_INF(0),     FP64_INF(0),     FP64_INF(1),     FP64_INF(1)     } },
             { /* =>      */ { FP64_INF(0),     FP64_INF(0),     FP64_INF(1),     FP64_INF(1)     } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO },
     /*
      * Overflow, Precision.
@@ -9854,31 +9854,31 @@
             { /*src1     */ { FP64_NORM_MAX(0),                                     FP64_NORM_MAX(0), FP64_2(0), FP64_NORM_MAX(1) } },
             { /* =>      */ { FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_NORM_MAX), FP64_NORM_MAX(0), FP64_1(0), FP64_NORM_MAX(1) } },
-              /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
-              /*256:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE },
           { { /*src2     */ { FP64_NORM_MAX(0), FP64_1(0), FP64_0(0),       FP64_NORM_MAX(0) } },
             { /*src1     */ { FP64_NORM_MAX(1), FP64_1(0), FP64_NORM_V3(1), FP64_NORM_MAX(0) } },
             { /* =>      */ { FP64_NORM_MAX(1), FP64_2(0), FP64_NORM_V3(1), FP64_NORM_MAX(0) } },
-              /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY,
-              /*256:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY,
+              /*256:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY },
           { { /*src2     */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1),                     FP64_NORM_V3(0), FP64_NORM_MAX(0) } },
             { /*src1     */ { FP64_NORM_MAX(0), FP64_NORM_MIN(1),                     FP64_NORM_V3(0), FP64_NORM_MAX(0) } },
             { /* =>      */ { FP64_0(0),        FP64_V(1, 0, FP64_EXP_NORM_MIN + 1),  FP64_0(0),       FP64_INF(0)      } },
-              /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY },
           { { /*src2     */ { FP64_NORM_MAX(0),                                     FP64_NORM_MIN(1),                    FP64_0(0), FP64_NORM_MAX(0) } },
             { /*src1     */ { FP64_NORM_MIN(0),                                     FP64_NORM_MIN(1),                    FP64_0(0), FP64_NORM_MAX(0) } },
             { /* =>      */ { FP64_V(1, FP64_FRAC_NORM_MAX - 1, FP64_EXP_NORM_MAX), FP64_V(1, 0, FP64_EXP_NORM_MIN + 1), FP64_0(0), FP64_INF(0)      } },
-              /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_PE,
-              /*256:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE },
           { { /*src2     */ { FP64_NORM_MIN(1), FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_V2(1) } },
             { /*src1     */ { FP64_NORM_MIN(1), FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_0(0)       } },
             { /* =>      */ { FP64_0(1),        FP64_NORM_MAX(0), FP64_INF(1),      FP64_NORM_V2(1) } },
-              /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY,
-              /*256:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY },
           { { /*src2     */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } },
             { /*src1     */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } },
@@ -9890,13 +9890,13 @@
             { /*src1     */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } },
             { /* =>      */ { FP64_0(0),        FP64_NORM_MAX(1), FP64_0(0),        FP64_NORM_MAX(0) } },
-              /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY,
-              /*256:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY,
+              /*256:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY },
           { { /*src2     */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } },
             { /*src1     */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(0) } },
             { /* =>      */ { FP64_0(0),        FP64_NORM_MAX(1), FP64_0(0),        FP64_INF(0)      } },
-              /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY,
-              /*256:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY },
+              /*mxcsr:in */ X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY,
+              /*256:out  */ X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY },
           { { /*src2     */ { FP64_NORM_SAFE_INT_MIN(0),                            FP64_NORM_MAX(0), FP64_0(0), FP64_NORM_SAFE_INT_MAX(1)                                } },
             { /*src1     */ { FP64_NORM_SAFE_INT_MAX(0),                            FP64_NORM_MAX(1), FP64_0(0), FP64_NORM_SAFE_INT_MAX(1)                                } },
@@ -9917,37 +9917,37 @@
             { /*src1     */ { FP64_V(0, 0x8000000000000, 0x409)/*1536*/, FP64_V(0, 0,               0x408)/* 512*/, FP64_V(0, 0xb800000000000, 0x404)/*55*/, FP64_V(0, 0xc000000000000, 0x401)/* 7*/ } },
             { /* =>      */ { FP64_V(0, 0,               0x408)/* 512*/, FP64_V(0, 0x8000000000000, 0x409)/*1536*/, FP64_V(0, 0xf000000000000, 0x404)/*62*/, FP64_V(0, 0xf000000000000, 0x404)/*62*/ } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP64_V(0, 0x9000000000000, 0x405)/*      100*/, FP64_V(0, 0xd6f3458800000, 0x41c)/*987654321*/, FP64_V(0, 0xd6eca42000000, 0x419)/*       123450000.5*/, FP64_V(0, 0xcf0033a34f337, 0x432)/*4072598000007579.5*/ } },
             { /*src1     */ { FP64_V(0, 0xd6f3458800000, 0x41c)/*987654321*/, FP64_V(1, 0x9000000000000, 0x405)/*     -100*/, FP64_V(0, 0xcf00348ec5858, 0x432)/*4072598123457580.0*/, FP64_V(0, 0xd6eca42000000, 0x419)/*       123450000.5*/ } },
             { /* =>      */ { FP64_V(0, 0xd6f3426800000, 0x41c)/*987654221*/, FP64_V(0, 0xd6f3426800000, 0x41c)/*987654221*/, FP64_V(0, 0xcf0033a34f337, 0x432)/*4072598000007579.5*/, FP64_V(0, 0xcf00348ec5858, 0x432)/*4072598123457580.0*/ } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_NORM_SAFE_INT_MAX(0),                                FP64_NORM_SAFE_INT_MAX(0)                                } },
             { /*src1     */ { FP64_NORM_SAFE_INT_MAX(0),                                FP64_1(0),                                                FP64_1(0),                                                FP64_1(1)                                                } },
             { /* =>      */ { FP64_1(0),                                                FP64_NORM_SAFE_INT_MAX(0),                                FP64_V(1, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP64_1(0),                                                FP64_NORM_SAFE_INT_MAX(0),               FP64_1(1),                                                FP64_1(1)                               } },
             { /*src1     */ { FP64_NORM_SAFE_INT_MAX(0),                                FP64_1(0),                               FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_NORM_SAFE_INT_MAX(1)               } },
             { /* =>      */ { FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_V(0, 0, FP64_EXP_SAFE_INT_MAX + 1), FP64_NORM_SAFE_INT_MAX(0),                                FP64_V(1, 0, FP64_EXP_SAFE_INT_MAX + 1) } },
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
           { { /*src2     */ { FP64_NORM_SAFE_INT_MAX(1),  FP64_NORM_SAFE_INT_MIN(0),               FP64_NORM_SAFE_INT_MIN(1),               FP64_NORM_SAFE_INT_MIN(0) } },
             { /*src1     */ { FP64_NORM_SAFE_INT_MAX(1),  FP64_NORM_SAFE_INT_MIN(0),               FP64_NORM_SAFE_INT_MIN(0),               FP64_0(0)                 } },
             { /* =>      */ { FP64_0(0),                  FP64_V(0, 0, FP64_EXP_SAFE_INT_MIN + 1), FP64_V(0, 0, FP64_EXP_SAFE_INT_MIN + 1), FP64_NORM_SAFE_INT_MIN(0) } },
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP },
           { { /*src2     */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_NORM_SAFE_INT_MIN(1),               FP64_NORM_SAFE_INT_MIN(0),               FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/ } },
             { /*src1     */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_NORM_SAFE_INT_MIN(1),               FP64_NORM_SAFE_INT_MIN(1),               FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/ } },
             { /* =>      */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_V(1, 0, FP64_EXP_SAFE_INT_MIN + 1), FP64_V(1, 0, FP64_EXP_SAFE_INT_MIN + 1), FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/ } },
-              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
     /** @todo More Normals. */
     /*
@@ -10037,37 +10037,37 @@
             { /*src1     */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } },
             { /* =>      */ { FP64_0(0),          FP64_0(0),          FP64_0(0),          FP64_0(0)         } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP },
           { { /*src2     */ { FP64_DENORM_MIN(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } },
             { /*src1     */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } },
             { /* =>      */ { FP64_0(0),          FP64_0(0),          FP64_0(0),          FP64_0(0)          } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP },
           { { /*src2     */ { FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MIN(0) } },
             { /*src1     */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } },
             { /* =>      */ { FP64_0(0),          FP64_0(0),          FP64_0(0),          FP64_0(0)          } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ },
+              /*mxcsr:in */ X86_MXCSR_DAZ,
+              /*128:out  */ X86_MXCSR_DAZ,
+              /*256:out  */ X86_MXCSR_DAZ },
           { { /*src2     */ { FP64_DENORM_MIN(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } },
             { /*src1     */ { FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0) } },
             { /* =>      */ { FP64_0(0),          FP64_0(0),          FP64_0(0),          FP64_0(0)          } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ },
+              /*mxcsr:in */ X86_MXCSR_DAZ,
+              /*128:out  */ X86_MXCSR_DAZ,
+              /*256:out  */ X86_MXCSR_DAZ },
           { { /*src2     */ { FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MIN(0) } },
             { /*src1     */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } },
             { /* =>      */ { FP64_0(0),          FP64_0(0),          FP64_0(0),          FP64_0(0)          } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
           { { /*src2     */ { FP64_DENORM_MIN(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } },
             { /*src1     */ { FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0) } },
             { /* =>      */ { FP64_0(0),          FP64_0(0),          FP64_0(0),          FP64_0(0)          } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
           { { /*src2     */ { FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MIN(0) } },
             { /*src1     */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } },
@@ -10166,25 +10166,25 @@
             { /*src1     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
             { /* =>      */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
             { /*src1     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
             { /* =>      */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_RC_ZERO },
           { { /*src2     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
             { /*src1     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
             { /* =>      */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
           { { /*src2     */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1) } },
             { /*src1     */ { FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0) } },
             { /* =>      */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0) } },
             { /*src1     */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0) } },
@@ -10196,25 +10196,25 @@
             { /*src1     */ { FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0) } },
             { /* =>      */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_RC_DOWN },
           { { /*src2     */ { FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0) } },
             { /*src1     */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0) } },
             { /* =>      */ { FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP },
+              /*mxcsr:in */ X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_RC_UP },
           { { /*src2     */ { FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0) } },
             { /*src1     */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0) } },
             { /* =>      */ { FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
           { { /*src2     */ { FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1) } },
             { /*src1     */ { FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(0) } },
             { /* =>      */ { FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
     /*
      * Infinity.
@@ -10223,31 +10223,31 @@
             { /*src1     */ { FP32_0(0),   FP32_INF(0), FP32_0(1),   FP32_INF(0), FP32_0(0),   FP32_INF(1), FP32_0(0),   FP32_INF(1) } },
             { /* =>      */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_0(0),   FP32_0(0),   FP32_0(0),   FP32_0(0)   } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP32_INF(0), FP32_0(0),   FP32_INF(0), FP32_0(1),   FP32_INF(1), FP32_0(0),   FP32_INF(1), FP32_0(0)   } },
             { /*src1     */ { FP32_0(0),   FP32_INF(0), FP32_0(1),   FP32_INF(0), FP32_0(0),   FP32_INF(1), FP32_0(0),   FP32_INF(1) } },
             { /* =>      */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_0(0),   FP32_0(0),   FP32_0(0),   FP32_0(0)   } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP },
+              /*mxcsr:in */ X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_RC_UP },
           { { /*src2     */ { FP32_INF(0), FP32_0(0),   FP32_INF(0), FP32_0(1),   FP32_INF(1), FP32_0(0),   FP32_INF(1), FP32_0(0)   } },
             { /*src1     */ { FP32_0(0),   FP32_INF(0), FP32_0(1),   FP32_INF(0), FP32_0(0),   FP32_INF(1), FP32_0(0),   FP32_INF(1) } },
             { /* =>      */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_0(0),   FP32_0(0),   FP32_0(0),   FP32_0(0)   } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_RC_DOWN },
           { { /*src2     */ { FP32_INF(0), FP32_0(0),   FP32_INF(0), FP32_0(1),   FP32_INF(1), FP32_0(0),   FP32_INF(1), FP32_0(0)   } },
             { /*src1     */ { FP32_0(0),   FP32_INF(0), FP32_0(1),   FP32_INF(0), FP32_0(0),   FP32_INF(1), FP32_0(0),   FP32_INF(1) } },
             { /* =>      */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_0(0),   FP32_0(0),   FP32_0(0),   FP32_0(0)   } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_RC_ZERO },
           { { /*src2     */ { FP32_INF(0), FP32_0(0),   FP32_INF(0), FP32_0(1),   FP32_INF(1), FP32_0(0),   FP32_INF(1), FP32_0(0)   } },
             { /*src1     */ { FP32_0(0),   FP32_INF(0), FP32_0(1),   FP32_INF(0), FP32_0(0),   FP32_INF(1), FP32_0(0),   FP32_INF(1) } },
             { /* =>      */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_0(0),   FP32_0(0),   FP32_0(0),   FP32_0(0)   } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
           { { /*src2     */ { FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(0) } },
             { /*src1     */ { FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_INF(0) } },
@@ -10259,31 +10259,31 @@
             { /*src1     */ { FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_INF(0) } },
             { /* =>      */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_INF(0), FP32_INF(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_RC_ZERO },
           { { /*src2     */ { FP32_INF(0),     FP32_NORM_V1(0), FP32_INF(1),     FP32_NORM_V3(1), FP32_INF(1),     FP32_NORM_V5(0), FP32_INF(1),     FP32_NORM_V7(0) } },
             { /*src1     */ { FP32_NORM_V0(0), FP32_INF(1),     FP32_NORM_V2(0), FP32_INF(1),     FP32_NORM_V4(1), FP32_INF(1),     FP32_NORM_V6(0), FP32_INF(0)     } },
             { /* =>      */ { FP32_INF(0),     FP32_NORM_V1(0), FP32_NORM_V2(0), FP32_NORM_V3(1), FP32_NORM_V4(1), FP32_NORM_V5(0), FP32_NORM_V6(0), FP32_INF(0)     } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP32_INF(0),     FP32_NORM_V1(0), FP32_INF(1),     FP32_NORM_V3(1), FP32_INF(1),     FP32_NORM_V5(0), FP32_INF(1),     FP32_NORM_V7(0) } },
             { /*src1     */ { FP32_NORM_V0(0), FP32_INF(1),     FP32_NORM_V2(0), FP32_INF(1),     FP32_NORM_V4(1), FP32_INF(1),     FP32_NORM_V6(0), FP32_INF(0)     } },
             { /* =>      */ { FP32_INF(0),     FP32_NORM_V1(0), FP32_NORM_V2(0), FP32_NORM_V3(1), FP32_NORM_V4(1), FP32_NORM_V5(0), FP32_NORM_V6(0), FP32_INF(0)     } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
           { { /*src2     */ { FP32_NORM_V7(0), FP32_INF(1),     FP32_NORM_V5(1), FP32_INF(1),     FP32_NORM_V3(0), FP32_INF(1),     FP32_NORM_V1(0), FP32_INF(0)     } },
             { /*src1     */ { FP32_INF(1),     FP32_NORM_V6(0), FP32_INF(1),     FP32_NORM_V4(1), FP32_INF(1),     FP32_NORM_V2(0), FP32_INF(0),     FP32_NORM_V0(0) } },
             { /* =>      */ { FP32_NORM_V7(0), FP32_NORM_V6(0), FP32_NORM_V5(1), FP32_NORM_V4(1), FP32_NORM_V3(0), FP32_NORM_V2(0), FP32_INF(0),     FP32_INF(0)     } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP },
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP },
           { { /*src2     */ { FP32_NORM_V7(0), FP32_INF(1),     FP32_NORM_V5(1), FP32_INF(1),     FP32_NORM_V3(0), FP32_INF(1),     FP32_NORM_V1(0), FP32_INF(0)     } },
             { /*src1     */ { FP32_INF(0),     FP32_NORM_V6(0), FP32_INF(0),     FP32_NORM_V4(1), FP32_INF(0),     FP32_NORM_V2(0), FP32_INF(1),     FP32_NORM_V0(0) } },
             { /* =>      */ { FP32_INF(0),     FP32_NORM_V6(0), FP32_INF(0),     FP32_NORM_V4(1), FP32_INF(0),     FP32_NORM_V2(0), FP32_NORM_V1(0), FP32_INF(0)     } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_RC_ZERO },
     /*
      * Normals.
@@ -10292,55 +10292,55 @@
             { /*src1     */ { FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0),        FP32_0(0),        FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_0(1),        FP32_NORM_MAX(0) } },
             { /* =>      */ { FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0),        FP32_NORM_MAX(1), FP32_0(1),        FP32_0(1),        FP32_NORM_MAX(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP32_NORM_MIN(0), FP32_0(0),        FP32_NORM_MIN(0), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_0(1),        FP32_NORM_MIN(1), FP32_NORM_MIN(1) } },
             { /*src1     */ { FP32_NORM_MIN(0), FP32_NORM_MIN(0), FP32_0(0),        FP32_0(0),        FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_0(1),        FP32_NORM_MIN(0) } },
             { /* =>      */ { FP32_NORM_MIN(0), FP32_NORM_MIN(0), FP32_NORM_MIN(0), FP32_0(0),        FP32_NORM_MIN(1), FP32_0(1),        FP32_0(1),        FP32_NORM_MIN(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP32_NORM_MIN(0), FP32_NORM_MIN(0), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1) } },
             { /*src1     */ { FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MIN(0), FP32_NORM_MIN(1), FP32_NORM_MIN(0), FP32_NORM_MIN(1) } },
             { /* =>      */ { FP32_NORM_MAX(0), FP32_NORM_MIN(0), FP32_NORM_MAX(0), FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MIN(0), FP32_NORM_MIN(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(1) } },
             { /*src1     */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1) } },
             { /* =>      */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_V(0, 0, 0x7d)/*0.25*/, FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_V(0, 0, 0x7d)/*0.25*/, FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_V(0, 0, 0x7d)/* 0.25*/, FP32_V(0, 0x600000, 0x7f)/*1.75*/, FP32_V(1, 0, 0x7d)/*-0.25*/ } },
             { /*src1     */ { FP32_V(1, 0,        0x7d)/*-0.25*/, FP32_V(0, 0, 0x7e)/*0.50*/, FP32_V(1, 0,        0x7d)/*-0.25*/, FP32_V(0, 0, 0x7e)/*0.50*/, FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_V(1, 0, 0x7e)/*-0.50*/, FP32_V(1, 0,        0x7d)/*0.25*/, FP32_V(1, 0, 0x7e)/*-0.50*/ } },
             { /* =>      */ { FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_V(0, 0, 0x7e)/*0.50*/, FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_V(0, 0, 0x7e)/*0.50*/, FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_V(0, 0, 0x7d)/* 0.25*/, FP32_V(0, 0x600000, 0x7f)/*1.75*/, FP32_V(1, 0, 0x7d)/*-0.25*/ } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
           { { /*src2     */ { FP32_NORM_MAX(0), FP32_NORM_V1(0), FP32_NORM_V2(1), FP32_NORM_V3(1), FP32_NORM_V5(0), FP32_0(1),       FP32_NORM_V5(1), FP32_0(0)       } },
             { /*src1     */ { FP32_NORM_V1(0),  FP32_NORM_V1(1), FP32_NORM_V2(0), FP32_NORM_V3(1), FP32_0(1),       FP32_NORM_V6(0), FP32_0(1),       FP32_NORM_V7(0) } },
             { /* =>      */ { FP32_NORM_MAX(0), FP32_NORM_V1(0), FP32_NORM_V2(0), FP32_NORM_V3(1), FP32_NORM_V5(0), FP32_NORM_V6(0), FP32_0(1),       FP32_NORM_V7(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_RC_DOWN },
           { { /*src2     */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_V(0, 0x5c0000, 0x84)/*55*/, FP32_V(1, 0x2514d6, 0x93)/*-1352346.75*/, FP32_V(1, 0x5c0000, 0x84)/*-55*/, FP32_V(1, 0x2514d6, 0x93)/*-1352346.75*/, FP32_V(1, 0x534000, 0x86)/*-211.25*/, FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_1(1) } },
             { /*src1     */ { FP32_V(0, 0x1ea980, 0x8f)/*  81235*/, FP32_V(0, 0x600000, 0x81)/* 7*/, FP32_V(0, 0x7c9000, 0x88)/*    1010.25*/, FP32_V(0, 0x600000, 0x81)/*  7*/, FP32_V(0, 0x253468, 0x93)/* 1353357.00*/, FP32_1(1),                            FP32_V(1, 0x712060, 0x92)/*- 987654*/, FP32_1(0) } },
             { /* =>      */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_V(0, 0x5c0000, 0x84)/*55*/, FP32_V(0, 0x7c9000, 0x88)/*    1010.25*/, FP32_V(0, 0x600000, 0x81)/*  7*/, FP32_V(0, 0x253468, 0x93)/* 1353357.00*/, FP32_1(1),                            FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_1(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_RC_ZERO },
           { { /*src2     */ { FP32_V(0, 0x600000, 0x7e)/*      0.875*/, FP32_V(0, 0x3ce348, 0x90)/*193421.125*/, FP32_V(0, 0x6423f2, 0x92)/*934463.125*/, FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0x16b43a, 0x93)/*1234567.25*/, FP32_V(0, 0x792318, 0x91)/*510232.75*/, FP32_V(0, 0x600000, 0x7e)/* 0.875*/ } },
             { /*src1     */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_V(0, 0x430ebc, 0x91)/*399477.875*/, FP32_V(0, 0x52e0b4, 0x92)/*863755.250*/, FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MAX(1), FP32_V(0, 0x00c6d3, 0x94)/*2109876.75*/, FP32_V(1, 0x316740, 0x8e)/*-45415.25*/, FP32_V(1, 0,        0x7d)/*-0.250*/ } },
             { /* =>      */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_V(0, 0x430ebc, 0x91)/*399477.875*/, FP32_V(0, 0x6423f2, 0x92)/*934463.125*/, FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0x00c6d3, 0x94)/*2109876.75*/, FP32_V(0, 0x792318, 0x91)/*510232.75*/, FP32_V(0, 0x600000, 0x7e)/* 0.875*/ } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_RC_DOWN },
           { { /*src2     */ { FP32_V(0, 0x490fda, 0x80)/*3.1415926*/, FP32_V(0, 0x620b2e, 0x92)/*925874.9*/, FP32_V(0, 0x5dd520, 0x8e)/* 56789.125*/, FP32_V(1, 0x40e6b6, 0x8c)/*-12345.678*/, FP32_V(1, 0x490fda, 0x80)/*-3.1415926*/, FP32_V(1, 0x620b2e, 0x92)/*-925874.8*/, FP32_V(0, 0x5dd520, 0x8e)/*56789.125*/, FP32_V(0, 0x40e6b6, 0x8c)/*12345.678*/ } },
             { /*src1     */ { FP32_V(0, 0x490fdb, 0x80)/*3.1415927*/, FP32_V(0, 0x620b2d, 0x92)/*925874.8*/, FP32_V(1, 0x5dd521, 0x8e)/*-56789.127*/, FP32_V(1, 0x40e6b7, 0x8c)/*-12345.679*/, FP32_V(1, 0x490fdb, 0x80)/*-3.1415927*/, FP32_V(0, 0x620b2d, 0x92)/* 925874.9*/, FP32_V(0, 0x5dd521, 0x8e)/*56789.127*/, FP32_V(0, 0x40e6b7, 0x8c)/*12345.679*/ } },
             { /* =>      */ { FP32_V(0, 0x490fdb, 0x80)/*3.1415927*/, FP32_V(0, 0x620b2e, 0x92)/*925874.9*/, FP32_V(0, 0x5dd520, 0x8e)/* 56789.125*/, FP32_V(1, 0x40e6b6, 0x8c)/*-12345.678*/, FP32_V(1, 0x490fda, 0x80)/*-3.1415926*/, FP32_V(0, 0x620b2d, 0x92)/* 925874.9*/, FP32_V(0, 0x5dd521, 0x8e)/*56789.127*/, FP32_V(0, 0x40e6b7, 0x8c)/*12345.678*/ } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
     /** @todo More Normals. */
     /*
@@ -10356,13 +10356,13 @@
             { /*src1     */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0) } },
             { /* =>      */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE },
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_DE,
+              /*256:out  */ X86_MXCSR_DE },
           { { /*src2     */ { FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } },
             { /*src1     */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0) } },
             { /* =>      */ { FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0)          } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP },
           { { /*src2     */ { FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0),          FP32_0(0), FP32_0(0), FP32_0(0) } },
             { /*src1     */ { FP32_0(0),          FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
@@ -10374,13 +10374,13 @@
             { /*src1     */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0)          } },
             { /* =>      */ { FP32_0(0), FP32_0(0),          FP32_0(0), FP32_0(0), FP32_0(0),          FP32_0(0), FP32_0(0), FP32_0(1)          } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ },
+              /*mxcsr:in */ X86_MXCSR_DAZ,
+              /*128:out  */ X86_MXCSR_DAZ,
+              /*256:out  */ X86_MXCSR_DAZ },
           { { /*src2     */ { FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } },
             { /*src1     */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0) } },
             { /* =>      */ { FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0)          } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP },
     /** @todo More Denormals. */
     /*35*/ FP32_TABLE_D9_PS_INVALIDS
@@ -10451,25 +10451,25 @@
             { /*src1     */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
             { /* =>      */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
             { /*src1     */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
             { /* =>      */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_RC_ZERO },
           { { /*src2     */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
             { /*src1     */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
             { /* =>      */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
           { { /*src2     */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } },
             { /*src1     */ { FP64_0(1), FP64_0(0), FP64_0(1), FP64_0(1) } },
             { /* =>      */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_0(0) } },
             { /*src1     */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } },
@@ -10481,25 +10481,25 @@
             { /*src1     */ { FP64_0(1), FP64_0(0), FP64_0(1), FP64_0(1) } },
             { /* =>      */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_RC_DOWN },
           { { /*src2     */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_0(0) } },
             { /*src1     */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } },
             { /* =>      */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP },
+              /*mxcsr:in */ X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_RC_UP },
           { { /*src2     */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_0(0) } },
             { /*src1     */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } },
             { /* =>      */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
           { { /*src2     */ { FP64_0(1), FP64_0(1), FP64_0(0), FP64_0(0) } },
             { /*src1     */ { FP64_0(1), FP64_0(1), FP64_0(0), FP64_0(0) } },
             { /* =>      */ { FP64_0(1), FP64_0(1), FP64_0(0), FP64_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
     /*
      * Infinity.
@@ -10508,31 +10508,31 @@
             { /*src1     */ { FP64_0(0),   FP64_INF(0), FP64_0(1),   FP64_INF(0) } },
             { /* =>      */ { FP64_INF(0), FP64_INF(0), FP64_INF(0), FP64_INF(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP64_INF(0), FP64_0(0),   FP64_INF(0), FP64_0(1)   } },
             { /*src1     */ { FP64_0(0),   FP64_INF(0), FP64_0(1),   FP64_INF(0) } },
             { /* =>      */ { FP64_INF(0), FP64_INF(0), FP64_INF(0), FP64_INF(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP },
+              /*mxcsr:in */ X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_RC_UP },
           { { /*src2     */ { FP64_INF(0), FP64_0(0),   FP64_INF(0), FP64_0(1)   } },
             { /*src1     */ { FP64_0(0),   FP64_INF(0), FP64_0(1),   FP64_INF(0) } },
             { /* =>      */ { FP64_INF(0), FP64_INF(0), FP64_INF(0), FP64_INF(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_RC_DOWN },
           { { /*src2     */ { FP64_INF(0), FP64_0(0),   FP64_INF(0), FP64_0(1)   } },
             { /*src1     */ { FP64_0(0),   FP64_INF(0), FP64_0(1),   FP64_INF(0) } },
             { /* =>      */ { FP64_INF(0), FP64_INF(0), FP64_INF(0), FP64_INF(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_RC_ZERO },
           { { /*src2     */ { FP64_INF(0), FP64_0(0),   FP64_INF(0), FP64_0(1)   } },
             { /*src1     */ { FP64_0(0),   FP64_INF(0), FP64_0(1),   FP64_INF(0) } },
             { /* =>      */ { FP64_INF(0), FP64_INF(0), FP64_INF(0), FP64_INF(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
           { { /*src2     */ { FP64_INF(0), FP64_INF(0), FP64_INF(1), FP64_INF(1) } },
             { /*src1     */ { FP64_INF(0), FP64_INF(1), FP64_INF(0), FP64_INF(1) } },
@@ -10544,31 +10544,31 @@
             { /*src1     */ { FP64_INF(0), FP64_INF(1), FP64_INF(0), FP64_INF(1) } },
             { /* =>      */ { FP64_INF(0), FP64_INF(0), FP64_INF(0), FP64_INF(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_RC_ZERO },
           { { /*src2     */ { FP64_INF(0),     FP64_NORM_V1(0), FP64_INF(1),     FP64_NORM_V3(1) } },
             { /*src1     */ { FP64_NORM_V0(0), FP64_INF(1),     FP64_NORM_V2(0), FP64_INF(1)     } },
             { /* =>      */ { FP64_INF(0),     FP64_NORM_V1(0), FP64_NORM_V2(0), FP64_NORM_V3(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP64_INF(0),     FP64_NORM_V1(0), FP64_INF(1),     FP64_NORM_V3(1) } },
             { /*src1     */ { FP64_NORM_V0(0), FP64_INF(1),     FP64_NORM_V2(0), FP64_INF(1)     } },
             { /* =>      */ { FP64_INF(0),     FP64_NORM_V1(0), FP64_NORM_V2(0), FP64_NORM_V3(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
           { { /*src2     */ { FP64_NORM_V1(0), FP64_INF(1),     FP64_NORM_V2(1), FP64_INF(1)     } },
             { /*src1     */ { FP64_INF(1),     FP64_NORM_V3(0), FP64_INF(1),     FP64_NORM_V0(1) } },
             { /* =>      */ { FP64_NORM_V1(0), FP64_NORM_V3(0), FP64_NORM_V2(1), FP64_NORM_V0(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP },
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP },
           { { /*src2     */ { FP64_NORM_V1(0), FP64_INF(1),     FP64_NORM_V3(1), FP64_INF(1)     } },
             { /*src1     */ { FP64_INF(0),     FP64_NORM_V2(0), FP64_INF(0),     FP64_NORM_V0(1) } },
             { /* =>      */ { FP64_INF(0),     FP64_NORM_V2(0), FP64_INF(0),     FP64_NORM_V0(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_RC_ZERO },
     /*
      * Normals.
@@ -10577,25 +10577,25 @@
             { /*src1     */ { FP64_NORM_V3(1), FP64_NORM_V1(0), FP64_NORM_V2(1), FP64_NORM_V1(0) } },
             { /* =>      */ { FP64_NORM_V0(0), FP64_NORM_V1(0), FP64_NORM_V2(0), FP64_NORM_V1(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP64_NORM_V0(0), FP64_0(1),       FP64_NORM_V2(0), FP64_0(1)       } },
             { /*src1     */ { FP64_0(0),       FP64_NORM_V1(1), FP64_0(0),       FP64_NORM_V1(0) } },
             { /* =>      */ { FP64_NORM_V0(0), FP64_0(1),       FP64_NORM_V2(0), FP64_NORM_V1(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_RC_ZERO },
           { { /*src2     */ { FP64_V(0, 0, 0x409)/*1024*/, FP64_V(0, 0xb800000000000, 0x404)/*55*/, FP64_V(0, 0x8000000000000, 0x409)/*1536*/, FP64_V(0, 0xf000000000000, 0x404)/* 62*/ } },
             { /*src1     */ { FP64_V(0, 0, 0x408)/* 512*/, FP64_V(0, 0xc000000000000, 0x401)/* 7*/, FP64_1(1),                                 FP64_V(1, 0xf000000000000, 0x404)/*-62*/ } },
             { /* =>      */ { FP64_V(0, 0, 0x409)/*1024*/, FP64_V(0, 0xb800000000000, 0x404)/*55*/, FP64_V(0, 0x8000000000000, 0x409)/*1536*/, FP64_V(0, 0xf000000000000, 0x404)/* 62*/ } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ },
+              /*mxcsr:in */ X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_FZ,
+              /*256:out  */ X86_MXCSR_FZ },
           { { /*src2     */ { FP64_V(0, 0x26580b4800000, 0x41d)/* 1234567890*/, FP64_V(0, 0xd6f3458800000, 0x41c)/*987654321*/, FP64_V(0, 0xd6f3426800000, 0x41c)/*987654221*/, FP64_V(0, 0xcf0033a34f337, 0x432)/*4072598000007579.5*/ } },
             { /*src1     */ { FP64_V(1, 0x26580b4800000, 0x41d)/*-1234567890*/, FP64_V(0, 0x9000000000000, 0x405)/*      100*/, FP64_1(0),                                      FP64_V(0, 0xd6eca42000000, 0x419)/*       123450000.5*/ } },
             { /* =>      */ { FP64_V(0, 0x26580b4800000, 0x41d)/* 1234567890*/, FP64_V(0, 0xd6f3458800000, 0x41c)/*987654321*/, FP64_V(0, 0xd6f3426800000, 0x41c)/*987654221*/, FP64_V(0, 0xcf0033a34f337, 0x432)/*4072598000007579.5*/ } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ },
+              /*mxcsr:in */ X86_MXCSR_DAZ,
+              /*128:out  */ X86_MXCSR_DAZ,
+              /*256:out  */ X86_MXCSR_DAZ },
           { { /*src2     */ { FP64_V(0, 0x26580b4800000, 0x41d)/* 1234567890*/, FP64_V(0, 0xd6f3458800000, 0x41c)/*987654321*/, FP64_V(0, 0xd6f3426800000, 0x41c)/*987654221*/, FP64_V(0, 0xcf0033a34f337, 0x432)/*4072598000007579.5*/ } },
             { /*src1     */ { FP64_V(1, 0x26580b4800000, 0x41d)/*-1234567890*/, FP64_V(0, 0x9000000000000, 0x405)/*     -100*/, FP64_1(0),                                      FP64_V(0, 0xd6eca42000000, 0x419)/*       123450000.5*/ } },
@@ -10607,7 +10607,7 @@
             { /*src1     */ { FP64_1(0),                 FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(0), FP64_0(0)                 } },
             { /* =>      */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MIN(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
           { { /*src2     */ { FP64_NORM_SAFE_INT_MIN(0), FP64_0(0),                 FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(1) } },
             { /*src1     */ { FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(1), FP64_0(0),                 FP64_NORM_SAFE_INT_MIN(0) } },
@@ -10619,13 +10619,13 @@
             { /*src1     */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_V(0, 0xb88e0395d49b0, 0x42d)/* 121098765432102.75*/ } },
             { /* =>      */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_V(0, 0xb88e0395d49b0, 0x42d)/* 121098765432102.75*/ } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP },
+              /*mxcsr:in */ X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_RC_UP },
           { { /*src2     */ { FP64_V(0, 0xc000000000000, 0x3ff)/*1.75*/, FP64_V(0, 0, 0x3fd)/*0.25*/, FP64_V(0, 0x26580b4c7e6b7, 0x41d)/*1234567891.1234567*/, FP64_V(0, 0xf9b0207d06184, 0x3fb)/*0.1234589833333129*/ } },
             { /*src1     */ { FP64_V(0, 0,               0x3fd)/*0.25*/, FP64_V(0, 0, 0x3fe)/*0.50*/, FP64_V(0, 0x26580b4c7e6bc, 0x41d)/*1234567891.1234580*/, FP64_V(0, 0xf9b0207d0617d, 0x3fb)/*0.1234589833333128*/ } },
             { /* =>      */ { FP64_V(0, 0xc000000000000, 0x3ff)/*1.75*/, FP64_V(0, 0, 0x3fe)/*0.50*/, FP64_V(0, 0x26580b4c7e6bc, 0x41d)/*1234567891.1234580*/, FP64_V(0, 0xf9b0207d06184, 0x3fb)/*0.1234589833333129*/ } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
     /*
      * Denormals.
@@ -10640,13 +10640,13 @@
             { /*src1     */ { FP64_0(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_0(0)          } },
             { /* =>      */ { FP64_0(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE },
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_DE,
+              /*256:out  */ X86_MXCSR_DE },
           { { /*src2     */ { FP64_DENORM_MIN(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } },
             { /*src1     */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } },
             { /* =>      */ { FP64_0(0),          FP64_0(0),          FP64_0(0),          FP64_0(0)          } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP },
           { { /*src2     */ { FP64_DENORM_MAX(0), FP64_0(0),          FP64_DENORM_MAX(0), FP64_0(0)          } },
             { /*src1     */ { FP64_0(0),          FP64_DENORM_MAX(0), FP64_0(0),          FP64_DENORM_MAX(0) } },
@@ -10658,13 +10658,13 @@
             { /*src1     */ { FP64_0(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_0(0)          } },
             { /* =>      */ { FP64_0(0), FP64_0(0),          FP64_0(0),          FP64_0(1)          } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ },
+              /*mxcsr:in */ X86_MXCSR_DAZ,
+              /*128:out  */ X86_MXCSR_DAZ,
+              /*256:out  */ X86_MXCSR_DAZ },
           { { /*src2     */ { FP64_DENORM_MIN(0), FP64_DENORM_MIN(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0) } },
             { /*src1     */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } },
             { /* =>      */ { FP64_0(0),          FP64_0(0),          FP64_0(0),          FP64_0(0)          } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP },
     /** @todo Denormals. */
     /*
@@ -10738,6 +10738,6 @@
             { /*src1     */ { FP32_0(0), FP32_0_x7(0) } },
             { /* =>      */ { FP32_0(0), FP32_0_x7(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_0(0), FP32_0_x7(0) } },
@@ -10750,42 +10750,42 @@
             { /*src1     */ { FP32_0(0), FP32_RAND_x7_V2 } },
             { /* =>      */ { FP32_0(0), FP32_RAND_x7_V2 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_0(0), FP32_RAND_x7_V2 } },
             { /*src1     */ { FP32_0(0), FP32_RAND_x7_V3 } },
             { /* =>      */ { FP32_0(0), FP32_RAND_x7_V3 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_0(0), FP32_RAND_x7_V3 } },
             { /*src1     */ { FP32_0(0), FP32_RAND_x7_V4 } },
             { /* =>      */ { FP32_0(0), FP32_RAND_x7_V4 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_0(0), FP32_RAND_x7_V4 } },
             { /*src1     */ { FP32_0(1), FP32_RAND_x7_V5 } },
             { /* =>      */ { FP32_0(0), FP32_RAND_x7_V5 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_0(0), FP32_RAND_x7_V5 } },
             { /*src1     */ { FP32_0(1), FP32_RAND_x7_V6 } },
             { /* =>      */ { FP32_0(0), FP32_RAND_x7_V6 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_0(1), FP32_RAND_x7_V6 } },
             { /*src1     */ { FP32_0(0), FP32_RAND_x7_V5 } },
             { /* =>      */ { FP32_0(1), FP32_RAND_x7_V5 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_0(1), FP32_RAND_x7_V7 } },
             { /*src1     */ { FP32_0(0), FP32_RAND_x7_V2 } },
             { /* =>      */ { FP32_0(1), FP32_RAND_x7_V2 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_0(1), FP32_RAND_x7_V1 } },
@@ -10798,6 +10798,6 @@
             { /*src1     */ { FP32_0(1), FP32_RAND_x7_V5 } },
             { /* =>      */ { FP32_0(1), FP32_RAND_x7_V5 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
               /*256:out  */ -1 },
     /*
@@ -10807,24 +10807,24 @@
             { /*src1     */ { FP32_0(0),   FP32_RAND_x7_V1 } },
             { /* =>      */ { FP32_INF(0), FP32_RAND_x7_V1 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_0(0),   FP32_RAND_x7_V5 } },
             { /*src1     */ { FP32_INF(0), FP32_RAND_x7_V3 } },
             { /* =>      */ { FP32_INF(0), FP32_RAND_x7_V3 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
+              /*mxcsr:in */ X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_RC_UP,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_INF(0), FP32_RAND_x7_V0 } },
             { /*src1     */ { FP32_0(0),   FP32_RAND_x7_V3 } },
             { /* =>      */ { FP32_INF(0), FP32_RAND_x7_V3 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_0(0),   FP32_RAND_x7_V2 } },
             { /*src1     */ { FP32_INF(1), FP32_RAND_x7_V0 } },
             { /* =>      */ { FP32_0(0),   FP32_RAND_x7_V0 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_INF(0), FP32_RAND_x7_V3 } },
@@ -10837,66 +10837,66 @@
             { /*src1     */ { FP32_INF(0), FP32_RAND_x7_V0 } },
             { /* =>      */ { FP32_INF(0), FP32_RAND_x7_V0 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_INF(1), FP32_RAND_x7_V1 } },
             { /*src1     */ { FP32_INF(1), FP32_RAND_x7_V2 } },
             { /* =>      */ { FP32_INF(1), FP32_RAND_x7_V2 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_INF(1), FP32_RAND_x7_V3 } },
             { /*src1     */ { FP32_INF(1), FP32_RAND_x7_V3 } },
             { /* =>      */ { FP32_INF(1), FP32_RAND_x7_V3 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_INF(1), FP32_RAND_x7_V1 } },
             { /*src1     */ { FP32_INF(0), FP32_RAND_x7_V1 } },
             { /* =>      */ { FP32_INF(0), FP32_RAND_x7_V1 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
+              /*mxcsr:in */ X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_RC_UP,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_INF(1), FP32_RAND_x7_V0 } },
             { /*src1     */ { FP32_INF(0), FP32_RAND_x7_V1 } },
             { /* =>      */ { FP32_INF(0), FP32_RAND_x7_V1 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_INF(0), FP32_RAND_x7_V3 } },
             { /*src1     */ { FP32_INF(1), FP32_RAND_x7_V2 } },
             { /* =>      */ { FP32_INF(0), FP32_RAND_x7_V2 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_INF(0), FP32_RAND_x7_V0 } },
             { /*src1     */ { FP32_INF(1), FP32_RAND_x7_V3 } },
             { /* =>      */ { FP32_INF(0), FP32_RAND_x7_V3 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
+              /*mxcsr:in */ X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_FZ,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_INF(0),     FP32_RAND_x7_V4 } },
             { /*src1     */ { FP32_NORM_V0(0), FP32_RAND_x7_V5 } },
             { /* =>      */ { FP32_INF(0),     FP32_RAND_x7_V5 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_INF(0),     FP32_RAND_x7_V6 } },
             { /*src1     */ { FP32_NORM_V3(0), FP32_RAND_x7_V5 } },
             { /* =>      */ { FP32_INF(0),     FP32_RAND_x7_V5 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_NORM_V7(0), FP32_RAND_x7_V7 } },
             { /*src1     */ { FP32_INF(1),     FP32_RAND_x7_V1 } },
             { /* =>      */ { FP32_NORM_V7(0), FP32_RAND_x7_V1 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_NORM_V7(0), FP32_RAND_x7_V4 } },
             { /*src1     */ { FP32_INF(0),     FP32_RAND_x7_V2 } },
             { /* =>      */ { FP32_INF(0),     FP32_RAND_x7_V2 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
     /*
@@ -10906,114 +10906,114 @@
             { /*src1     */ { FP32_NORM_MAX(0), FP32_RAND_x7_V3 } },
             { /* =>      */ { FP32_NORM_MAX(0), FP32_RAND_x7_V3 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_NORM_MIN(0), FP32_RAND_x7_V3 } },
             { /*src1     */ { FP32_NORM_MIN(0), FP32_RAND_x7_V2 } },
             { /* =>      */ { FP32_NORM_MIN(0), FP32_RAND_x7_V2 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_NORM_MIN(0), FP32_RAND_x7_V3 } },
             { /*src1     */ { FP32_NORM_MAX(0), FP32_RAND_x7_V1 } },
             { /* =>      */ { FP32_NORM_MAX(0), FP32_RAND_x7_V1 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_NORM_MAX(0), FP32_RAND_x7_V2 } },
             { /*src1     */ { FP32_NORM_MAX(0), FP32_RAND_x7_V0 } },
             { /* =>      */ { FP32_NORM_MAX(0), FP32_RAND_x7_V0 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_x7_V2 } },
             { /*src1     */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V1 } },
             { /* =>      */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V1 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V6 } },
             { /*src1     */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V1 } },
             { /* =>      */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V1 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V0 } },
             { /*src1     */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_x7_V1 } },
             { /* =>      */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V1 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_RAND_x7_V1 } },
             { /*src1     */ { FP32_V(1, 0,        0x7d)/*-0.25*/, FP32_RAND_x7_V2 } },
             { /* =>      */ { FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_RAND_x7_V2 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_V(0, 0, 0x7d)/*0.25*/, FP32_RAND_x7_V3 } },
             { /*src1     */ { FP32_V(0, 0, 0x7e)/*0.50*/, FP32_RAND_x7_V1 } },
             { /* =>      */ { FP32_V(0, 0, 0x7e)/*0.50*/, FP32_RAND_x7_V1 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_NORM_MAX(0), FP32_RAND_x7_V1 } },
             { /*src1     */ { FP32_NORM_V1(0),  FP32_RAND_x7_V0 } },
             { /* =>      */ { FP32_NORM_MAX(0), FP32_RAND_x7_V0 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
+              /*mxcsr:in */ X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_RC_DOWN,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_RAND_x7_V3 } },
             { /*src1     */ { FP32_V(0, 0x1ea980, 0x8f)/*  81235*/, FP32_RAND_x7_V1 } },
             { /* =>      */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_RAND_x7_V1 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_V(1, 0x2514d6, 0x93)/*-1352346.75*/, FP32_RAND_x7_V2 } },
             { /*src1     */ { FP32_V(0, 0x7c9000, 0x88)/*    1010.25*/, FP32_RAND_x7_V0 } },
             { /* =>      */ { FP32_V(0, 0x7c9000, 0x88)/*    1010.25*/, FP32_RAND_x7_V0 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_V(1, 0x2514d6, 0x93)/*-1352346.75*/, FP32_RAND_x7_V4 } },
             { /*src1     */ { FP32_V(0, 0x253468, 0x93)/* 1353357.00*/, FP32_RAND_x7_V4 } },
             { /* =>      */ { FP32_V(0, 0x253468, 0x93)/* 1353357.00*/, FP32_RAND_x7_V4 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_V(1, 0x40e6b6, 0x8c)/*-12345.678*/, FP32_RAND_x7_V3 } },
             { /*src1     */ { FP32_V(1, 0x40e6b7, 0x8c)/*-12345.679*/, FP32_RAND_x7_V1 } },
             { /* =>      */ { FP32_V(1, 0x40e6b6, 0x8c)/*-12345.678*/, FP32_RAND_x7_V1 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_V(0, 0x620b2e, 0x92)/*925874.9*/, FP32_RAND_x7_V2 } },
             { /*src1     */ { FP32_V(0, 0x620b2d, 0x92)/*925874.8*/, FP32_RAND_x7_V4 } },
             { /* =>      */ { FP32_V(0, 0x620b2e, 0x92)/*925874.9*/, FP32_RAND_x7_V4 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_V(0, 0x490fda, 0x80)/*3.1415926*/, FP32_RAND_x7_V3 } },
             { /*src1     */ { FP32_V(0, 0x490fdb, 0x80)/*3.1415927*/, FP32_RAND_x7_V1 } },
             { /* =>      */ { FP32_V(0, 0x490fdb, 0x80)/*3.1415927*/, FP32_RAND_x7_V1 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_V(1, 0x40e6b6, 0x8c)/*-12345.678*/, FP32_RAND_x7_V0 } },
             { /*src1     */ { FP32_V(1, 0x40e6b7, 0x8c)/*-12345.679*/, FP32_RAND_x7_V0 } },
             { /* =>      */ { FP32_V(1, 0x40e6b6, 0x8c)/*-12345.678*/, FP32_RAND_x7_V0 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_V(0, 0x5dd520, 0x8e)/* 56789.125*/, FP32_RAND_x7_V6 } },
             { /*src1     */ { FP32_V(1, 0x5dd521, 0x8e)/*-56789.127*/, FP32_RAND_x7_V4 } },
             { /* =>      */ { FP32_V(0, 0x5dd520, 0x8e)/* 56789.125*/, FP32_RAND_x7_V4 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_RAND_x7_V7 } },
             { /*src1     */ { FP32_V(1, 0,        0x7d)/*-0.250*/, FP32_RAND_x7_V1 } },
             { /* =>      */ { FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_RAND_x7_V1 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
+              /*mxcsr:in */ X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_RC_UP,
               /*256:out  */ -1 },
     /** @todo More Normals. */
@@ -11030,54 +11030,54 @@
             { /*src1     */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V1 } },
             { /* =>      */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V1 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_DE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_DENORM_MIN(0), FP32_RAND_x7_V4 } },
             { /*src1     */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V3 } },
             { /* =>      */ { FP32_0(0),          FP32_RAND_x7_V3 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V7 } },
             { /*src1     */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V4 } },
             { /* =>      */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V4 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_DE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V6 } },
             { /*src1     */ { FP32_DENORM_MAX(1), FP32_RAND_x7_V4 } },
             { /* =>      */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V4 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_DE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_DENORM_MAX(1), FP32_RAND_x7_V3 } },
             { /*src1     */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V2 } },
             { /* =>      */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V2 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_DE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_DENORM_MIN(1), FP32_RAND_x7_V7 } },
             { /*src1     */ { FP32_DENORM_MIN(0), FP32_RAND_x7_V2 } },
             { /* =>      */ { FP32_DENORM_MIN(0), FP32_RAND_x7_V2 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_DE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_DENORM_MIN(1), FP32_RAND_x7_V5 } },
             { /*src1     */ { FP32_DENORM_MIN(1), FP32_RAND_x7_V1 } },
             { /* =>      */ { FP32_DENORM_MIN(1), FP32_RAND_x7_V1 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_DE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_DENORM_MIN(1), FP32_RAND_x7_V2 } },
             { /*src1     */ { FP32_DENORM_MIN(1), FP32_RAND_x7_V3 } },
             { /* =>      */ { FP32_0(1),          FP32_RAND_x7_V3 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
+              /*mxcsr:in */ X86_MXCSR_DAZ,
+              /*128:out  */ X86_MXCSR_DAZ,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_DENORM_MIN(0), FP32_RAND_x7_V0 } },
             { /*src1     */ { FP32_0(0),          FP32_RAND_x7_V0 } },
             { /* =>      */ { FP32_DENORM_MIN(0), FP32_RAND_x7_V0 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_DE,
               /*256:out  */ -1 },
     /** @todo More Denormals. */
@@ -11139,6 +11139,6 @@
             { /*src1     */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
             { /* =>      */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
@@ -11151,42 +11151,42 @@
             { /*src1     */ { FP64_0(0), FP64_INF(1), FP64_QNAN(0), FP64_SNAN(1) } },
             { /* =>      */ { FP64_0(0), FP64_INF(1), FP64_QNAN(0), FP64_SNAN(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V0(0), FP64_RAND_V0(0) } },
             { /*src1     */ { FP64_0(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(0) } },
             { /* =>      */ { FP64_0(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_0(0), FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V1(0) } },
             { /*src1     */ { FP64_0(0), FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V2(1) } },
             { /* =>      */ { FP64_0(0), FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V2(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V3(0) } },
             { /*src1     */ { FP64_0(1), FP64_RAND_V1(0), FP64_RAND_V2(0), FP64_RAND_V3(0) } },
             { /* =>      */ { FP64_0(0), FP64_RAND_V1(0), FP64_RAND_V2(0), FP64_RAND_V3(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_0(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(0) } },
             { /*src1     */ { FP64_0(1), FP64_RAND_V2(1), FP64_RAND_V3(0), FP64_RAND_V0(1) } },
             { /* =>      */ { FP64_0(0), FP64_RAND_V2(1), FP64_RAND_V3(0), FP64_RAND_V0(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_0(1), FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V3(1) } },
             { /*src1     */ { FP64_0(0), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V3(0) } },
             { /* =>      */ { FP64_0(1), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V3(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_0(1), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V1(0) } },
             { /*src1     */ { FP64_0(0), FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V3(0) } },
             { /* =>      */ { FP64_0(1), FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V3(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_0(1), FP64_RAND_V1(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } },
@@ -11199,6 +11199,6 @@
             { /*src1     */ { FP64_0(1), FP64_RAND_V1(0), FP64_RAND_V0(1), FP64_RAND_V2(1) } },
             { /* =>      */ { FP64_0(1), FP64_RAND_V1(0), FP64_RAND_V0(1), FP64_RAND_V2(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
               /*256:out  */ -1 },
     /*
@@ -11208,24 +11208,24 @@
             { /*src1     */ { FP64_0(0),   FP64_RAND_V1(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } },
             { /* =>      */ { FP64_INF(0), FP64_RAND_V1(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_0(0),   FP64_RAND_V1(1), FP64_RAND_V1(1), FP64_RAND_V3(1) } },
             { /*src1     */ { FP64_INF(0), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } },
             { /* =>      */ { FP64_INF(0), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
+              /*mxcsr:in */ X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_RC_UP,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_INF(0), FP64_INF(1),     FP64_SNAN(1),    FP64_QNAN(1)    } },
             { /*src1     */ { FP64_0(0),   FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } },
             { /* =>      */ { FP64_INF(0), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_0(0),   FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V3(0) } },
             { /*src1     */ { FP64_INF(1), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V0(1) } },
             { /* =>      */ { FP64_0(0),   FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V0(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_INF(0), FP64_RAND_V3(1), FP64_RAND_V3(1), FP64_RAND_V0(1) } },
@@ -11238,66 +11238,66 @@
             { /*src1     */ { FP64_INF(0), FP64_RAND_V0(1), FP64_RAND_V0(1), FP64_RAND_V3(1) } },
             { /* =>      */ { FP64_INF(0), FP64_RAND_V0(1), FP64_RAND_V0(1), FP64_RAND_V3(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_INF(1), FP64_RAND_V3(0),   FP64_RAND_V2(1), FP64_RAND_V3(0) } },
             { /*src1     */ { FP64_INF(1), FP64_QNAN_V(1, 1), FP64_RAND_V1(1), FP64_RAND_V2(0) } },
             { /* =>      */ { FP64_INF(1), FP64_QNAN_V(1, 1), FP64_RAND_V1(1), FP64_RAND_V2(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_INF(1), FP64_RAND_V2(1), FP64_RAND_V1(1), FP64_RAND_V0(1) } },
             { /*src1     */ { FP64_INF(1), FP64_RAND_V0(0), FP64_RAND_V3(1), FP64_RAND_V0(1) } },
             { /* =>      */ { FP64_INF(1), FP64_RAND_V0(0), FP64_RAND_V3(1), FP64_RAND_V0(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_INF(1), FP64_RAND_V1(1), FP64_RAND_V3(1), FP64_RAND_V0(1) } },
             { /*src1     */ { FP64_INF(0), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V1(1) } },
             { /* =>      */ { FP64_INF(0), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V1(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
+              /*mxcsr:in */ X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_RC_UP,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_INF(1), FP64_RAND_V0(1), FP64_RAND_V2(1), FP64_RAND_V0(1) } },
             { /*src1     */ { FP64_INF(0), FP64_RAND_V0(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },
             { /* =>      */ { FP64_INF(0), FP64_RAND_V0(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_INF(0), FP64_RAND_V2(1), FP64_RAND_V3(1), FP64_RAND_V0(1) } },
             { /*src1     */ { FP64_INF(1), FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V1(1) } },
             { /* =>      */ { FP64_INF(0), FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V1(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_INF(0), FP64_RAND_V0(1), FP64_RAND_V2(1), FP64_RAND_V0(1) } },
             { /*src1     */ { FP64_INF(1), FP64_RAND_V0(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },
             { /* =>      */ { FP64_INF(0), FP64_RAND_V0(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
+              /*mxcsr:in */ X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_FZ,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_INF(0),     FP64_RAND_V0(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } },
             { /*src1     */ { FP64_NORM_V0(0), FP64_RAND_V1(1), FP64_RAND_V3(1), FP64_RAND_V1(1) } },
             { /* =>      */ { FP64_INF(0),     FP64_RAND_V1(1), FP64_RAND_V3(1), FP64_RAND_V1(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_INF(0),     FP64_INF(0), FP64_SNAN(1), FP64_INF(1)  } },
             { /*src1     */ { FP64_NORM_V3(0), FP64_INF(1), FP64_QNAN(1), FP64_SNAN(1) } },
             { /* =>      */ { FP64_INF(0),     FP64_INF(1), FP64_QNAN(1), FP64_SNAN(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_NORM_V2(0), FP64_RAND_V3(1), FP64_QNAN(1),    FP64_SNAN(1)    } },
             { /*src1     */ { FP64_INF(1),     FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V1(1) } },
             { /* =>      */ { FP64_NORM_V2(0), FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V1(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_NORM_V2(0), FP64_SNAN(0), FP64_RAND_V2(0), FP64_RAND_V3(0) } },
             { /*src1     */ { FP64_INF(0),     FP64_RAND_V2(0),   FP64_RAND_V1(0), FP64_RAND_V2(1) } },
             { /* =>      */ { FP64_INF(0),     FP64_RAND_V2(0),   FP64_RAND_V1(0), FP64_RAND_V2(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
     /*
@@ -11307,114 +11307,114 @@
             { /*src1     */ { FP64_NORM_MAX(0), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V2(1) } },
             { /* =>      */ { FP64_NORM_MAX(0), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V2(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_NORM_MIN(0), FP64_RAND_V3(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } },
             { /*src1     */ { FP64_NORM_MIN(0), FP64_RAND_V2(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } },
             { /* =>      */ { FP64_NORM_MIN(0), FP64_RAND_V2(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_NORM_MIN(0), FP64_RAND_V3(1), FP64_RAND_V0(1), FP64_RAND_V3(0) } },
             { /*src1     */ { FP64_NORM_MAX(0), FP64_RAND_V1(0), FP64_RAND_V3(0), FP64_RAND_V1(0) } },
             { /* =>      */ { FP64_NORM_MAX(0), FP64_RAND_V1(0), FP64_RAND_V3(0), FP64_RAND_V1(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_NORM_MAX(0), FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V3(0) } },
             { /*src1     */ { FP64_NORM_MAX(0), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V1(1) } },
             { /* =>      */ { FP64_NORM_MAX(0), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V1(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_NORM_SAFE_INT_MIN(0), FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V3(0) } },
             { /*src1     */ { FP64_NORM_SAFE_INT_MAX(0), FP64_RAND_V1(0), FP64_RAND_V1(0), FP64_RAND_V3(1) } },
             { /* =>      */ { FP64_NORM_SAFE_INT_MAX(0), FP64_RAND_V1(0), FP64_RAND_V1(0), FP64_RAND_V3(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_NORM_SAFE_INT_MAX(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },
             { /*src1     */ { FP64_NORM_SAFE_INT_MAX(0), FP64_RAND_V1(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } },
             { /* =>      */ { FP64_NORM_SAFE_INT_MAX(0), FP64_RAND_V1(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_NORM_SAFE_INT_MAX(0), FP64_INF(0),     FP64_QNAN(1),    FP64_QNAN(0)    } },
             { /*src1     */ { FP64_NORM_SAFE_INT_MIN(0), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } },
             { /* =>      */ { FP64_NORM_SAFE_INT_MAX(0), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_V(0, 0, 0x409)/*1024*/,  FP64_RAND_V1(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } },
             { /*src1     */ { FP64_V(0, 0, 0x408)/* 512*/,  FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V3(1) } },
             { /* =>      */ { FP64_V(0, 0, 0x409)/*1024*/,  FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V3(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/,  FP64_RAND_V2(1), FP64_RAND_V2(0), FP64_RAND_V3(1) } },
             { /*src1     */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/,  FP64_RAND_V0(0), FP64_RAND_V2(0), FP64_RAND_V0(0) } },
             { /* =>      */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/,  FP64_RAND_V0(0), FP64_RAND_V2(0), FP64_RAND_V0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_NORM_MAX(0), FP64_RAND_V0(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } },
             { /*src1     */ { FP64_NORM_V1(0),  FP64_RAND_V0(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } },
             { /* =>      */ { FP64_NORM_MAX(0), FP64_RAND_V0(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
+              /*mxcsr:in */ X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_RC_DOWN,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_V(0, 0xc000000000000, 0x3ff)/*1.75*/, FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V3(0) } },
             { /*src1     */ { FP64_V(0, 0,               0x3fd)/*0.25*/, FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V1(0) } },
             { /* =>      */ { FP64_V(0, 0xc000000000000, 0x3ff)/*1.75*/, FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V1(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_V(1, 0, 0x3fd)/*-0.25*/, FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V3(0) } },
             { /*src1     */ { FP64_V(1, 0, 0x3fe)/*-0.50*/, FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V1(1) } },
             { /* =>      */ { FP64_V(1, 0, 0x3fd)/*-0.25*/, FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V1(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_V(0, 0x26580b4c7e6b7, 0x41d)/*1234567891.1234567*/, FP64_RAND_V2(1), FP64_RAND_V3(1), FP64_RAND_V3(1) } },
             { /*src1     */ { FP64_V(0, 0x26580b4c7e6bc, 0x41d)/*1234567891.1234580*/, FP64_RAND_V3(0), FP64_RAND_V1(0), FP64_RAND_V0(1) } },
             { /* =>      */ { FP64_V(0, 0x26580b4c7e6bc, 0x41d)/*1234567891.1234580*/, FP64_RAND_V3(0), FP64_RAND_V1(0), FP64_RAND_V0(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_V(0, 0xf9b0207d06184, 0x3fb)/*0.1234589833333129*/, FP64_RAND_V3(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } },
             { /*src1     */ { FP64_V(0, 0xf9b0207d0617d, 0x3fb)/*0.1234589833333128*/, FP64_RAND_V1(1), FP64_RAND_V0(0), FP64_RAND_V0(1) } },
             { /* =>      */ { FP64_V(0, 0xf9b0207d06184, 0x3fb)/*0.1234589833333129*/, FP64_RAND_V1(1), FP64_RAND_V0(0), FP64_RAND_V0(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/* 121098765432102.75*/,  FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } },
             { /*src1     */ { FP64_V(1, 0xbcd80e0108cc0, 0x42e)/*-244555555308646.00*/,  FP64_RAND_V3(0), FP64_RAND_V3(1), FP64_RAND_V0(1) } },
             { /* =>      */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/* 121098765432102.75*/,  FP64_RAND_V3(0), FP64_RAND_V3(1), FP64_RAND_V0(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_V(0, 0xcf0033a34f337, 0x432)/*4072598000007579.5*/, FP64_RAND_V3(1), FP64_RAND_V2(1), FP64_RAND_V1(1) } },
             { /*src1     */ { FP64_V(0, 0xd6eca42000000, 0x419)/*       123450000.5*/, FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },
             { /* =>      */ { FP64_V(0, 0xcf0033a34f337, 0x432)/*4072598000007579.5*/, FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_V(1, 0xbcd80e0108cc0, 0x42e)/*-244555555308646.00*/, FP64_INF(1), FP64_SNAN(1), FP64_INF(1)  } },
             { /*src1     */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/* 121098765432102.75*/, FP64_INF(1), FP64_QNAN(0), FP64_SNAN(0) } },
             { /* =>      */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/* 121098765432102.75*/, FP64_INF(1), FP64_QNAN(0), FP64_SNAN(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/* 244555555308646.00*/, FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(0) } },
             { /*src1     */ { FP64_V(1, 0xb88e0395d49b0, 0x42d)/*-121098765432102.75*/, FP64_RAND_V0(0), FP64_RAND_V0(0), FP64_RAND_V2(1) } },
             { /* =>      */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/* 244555555308646.00*/, FP64_RAND_V0(0), FP64_RAND_V0(0), FP64_RAND_V2(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_V(1, 0xcf0033a34f337, 0x432)/*-4072598000007579.5*/, FP64_RAND_V1(0), FP64_RAND_V2(0), FP64_RAND_V1(0) } },
             { /*src1     */ { FP64_V(0, 0xd6eca42000000, 0x419)/*        123450000.5*/, FP64_RAND_V2(0), FP64_RAND_V2(1), FP64_RAND_V3(0) } },
             { /* =>      */ { FP64_V(0, 0xd6eca42000000, 0x419)/*        123450000.5*/, FP64_RAND_V2(0), FP64_RAND_V2(1), FP64_RAND_V3(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
+              /*mxcsr:in */ X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_RC_UP,
               /*256:out  */ -1 },
     /** @todo More Normals. */
@@ -11431,54 +11431,54 @@
             { /*src1     */ { FP64_DENORM_MAX(0), FP64_RAND_V2(0), FP64_RAND_V3(1), FP64_RAND_V2(0) } },
             { /* =>      */ { FP64_DENORM_MAX(0), FP64_RAND_V2(0), FP64_RAND_V3(1), FP64_RAND_V2(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_DE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_DENORM_MIN(0), FP64_INF(1), FP64_SNAN(0), FP64_INF(1)  } },
             { /*src1     */ { FP64_DENORM_MAX(0), FP64_INF(0), FP64_QNAN(1), FP64_SNAN(1) } },
             { /* =>      */ { FP64_0(0),          FP64_INF(0), FP64_QNAN(1), FP64_SNAN(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_DENORM_MAX(0), FP64_RAND_V2(1), FP64_RAND_V0(1), FP64_RAND_V3(0) } },
             { /*src1     */ { FP64_DENORM_MAX(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },
             { /* =>      */ { FP64_DENORM_MAX(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_DE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_DENORM_MAX(0), FP64_RAND_V1(1), FP64_RAND_V2(1), FP64_RAND_V2(0) } },
             { /*src1     */ { FP64_DENORM_MAX(1), FP64_RAND_V0(0), FP64_RAND_V3(0), FP64_RAND_V0(0) } },
             { /* =>      */ { FP64_DENORM_MAX(0), FP64_RAND_V0(0), FP64_RAND_V3(0), FP64_RAND_V0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_DE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_DENORM_MAX(1), FP64_RAND_V3(1), FP64_RAND_V0(0), FP64_RAND_V3(1) } },
             { /*src1     */ { FP64_DENORM_MAX(0), FP64_RAND_V2(1), FP64_RAND_V3(1), FP64_RAND_V2(1) } },
             { /* =>      */ { FP64_DENORM_MAX(0), FP64_RAND_V2(1), FP64_RAND_V3(1), FP64_RAND_V2(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_DE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_DENORM_MIN(1), FP64_RAND_V0(1), FP64_RAND_V3(1), FP64_RAND_V2(1) } },
             { /*src1     */ { FP64_DENORM_MIN(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
             { /* =>      */ { FP64_DENORM_MIN(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_DE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_DENORM_MIN(1), FP64_INF(0),     FP64_QNAN(1),    FP64_SNAN(1) } },
             { /*src1     */ { FP64_DENORM_MIN(1), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V0(1)   } },
             { /* =>      */ { FP64_DENORM_MIN(1), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V0(1)   } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_DE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_DENORM_MIN(1), FP64_SNAN(1),    FP64_SNAN(0),    FP64_QNAN(0)    } },
             { /*src1     */ { FP64_DENORM_MIN(1), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } },
             { /* =>      */ { FP64_0(1),          FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
+              /*mxcsr:in */ X86_MXCSR_DAZ,
+              /*128:out  */ X86_MXCSR_DAZ,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_DENORM_MIN(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
             { /*src1     */ { FP64_0(0),          FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(0) } },
             { /* =>      */ { FP64_DENORM_MIN(0), FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_DE,
               /*256:out  */ -1 },
     /** @todo More Denormals. */
@@ -11542,25 +11542,25 @@
             { /*src1     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
             { /* =>      */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
             { /*src1     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
             { /* =>      */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_RC_ZERO },
           { { /*src2     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
             { /*src1     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
             { /* =>      */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
           { { /*src2     */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1) } },
             { /*src1     */ { FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0) } },
             { /* =>      */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0) } },
             { /*src1     */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0) } },
@@ -11572,25 +11572,25 @@
             { /*src1     */ { FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0) } },
             { /* =>      */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_RC_DOWN },
           { { /*src2     */ { FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0) } },
             { /*src1     */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0) } },
             { /* =>      */ { FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP },
+              /*mxcsr:in */ X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_RC_UP },
           { { /*src2     */ { FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0) } },
             { /*src1     */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0) } },
             { /* =>      */ { FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
           { { /*src2     */ { FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1) } },
             { /*src1     */ { FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(0) } },
             { /* =>      */ { FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
     /*
      * Infinity.
@@ -11599,31 +11599,31 @@
             { /*src1     */ { FP32_0(0),   FP32_INF(0), FP32_0(0),   FP32_INF(0), FP32_0(0),   FP32_INF(1), FP32_0(0),   FP32_INF(1) } },
             { /* =>      */ { FP32_0(0),   FP32_0(0),   FP32_INF(1), FP32_0(1),   FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP32_INF(0), FP32_0(0),   FP32_INF(0), FP32_0(1),   FP32_INF(1), FP32_0(0),   FP32_INF(1), FP32_0(0)   } },
             { /*src1     */ { FP32_0(0),   FP32_INF(1), FP32_0(1),   FP32_INF(1), FP32_0(0),   FP32_INF(1), FP32_0(0),   FP32_INF(1) } },
             { /* =>      */ { FP32_0(0),   FP32_INF(1), FP32_0(1),   FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP },
+              /*mxcsr:in */ X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_RC_UP },
           { { /*src2     */ { FP32_INF(0), FP32_0(0),   FP32_INF(0), FP32_0(1),   FP32_INF(1), FP32_0(0),   FP32_INF(1), FP32_0(0)   } },
             { /*src1     */ { FP32_0(0),   FP32_INF(0), FP32_0(1),   FP32_INF(0), FP32_0(0),   FP32_INF(1), FP32_0(0),   FP32_INF(1) } },
             { /* =>      */ { FP32_0(0),   FP32_0(0),   FP32_0(1),   FP32_0(1),   FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_RC_DOWN },
           { { /*src2     */ { FP32_INF(0), FP32_0(0),   FP32_INF(0), FP32_0(1),   FP32_INF(1), FP32_0(0),   FP32_INF(1), FP32_0(0)   } },
             { /*src1     */ { FP32_0(0),   FP32_INF(0), FP32_0(1),   FP32_INF(0), FP32_0(0),   FP32_INF(1), FP32_0(0),   FP32_INF(1) } },
             { /* =>      */ { FP32_0(0),   FP32_0(0),   FP32_0(1),   FP32_0(1),   FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_RC_ZERO },
           { { /*src2     */ { FP32_INF(0), FP32_0(0),   FP32_INF(0), FP32_0(1),   FP32_INF(1), FP32_0(0),   FP32_INF(1), FP32_0(0)   } },
             { /*src1     */ { FP32_0(0),   FP32_INF(0), FP32_0(1),   FP32_INF(0), FP32_0(0),   FP32_INF(1), FP32_0(0),   FP32_INF(1) } },
             { /* =>      */ { FP32_0(0),   FP32_0(0),   FP32_0(1),   FP32_0(1),   FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
           { { /*src2     */ { FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(0) } },
             { /*src1     */ { FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_INF(0) } },
@@ -11635,31 +11635,31 @@
             { /*src1     */ { FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_INF(0) } },
             { /* =>      */ { FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_RC_ZERO },
           { { /*src2     */ { FP32_INF(0),     FP32_NORM_V1(0), FP32_INF(1),     FP32_NORM_V3(1), FP32_INF(1),     FP32_NORM_V5(0), FP32_INF(1),     FP32_NORM_V7(0) } },
             { /*src1     */ { FP32_NORM_V0(0), FP32_INF(1),     FP32_NORM_V2(0), FP32_INF(1),     FP32_NORM_V4(1), FP32_INF(1),     FP32_NORM_V6(0), FP32_INF(0)     } },
             { /* =>      */ { FP32_NORM_V0(0), FP32_INF(1),     FP32_INF(1),     FP32_INF(1),     FP32_INF(1),     FP32_INF(1),     FP32_INF(1),     FP32_NORM_V7(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP32_INF(0),     FP32_NORM_V1(0), FP32_INF(1),     FP32_NORM_V3(1), FP32_INF(0),     FP32_NORM_V5(0), FP32_INF(1),     FP32_NORM_V7(0) } },
             { /*src1     */ { FP32_NORM_V0(0), FP32_INF(1),     FP32_NORM_V2(0), FP32_INF(0),     FP32_NORM_V4(1), FP32_INF(1),     FP32_NORM_V6(0), FP32_INF(0)     } },
             { /* =>      */ { FP32_NORM_V0(0), FP32_INF(1),     FP32_INF(1),     FP32_NORM_V3(1), FP32_NORM_V4(1), FP32_INF(1),     FP32_INF(1),     FP32_NORM_V7(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
           { { /*src2     */ { FP32_NORM_V7(0), FP32_INF(0),     FP32_NORM_V5(0), FP32_INF(0),     FP32_NORM_V3(0), FP32_INF(0),     FP32_NORM_V1(0), FP32_INF(0)     } },
             { /*src1     */ { FP32_INF(1),     FP32_NORM_V6(1), FP32_INF(0),     FP32_NORM_V4(0), FP32_INF(0),     FP32_NORM_V2(1), FP32_INF(1),     FP32_NORM_V0(1) } },
             { /* =>      */ { FP32_INF(1),     FP32_NORM_V6(1), FP32_NORM_V5(0), FP32_NORM_V4(0), FP32_NORM_V3(0), FP32_NORM_V2(1), FP32_INF(1),     FP32_NORM_V0(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP },
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP },
           { { /*src2     */ { FP32_NORM_V7(0), FP32_INF(0),     FP32_NORM_V5(1), FP32_INF(0),     FP32_NORM_V3(1), FP32_INF(0),     FP32_NORM_V1(1), FP32_INF(0)     } },
             { /*src1     */ { FP32_INF(0),     FP32_NORM_V6(1), FP32_INF(0),     FP32_NORM_V4(1), FP32_INF(0),     FP32_NORM_V2(1), FP32_INF(0),     FP32_NORM_V0(1) } },
             { /* =>      */ { FP32_NORM_V7(0), FP32_NORM_V6(1), FP32_NORM_V5(1), FP32_NORM_V4(1), FP32_NORM_V3(1), FP32_NORM_V2(1), FP32_NORM_V1(1), FP32_NORM_V0(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_RC_ZERO },
     /*
      * Normals.
@@ -11668,55 +11668,55 @@
             { /*src1     */ { FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_0(0),        FP32_0(0),        FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_0(1),        FP32_NORM_MAX(0) } },
             { /* =>      */ { FP32_NORM_MAX(0), FP32_0(0),        FP32_0(0),        FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP32_NORM_MIN(0), FP32_0(0),        FP32_NORM_MIN(0), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_0(1),        FP32_NORM_MIN(1), FP32_NORM_MIN(1) } },
             { /*src1     */ { FP32_NORM_MIN(0), FP32_NORM_MIN(0), FP32_0(0),        FP32_0(0),        FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_0(1),        FP32_NORM_MIN(0) } },
             { /* =>      */ { FP32_NORM_MIN(0), FP32_0(0),        FP32_0(0),        FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MIN(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP32_NORM_MIN(0), FP32_NORM_MIN(0), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1) } },
             { /*src1     */ { FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MIN(0), FP32_NORM_MIN(1), FP32_NORM_MIN(0), FP32_NORM_MIN(1) } },
             { /* =>      */ { FP32_NORM_MIN(0), FP32_NORM_MAX(1), FP32_NORM_MIN(1), FP32_NORM_MAX(1), FP32_NORM_MIN(0), FP32_NORM_MIN(1), FP32_NORM_MAX(1), FP32_NORM_MAX(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(1) } },
             { /*src1     */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1) } },
             { /* =>      */ { FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_V(0, 0, 0x7d)/*0.25*/, FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_V(0, 0, 0x7d)/*0.25*/, FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_V(0, 0, 0x7d)/* 0.25*/, FP32_V(0, 0x600000, 0x7f)/*1.75*/, FP32_V(1, 0, 0x7d)/*-0.25*/ } },
             { /*src1     */ { FP32_V(1, 0,        0x7d)/*-0.25*/, FP32_V(0, 0, 0x7e)/*0.50*/, FP32_V(1, 0,        0x7d)/*-0.25*/, FP32_V(0, 0, 0x7e)/*0.50*/, FP32_V(1, 0x600000, 0x7f)/*-1.75*/, FP32_V(1, 0, 0x7e)/*-0.50*/, FP32_V(1, 0,        0x7d)/*0.25*/, FP32_V(1, 0, 0x7e)/*-0.50*/ } },
             { /* =>      */ { FP32_V(1, 0,        0x7d)/*-0.25*/, FP32_V(0, 0, 0x7d)/*0.25*/, FP32_V(1, 0,        0x7d)/*-0.25*/, FP32_V(0, 0, 0x7d)/*0.25*/, FP32_V(1, 0x600000, 0x7f)/*-1.75*/, FP32_V(1, 0, 0x7e)/*-0.50*/, FP32_V(1, 0,        0x7d)/*0.25*/, FP32_V(1, 0, 0x7e)/*-0.50*/ } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
           { { /*src2     */ { FP32_NORM_MAX(0), FP32_NORM_V1(0), FP32_NORM_V2(1), FP32_NORM_V3(1), FP32_NORM_V5(0), FP32_0(1),       FP32_NORM_V5(1), FP32_0(0)       } },
             { /*src1     */ { FP32_NORM_V1(0),  FP32_NORM_V1(1), FP32_NORM_V2(0), FP32_NORM_V3(1), FP32_0(1),       FP32_NORM_V6(0), FP32_0(1),       FP32_NORM_V7(1) } },
             { /* =>      */ { FP32_NORM_V1(0),  FP32_NORM_V1(1), FP32_NORM_V2(1), FP32_NORM_V3(1), FP32_0(1),       FP32_0(1),       FP32_NORM_V5(1), FP32_NORM_V7(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_RC_DOWN },
           { { /*src2     */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_V(0, 0x600000, 0x81)/* 7*/, FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_V(0, 0x5c0000, 0x84)/* 55*/, FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_V(1, 0x534000, 0x86)/*-211.25*/, FP32_V(0, 0x74429f, 0x97)/*32015678*/, FP32_1(1) } },
             { /*src1     */ { FP32_V(0, 0x1ea980, 0x8f)/*  81235*/, FP32_V(0, 0x5c0000, 0x84)/*55*/, FP32_V(0, 0x7c9000, 0x88)/*   1010.25*/, FP32_V(1, 0x600000, 0x81)/* -7*/, FP32_V(0, 0x253468, 0x93)/*1353357.00*/, FP32_1(1),                            FP32_V(0, 0x712060, 0x92)/*  987654*/, FP32_1(0) } },
             { /* =>      */ { FP32_V(0, 0x1ea980, 0x8f)/*  81235*/, FP32_V(0, 0x600000, 0x81)/* 7*/, FP32_V(0, 0x7c9000, 0x88)/*   1010.25*/, FP32_V(1, 0x600000, 0x81)/* -7*/, FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_V(1, 0x534000, 0x86)/*-211.25*/, FP32_V(0, 0x712060, 0x92)/*  987654*/, FP32_1(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_RC_ZERO },
           { { /*src2     */ { FP32_V(0, 0x600000, 0x7e)/*      0.875*/, FP32_V(0, 0x3ce348, 0x90)/*193421.125*/, FP32_V(0, 0x6423f2, 0x92)/*934463.125*/, FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0x16b43a, 0x93)/*1234567.25*/, FP32_V(0, 0x792318, 0x91)/*510232.75*/, FP32_V(0, 0x600000, 0x7e)/* 0.875*/ } },
             { /*src1     */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_V(0, 0x430ebc, 0x91)/*399477.875*/, FP32_V(0, 0x52e0b4, 0x92)/*863755.250*/, FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MAX(1), FP32_V(0, 0x00c6d3, 0x94)/*2109876.75*/, FP32_V(1, 0x316740, 0x8e)/*-45415.25*/, FP32_V(1, 0,        0x7d)/*-0.250*/ } },
             { /* =>      */ { FP32_V(0, 0x600000, 0x7e)/*      0.875*/, FP32_V(0, 0x3ce348, 0x90)/*193421.125*/, FP32_V(0, 0x52e0b4, 0x92)/*863755.250*/, FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MAX(1), FP32_V(0, 0x16b43a, 0x93)/*1234567.25*/, FP32_V(1, 0x316740, 0x8e)/*-45415.25*/, FP32_V(1, 0,        0x7d)/*-0.250*/ } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_RC_DOWN },
           { { /*src2     */ { FP32_V(0, 0x490fda, 0x80)/*3.1415926*/, FP32_V(0, 0x620b2e, 0x92)/*925874.9*/, FP32_V(0, 0x5dd520, 0x8e)/* 56789.125*/, FP32_V(1, 0x40e6b6, 0x8c)/*-12345.678*/, FP32_V(1, 0x490fda, 0x80)/*-3.1415926*/, FP32_V(1, 0x620b2e, 0x92)/*-925874.8*/, FP32_V(0, 0x5dd520, 0x8e)/*56789.125*/, FP32_V(0, 0x40e6b6, 0x8c)/*12345.678*/ } },
             { /*src1     */ { FP32_V(0, 0x490fdb, 0x80)/*3.1415927*/, FP32_V(0, 0x620b2d, 0x92)/*925874.8*/, FP32_V(1, 0x5dd521, 0x8e)/*-56789.127*/, FP32_V(1, 0x40e6b7, 0x8c)/*-12345.679*/, FP32_V(1, 0x490fdb, 0x80)/*-3.1415927*/, FP32_V(0, 0x620b2d, 0x92)/* 925874.9*/, FP32_V(0, 0x5dd521, 0x8e)/*56789.127*/, FP32_V(0, 0x40e6b7, 0x8c)/*12345.679*/ } },
             { /* =>      */ { FP32_V(0, 0x490fda, 0x80)/*3.1415926*/, FP32_V(0, 0x620b2d, 0x92)/*925874.8*/, FP32_V(1, 0x5dd521, 0x8e)/*-56789.127*/, FP32_V(1, 0x40e6b7, 0x8c)/*-12345.679*/, FP32_V(1, 0x490fdb, 0x80)/*-3.1415927*/, FP32_V(1, 0x620b2e, 0x92)/*-925874.8*/, FP32_V(0, 0x5dd520, 0x8e)/*56789.125*/, FP32_V(0, 0x40e6b6, 0x8c)/*12345.678*/ } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
     /** @todo More Normals. */
     /*
@@ -11732,13 +11732,13 @@
             { /*src1     */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0) } },
             { /* =>      */ { FP32_0(0), FP32_0(0),          FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0),          FP32_0(0), FP32_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE },
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_DE,
+              /*256:out  */ X86_MXCSR_DE },
           { { /*src2     */ { FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } },
             { /*src1     */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0) } },
             { /* =>      */ { FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0)          } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP },
           { { /*src2     */ { FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0),          FP32_0(0), FP32_0(0), FP32_0(0) } },
             { /*src1     */ { FP32_0(0),         FP32_0(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0) } },
@@ -11750,13 +11750,13 @@
             { /*src1     */ { FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(0), FP32_0(0)          } },
             { /* =>      */ { FP32_0(0), FP32_0(0),          FP32_0(0), FP32_0(0), FP32_0(0),          FP32_0(0), FP32_0(0), FP32_0(1)          } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ },
+              /*mxcsr:in */ X86_MXCSR_DAZ,
+              /*128:out  */ X86_MXCSR_DAZ,
+              /*256:out  */ X86_MXCSR_DAZ },
           { { /*src2     */ { FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } },
             { /*src1     */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0) } },
             { /* =>      */ { FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0),          FP32_0(0)          } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP },
     /** @todo More Denormals. */
     /*35*/ FP32_TABLE_D9_PS_INVALIDS
@@ -11827,25 +11827,25 @@
             { /*src1     */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
             { /* =>      */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
             { /*src1     */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
             { /* =>      */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_RC_ZERO },
           { { /*src2     */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
             { /*src1     */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
             { /* =>      */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
           { { /*src2     */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } },
             { /*src1     */ { FP64_0(1), FP64_0(0), FP64_0(1), FP64_0(1) } },
             { /* =>      */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_0(0) } },
             { /*src1     */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } },
@@ -11857,25 +11857,25 @@
             { /*src1     */ { FP64_0(1), FP64_0(0), FP64_0(1), FP64_0(1) } },
             { /* =>      */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_RC_DOWN },
           { { /*src2     */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_0(0) } },
             { /*src1     */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } },
             { /* =>      */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP },
+              /*mxcsr:in */ X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_RC_UP },
           { { /*src2     */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_0(0) } },
             { /*src1     */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } },
             { /* =>      */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
           { { /*src2     */ { FP64_0(1), FP64_0(1), FP64_0(0), FP64_0(0) } },
             { /*src1     */ { FP64_0(1), FP64_0(1), FP64_0(0), FP64_0(0) } },
             { /* =>      */ { FP64_0(1), FP64_0(1), FP64_0(0), FP64_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
     /*
      * Infinity.
@@ -11884,31 +11884,31 @@
             { /*src1     */ { FP64_0(0),   FP64_INF(0), FP64_0(1),   FP64_INF(1) } },
             { /* =>      */ { FP64_0(0),   FP64_0(0),   FP64_0(1),   FP64_INF(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP64_INF(0), FP64_0(0),   FP64_INF(0), FP64_0(1)   } },
             { /*src1     */ { FP64_0(0),   FP64_INF(1), FP64_0(1),   FP64_INF(1) } },
             { /* =>      */ { FP64_0(0),   FP64_INF(1), FP64_0(1),   FP64_INF(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP },
+              /*mxcsr:in */ X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_RC_UP },
           { { /*src2     */ { FP64_INF(0), FP64_0(0),   FP64_INF(0), FP64_0(1)   } },
             { /*src1     */ { FP64_0(0),   FP64_INF(1), FP64_0(1),   FP64_INF(1) } },
             { /* =>      */ { FP64_0(0),   FP64_INF(1), FP64_0(1),   FP64_INF(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_RC_DOWN },
           { { /*src2     */ { FP64_INF(0), FP64_0(0),   FP64_INF(0), FP64_0(1)   } },
             { /*src1     */ { FP64_0(0),   FP64_INF(1), FP64_0(1),   FP64_INF(1) } },
             { /* =>      */ { FP64_0(0),   FP64_INF(1), FP64_0(1),   FP64_INF(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_RC_ZERO },
           { { /*src2     */ { FP64_INF(0), FP64_0(0),   FP64_INF(0), FP64_0(1)   } },
             { /*src1     */ { FP64_0(0),   FP64_INF(0), FP64_0(1),   FP64_INF(1) } },
             { /* =>      */ { FP64_0(0),   FP64_0(0),   FP64_0(1),   FP64_INF(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
           { { /*src2     */ { FP64_INF(0), FP64_INF(0), FP64_INF(1), FP64_INF(1) } },
             { /*src1     */ { FP64_INF(0), FP64_INF(1), FP64_INF(0), FP64_INF(1) } },
@@ -11920,31 +11920,31 @@
             { /*src1     */ { FP64_INF(0), FP64_INF(1), FP64_INF(0), FP64_INF(1) } },
             { /* =>      */ { FP64_INF(0), FP64_INF(1), FP64_INF(1), FP64_INF(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_RC_ZERO },
           { { /*src2     */ { FP64_INF(0),     FP64_NORM_V1(0), FP64_INF(1),     FP64_NORM_V3(1) } },
             { /*src1     */ { FP64_NORM_V0(0), FP64_INF(1),     FP64_NORM_V2(0), FP64_INF(1)     } },
             { /* =>      */ { FP64_NORM_V0(0), FP64_INF(1),     FP64_INF(1),     FP64_INF(1)     } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP64_INF(0),     FP64_NORM_V1(0), FP64_INF(1),     FP64_NORM_V3(1) } },
             { /*src1     */ { FP64_NORM_V0(0), FP64_INF(1),     FP64_NORM_V2(0), FP64_INF(1)     } },
             { /* =>      */ { FP64_NORM_V0(0), FP64_INF(1),     FP64_INF(1),     FP64_INF(1)     } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
           { { /*src2     */ { FP64_INF(0),     FP64_NORM_V1(0), FP64_INF(1),     FP64_NORM_V3(1) } },
             { /*src1     */ { FP64_NORM_V0(0), FP64_INF(1),     FP64_NORM_V2(0), FP64_INF(1)     } },
             { /* =>      */ { FP64_NORM_V0(0), FP64_INF(1),     FP64_INF(1),     FP64_INF(1)     } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP },
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP },
           { { /*src2     */ { FP64_INF(0),     FP64_NORM_V1(0), FP64_INF(1),     FP64_NORM_V3(1) } },
             { /*src1     */ { FP64_NORM_V0(0), FP64_INF(1),     FP64_NORM_V2(0), FP64_INF(1)     } },
             { /* =>      */ { FP64_NORM_V0(0), FP64_INF(1),     FP64_INF(1),     FP64_INF(1)     } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_RC_ZERO },
     /*
      * Normals.
@@ -11953,25 +11953,25 @@
             { /*src1     */ { FP64_NORM_V3(1), FP64_NORM_V1(0), FP64_NORM_V2(1), FP64_NORM_V1(0) } },
             { /* =>      */ { FP64_NORM_V3(1), FP64_NORM_V1(1), FP64_NORM_V2(1), FP64_NORM_V1(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src2     */ { FP64_NORM_V0(0), FP64_0(1),       FP64_NORM_V2(0), FP64_0(1)       } },
             { /*src1     */ { FP64_0(0),       FP64_NORM_V1(1), FP64_0(0),       FP64_NORM_V1(0) } },
             { /* =>      */ { FP64_0(0),       FP64_NORM_V1(1), FP64_0(0),       FP64_0(1)       } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_RC_ZERO },
           { { /*src2     */ { FP64_V(0, 0, 0x409)/*1024*/, FP64_V(0, 0xb800000000000, 0x404)/*55*/, FP64_V(1, 0x8000000000000, 0x409)/*-1536*/, FP64_V(0, 0xf000000000000, 0x404)/* 62*/ } },
             { /*src1     */ { FP64_V(0, 0, 0x408)/* 512*/, FP64_V(0, 0xc000000000000, 0x401)/* 7*/, FP64_1(1),                                  FP64_V(1, 0xf000000000000, 0x404)/*-62*/ } },
             { /* =>      */ { FP64_V(0, 0, 0x408)/* 512*/, FP64_V(0, 0xc000000000000, 0x401)/* 7*/, FP64_V(1, 0x8000000000000, 0x409)/*-1536*/, FP64_V(1, 0xf000000000000, 0x404)/*-62*/ } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ },
+              /*mxcsr:in */ X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_FZ,
+              /*256:out  */ X86_MXCSR_FZ },
           { { /*src2     */ { FP64_V(0, 0x26580b4800000, 0x41d)/* 1234567890*/, FP64_V(0, 0xd6f3458800000, 0x41c)/*987654321*/, FP64_V(1, 0xd6f3426800000, 0x41c)/*-987654221*/, FP64_V(0, 0xcf0033a34f337, 0x432)/*4072598000007579.5*/ } },
             { /*src1     */ { FP64_V(1, 0x26580b4800000, 0x41d)/*-1234567890*/, FP64_V(0, 0x9000000000000, 0x405)/*      100*/, FP64_1(0),                                       FP64_V(0, 0xd6eca42000000, 0x419)/*       123450000.5*/ } },
             { /* =>      */ { FP64_V(1, 0x26580b4800000, 0x41d)/*-1234567890*/, FP64_V(0, 0x9000000000000, 0x405)/*      100*/, FP64_V(1, 0xd6f3426800000, 0x41c)/*-987654221*/, FP64_V(0, 0xd6eca42000000, 0x419)/*       123450000.5*/ } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ },
+              /*mxcsr:in */ X86_MXCSR_DAZ,
+              /*128:out  */ X86_MXCSR_DAZ,
+              /*256:out  */ X86_MXCSR_DAZ },
           { { /*src2     */ { FP64_V(0, 0x26580b4800000, 0x41d)/* 1234567890*/, FP64_V(0, 0xd6f3458800000, 0x41c)/*987654321*/, FP64_V(0, 0xd6f3426800000, 0x41c)/*987654221*/, FP64_V(0, 0xcf0033a34f337, 0x432)/*4072598000007579.5*/ } },
             { /*src1     */ { FP64_V(1, 0x26580b4800000, 0x41d)/*-1234567890*/, FP64_V(0, 0x9000000000000, 0x405)/*     -100*/, FP64_1(0),                                      FP64_V(0, 0xd6eca42000000, 0x419)/*       123450000.5*/ } },
@@ -11983,7 +11983,7 @@
             { /*src1     */ { FP64_1(0),                 FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(0), FP64_0(0)                 } },
             { /* =>      */ { FP64_1(0),                 FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(0), FP64_0(0)                 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO },
           { { /*src2     */ { FP64_NORM_SAFE_INT_MIN(0), FP64_0(0),                 FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(1) } },
             { /*src1     */ { FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(1), FP64_0(0),                 FP64_NORM_SAFE_INT_MIN(0) } },
@@ -11995,13 +11995,13 @@
             { /*src1     */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_V(0, 0xb88e0395d49b0, 0x42d)/* 121098765432102.75*/ } },
             { /* =>      */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_V(1, 0xbcd80e0108cc0, 0x42e)/*-244555555308646.00*/ } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP },
+              /*mxcsr:in */ X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_RC_UP },
           { { /*src2     */ { FP64_V(0, 0xc000000000000, 0x3ff)/*1.75*/, FP64_V(0, 0, 0x3fd)/*0.25*/, FP64_V(0, 0x26580b4c7e6b7, 0x41d)/*1234567891.1234567*/, FP64_V(0, 0xf9b0207d06184, 0x3fb)/*0.1234589833333129*/ } },
             { /*src1     */ { FP64_V(0, 0,               0x3fd)/*0.25*/, FP64_V(0, 0, 0x3fe)/*0.50*/, FP64_V(0, 0x26580b4c7e6bc, 0x41d)/*1234567891.1234580*/, FP64_V(0, 0xf9b0207d0617d, 0x3fb)/*0.1234589833333128*/ } },
             { /* =>      */ { FP64_V(0, 0,               0x3fd)/*0.25*/, FP64_V(0, 0, 0x3fd)/*0.25*/, FP64_V(0, 0x26580b4c7e6b7, 0x41d)/*1234567891.1234567*/, FP64_V(0, 0xf9b0207d0617d, 0x3fb)/*0.1234589833333128*/ } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
     /*
      * Denormals.
@@ -12016,13 +12016,13 @@
             { /*src1     */ { FP64_0(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_0(0)          } },
             { /* =>      */ { FP64_0(0), FP64_0(0),          FP64_0(0),          FP64_0(0)          } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE },
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_DE,
+              /*256:out  */ X86_MXCSR_DE },
           { { /*src2     */ { FP64_DENORM_MIN(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } },
             { /*src1     */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } },
             { /* =>      */ { FP64_0(0),          FP64_0(0),          FP64_0(0),          FP64_0(0)          } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP },
           { { /*src2     */ { FP64_DENORM_MAX(0), FP64_0(0),          FP64_DENORM_MAX(0), FP64_0(0)          } },
             { /*src1     */ { FP64_0(0),          FP64_DENORM_MAX(0), FP64_0(0),          FP64_DENORM_MAX(0) } },
@@ -12034,13 +12034,13 @@
             { /*src1     */ { FP64_0(0), FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), FP64_0(0)          } },
             { /* =>      */ { FP64_0(0), FP64_0(0),          FP64_0(0),          FP64_0(1)          } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ },
+              /*mxcsr:in */ X86_MXCSR_DAZ,
+              /*128:out  */ X86_MXCSR_DAZ,
+              /*256:out  */ X86_MXCSR_DAZ },
           { { /*src2     */ { FP64_DENORM_MIN(0), FP64_DENORM_MIN(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0) } },
             { /*src1     */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } },
             { /* =>      */ { FP64_0(0),          FP64_0(0),          FP64_0(0),          FP64_0(0)          } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP },
     /** @todo Denormals. */
     /*
@@ -12114,6 +12114,6 @@
             { /*src1     */ { FP32_0(0), FP32_0_x7(0) } },
             { /* =>      */ { FP32_0(0), FP32_0_x7(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_0(0), FP32_0_x7(0) } },
@@ -12126,42 +12126,42 @@
             { /*src1     */ { FP32_0(0), FP32_RAND_x7_V1 } },
             { /* =>      */ { FP32_0(0), FP32_RAND_x7_V1 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_0(0), FP32_RAND_x7_V0 } },
             { /*src1     */ { FP32_0(0), FP32_RAND_x7_V6 } },
             { /* =>      */ { FP32_0(0), FP32_RAND_x7_V6 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_0(0), FP32_RAND_x7_V6 } },
             { /*src1     */ { FP32_0(0), FP32_RAND_x7_V0 } },
             { /* =>      */ { FP32_0(0), FP32_RAND_x7_V0 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_0(0), FP32_RAND_x7_V0 } },
             { /*src1     */ { FP32_0(1), FP32_RAND_x7_V6 } },
             { /* =>      */ { FP32_0(0), FP32_RAND_x7_V6 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_0(0), FP32_RAND_x7_V2 } },
             { /*src1     */ { FP32_0(1), FP32_RAND_x7_V3 } },
             { /* =>      */ { FP32_0(0), FP32_RAND_x7_V3 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_0(1), FP32_RAND_x7_V6 } },
             { /*src1     */ { FP32_0(0), FP32_RAND_x7_V0 } },
             { /* =>      */ { FP32_0(1), FP32_RAND_x7_V0 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_0(1), FP32_RAND_x7_V5 } },
             { /*src1     */ { FP32_0(0), FP32_RAND_x7_V0 } },
             { /* =>      */ { FP32_0(1), FP32_RAND_x7_V0 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_XCPT_FLAGS | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_0(1), FP32_RAND_x7_V6 } },
@@ -12174,6 +12174,6 @@
             { /*src1     */ { FP32_0(1), FP32_RAND_x7_V7 } },
             { /* =>      */ { FP32_0(1), FP32_RAND_x7_V7 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
               /*256:out  */ -1 },
     /*
@@ -12183,24 +12183,24 @@
             { /*src1     */ { FP32_0(0),   FP32_RAND_x7_V7 } },
             { /* =>      */ { FP32_0(0),   FP32_RAND_x7_V7 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_0(0),   FP32_RAND_x7_V2 } },
             { /*src1     */ { FP32_INF(0), FP32_RAND_x7_V6 } },
             { /* =>      */ { FP32_0(0),   FP32_RAND_x7_V6 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
+              /*mxcsr:in */ X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_RC_UP,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_INF(0), FP32_RAND_x7_V2 } },
             { /*src1     */ { FP32_0(0),   FP32_RAND_x7_V4 } },
             { /* =>      */ { FP32_0(0),   FP32_RAND_x7_V4 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_0(0),   FP32_RAND_x7_V2 } },
             { /*src1     */ { FP32_INF(1), FP32_RAND_x7_V0 } },
             { /* =>      */ { FP32_INF(1), FP32_RAND_x7_V0 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_INF(0), FP32_RAND_x7_V3 } },
@@ -12213,66 +12213,66 @@
             { /*src1     */ { FP32_INF(0), FP32_RAND_x7_V6 } },
             { /* =>      */ { FP32_INF(0), FP32_RAND_x7_V6 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_INF(1), FP32_RAND_x7_V3 } },
             { /*src1     */ { FP32_INF(1), FP32_RAND_x7_V5 } },
             { /* =>      */ { FP32_INF(1), FP32_RAND_x7_V5 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_INF(1), FP32_RAND_x7_V3 } },
             { /*src1     */ { FP32_INF(1), FP32_RAND_x7_V0 } },
             { /* =>      */ { FP32_INF(1), FP32_RAND_x7_V0 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_INF(1), FP32_RAND_x7_V3 } },
             { /*src1     */ { FP32_INF(0), FP32_RAND_x7_V1 } },
             { /* =>      */ { FP32_INF(1), FP32_RAND_x7_V1 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
+              /*mxcsr:in */ X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_RC_UP,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_INF(1), FP32_RAND_x7_V1 } },
             { /*src1     */ { FP32_INF(0), FP32_RAND_x7_V1 } },
             { /* =>      */ { FP32_INF(1), FP32_RAND_x7_V1 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_INF(0), FP32_RAND_x7_V0 } },
             { /*src1     */ { FP32_INF(1), FP32_RAND_x7_V1 } },
             { /* =>      */ { FP32_INF(1), FP32_RAND_x7_V1 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_INF(0), FP32_RAND_x7_V1 } },
             { /*src1     */ { FP32_INF(1), FP32_RAND_x7_V5 } },
             { /* =>      */ { FP32_INF(1), FP32_RAND_x7_V5 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
+              /*mxcsr:in */ X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_FZ,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_INF(0),     FP32_RAND_x7_V0 } },
             { /*src1     */ { FP32_NORM_V0(0), FP32_RAND_x7_V4 } },
             { /* =>      */ { FP32_NORM_V0(0), FP32_RAND_x7_V4 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_INF(0),     FP32_RAND_x7_V0 } },
             { /*src1     */ { FP32_NORM_V3(0), FP32_RAND_x7_V3 } },
             { /* =>      */ { FP32_NORM_V3(0), FP32_RAND_x7_V3 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_NORM_V7(0), FP32_RAND_x7_V2 } },
             { /*src1     */ { FP32_INF(1),     FP32_RAND_x7_V3 } },
             { /* =>      */ { FP32_INF(1),     FP32_RAND_x7_V3 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_NORM_V7(0), FP32_RAND_x7_V5 } },
             { /*src1     */ { FP32_INF(0),     FP32_RAND_x7_V5 } },
             { /* =>      */ { FP32_NORM_V7(0), FP32_RAND_x7_V5 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
     /*
@@ -12282,114 +12282,114 @@
             { /*src1     */ { FP32_NORM_MAX(0), FP32_RAND_x7_V1 } },
             { /* =>      */ { FP32_NORM_MAX(0), FP32_RAND_x7_V1 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_NORM_MIN(0), FP32_RAND_x7_V3 } },
             { /*src1     */ { FP32_NORM_MIN(0), FP32_RAND_x7_V2 } },
             { /* =>      */ { FP32_NORM_MIN(0), FP32_RAND_x7_V2 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_NORM_MIN(0), FP32_RAND_x7_V3 } },
             { /*src1     */ { FP32_NORM_MAX(0), FP32_RAND_x7_V1 } },
             { /* =>      */ { FP32_NORM_MIN(0), FP32_RAND_x7_V1 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_NORM_MAX(0), FP32_RAND_x7_V2 } },
             { /*src1     */ { FP32_NORM_MAX(0), FP32_RAND_x7_V0 } },
             { /* =>      */ { FP32_NORM_MAX(0), FP32_RAND_x7_V0 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_x7_V2 } },
             { /*src1     */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V5 } },
             { /* =>      */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_x7_V5 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V6 } },
             { /*src1     */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V1 } },
             { /* =>      */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V1 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V6 } },
             { /*src1     */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_x7_V3 } },
             { /* =>      */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_x7_V3 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_V(0, 0x600000, 0x7f)/* 1.75*/, FP32_RAND_x7_V1 } },
             { /*src1     */ { FP32_V(1, 0,        0x7d)/*-0.25*/, FP32_RAND_x7_V1 } },
             { /* =>      */ { FP32_V(1, 0,        0x7d)/*-0.25*/, FP32_RAND_x7_V1 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_V(0, 0, 0x7d)/*0.25*/, FP32_RAND_x7_V2 } },
             { /*src1     */ { FP32_V(0, 0, 0x7e)/*0.50*/, FP32_RAND_x7_V1 } },
             { /* =>      */ { FP32_V(0, 0, 0x7d)/*0.25*/, FP32_RAND_x7_V1 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_NORM_MAX(0), FP32_RAND_x7_V0 } },
             { /*src1     */ { FP32_NORM_V1(0),  FP32_RAND_x7_V0 } },
             { /* =>      */ { FP32_NORM_V1(0),  FP32_RAND_x7_V0 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
+              /*mxcsr:in */ X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_RC_DOWN,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_RAND_x7_V3 } },
             { /*src1     */ { FP32_V(0, 0x1ea980, 0x8f)/*  81235*/, FP32_RAND_x7_V0 } },
             { /* =>      */ { FP32_V(0, 0x1ea980, 0x8f)/*  81235*/, FP32_RAND_x7_V0 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_V(1, 0x2514d6, 0x93)/*-1352346.75*/, FP32_RAND_x7_V2 } },
             { /*src1     */ { FP32_V(0, 0x7c9000, 0x88)/*    1010.25*/, FP32_RAND_x7_V0 } },
             { /* =>      */ { FP32_V(1, 0x2514d6, 0x93)/*-1352346.75*/, FP32_RAND_x7_V0 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_V(1, 0x2514d6, 0x93)/*-1352346.75*/, FP32_RAND_x7_V2 } },
             { /*src1     */ { FP32_V(0, 0x253468, 0x93)/* 1353357.00*/, FP32_RAND_x7_V3 } },
             { /* =>      */ { FP32_V(1, 0x2514d6, 0x93)/*-1352346.75*/, FP32_RAND_x7_V3 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_V(1, 0x40e6b6, 0x8c)/*-12345.678*/, FP32_RAND_x7_V4 } },
             { /*src1     */ { FP32_V(1, 0x40e6b7, 0x8c)/*-12345.679*/, FP32_RAND_x7_V6 } },
             { /* =>      */ { FP32_V(1, 0x40e6b7, 0x8c)/*-12345.679*/, FP32_RAND_x7_V6 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_V(0, 0x620b2e, 0x92)/*925874.9*/, FP32_RAND_x7_V5 } },
             { /*src1     */ { FP32_V(0, 0x620b2d, 0x92)/*925874.8*/, FP32_RAND_x7_V0 } },
             { /* =>      */ { FP32_V(0, 0x620b2d, 0x92)/*925874.8*/, FP32_RAND_x7_V0 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_V(0, 0x490fda, 0x80)/*3.1415926*/, FP32_RAND_x7_V6 } },
             { /*src1     */ { FP32_V(0, 0x490fdb, 0x80)/*3.1415927*/, FP32_RAND_x7_V0 } },
             { /* =>      */ { FP32_V(0, 0x490fda, 0x80)/*3.1415926*/, FP32_RAND_x7_V0 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_V(1, 0x40e6b6, 0x8c)/*-12345.678*/, FP32_RAND_x7_V5 } },
             { /*src1     */ { FP32_V(1, 0x40e6b7, 0x8c)/*-12345.679*/, FP32_RAND_x7_V0 } },
             { /* =>      */ { FP32_V(1, 0x40e6b7, 0x8c)/*-12345.679*/, FP32_RAND_x7_V0 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_V(0, 0x5dd520, 0x8e)/* 56789.125*/, FP32_RAND_x7_V4 } },
             { /*src1     */ { FP32_V(1, 0x5dd521, 0x8e)/*-56789.127*/, FP32_RAND_x7_V0 } },
             { /* =>      */ { FP32_V(1, 0x5dd521, 0x8e)/*-56789.127*/, FP32_RAND_x7_V0 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_RAND_x7_V3 } },
             { /*src1     */ { FP32_V(1, 0,        0x7d)/*-0.250*/, FP32_RAND_x7_V6 } },
             { /* =>      */ { FP32_V(1, 0,        0x7d)/*-0.250*/, FP32_RAND_x7_V6 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
+              /*mxcsr:in */ X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_RC_UP,
               /*256:out  */ -1 },
     /** @todo More Normals. */
@@ -12406,54 +12406,54 @@
             { /*src1     */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V4 } },
             { /* =>      */ { FP32_0(0),          FP32_RAND_x7_V4 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_DE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_DENORM_MIN(0), FP32_RAND_x7_V6 } },
             { /*src1     */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V3 } },
             { /* =>      */ { FP32_0(0),          FP32_RAND_x7_V3 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V5 } },
             { /*src1     */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V4 } },
             { /* =>      */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V4 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_DE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V1 } },
             { /*src1     */ { FP32_DENORM_MAX(1), FP32_RAND_x7_V3 } },
             { /* =>      */ { FP32_DENORM_MAX(1), FP32_RAND_x7_V3 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_DE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_DENORM_MAX(1), FP32_RAND_x7_V3 } },
             { /*src1     */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V0 } },
             { /* =>      */ { FP32_DENORM_MAX(1), FP32_RAND_x7_V0 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_DE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_DENORM_MIN(1), FP32_RAND_x7_V7 } },
             { /*src1     */ { FP32_DENORM_MIN(0), FP32_RAND_x7_V0 } },
             { /* =>      */ { FP32_DENORM_MIN(1), FP32_RAND_x7_V0 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_DE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_DENORM_MIN(1), FP32_RAND_x7_V6 } },
             { /*src1     */ { FP32_DENORM_MIN(1), FP32_RAND_x7_V3 } },
             { /* =>      */ { FP32_DENORM_MIN(1), FP32_RAND_x7_V3 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_DE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_DENORM_MIN(1), FP32_RAND_x7_V6 } },
             { /*src1     */ { FP32_DENORM_MIN(1), FP32_RAND_x7_V1 } },
             { /* =>      */ { FP32_0(1),          FP32_RAND_x7_V1 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
+              /*mxcsr:in */ X86_MXCSR_DAZ,
+              /*128:out  */ X86_MXCSR_DAZ,
               /*256:out  */ -1 },
           { { /*src2     */ { FP32_DENORM_MIN(0), FP32_RAND_x7_V6 } },
             { /*src1     */ { FP32_0(0),          FP32_RAND_x7_V2 } },
             { /* =>      */ { FP32_0(0),          FP32_RAND_x7_V2 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_DE,
               /*256:out  */ -1 },
     /** @todo More Denormals. */
@@ -12515,6 +12515,6 @@
             { /*src1     */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
             { /* =>      */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
@@ -12527,42 +12527,42 @@
             { /*src1     */ { FP64_0(0), FP64_INF(1), FP64_QNAN(0), FP64_SNAN(1) } },
             { /* =>      */ { FP64_0(0), FP64_INF(1), FP64_QNAN(0), FP64_SNAN(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V0(0), FP64_RAND_V0(0) } },
             { /*src1     */ { FP64_0(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(0) } },
             { /* =>      */ { FP64_0(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V1(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_0(0), FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V1(0) } },
             { /*src1     */ { FP64_0(0), FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V2(1) } },
             { /* =>      */ { FP64_0(0), FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V2(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_0(0), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V3(0) } },
             { /*src1     */ { FP64_0(1), FP64_RAND_V1(0), FP64_RAND_V2(0), FP64_RAND_V3(0) } },
             { /* =>      */ { FP64_0(0), FP64_RAND_V1(0), FP64_RAND_V2(0), FP64_RAND_V3(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_0(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(0) } },
             { /*src1     */ { FP64_0(1), FP64_RAND_V2(1), FP64_RAND_V3(0), FP64_RAND_V0(1) } },
             { /* =>      */ { FP64_0(0), FP64_RAND_V2(1), FP64_RAND_V3(0), FP64_RAND_V0(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_0(1), FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V3(1) } },
             { /*src1     */ { FP64_0(0), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V3(0) } },
             { /* =>      */ { FP64_0(1), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V3(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_0(1), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V1(0) } },
             { /*src1     */ { FP64_0(0), FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V3(0) } },
             { /* =>      */ { FP64_0(1), FP64_RAND_V0(1), FP64_RAND_V1(1), FP64_RAND_V3(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_0(1), FP64_RAND_V1(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } },
@@ -12575,6 +12575,6 @@
             { /*src1     */ { FP64_0(1), FP64_RAND_V1(0), FP64_RAND_V0(1), FP64_RAND_V2(1) } },
             { /* =>      */ { FP64_0(1), FP64_RAND_V1(0), FP64_RAND_V0(1), FP64_RAND_V2(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
               /*256:out  */ -1 },
     /*
@@ -12584,24 +12584,24 @@
             { /*src1     */ { FP64_0(0),   FP64_RAND_V1(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } },
             { /* =>      */ { FP64_0(0),   FP64_RAND_V1(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_0(0),   FP64_RAND_V1(1), FP64_RAND_V1(1), FP64_RAND_V3(1) } },
             { /*src1     */ { FP64_INF(0), FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } },
             { /* =>      */ { FP64_0(0),   FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
+              /*mxcsr:in */ X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_RC_UP,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_INF(0), FP64_INF(1),     FP64_SNAN(1),    FP64_QNAN(1)    } },
             { /*src1     */ { FP64_0(0),   FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } },
             { /* =>      */ { FP64_0(0),   FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_0(0),   FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V3(0) } },
             { /*src1     */ { FP64_INF(1), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V0(1) } },
             { /* =>      */ { FP64_INF(1), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V0(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_INF(0), FP64_RAND_V3(1), FP64_RAND_V3(1), FP64_RAND_V0(1) } },
@@ -12614,66 +12614,66 @@
             { /*src1     */ { FP64_INF(0), FP64_RAND_V0(1), FP64_RAND_V0(1), FP64_RAND_V3(1) } },
             { /* =>      */ { FP64_INF(0), FP64_RAND_V0(1), FP64_RAND_V0(1), FP64_RAND_V3(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_INF(1), FP64_RAND_V3(0),   FP64_RAND_V2(1), FP64_RAND_V3(0) } },
             { /*src1     */ { FP64_INF(1), FP64_QNAN_V(1, 1), FP64_RAND_V1(1), FP64_RAND_V2(0) } },
             { /* =>      */ { FP64_INF(1), FP64_QNAN_V(1, 1), FP64_RAND_V1(1), FP64_RAND_V2(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_INF(1), FP64_RAND_V2(1), FP64_RAND_V1(1), FP64_RAND_V0(1) } },
             { /*src1     */ { FP64_INF(1), FP64_RAND_V0(0), FP64_RAND_V3(1), FP64_RAND_V0(1) } },
             { /* =>      */ { FP64_INF(1), FP64_RAND_V0(0), FP64_RAND_V3(1), FP64_RAND_V0(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_INF(1), FP64_RAND_V1(1), FP64_RAND_V3(1), FP64_RAND_V0(1) } },
             { /*src1     */ { FP64_INF(0), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V1(1) } },
             { /* =>      */ { FP64_INF(1), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V1(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
+              /*mxcsr:in */ X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_RC_UP,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_INF(1), FP64_RAND_V0(1), FP64_RAND_V2(1), FP64_RAND_V0(1) } },
             { /*src1     */ { FP64_INF(0), FP64_RAND_V0(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },
             { /* =>      */ { FP64_INF(1), FP64_RAND_V0(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_INF(0), FP64_RAND_V2(1), FP64_RAND_V3(1), FP64_RAND_V0(1) } },
             { /*src1     */ { FP64_INF(1), FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V1(1) } },
             { /* =>      */ { FP64_INF(1), FP64_RAND_V2(0), FP64_RAND_V3(0), FP64_RAND_V1(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_INF(0), FP64_RAND_V0(1), FP64_RAND_V2(1), FP64_RAND_V0(1) } },
             { /*src1     */ { FP64_INF(1), FP64_RAND_V0(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },
             { /* =>      */ { FP64_INF(1), FP64_RAND_V0(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
+              /*mxcsr:in */ X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_FZ,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_INF(0),     FP64_RAND_V0(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } },
             { /*src1     */ { FP64_NORM_V0(0), FP64_RAND_V1(1), FP64_RAND_V3(1), FP64_RAND_V1(1) } },
             { /* =>      */ { FP64_NORM_V0(0), FP64_RAND_V1(1), FP64_RAND_V3(1), FP64_RAND_V1(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_INF(0),     FP64_INF(0), FP64_SNAN(1), FP64_INF(1)  } },
             { /*src1     */ { FP64_NORM_V3(0), FP64_INF(1), FP64_QNAN(1), FP64_SNAN(1) } },
             { /* =>      */ { FP64_NORM_V3(0), FP64_INF(1), FP64_QNAN(1), FP64_SNAN(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_NORM_V2(0), FP64_RAND_V3(1), FP64_QNAN(1),    FP64_SNAN(1)    } },
             { /*src1     */ { FP64_INF(1),     FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V1(1) } },
             { /* =>      */ { FP64_INF(1),     FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V1(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_NORM_V2(0), FP64_SNAN(0), FP64_RAND_V2(0), FP64_RAND_V3(0) } },
             { /*src1     */ { FP64_INF(0),     FP64_RAND_V2(0),   FP64_RAND_V1(0), FP64_RAND_V2(1) } },
             { /* =>      */ { FP64_NORM_V2(0), FP64_RAND_V2(0),   FP64_RAND_V1(0), FP64_RAND_V2(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
     /*
@@ -12683,114 +12683,114 @@
             { /*src1     */ { FP64_NORM_MAX(0), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V2(1) } },
             { /* =>      */ { FP64_NORM_MAX(0), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V2(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_NORM_MIN(0), FP64_RAND_V3(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } },
             { /*src1     */ { FP64_NORM_MIN(0), FP64_RAND_V2(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } },
             { /* =>      */ { FP64_NORM_MIN(0), FP64_RAND_V2(0), FP64_RAND_V1(1), FP64_RAND_V2(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_NORM_MIN(0), FP64_RAND_V3(1), FP64_RAND_V0(1), FP64_RAND_V3(0) } },
             { /*src1     */ { FP64_NORM_MAX(0), FP64_RAND_V1(0), FP64_RAND_V3(0), FP64_RAND_V1(0) } },
             { /* =>      */ { FP64_NORM_MIN(0), FP64_RAND_V1(0), FP64_RAND_V3(0), FP64_RAND_V1(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_NORM_MAX(0), FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V3(0) } },
             { /*src1     */ { FP64_NORM_MAX(0), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V1(1) } },
             { /* =>      */ { FP64_NORM_MAX(0), FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V1(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_NORM_SAFE_INT_MIN(0), FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V3(0) } },
             { /*src1     */ { FP64_NORM_SAFE_INT_MAX(0), FP64_RAND_V1(0), FP64_RAND_V1(0), FP64_RAND_V3(1) } },
             { /* =>      */ { FP64_NORM_SAFE_INT_MIN(0), FP64_RAND_V1(0), FP64_RAND_V1(0), FP64_RAND_V3(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_NORM_SAFE_INT_MAX(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },
             { /*src1     */ { FP64_NORM_SAFE_INT_MAX(0), FP64_RAND_V1(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } },
             { /* =>      */ { FP64_NORM_SAFE_INT_MAX(0), FP64_RAND_V1(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_NORM_SAFE_INT_MAX(0), FP64_INF(0),     FP64_QNAN(1),    FP64_QNAN(0)    } },
             { /*src1     */ { FP64_NORM_SAFE_INT_MIN(0), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } },
             { /* =>      */ { FP64_NORM_SAFE_INT_MIN(0), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_V(0, 0, 0x409)/*1024*/,  FP64_RAND_V1(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } },
             { /*src1     */ { FP64_V(0, 0, 0x408)/* 512*/,  FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V3(1) } },
             { /* =>      */ { FP64_V(0, 0, 0x408)/* 512*/,  FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V3(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/,  FP64_RAND_V2(1), FP64_RAND_V2(0), FP64_RAND_V3(1) } },
             { /*src1     */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/,  FP64_RAND_V0(0), FP64_RAND_V2(0), FP64_RAND_V0(0) } },
             { /* =>      */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/,  FP64_RAND_V0(0), FP64_RAND_V2(0), FP64_RAND_V0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_NORM_MAX(0), FP64_RAND_V0(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } },
             { /*src1     */ { FP64_NORM_V1(0),  FP64_RAND_V0(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } },
             { /* =>      */ { FP64_NORM_V1(0),  FP64_RAND_V0(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
+              /*mxcsr:in */ X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_RC_DOWN,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_V(0, 0xc000000000000, 0x3ff)/*1.75*/, FP64_RAND_V3(0), FP64_RAND_V2(1), FP64_RAND_V3(0) } },
             { /*src1     */ { FP64_V(0, 0,               0x3fd)/*0.25*/, FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V1(0) } },
             { /* =>      */ { FP64_V(0, 0,               0x3fd)/*0.25*/, FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V1(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_V(1, 0, 0x3fd)/*-0.25*/, FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V3(0) } },
             { /*src1     */ { FP64_V(1, 0, 0x3fe)/*-0.50*/, FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V1(1) } },
             { /* =>      */ { FP64_V(1, 0, 0x3fe)/*-0.50*/, FP64_RAND_V0(0), FP64_RAND_V1(0), FP64_RAND_V1(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_V(0, 0x26580b4c7e6b7, 0x41d)/*1234567891.1234567*/, FP64_RAND_V2(1), FP64_RAND_V3(1), FP64_RAND_V3(1) } },
             { /*src1     */ { FP64_V(0, 0x26580b4c7e6bc, 0x41d)/*1234567891.1234580*/, FP64_RAND_V3(0), FP64_RAND_V1(0), FP64_RAND_V0(1) } },
             { /* =>      */ { FP64_V(0, 0x26580b4c7e6b7, 0x41d)/*1234567891.1234567*/, FP64_RAND_V3(0), FP64_RAND_V1(0), FP64_RAND_V0(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_V(0, 0xf9b0207d06184, 0x3fb)/*0.1234589833333129*/, FP64_RAND_V3(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } },
             { /*src1     */ { FP64_V(0, 0xf9b0207d0617d, 0x3fb)/*0.1234589833333128*/, FP64_RAND_V1(1), FP64_RAND_V0(0), FP64_RAND_V0(1) } },
             { /* =>      */ { FP64_V(0, 0xf9b0207d0617d, 0x3fb)/*0.1234589833333128*/, FP64_RAND_V1(1), FP64_RAND_V0(0), FP64_RAND_V0(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/* 121098765432102.75*/,  FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V3(1) } },
             { /*src1     */ { FP64_V(1, 0xbcd80e0108cc0, 0x42e)/*-244555555308646.00*/,  FP64_RAND_V3(0), FP64_RAND_V3(1), FP64_RAND_V0(1) } },
             { /* =>      */ { FP64_V(1, 0xbcd80e0108cc0, 0x42e)/*-244555555308646.00*/,  FP64_RAND_V3(0), FP64_RAND_V3(1), FP64_RAND_V0(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_V(0, 0xcf0033a34f337, 0x432)/*4072598000007579.5*/, FP64_RAND_V3(1), FP64_RAND_V2(1), FP64_RAND_V1(1) } },
             { /*src1     */ { FP64_V(0, 0xd6eca42000000, 0x419)/*       123450000.5*/, FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },
             { /* =>      */ { FP64_V(0, 0xd6eca42000000, 0x419)/*       123450000.5*/, FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_V(1, 0xbcd80e0108cc0, 0x42e)/*-244555555308646.00*/, FP64_INF(1), FP64_SNAN(1), FP64_INF(1)  } },
             { /*src1     */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/* 121098765432102.75*/, FP64_INF(1), FP64_QNAN(0), FP64_SNAN(0) } },
             { /* =>      */ { FP64_V(1, 0xbcd80e0108cc0, 0x42e)/*-244555555308646.00*/, FP64_INF(1), FP64_QNAN(0), FP64_SNAN(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/* 244555555308646.00*/, FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(0) } },
             { /*src1     */ { FP64_V(1, 0xb88e0395d49b0, 0x42d)/*-121098765432102.75*/, FP64_RAND_V0(0), FP64_RAND_V0(0), FP64_RAND_V2(1) } },
             { /* =>      */ { FP64_V(1, 0xb88e0395d49b0, 0x42d)/*-121098765432102.75*/, FP64_RAND_V0(0), FP64_RAND_V0(0), FP64_RAND_V2(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_V(1, 0xcf0033a34f337, 0x432)/*-4072598000007579.5*/, FP64_RAND_V1(0), FP64_RAND_V2(0), FP64_RAND_V1(0) } },
             { /*src1     */ { FP64_V(0, 0xd6eca42000000, 0x419)/*        123450000.5*/, FP64_RAND_V2(0), FP64_RAND_V2(1), FP64_RAND_V3(0) } },
             { /* =>      */ { FP64_V(1, 0xcf0033a34f337, 0x432)/*-4072598000007579.5*/, FP64_RAND_V2(0), FP64_RAND_V2(1), FP64_RAND_V3(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
+              /*mxcsr:in */ X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_RC_UP,
               /*256:out  */ -1 },
     /** @todo More Normals. */
@@ -12807,54 +12807,54 @@
             { /*src1     */ { FP64_DENORM_MAX(0), FP64_RAND_V2(0), FP64_RAND_V3(1), FP64_RAND_V2(0) } },
             { /* =>      */ { FP64_0(0),          FP64_RAND_V2(0), FP64_RAND_V3(1), FP64_RAND_V2(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_DE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_DENORM_MIN(0), FP64_INF(1), FP64_SNAN(0), FP64_INF(1)  } },
             { /*src1     */ { FP64_DENORM_MAX(0), FP64_INF(0), FP64_QNAN(1), FP64_SNAN(1) } },
             { /* =>      */ { FP64_0(0),          FP64_INF(0), FP64_QNAN(1), FP64_SNAN(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_DENORM_MAX(0), FP64_RAND_V2(1), FP64_RAND_V0(1), FP64_RAND_V3(0) } },
             { /*src1     */ { FP64_DENORM_MAX(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },
             { /* =>      */ { FP64_DENORM_MAX(0), FP64_RAND_V3(0), FP64_RAND_V2(0), FP64_RAND_V3(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_DE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_DENORM_MAX(0), FP64_RAND_V1(1), FP64_RAND_V2(1), FP64_RAND_V2(0) } },
             { /*src1     */ { FP64_DENORM_MAX(1), FP64_RAND_V0(0), FP64_RAND_V3(0), FP64_RAND_V0(0) } },
             { /* =>      */ { FP64_DENORM_MAX(1), FP64_RAND_V0(0), FP64_RAND_V3(0), FP64_RAND_V0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_DE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_DENORM_MAX(1), FP64_RAND_V3(1), FP64_RAND_V0(0), FP64_RAND_V3(1) } },
             { /*src1     */ { FP64_DENORM_MAX(0), FP64_RAND_V2(1), FP64_RAND_V3(1), FP64_RAND_V2(1) } },
             { /* =>      */ { FP64_DENORM_MAX(1), FP64_RAND_V2(1), FP64_RAND_V3(1), FP64_RAND_V2(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_DE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_DENORM_MIN(1), FP64_RAND_V0(1), FP64_RAND_V3(1), FP64_RAND_V2(1) } },
             { /*src1     */ { FP64_DENORM_MIN(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
             { /* =>      */ { FP64_DENORM_MIN(1), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_DE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_DENORM_MIN(1), FP64_INF(0),     FP64_QNAN(1),    FP64_SNAN(1) } },
             { /*src1     */ { FP64_DENORM_MIN(1), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V0(1)   } },
             { /* =>      */ { FP64_DENORM_MIN(1), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V0(1)   } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_DE,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_DENORM_MIN(1), FP64_SNAN(1),    FP64_SNAN(0),    FP64_QNAN(0)    } },
             { /*src1     */ { FP64_DENORM_MIN(1), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } },
             { /* =>      */ { FP64_0(1),          FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
+              /*mxcsr:in */ X86_MXCSR_DAZ,
+              /*128:out  */ X86_MXCSR_DAZ,
               /*256:out  */ -1 },
           { { /*src2     */ { FP64_DENORM_MIN(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
             { /*src1     */ { FP64_0(0),          FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(0) } },
             { /* =>      */ { FP64_0(0),          FP64_RAND_V0(0), FP64_RAND_V1(1), FP64_RAND_V2(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE,
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_DE,
               /*256:out  */ -1 },
     /** @todo More Denormals. */
@@ -12918,7 +12918,7 @@
             { /*unused   */ { FP32_ROW_UNUSED } },
             { /* =>      */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src1     */ { FP32_0(0),   FP32_0(0),   FP32_0(0),   FP32_0(0),   FP32_0(0),   FP32_0(0),   FP32_0(0),   FP32_0(0)   } },
             { /*unused   */ { FP32_ROW_UNUSED } },
@@ -12945,7 +12945,7 @@
             { /*unused   */ { FP32_ROW_UNUSED } },
             { /* =>      */ { FP32_0(0),   FP32_0(1),   FP32_0(1),   FP32_0(0),   FP32_0(1),   FP32_0(1),   FP32_0(1),   FP32_0(0)   } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src1     */ { FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(0) } },
             { /*unused   */ { FP32_ROW_UNUSED } },
@@ -13087,7 +13087,7 @@
             { /*unused   */ { FP32_ROW_UNUSED } },
             { /* =>      */ { FP32_INF(0),        FP32_INF(1),        FP32_INF(0),        FP32_INF(1),        FP32_INF(0),        FP32_INF(1),        FP32_INF(1),        FP32_INF(0)        } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src1     */ { FP32_DENORM_MAX(1), FP32_DENORM_MAX(1), FP32_DENORM_MIN(1), FP32_DENORM_MIN(1), FP32_DENORM_MIN(0), FP32_DENORM_MIN(1), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } },
             { /*unused   */ { FP32_ROW_UNUSED } },
@@ -13139,7 +13139,7 @@
             { /*unused   */ { FP32_ROW_UNUSED } },
             { /* =>      */ { FP32_QNAN_V(0, 1), FP32_QNAN_V(1, 1), FP32_QNAN(0), FP32_QNAN(1), FP32_QNAN_V(1, 1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN_V(1, 1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src1     */ { FP32_SNAN(0),      FP32_SNAN(1),      FP32_QNAN(0), FP32_QNAN(1), FP32_SNAN(1),      FP32_QNAN(1), FP32_QNAN(1), FP32_SNAN(1)      } },
             { /*unused   */ { FP32_ROW_UNUSED } },
@@ -13250,12 +13250,12 @@
             { /*src2     */ { FP32_RAND_V2(0), FP32_RAND_x7_V2 } },
             { /* =>      */ { FP32_INF(0),     FP32_RAND_x7_V2 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src1     */ { FP32_0(1),       FP32_RAND_x7_V0 } },
             { /*src2     */ { FP32_RAND_V3(1), FP32_RAND_x7_V1 } },
             { /* =>      */ { FP32_INF(1),     FP32_RAND_x7_V1 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1  },
           { { /*src1     */ { FP32_0(1),       FP32_RAND_x7_V2 } },
@@ -13289,6 +13289,6 @@
             { /*unused   */ { FP32_RAND_V2(0), FP32_RAND_x7_V0 } },
             { /* =>      */ { FP32_0(0),       FP32_RAND_x7_V0 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src1     */ { FP32_INF(0),     FP32_RAND_x7_V3 } },
@@ -13508,12 +13508,12 @@
             { /*unused   */ { FP32_RAND_V2(0),                       FP32_RAND_x7_V3 } },
             { /* =>      */ { FP32_V(0, 1112064, 107),               FP32_RAND_x7_V3 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src1     */ { FP32_V(0, 0x620b2d, 0x92)/*925874.8*/, FP32_RAND_x7_V4 } },
             { /*unused   */ { FP32_RAND_V2(0),                       FP32_RAND_x7_V3 } },
             { /* =>      */ { FP32_V(0, 1112064, 107),               FP32_RAND_x7_V3 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ -1 },
           { { /*src1     */ { FP32_V(0, 0x600000, 0x7e)/*0.875*/, FP32_RAND_x7_V4 } },
@@ -13526,6 +13526,6 @@
             { /*unused   */ { FP32_RAND_V1(0),                        FP32_RAND_x7_V3 } },
             { /* =>      */ { FP32_V(0, 2293760, 125),                FP32_RAND_x7_V3 } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
               /*256:out  */ -1 },
           { { /*src1     */ { FP32_V(0, 0x490fda, 0x80)/*3.1415926*/, FP32_RAND_x7_V2 } },
@@ -13620,7 +13620,7 @@
             { /*unused   */ { FP32_ROW_UNUSED } },
             { /* =>      */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src1     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1) } },
             { /*unused   */ { FP32_ROW_UNUSED } },
@@ -13638,7 +13638,7 @@
             { /*unused   */ { FP32_ROW_UNUSED } },
             { /* =>      */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
     /*
      * Infinity.
@@ -13662,25 +13662,25 @@
             { /*unused   */ { FP32_ROW_UNUSED } },
             { /* =>      */ { FP32_0(0), FP32_1(0), FP32_1(0), FP32_0(1), FP32_1(0), FP32_0(0), FP32_1(0), FP32_V(0, 0x3504f3, 0x7f)/*sqrt(2)*/ } },
-              /*mxcsr:in */ X86_MXCSR_PM | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_PM | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_PM | X86_MXCSR_RC_DOWN | X86_MXCSR_PE },
+              /*mxcsr:in */ X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_RC_DOWN | X86_MXCSR_PE },
           { { /*src1     */ { FP32_0(0), FP32_1(0), FP32_1(0), FP32_0(1), FP32_1(0), FP32_0(0), FP32_1(0), FP32_2(0)                             } },
             { /*unused   */ { FP32_ROW_UNUSED } },
             { /* =>      */ { FP32_0(0), FP32_1(0), FP32_1(0), FP32_0(1), FP32_1(0), FP32_0(0), FP32_1(0), FP32_V(0, 0x3504f4, 0x7f)/*sqrt^(2)*/ } },
-              /*mxcsr:in */ X86_MXCSR_PM | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_PM | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_PE },
+              /*mxcsr:in */ X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_RC_UP | X86_MXCSR_PE },
           { { /*src1     */ { FP32_0(0), FP32_1(0), FP32_1(0), FP32_0(1), FP32_1(0), FP32_0(0), FP32_1(0), FP32_2(0)                            } },
             { /*unused   */ { FP32_ROW_UNUSED } },
             { /* =>      */ { FP32_0(0), FP32_1(0), FP32_1(0), FP32_0(1), FP32_1(0), FP32_0(0), FP32_1(0), FP32_V(0, 0x3504f3, 0x7f)/*sqrt(2)*/ } },
-              /*mxcsr:in */ X86_MXCSR_PM | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_PM | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_PE },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE },
           { { /*src1     */ { FP32_0(0), FP32_1(0), FP32_1(0), FP32_0(1), FP32_1(0), FP32_0(0), FP32_1(0), FP32_2(0)                            } },
             { /*unused   */ { FP32_ROW_UNUSED } },
             { /* =>      */ { FP32_0(0), FP32_1(0), FP32_1(0), FP32_0(1), FP32_1(0), FP32_0(0), FP32_1(0), FP32_V(0, 0x3504f3, 0x7f)/*sqrt(2)*/ } },
-              /*mxcsr:in */ X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_DAZ,
-              /*128:out  */ X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_DAZ,
-              /*256:out  */ X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_DAZ | X86_MXCSR_PE },
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_DAZ,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_DAZ,
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_DAZ | X86_MXCSR_PE },
     /*
      * Normals.
@@ -13696,7 +13696,7 @@
                               FP32_V(0,0x561776,0x5d)/*sqrt(FP32_NORM_V6)*/,
                               FP32_V(0,0x3504f3,0x68)/*sqrt(FP32_NORM_V7)*/ } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_PE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_PE },
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_PE },
           { { /*src1     */ { FP32_V(0,0x44000,0x88)/*529.0*/,
                               FP32_V(0,0x0,0x87)/*256.0*/,
@@ -13716,7 +13716,7 @@
                               FP32_V(0,0x5fffff,0x7d)/*7/16-*/,
                               FP32_V(0,0x778001,0x85)/*123.75+*/ } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_PE },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ X86_MXCSR_PE },
           { { /*src1     */ { FP32_V(0,0x44000,0x88)/*529.0*/,
                               FP32_V(0,0x0,0x87)/*256.0*/,
@@ -13736,7 +13736,7 @@
                               FP32_V(0,0x5fffff,0x7d)/*7/16-*/,
                               FP32_V(0,0x778000,0x85)/*123.75[DOWN]*/ } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_PE | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_PE | X86_MXCSR_RC_DOWN },
           { { /*src1     */ { FP32_V(0,0x44000,0x88)/*529.0*/,
                               FP32_V(0,0x0,0x87)/*256.0*/,
@@ -13756,7 +13756,7 @@
                               FP32_V(0,0x600000,0x7d)/*7/16[UP]*/,
                               FP32_V(0,0x778001,0x85)/*123.75+*/ } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_PE | X86_MXCSR_RC_UP },
+              /*mxcsr:in */ X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_PE | X86_MXCSR_RC_UP },
           { { /*src1     */ { FP32_V(0,0x44000,0x88)/*529.0*/,
                               FP32_V(0,0x0,0x87)/*256.0*/,
@@ -13776,7 +13776,7 @@
                               FP32_V(0,0x5fffff,0x7d)/*7/16-*/,
                               FP32_V(0,0x778000,0x85)/*123.75[ZERO=DOWN]*/ } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_PE | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_PE | X86_MXCSR_RC_ZERO },
           { { /*src1     */ { FP32_NORM_MAX(0),
                               FP32_NORM_MIN(0),
@@ -13796,7 +13796,7 @@
                               FP32_QNAN(1),
                               FP32_QNAN(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_PE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_PE | X86_MXCSR_IE | BS3_MXCSR_PE_FUZZY /* IEM */ },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_PE | X86_MXCSR_IE | BS3_MXCSR_PE_FUZZY /* IEM */ },
     /** @todo More Normals. */
    /*
@@ -13818,31 +13818,31 @@
             { /*unused   */ { FP32_ROW_UNUSED } },
             { /* =>      */ { FP32_V(0,0x3504f3+1,0x34), FP32_V(0,0x7fffff,0x3f), FP32_0(0), FP32_0(1), FP32_QNAN(1),     FP32_QNAN(1),       FP32_0(1), FP32_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_IE | X86_MXCSR_PE | X86_MXCSR_RC_UP | BS3_MXCSR_PE_FUZZY /* IEM */ },
+              /*mxcsr:in */ X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_DE | X86_MXCSR_IE | X86_MXCSR_PE | X86_MXCSR_RC_UP | BS3_MXCSR_PE_FUZZY /* IEM */ },
           { { /*src1     */ { FP32_DENORM_MIN(0),      FP32_DENORM_MAX(0),      FP32_0(0), FP32_0(1), FP32_DENORM_MIN(1), FP32_DENORM_MAX(1), FP32_0(1), FP32_0(0) } },
             { /*unused   */ { FP32_ROW_UNUSED } },
             { /* =>      */ { FP32_V(0,0x3504f3,0x34), FP32_V(0,0x7fffff-1,0x3f), FP32_0(0), FP32_0(1), FP32_QNAN(1),     FP32_QNAN(1),       FP32_0(1), FP32_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_IE | X86_MXCSR_PE | X86_MXCSR_RC_DOWN | BS3_MXCSR_PE_FUZZY /* IEM */ },
+              /*mxcsr:in */ X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_DE | X86_MXCSR_IE | X86_MXCSR_PE | X86_MXCSR_RC_DOWN | BS3_MXCSR_PE_FUZZY /* IEM */ },
           { { /*src1     */ { FP32_DENORM_MIN(0),      FP32_DENORM_MAX(0),      FP32_0(0), FP32_0(1), FP32_DENORM_MIN(1), FP32_DENORM_MAX(1), FP32_0(1), FP32_0(0) } },
             { /*unused   */ { FP32_ROW_UNUSED } },
             { /* =>      */ { FP32_V(0,0x3504f3,0x34), FP32_V(0,0x7fffff-1,0x3f), FP32_0(0), FP32_0(1), FP32_QNAN(1),     FP32_QNAN(1),       FP32_0(1), FP32_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_IE | X86_MXCSR_PE | X86_MXCSR_RC_ZERO | BS3_MXCSR_PE_FUZZY /* IEM */ },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_DE | X86_MXCSR_IE | X86_MXCSR_PE | X86_MXCSR_RC_ZERO | BS3_MXCSR_PE_FUZZY /* IEM */ },
           { { /*src1     */ { FP32_DENORM_MIN(0),      FP32_DENORM_MAX(0),      FP32_0(0), FP32_0(1), FP32_DENORM_MIN(1), FP32_DENORM_MAX(1), FP32_0(1), FP32_0(0) } },
             { /*unused   */ { FP32_ROW_UNUSED } },
             { /* =>      */ { FP32_V(0,0x3504f3,0x34), FP32_V(0,0x7fffff,0x3f), FP32_0(0), FP32_0(1), FP32_QNAN(1),       FP32_QNAN(1),       FP32_0(1), FP32_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_FZ,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_IE | X86_MXCSR_PE | X86_MXCSR_FZ | BS3_MXCSR_PE_FUZZY /* IEM */ },
+              /*mxcsr:in */ X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_FZ,
+              /*256:out  */ X86_MXCSR_DE | X86_MXCSR_IE | X86_MXCSR_PE | X86_MXCSR_FZ | BS3_MXCSR_PE_FUZZY /* IEM */ },
           { { /*src1     */ { FP32_DENORM_MIN(0),      FP32_DENORM_MAX(0),      FP32_0(0), FP32_0(1), FP32_DENORM_MIN(1), FP32_DENORM_MAX(1), FP32_0(1), FP32_0(0) } },
             { /*unused   */ { FP32_ROW_UNUSED } },
             { /* =>      */ { FP32_0(0),               FP32_0(0),               FP32_0(0), FP32_0(1), FP32_0(1),          FP32_0(1),          FP32_0(1), FP32_0(0) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ },
+              /*mxcsr:in */ X86_MXCSR_DAZ,
+              /*128:out  */ X86_MXCSR_DAZ,
+              /*256:out  */ X86_MXCSR_DAZ },
     /** @todo More Denormals. */
     /*
@@ -13918,7 +13918,7 @@
             { /*unused   */ { FP64_ROW_UNUSED } },
             { /* =>      */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
           { { /*src1     */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } },
             { /*unused   */ { FP64_ROW_UNUSED } },
@@ -13936,7 +13936,7 @@
             { /*unused   */ { FP64_ROW_UNUSED } },
             { /* =>      */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN },
     /*
      * Infinity.
@@ -13960,25 +13960,25 @@
             { /*unused   */ { FP64_ROW_UNUSED } },
             { /* =>      */ { FP64_0(0), FP64_1(0), FP64_0(1), FP64_V(0,0x6a09e667f3bcc,0x3ff)/*sqrt(2)v*/ } },
-              /*mxcsr:in */ X86_MXCSR_PM | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_PM | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_PM | X86_MXCSR_RC_DOWN | X86_MXCSR_PE },
+              /*mxcsr:in */ X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_RC_DOWN | X86_MXCSR_PE },
           { { /*src1     */ { FP64_0(0), FP64_1(0), FP64_0(1), FP64_2(0)                                  } },
             { /*unused   */ { FP64_ROW_UNUSED } },
             { /* =>      */ { FP64_0(0), FP64_1(0), FP64_0(1), FP64_V(0,0x6a09e667f3bcd,0x3ff)/*sqrt(2)*/ } },
-              /*mxcsr:in */ X86_MXCSR_PM | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_PM | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_PE },
+              /*mxcsr:in */ X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_RC_UP | X86_MXCSR_PE },
           { { /*src1     */ { FP64_0(0), FP64_1(0), FP64_0(1), FP64_2(0)                                   } },
             { /*unused   */ { FP64_ROW_UNUSED } },
             { /* =>      */ { FP64_0(0), FP64_1(0), FP64_0(1), FP64_V(0,0x6a09e667f3bcc,0x3ff)/*sqrt(2)v*/ } },
-              /*mxcsr:in */ X86_MXCSR_PM | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_PM | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_PE },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE },
           { { /*src1     */ { FP64_0(0), FP64_1(0), FP64_0(1), FP64_2(0)                                  } },
             { /*unused   */ { FP64_ROW_UNUSED } },
             { /* =>      */ { FP64_0(0), FP64_1(0), FP64_0(1), FP64_V(0,0x6a09e667f3bcd,0x3ff)/*sqrt(2)*/ } },
-              /*mxcsr:in */ X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_DAZ,
-              /*128:out  */ X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_DAZ,
-              /*256:out  */ X86_MXCSR_PM | X86_MXCSR_FZ | X86_MXCSR_DAZ | X86_MXCSR_PE },
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_DAZ,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_DAZ,
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_DAZ | X86_MXCSR_PE },
     /*
      * Normals.
@@ -13990,7 +13990,7 @@
                               FP64_V(0,0x568cddb7b5f47,0x5fe)/*sqrt(FP64_NORM_V2)*/,
                               FP64_V(0,0x4ebe86dd38102,0x440)/*sqrt(FP64_NORM_V3)*/ } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_PE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_PE },
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_PE },
           { { /*src1     */ { FP64_V(0,0xf46c4c48b9b90,0x42f)/*23456789^2*/,
                               FP64_V(0,0x153e1f1867880,0x408)/*(12345678/524288)^2*/,
@@ -14002,7 +14002,7 @@
                               FP64_V(0,0x65ec150000006,0x417)/*23456789+*/,
                               FP64_V(0,0x78c29bfffffff,0x403)/*12345678/524288-*/ } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
-              /*128:out  */ X86_MXCSR_XCPT_MASK,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_PE },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ X86_MXCSR_PE },
           { { /*src1     */ { FP64_V(0,0xf46c4c48b9b90,0x42f)/*23456789^2*/,
                               FP64_V(0,0x153e1f1867880,0x408)/*(12345678/524288)^2*/,
@@ -14014,7 +14014,7 @@
                               FP64_V(0,0x65ec150000005,0x417)/*23456789+[DOWN]*/,
                               FP64_V(0,0x78c29bfffffff,0x403)/*12345678/524288-*/ } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_PE | X86_MXCSR_RC_DOWN },
+              /*mxcsr:in */ X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_PE | X86_MXCSR_RC_DOWN },
           { { /*src1     */ { FP64_V(0,0xf46c4c48b9b90,0x42f)/*23456789^2*/,
                               FP64_V(0,0x153e1f1867880,0x408)/*(12345678/524288)^2*/,
@@ -14026,7 +14026,7 @@
                               FP64_V(0,0x65ec150000006,0x417)/*23456789+*/,
                               FP64_V(0,0x78c29c0000000,0x403)/*12345678/524288[UP]*/ } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_PE | X86_MXCSR_RC_UP },
+              /*mxcsr:in */ X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_PE | X86_MXCSR_RC_UP },
           { { /*src1     */ { FP64_V(0,0xf46c4c48b9b90,0x42f)/*23456789^2*/,
                               FP64_V(0,0x153e1f1867880,0x408)/*(12345678/524288)^2*/,
@@ -14038,7 +14038,7 @@
                               FP64_V(0,0x65ec150000005,0x417)/*23456789+[ZERO]*/,
                               FP64_V(0,0x78c29bfffffff,0x403)/*12345678/524288-*/ } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_PE | X86_MXCSR_RC_ZERO },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_PE | X86_MXCSR_RC_ZERO },
           { { /*src1     */ { FP64_NORM_MAX(0),
                               FP64_NORM_MIN(0),
@@ -14050,7 +14050,7 @@
                               FP64_QNAN(1),
                               FP64_QNAN(1) } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_PE,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_PE | X86_MXCSR_IE | BS3_MXCSR_PE_FUZZY /* IEM */ },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_PE | X86_MXCSR_IE | BS3_MXCSR_PE_FUZZY /* IEM */ },
     /** @todo More Normals. */
    /*
@@ -14072,31 +14072,31 @@
             { /*unused   */ { FP64_ROW_UNUSED } },
             { /* =>      */ { FP64_V(0,0x0,0x1e6), FP64_V(0,0xfffffffffffff,0x1ff), FP64_QNAN(1),       FP64_QNAN(1)       } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_UP,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_RC_UP,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_IE | X86_MXCSR_PE | X86_MXCSR_RC_UP | BS3_MXCSR_PE_FUZZY /* IEM */ },
+              /*mxcsr:in */ X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_DE | X86_MXCSR_IE | X86_MXCSR_PE | X86_MXCSR_RC_UP | BS3_MXCSR_PE_FUZZY /* IEM */ },
           { { /*src1     */ { FP64_DENORM_MIN(0),  FP64_DENORM_MAX(0),              FP64_DENORM_MIN(1), FP64_DENORM_MAX(1) } },
             { /*unused   */ { FP64_ROW_UNUSED } },
             { /* =>      */ { FP64_V(0,0x0,0x1e6), FP64_V(0,0xffffffffffffe,0x1ff), FP64_QNAN(1),       FP64_QNAN(1)       } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_DOWN,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_RC_DOWN,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_IE | X86_MXCSR_PE | X86_MXCSR_RC_DOWN | BS3_MXCSR_PE_FUZZY /* IEM */ },
+              /*mxcsr:in */ X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_RC_DOWN,
+              /*256:out  */ X86_MXCSR_DE | X86_MXCSR_IE | X86_MXCSR_PE | X86_MXCSR_RC_DOWN | BS3_MXCSR_PE_FUZZY /* IEM */ },
           { { /*src1     */ { FP64_DENORM_MIN(0),  FP64_DENORM_MAX(0),              FP64_DENORM_MIN(1), FP64_DENORM_MAX(1) } },
             { /*unused   */ { FP64_ROW_UNUSED } },
             { /* =>      */ { FP64_V(0,0x0,0x1e6), FP64_V(0,0xffffffffffffe,0x1ff), FP64_QNAN(1),       FP64_QNAN(1)       } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_RC_ZERO,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_IE | X86_MXCSR_PE | X86_MXCSR_RC_ZERO | BS3_MXCSR_PE_FUZZY /* IEM */ },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_DE | X86_MXCSR_IE | X86_MXCSR_PE | X86_MXCSR_RC_ZERO | BS3_MXCSR_PE_FUZZY /* IEM */ },
           { { /*src1     */ { FP64_DENORM_MIN(0),  FP64_DENORM_MAX(0),              FP64_DENORM_MIN(1), FP64_DENORM_MAX(1) } },
             { /*unused   */ { FP64_ROW_UNUSED } },
             { /* =>      */ { FP64_V(0,0x0,0x1e6), FP64_V(0,0xfffffffffffff,0x1ff), FP64_QNAN(1),       FP64_QNAN(1)       } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_FZ,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DE | X86_MXCSR_IE | X86_MXCSR_PE | X86_MXCSR_FZ | BS3_MXCSR_PE_FUZZY /* IEM */ },
+              /*mxcsr:in */ X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_FZ,
+              /*256:out  */ X86_MXCSR_DE | X86_MXCSR_IE | X86_MXCSR_PE | X86_MXCSR_FZ | BS3_MXCSR_PE_FUZZY /* IEM */ },
           { { /*src1     */ { FP64_DENORM_MIN(0), FP64_DENORM_MAX(0), FP64_DENORM_MIN(1), FP64_DENORM_MAX(1) } },
             { /*unused   */ { FP64_ROW_UNUSED } },
             { /* =>      */ { FP64_0(0),          FP64_0(0),          FP64_0(1),          FP64_0(1),         } },
-              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
-              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ,
-              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ },
+              /*mxcsr:in */ X86_MXCSR_DAZ,
+              /*128:out  */ X86_MXCSR_DAZ,
+              /*256:out  */ X86_MXCSR_DAZ },
     /** @todo More Denormals. */
     /*
