- Timestamp:
- Oct 15, 2024 5:19:53 AM (6 weeks ago)
- Location:
- trunk/src/VBox/ValidationKit/bootsectors
- Files:
-
- 2 edited
-
bs3-cpu-instr-4-template.mac (modified) (3 diffs)
-
bs3-cpu-instr-4.c32 (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4-template.mac
r106306 r106316 664 664 ;; [v]sqrtps 665 665 ; 666 EMIT_INSTR_PLUS_ICEBP sqrtps, XMM1, XMM2667 EMIT_INSTR_PLUS_ICEBP sqrtps, XMM1, FSxBX668 EMIT_INSTR_PLUS_ICEBP_C64 sqrtps, XMM8, XMM9669 EMIT_INSTR_PLUS_ICEBP_C64 sqrtps, XMM8, FSxBX666 EMIT_INSTR_PLUS_ICEBP sqrtps, XMM1, XMM2 667 EMIT_INSTR_PLUS_ICEBP sqrtps, XMM1, FSxBX 668 EMIT_INSTR_PLUS_ICEBP_C64 sqrtps, XMM8, XMM9 669 EMIT_INSTR_PLUS_ICEBP_C64 sqrtps, XMM8, FSxBX 670 670 671 671 EMIT_INSTR_PLUS_ICEBP vsqrtps, XMM1, XMM2 … … 682 682 ;; [v]sqrtpd 683 683 ; 684 EMIT_INSTR_PLUS_ICEBP sqrtpd, XMM1, XMM2685 EMIT_INSTR_PLUS_ICEBP sqrtpd, XMM1, FSxBX686 EMIT_INSTR_PLUS_ICEBP_C64 sqrtpd, XMM8, XMM9687 EMIT_INSTR_PLUS_ICEBP_C64 sqrtpd, XMM8, FSxBX684 EMIT_INSTR_PLUS_ICEBP sqrtpd, XMM1, XMM2 685 EMIT_INSTR_PLUS_ICEBP sqrtpd, XMM1, FSxBX 686 EMIT_INSTR_PLUS_ICEBP_C64 sqrtpd, XMM8, XMM9 687 EMIT_INSTR_PLUS_ICEBP_C64 sqrtpd, XMM8, FSxBX 688 688 689 689 EMIT_INSTR_PLUS_ICEBP vsqrtpd, XMM1, XMM2 … … 735 735 EMIT_INSTR_PLUS_ICEBP vsqrtsd, XMM1, XMM1, FSxBX 736 736 737 ; 738 ;; [v]rsqrtps 739 ; 740 EMIT_INSTR_PLUS_ICEBP rsqrtps, XMM1, XMM2 741 EMIT_INSTR_PLUS_ICEBP rsqrtps, XMM1, FSxBX 742 EMIT_INSTR_PLUS_ICEBP_C64 rsqrtps, XMM8, XMM9 743 EMIT_INSTR_PLUS_ICEBP_C64 rsqrtps, XMM8, FSxBX 744 745 EMIT_INSTR_PLUS_ICEBP vrsqrtps, XMM1, XMM2 746 EMIT_INSTR_PLUS_ICEBP vrsqrtps, XMM1, FSxBX 747 EMIT_INSTR_PLUS_ICEBP_C64 vrsqrtps, XMM8, XMM9 748 EMIT_INSTR_PLUS_ICEBP_C64 vrsqrtps, XMM8, FSxBX 749 750 EMIT_INSTR_PLUS_ICEBP vrsqrtps, YMM1, YMM2 751 EMIT_INSTR_PLUS_ICEBP vrsqrtps, YMM1, FSxBX 752 EMIT_INSTR_PLUS_ICEBP_C64 vrsqrtps, YMM8, YMM9 753 EMIT_INSTR_PLUS_ICEBP_C64 vrsqrtps, YMM8, FSxBX 754 755 EMIT_INSTR_PLUS_ICEBP rsqrtps, XMM1, XMM1 756 EMIT_INSTR_PLUS_ICEBP vrsqrtps, XMM1, XMM1 757 EMIT_INSTR_PLUS_ICEBP vrsqrtps, YMM1, YMM1 758 737 759 %endif ; BS3_INSTANTIATING_CMN 738 760 -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32
r106306 r106316 15248 15248 15249 15249 15250 /* 15251 * [V]RSQRTPS. 15252 */ 15253 /** @todo this fails entirely under IEM: the instructions rcpps, rcpss, rsqrtps, rsqrtss, are all implemented with too much precision! */ 15254 BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_rsqrtps(uint8_t bMode) 15255 { 15256 static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValues[] = 15257 { 15258 /** @todo move these up with the rest of the value defines */ 15259 #define FP32_RSQRT_1_0 FP32_V(0, 0x7ff000, 0x7e) /* 1/sqrt(1) != 1, yay Intel */ 15260 #define FP32_RSQRT_2_0 FP32_V(0, 0x34f800, 0x7e) /* 1/sqrt(2) */ 15261 #define FP32_RSQRT_NORM_V0 FP32_V(0, 0x510000, 0xbd) /* 1/sqrt(NORM_V0) */ 15262 #define FP32_RSQRT_NORM_V1 FP32_V(0, 0x419800, 0x66) /* 1/sqrt(NORM_V1) */ 15263 #define FP32_RSQRT_NORM_V2 FP32_V(0, 0x35b800, 0x7f) /* 1/sqrt(NORM_V2) */ 15264 #define FP32_RSQRT_NORM_V3 FP32_V(0, 0x439000, 0x3f) /* 1/sqrt(NORM_V3) */ 15265 #define FP32_RSQRT_NORM_V4 FP32_V(0, 0x22e800, 0x60) /* 1/sqrt(NORM_V4) */ 15266 #define FP32_RSQRT_NORM_V5 FP32_V(0, 0x7ed000, 0x55) /* 1/sqrt(NORM_V5) */ 15267 #define FP32_RSQRT_NORM_V6 FP32_V(0, 0x191000, 0xa0) /* 1/sqrt(NORM_V6) */ 15268 #define FP32_RSQRT_NORM_V7 FP32_V(0, 0x350800, 0x95) /* 1/sqrt(NORM_V7) */ 15269 #define FP32_VAL_529_0 FP32_V(0, 0x044000, 0x88) /* 529.0 */ 15270 #define FP32_VAL_256_0 FP32_V(0, 0x000000, 0x87) /* 256.0 */ 15271 #define FP32_VAL_7q16sq FP32_V(0, 0x440000, 0x7c) /* (7/16)^2 */ 15272 #define FP32_VAL_123_75sq FP32_V(0, 0x6f4840, 0x8c) /* 123.75^2 */ 15273 #define FP32_VAL_528_0 FP32_V(0, 0x040000, 0x88) /* 528.0 */ 15274 #define FP32_VAL_257_0 FP32_V(0, 0x008000, 0x87) /* 257.0 */ 15275 #define FP32_VAL_7q16sq_d FP32_V(0, 0x43ffff, 0x7c) /* (7/16)^2 - epsilon */ 15276 #define FP32_VAL_123_75sq_e FP32_V(0, 0x6f4841, 0x8c) /* 123.75^2 + epsilon */ 15277 #define FP32_RSQRT_529_0 FP32_V(0, 0x320800, 0x7a) /* 1/23.0 */ 15278 #define FP32_RSQRT_256_0 FP32_V(0, 0x7ff000, 0x7a) /* 1/16.0 */ 15279 #define FP32_RSQRT_7q16sq FP32_V(0, 0x124000, 0x80) /* 1/(7/16) */ 15280 #define FP32_RSQRT_123_75sq FP32_V(0, 0x046000, 0x78) /* 1/123.75 */ 15281 #define FP32_RSQRT_528_0 FP32_V(0, 0x323800, 0x7a) /* 1/sqrt(528.0) */ 15282 #define FP32_RSQRT_257_0 FP32_V(0, 0x7f7000, 0x7a) /* 1/sqrt(257.0) */ 15283 #define FP32_RSQRT_7q16sq_d FP32_V(0, 0x125000, 0x80) /* 1/(7/16[DOWN]) */ 15284 #define FP32_RSQRT_123_75sq_e FP32_V(0, 0x046000, 0x78) /* 1/(123.75[!UP]) */ 15285 #define FP32_RSQRT_NORM_MAX FP32_V(0, 0x000800, 0x3f) /* 1/sqrt(NORM_MAX) */ 15286 #define FP32_RSQRT_NORM_MIN FP32_V(0, 0x7ff000, 0xbd) /* 1/sqrt(NORM_MIN) */ 15287 #define FP32_RSQRT_NS_INT_MAX FP32_V(0, 0x000800, 0x73) /* 1/sqrt(NORM_SAFE_INT_MAX) */ 15288 #define FP32_RSQRT_NS_INT_MIN FP32_V(0, 0x7ff000, 0xbd) /* 1/sqrt(NORM_SAFE_INT_MIN) */ 15289 /* 15290 * Zero. 15291 */ 15292 /* 0*/{ { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1) } }, 15293 { /*unused */ { FP32_ROW_UNUSED } }, 15294 { /* => */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1) } }, 15295 /*mxcsr:in */ 0, 15296 /*128:out */ 0, 15297 /*256:out */ 0 }, 15298 { { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1) } }, 15299 { /*unused */ { FP32_ROW_UNUSED } }, 15300 { /* => */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1) } }, 15301 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 15302 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 15303 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP }, 15304 { { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1) } }, 15305 { /*unused */ { FP32_ROW_UNUSED } }, 15306 { /* => */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1) } }, 15307 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 15308 /*128:out */ X86_MXCSR_RC_ZERO, 15309 /*256:out */ X86_MXCSR_RC_ZERO }, 15310 { { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1) } }, 15311 { /*unused */ { FP32_ROW_UNUSED } }, 15312 { /* => */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1) } }, 15313 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 15314 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 15315 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN }, 15316 /* 15317 * Infinity. 15318 */ 15319 /* 4*/{ { /*src1 */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0) } }, 15320 { /*unused */ { FP32_ROW_UNUSED } }, 15321 { /* => */ { FP32_0(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_QNAN(1), FP32_INF(0), FP32_INF(0), FP32_INF(0) } }, 15322 /*mxcsr:in */ 0, 15323 /*128:out */ 0, 15324 /*256:out */ 0 }, 15325 /* 15326 * Precision, Overflow, Underflow not possible. 15327 */ 15328 /* 5*/{ { /*src1 */ { FP32_0(0), FP32_1(0), FP32_1(0), FP32_0(1), FP32_1(0), FP32_0(0), FP32_1(0), FP32_2(0) } }, 15329 { /*unused */ { FP32_ROW_UNUSED } }, 15330 { /* => */ { FP32_INF(0), FP32_RSQRT_1_0, FP32_RSQRT_1_0, FP32_INF(1), FP32_RSQRT_1_0, FP32_INF(0), FP32_RSQRT_1_0, FP32_RSQRT_2_0 } }, 15331 /*mxcsr:in */ 0, 15332 /*128:out */ 0, 15333 /*256:out */ 0 }, 15334 { { /*src1 */ { FP32_0(0), FP32_1(0), FP32_1(0), FP32_0(1), FP32_1(0), FP32_0(0), FP32_1(0), FP32_2(0) } }, 15335 { /*unused */ { FP32_ROW_UNUSED } }, 15336 { /* => */ { FP32_INF(0), FP32_RSQRT_1_0, FP32_RSQRT_1_0, FP32_INF(1), FP32_RSQRT_1_0, FP32_INF(0), FP32_RSQRT_1_0, FP32_RSQRT_2_0 } }, 15337 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 15338 /*128:out */ X86_MXCSR_RC_DOWN, 15339 /*256:out */ X86_MXCSR_RC_DOWN }, 15340 { { /*src1 */ { FP32_0(0), FP32_1(0), FP32_1(0), FP32_0(1), FP32_1(0), FP32_0(0), FP32_1(0), FP32_2(0) } }, 15341 { /*unused */ { FP32_ROW_UNUSED } }, 15342 { /* => */ { FP32_INF(0), FP32_RSQRT_1_0, FP32_RSQRT_1_0, FP32_INF(1), FP32_RSQRT_1_0, FP32_INF(0), FP32_RSQRT_1_0, FP32_RSQRT_2_0 } }, 15343 /*mxcsr:in */ X86_MXCSR_RC_UP, 15344 /*128:out */ X86_MXCSR_RC_UP, 15345 /*256:out */ X86_MXCSR_RC_UP }, 15346 { { /*src1 */ { FP32_0(0), FP32_1(0), FP32_1(0), FP32_0(1), FP32_1(0), FP32_0(0), FP32_1(0), FP32_2(0) } }, 15347 { /*unused */ { FP32_ROW_UNUSED } }, 15348 { /* => */ { FP32_INF(0), FP32_RSQRT_1_0, FP32_RSQRT_1_0, FP32_INF(1), FP32_RSQRT_1_0, FP32_INF(0), FP32_RSQRT_1_0, FP32_RSQRT_2_0 } }, 15349 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 15350 /*128:out */ X86_MXCSR_RC_ZERO, 15351 /*256:out */ X86_MXCSR_RC_ZERO }, 15352 { { /*src1 */ { FP32_0(0), FP32_1(0), FP32_1(0), FP32_0(1), FP32_1(0), FP32_0(0), FP32_1(0), FP32_2(0) } }, 15353 { /*unused */ { FP32_ROW_UNUSED } }, 15354 { /* => */ { FP32_INF(0), FP32_RSQRT_1_0, FP32_RSQRT_1_0, FP32_INF(1), FP32_RSQRT_1_0, FP32_INF(0), FP32_RSQRT_1_0, FP32_RSQRT_2_0 } }, 15355 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_DAZ, 15356 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_DAZ, 15357 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_DAZ }, 15358 /* 15359 * Normals. 15360 */ 15361 /*10*/{ { /*src1 */ { FP32_NORM_V0(0), FP32_NORM_V1(0), FP32_NORM_V2(0), FP32_NORM_V3(0), FP32_NORM_V4(0), FP32_NORM_V5(0), FP32_NORM_V6(0), FP32_NORM_V7(0) } }, 15362 { /*unused */ { FP32_ROW_UNUSED } }, 15363 { /* => */ { FP32_RSQRT_NORM_V0, FP32_RSQRT_NORM_V1, FP32_RSQRT_NORM_V2, FP32_RSQRT_NORM_V3, FP32_RSQRT_NORM_V4, FP32_RSQRT_NORM_V5, FP32_RSQRT_NORM_V6, FP32_RSQRT_NORM_V7 } }, 15364 /*mxcsr:in */ 0, 15365 /*128:out */ 0, 15366 /*256:out */ 0 }, 15367 { { /*src1 */ { FP32_VAL_529_0, FP32_VAL_256_0, FP32_VAL_7q16sq, FP32_VAL_123_75sq, FP32_VAL_528_0, FP32_VAL_257_0, FP32_VAL_7q16sq_d, FP32_VAL_123_75sq_e } }, 15368 { /*unused */ { FP32_ROW_UNUSED } }, 15369 { /* => */ { FP32_RSQRT_529_0, FP32_RSQRT_256_0, FP32_RSQRT_7q16sq, FP32_RSQRT_123_75sq, FP32_RSQRT_528_0, FP32_RSQRT_257_0, FP32_RSQRT_7q16sq_d, FP32_RSQRT_123_75sq_e } }, 15370 /*mxcsr:in */ 0, 15371 /*128:out */ 0, 15372 /*256:out */ 0 }, 15373 { { /*src1 */ { FP32_VAL_529_0, FP32_VAL_256_0, FP32_VAL_7q16sq, FP32_VAL_123_75sq, FP32_VAL_528_0, FP32_VAL_257_0, FP32_VAL_7q16sq_d, FP32_VAL_123_75sq_e } }, 15374 { /*unused */ { FP32_ROW_UNUSED } }, 15375 { /* => */ { FP32_RSQRT_529_0, FP32_RSQRT_256_0, FP32_RSQRT_7q16sq, FP32_RSQRT_123_75sq, FP32_RSQRT_528_0, FP32_RSQRT_257_0, FP32_RSQRT_7q16sq_d, FP32_RSQRT_123_75sq_e } }, 15376 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 15377 /*128:out */ X86_MXCSR_RC_DOWN, 15378 /*256:out */ X86_MXCSR_RC_DOWN }, 15379 { { /*src1 */ { FP32_VAL_529_0, FP32_VAL_256_0, FP32_VAL_7q16sq, FP32_VAL_123_75sq, FP32_VAL_528_0, FP32_VAL_257_0, FP32_VAL_7q16sq_d, FP32_VAL_123_75sq_e } }, 15380 { /*unused */ { FP32_ROW_UNUSED } }, 15381 { /* => */ { FP32_RSQRT_529_0, FP32_RSQRT_256_0, FP32_RSQRT_7q16sq, FP32_RSQRT_123_75sq, FP32_RSQRT_528_0, FP32_RSQRT_257_0, FP32_RSQRT_7q16sq_d, FP32_RSQRT_123_75sq_e } }, 15382 /*mxcsr:in */ X86_MXCSR_RC_UP, 15383 /*128:out */ X86_MXCSR_RC_UP, 15384 /*256:out */ X86_MXCSR_RC_UP }, 15385 { { /*src1 */ { FP32_VAL_529_0, FP32_VAL_256_0, FP32_VAL_7q16sq, FP32_VAL_123_75sq, FP32_VAL_528_0, FP32_VAL_257_0, FP32_VAL_7q16sq_d, FP32_VAL_123_75sq_e } }, 15386 { /*unused */ { FP32_ROW_UNUSED } }, 15387 { /* => */ { FP32_RSQRT_529_0, FP32_RSQRT_256_0, FP32_RSQRT_7q16sq, FP32_RSQRT_123_75sq, FP32_RSQRT_528_0, FP32_RSQRT_257_0, FP32_RSQRT_7q16sq_d, FP32_RSQRT_123_75sq_e } }, 15388 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 15389 /*128:out */ X86_MXCSR_RC_ZERO, 15390 /*256:out */ X86_MXCSR_RC_ZERO }, 15391 { { /*src1 */ { FP32_NORM_MAX(0), FP32_NORM_MIN(0), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_MAX(1), FP32_NORM_MIN(1), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MIN(1) } }, 15392 { /*unused */ { FP32_ROW_UNUSED } }, 15393 { /* => */ { FP32_RSQRT_NORM_MAX, FP32_RSQRT_NORM_MIN, FP32_RSQRT_NS_INT_MAX, FP32_RSQRT_NS_INT_MIN, FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1) } }, 15394 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 15395 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 15396 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ }, 15397 /* 15398 * Denormals. 15399 */ 15400 /*16*/{ { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(1), FP32_DENORM_MAX(1), FP32_DENORM_MAX(1), FP32_0(1), FP32_0(0) } }, 15401 { /*unused */ { FP32_ROW_UNUSED } }, 15402 { /* => */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(0) } }, 15403 /*mxcsr:in */ 0, 15404 /*128:out */ 0, 15405 /*256:out */ 0 }, 15406 { { /*src1 */ { FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_0(0), FP32_0(1), FP32_DENORM_MIN(1), FP32_DENORM_MIN(1), FP32_0(1), FP32_0(0) } }, 15407 { /*unused */ { FP32_ROW_UNUSED } }, 15408 { /* => */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(0) } }, 15409 /*mxcsr:in */ 0, 15410 /*128:out */ 0, 15411 /*256:out */ 0 }, 15412 { { /*src1 */ { FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(1), FP32_DENORM_MIN(1), FP32_DENORM_MAX(1), FP32_0(1), FP32_0(0) } }, 15413 { /*unused */ { FP32_ROW_UNUSED } }, 15414 { /* => */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(0) } }, 15415 /*mxcsr:in */ X86_MXCSR_RC_UP, 15416 /*128:out */ X86_MXCSR_RC_UP, 15417 /*256:out */ X86_MXCSR_RC_UP }, 15418 { { /*src1 */ { FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(1), FP32_DENORM_MIN(1), FP32_DENORM_MAX(1), FP32_0(1), FP32_0(0) } }, 15419 { /*unused */ { FP32_ROW_UNUSED } }, 15420 { /* => */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(0) } }, 15421 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 15422 /*128:out */ X86_MXCSR_RC_DOWN, 15423 /*256:out */ X86_MXCSR_RC_DOWN }, 15424 { { /*src1 */ { FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(1), FP32_DENORM_MIN(1), FP32_DENORM_MAX(1), FP32_0(1), FP32_0(0) } }, 15425 { /*unused */ { FP32_ROW_UNUSED } }, 15426 { /* => */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(0) } }, 15427 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 15428 /*128:out */ X86_MXCSR_RC_ZERO, 15429 /*256:out */ X86_MXCSR_RC_ZERO }, 15430 { { /*src1 */ { FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_0(0), FP32_0(1), FP32_DENORM_MIN(1), FP32_DENORM_MAX(1), FP32_0(1), FP32_0(0) } }, 15431 { /*unused */ { FP32_ROW_UNUSED } }, 15432 { /* => */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(1), FP32_INF(0) } }, 15433 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_DAZ, 15434 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_DAZ, 15435 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_DAZ }, 15436 /* 15437 * Invalids. 15438 */ 15439 /** @todo Invalids. */ 15440 /*22*/ /* FP32_TABLE_D10_PS_INVALIDS */ 15441 }; 15442 15443 #define PASS_s_aValues RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues 15444 static BS3CPUINSTR4_TEST1_T const s_aTests16[] = 15445 { 15446 { bs3CpuInstr4_rsqrtps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, PASS_s_aValues }, 15447 { bs3CpuInstr4_rsqrtps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, PASS_s_aValues }, 15448 15449 { bs3CpuInstr4_vrsqrtps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, PASS_s_aValues }, 15450 { bs3CpuInstr4_vrsqrtps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_128, 1, 1, 255, PASS_s_aValues }, 15451 15452 { bs3CpuInstr4_vrsqrtps_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 1, 2, PASS_s_aValues }, 15453 { bs3CpuInstr4_vrsqrtps_YMM1_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_256, 1, 1, 255, PASS_s_aValues }, 15454 15455 { bs3CpuInstr4_rsqrtps_XMM1_XMM1_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 1, PASS_s_aValues }, 15456 { bs3CpuInstr4_vrsqrtps_XMM1_XMM1_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 1, PASS_s_aValues }, 15457 { bs3CpuInstr4_vrsqrtps_YMM1_YMM1_icebp_c16, 255, RM_REG, T_AVX_256, 1, 1, 1, PASS_s_aValues }, 15458 }; 15459 static BS3CPUINSTR4_TEST1_T const s_aTests32[] = 15460 { 15461 { bs3CpuInstr4_rsqrtps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, PASS_s_aValues }, 15462 { bs3CpuInstr4_rsqrtps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, PASS_s_aValues }, 15463 15464 { bs3CpuInstr4_vrsqrtps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, PASS_s_aValues }, 15465 { bs3CpuInstr4_vrsqrtps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_128, 1, 1, 255, PASS_s_aValues }, 15466 15467 { bs3CpuInstr4_vrsqrtps_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 1, 2, PASS_s_aValues }, 15468 { bs3CpuInstr4_vrsqrtps_YMM1_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_256, 1, 1, 255, PASS_s_aValues }, 15469 15470 { bs3CpuInstr4_rsqrtps_XMM1_XMM1_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 1, PASS_s_aValues }, 15471 { bs3CpuInstr4_vrsqrtps_XMM1_XMM1_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 1, PASS_s_aValues }, 15472 { bs3CpuInstr4_vrsqrtps_YMM1_YMM1_icebp_c32, 255, RM_REG, T_AVX_256, 1, 1, 1, PASS_s_aValues }, 15473 }; 15474 static BS3CPUINSTR4_TEST1_T const s_aTests64[] = 15475 { 15476 { bs3CpuInstr4_rsqrtps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, PASS_s_aValues }, 15477 { bs3CpuInstr4_rsqrtps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, PASS_s_aValues }, 15478 15479 { bs3CpuInstr4_vrsqrtps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, PASS_s_aValues }, 15480 { bs3CpuInstr4_vrsqrtps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 1, 1, 255, PASS_s_aValues }, 15481 15482 { bs3CpuInstr4_vrsqrtps_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 1, 2, PASS_s_aValues }, 15483 { bs3CpuInstr4_vrsqrtps_YMM1_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 1, 1, 255, PASS_s_aValues }, 15484 15485 { bs3CpuInstr4_rsqrtps_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, PASS_s_aValues }, 15486 { bs3CpuInstr4_rsqrtps_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 8, 8, 255, PASS_s_aValues }, 15487 15488 { bs3CpuInstr4_vrsqrtps_XMM8_XMM9_icebp_c64, 255, RM_REG, T_AVX_128, 8, 8, 9, PASS_s_aValues }, 15489 { bs3CpuInstr4_vrsqrtps_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 8, 8, 255, PASS_s_aValues }, 15490 { bs3CpuInstr4_vrsqrtps_YMM8_YMM9_icebp_c64, 255, RM_REG, T_AVX_256, 8, 8, 9, PASS_s_aValues }, 15491 { bs3CpuInstr4_vrsqrtps_YMM8_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 8, 8, 255, PASS_s_aValues }, 15492 15493 { bs3CpuInstr4_rsqrtps_XMM1_XMM1_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 1, PASS_s_aValues }, 15494 { bs3CpuInstr4_vrsqrtps_XMM1_XMM1_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 1, PASS_s_aValues }, 15495 { bs3CpuInstr4_vrsqrtps_YMM1_YMM1_icebp_c64, 255, RM_REG, T_AVX_256, 1, 1, 1, PASS_s_aValues }, 15496 }; 15497 #undef PASS_s_aValues 15498 15499 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 15500 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode); 15501 return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 15502 g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2)); 15503 } 15504 15505 15250 15506 /** 15251 15507 * The 32-bit protected mode main function. … … 15303 15559 { "[v]sqrtss", bs3CpuInstr4_v_sqrtss, 0 }, 15304 15560 { "[v]sqrtsd", bs3CpuInstr4_v_sqrtsd, 0 }, 15561 { "[v]rsqrtps", bs3CpuInstr4_v_rsqrtps, 0 }, 15305 15562 #endif 15306 15563 };
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