Changeset 106317 in vbox for trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32

Timestamp:

Oct 15, 2024 5:50:07 AM (6 weeks ago)

Author:

vboxsync

Message:

ValidationKit/bootsectors: Implement SIMD FP testcases for [v]sqrtss, [v]sqrtsd: same-register forms; bugref:10658

File:

• trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32 (modified) (6 diffs)

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32

@@ -14090 +14090 @@
         { bs3CpuInstr4_vsqrtps_YMM1_YMM2_icebp_c16,  255, RM_REG, T_AVX_256, 1, 1, 2,   PASS_s_aValues },
         { bs3CpuInstr4_vsqrtps_YMM1_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_256, 1, 1, 255, PASS_s_aValues },
+
+        { bs3CpuInstr4_sqrtps_XMM1_XMM1_icebp_c16,   255, RM_REG, T_SSE,     1, 1, 1,   PASS_s_aValues },
+        { bs3CpuInstr4_vsqrtps_XMM1_XMM1_icebp_c16,  255, RM_REG, T_AVX_128, 1, 1, 1,   PASS_s_aValues },
+        { bs3CpuInstr4_vsqrtps_YMM1_YMM1_icebp_c16,  255, RM_REG, T_AVX_256, 1, 1, 1,   PASS_s_aValues },
     };
     static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
@@ -14101 +14105 @@
         { bs3CpuInstr4_vsqrtps_YMM1_YMM2_icebp_c32,  255, RM_REG, T_AVX_256, 1, 1, 2,   PASS_s_aValues },
         { bs3CpuInstr4_vsqrtps_YMM1_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_256, 1, 1, 255, PASS_s_aValues },
+
+        { bs3CpuInstr4_sqrtps_XMM1_XMM1_icebp_c32,   255, RM_REG, T_SSE,     1, 1, 1,   PASS_s_aValues },
+        { bs3CpuInstr4_vsqrtps_XMM1_XMM1_icebp_c32,  255, RM_REG, T_AVX_128, 1, 1, 1,   PASS_s_aValues },
+        { bs3CpuInstr4_vsqrtps_YMM1_YMM1_icebp_c32,  255, RM_REG, T_AVX_256, 1, 1, 1,   PASS_s_aValues },
     };
     static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
@@ -14120 +14128 @@
         { bs3CpuInstr4_vsqrtps_YMM8_YMM9_icebp_c64,  255, RM_REG, T_AVX_256, 8, 8, 9,   PASS_s_aValues },
         { bs3CpuInstr4_vsqrtps_YMM8_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 8, 8, 255, PASS_s_aValues },
+
+        { bs3CpuInstr4_sqrtps_XMM1_XMM1_icebp_c64,   255, RM_REG, T_SSE,     1, 1, 1,   PASS_s_aValues },
+        { bs3CpuInstr4_vsqrtps_XMM1_XMM1_icebp_c64,  255, RM_REG, T_AVX_128, 1, 1, 1,   PASS_s_aValues },
+        { bs3CpuInstr4_vsqrtps_YMM1_YMM1_icebp_c64,  255, RM_REG, T_AVX_256, 1, 1, 1,   PASS_s_aValues },
     };
 #undef PASS_s_aValues
@@ -14344 +14356 @@
         { bs3CpuInstr4_vsqrtpd_YMM1_YMM2_icebp_c16,  255, RM_REG, T_AVX_256, 1, 1, 2,   PASS_s_aValues },
         { bs3CpuInstr4_vsqrtpd_YMM1_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_256, 1, 1, 255, PASS_s_aValues },
+
+        { bs3CpuInstr4_sqrtpd_XMM1_XMM1_icebp_c16,   255, RM_REG, T_SSE,     1, 1, 1,   PASS_s_aValues },
+        { bs3CpuInstr4_vsqrtpd_XMM1_XMM1_icebp_c16,  255, RM_REG, T_AVX_128, 1, 1, 1,   PASS_s_aValues },
+        { bs3CpuInstr4_vsqrtpd_YMM1_YMM1_icebp_c16,  255, RM_REG, T_AVX_256, 1, 1, 1,   PASS_s_aValues },
     };
     static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
@@ -14355 +14371 @@
         { bs3CpuInstr4_vsqrtpd_YMM1_YMM2_icebp_c32,  255, RM_REG, T_AVX_256, 1, 1, 2,   PASS_s_aValues },
         { bs3CpuInstr4_vsqrtpd_YMM1_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_256, 1, 1, 255, PASS_s_aValues },
+
+        { bs3CpuInstr4_sqrtpd_XMM1_XMM1_icebp_c32,   255, RM_REG, T_SSE,     1, 1, 1,   PASS_s_aValues },
+        { bs3CpuInstr4_vsqrtpd_XMM1_XMM1_icebp_c32,  255, RM_REG, T_AVX_128, 1, 1, 1,   PASS_s_aValues },
+        { bs3CpuInstr4_vsqrtpd_YMM1_YMM1_icebp_c32,  255, RM_REG, T_AVX_256, 1, 1, 1,   PASS_s_aValues },
     };
     static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
@@ -14374 +14394 @@
         { bs3CpuInstr4_vsqrtpd_YMM8_YMM9_icebp_c64,  255, RM_REG, T_AVX_256, 8, 8, 9,   PASS_s_aValues },
         { bs3CpuInstr4_vsqrtpd_YMM8_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 8, 8, 255, PASS_s_aValues },
+
+        { bs3CpuInstr4_sqrtpd_XMM1_XMM1_icebp_c64,   255, RM_REG, T_SSE,     1, 1, 1,   PASS_s_aValues },
+        { bs3CpuInstr4_vsqrtpd_XMM1_XMM1_icebp_c64,  255, RM_REG, T_AVX_128, 1, 1, 1,   PASS_s_aValues },
+        { bs3CpuInstr4_vsqrtpd_YMM1_YMM1_icebp_c64,  255, RM_REG, T_AVX_256, 1, 1, 1,   PASS_s_aValues },
     };
 #undef PASS_s_aValues