Changeset 106330 in vbox
- Timestamp:
- Oct 15, 2024 2:20:09 PM (6 weeks ago)
- Location:
- trunk/src/VBox/ValidationKit/bootsectors
- Files:
-
- 2 edited
-
bs3-cpu-instr-4-template.mac (modified) (1 diff)
-
bs3-cpu-instr-4.c32 (modified) (88 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4-template.mac
r106317 r106330 661 661 EMIT_INSTR_PLUS_ICEBP_C64 vrcpss, XMM13, XMM14, FSxBX 662 662 663 EMIT_INSTR_PLUS_ICEBP rcpss, XMM1, XMM1 664 EMIT_INSTR_PLUS_ICEBP vrcpss, XMM1, XMM1, XMM1 665 EMIT_INSTR_PLUS_ICEBP vrcpss, XMM1, XMM1, XMM2 666 EMIT_INSTR_PLUS_ICEBP vrcpss, XMM1, XMM2, XMM2 667 EMIT_INSTR_PLUS_ICEBP vrcpss, XMM1, XMM1, FSxBX 668 EMIT_INSTR_PLUS_ICEBP_C64 vrcpss, XMM15, XMM15, XMM15 669 EMIT_INSTR_PLUS_ICEBP_C64 vrcpss, XMM15, XMM15, XMM13 670 EMIT_INSTR_PLUS_ICEBP_C64 vrcpss, XMM13, XMM14, XMM14 671 663 672 ; 664 673 ;; [v]sqrtps -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32
r106317 r106330 2302 2302 #ifdef DEBUG_ramshankar 2303 2303 # undef BS3_SKIPIT_AVG_SKIP 2304 # define BS3_SKIPIT_AVG_SKIP 802304 # define BS3_SKIPIT_AVG_SKIP 66 2305 2305 #endif 2306 2306 … … 13290 13290 */ 13291 13291 /* 6*/{ { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V1 } }, 13292 { /* unused*/ { FP32_RAND_V2(0), FP32_RAND_x7_V0 } },13292 { /*src2 */ { FP32_RAND_V2(0), FP32_RAND_x7_V0 } }, 13293 13293 { /* => */ { FP32_0(0), FP32_RAND_x7_V0 } }, 13294 13294 /*mxcsr:in */ 0, … … 13296 13296 /*256:out */ -1 }, 13297 13297 { { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V3 } }, 13298 { /* unused*/ { FP32_RAND_V2(0), FP32_RAND_x7_V1 } },13298 { /*src2 */ { FP32_RAND_V2(0), FP32_RAND_x7_V1 } }, 13299 13299 { /* => */ { FP32_0(0), FP32_RAND_x7_V1 } }, 13300 13300 /*mxcsr:in */ X86_MXCSR_RC_ZERO, … … 13302 13302 /*256:out */ -1 }, 13303 13303 { { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V5 } }, 13304 { /* unused*/ { FP32_RAND_V2(0), FP32_RAND_x7_V3 } },13304 { /*src2 */ { FP32_RAND_V2(0), FP32_RAND_x7_V3 } }, 13305 13305 { /* => */ { FP32_0(0), FP32_RAND_x7_V3 } }, 13306 13306 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, … … 13308 13308 /*256:out */ -1 }, 13309 13309 { { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V6 } }, 13310 { /* unused*/ { FP32_RAND_V2(0), FP32_RAND_x7_V0 } },13310 { /*src2 */ { FP32_RAND_V2(0), FP32_RAND_x7_V0 } }, 13311 13311 { /* => */ { FP32_0(0), FP32_RAND_x7_V0 } }, 13312 13312 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, … … 13314 13314 /*256:out */ -1 }, 13315 13315 { { /*src1 */ { FP32_INF(1), FP32_RAND_x7_V6 } }, 13316 { /* unused*/ { FP32_RAND_V2(0), FP32_RAND_x7_V2 } },13316 { /*src2 */ { FP32_RAND_V2(0), FP32_RAND_x7_V2 } }, 13317 13317 { /* => */ { FP32_0(1), FP32_RAND_x7_V2 } }, 13318 13318 /*mxcsr:in */ X86_MXCSR_FZ, … … 13320 13320 /*256:out */ -1 }, 13321 13321 { { /*src1 */ { FP32_INF(1), FP32_RAND_x7_V5 } }, 13322 { /* unused*/ { FP32_RAND_V2(0), FP32_RAND_x7_V1 } },13322 { /*src2 */ { FP32_RAND_V2(0), FP32_RAND_x7_V1 } }, 13323 13323 { /* => */ { FP32_0(1), FP32_RAND_x7_V1 } }, 13324 13324 /*mxcsr:in */ X86_MXCSR_RC_ZERO, … … 13326 13326 /*256:out */ -1 }, 13327 13327 { { /*src1 */ { FP32_INF(1), FP32_RAND_x7_V6 } }, 13328 { /* unused*/ { FP32_RAND_V3(0), FP32_RAND_x7_V2 } },13328 { /*src2 */ { FP32_RAND_V3(0), FP32_RAND_x7_V2 } }, 13329 13329 { /* => */ { FP32_0(1), FP32_RAND_x7_V2 } }, 13330 13330 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, … … 13332 13332 /*256:out */ -1 }, 13333 13333 { { /*src1 */ { FP32_INF(1), FP32_RAND_x7_V3 } }, 13334 { /* unused*/ { FP32_RAND_V4(0), FP32_RAND_x7_V1 } },13334 { /*src2 */ { FP32_RAND_V4(0), FP32_RAND_x7_V1 } }, 13335 13335 { /* => */ { FP32_0(1), FP32_RAND_x7_V1 } }, 13336 13336 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, … … 13338 13338 /*256:out */ -1 }, 13339 13339 { { /*src1 */ { FP32_INF(1), FP32_RAND_x7_V6 } }, 13340 { /* unused*/ { FP32_RAND_V5(0), FP32_RAND_x7_V0 } },13340 { /*src2 */ { FP32_RAND_V5(0), FP32_RAND_x7_V0 } }, 13341 13341 { /* => */ { FP32_0(1), FP32_RAND_x7_V0 } }, 13342 13342 /*mxcsr:in */ X86_MXCSR_FZ, … … 13347 13347 */ 13348 13348 /*15*/{ { /*src1 */ { FP32_1(0), FP32_RAND_x7_V3 } }, 13349 { /* unused*/ { FP32_RAND_V3(0), FP32_RAND_x7_V2 } },13349 { /*src2 */ { FP32_RAND_V3(0), FP32_RAND_x7_V2 } }, 13350 13350 { /* => */ { FP32_V(0, 0x7ff000, RTFLOAT32U_EXP_BIAS - 1), FP32_RAND_x7_V2 } }, 13351 13351 /*mxcsr:in */ 0, … … 13353 13353 /*256:out */ -1 }, 13354 13354 { { /*src1 */ { FP32_1(0), FP32_RAND_x7_V3 } }, 13355 { /* unused*/ { FP32_RAND_V2(0), FP32_RAND_x7_V0 } },13355 { /*src2 */ { FP32_RAND_V2(0), FP32_RAND_x7_V0 } }, 13356 13356 { /* => */ { FP32_V(0, 0x7ff000, RTFLOAT32U_EXP_BIAS - 1), FP32_RAND_x7_V0 } }, 13357 13357 /*mxcsr:in */ X86_MXCSR_RC_DOWN, … … 13359 13359 /*256:out */ -1 }, 13360 13360 { { /*src1 */ { FP32_1(0), FP32_RAND_x7_V3 } }, 13361 { /* unused*/ { FP32_RAND_V2(0), FP32_RAND_x7_V1 } },13361 { /*src2 */ { FP32_RAND_V2(0), FP32_RAND_x7_V1 } }, 13362 13362 { /* => */ { FP32_V(0, 0x7ff000, RTFLOAT32U_EXP_BIAS - 1), FP32_RAND_x7_V1 } }, 13363 13363 /*mxcsr:in */ X86_MXCSR_RC_UP, … … 13365 13365 /*256:out */ -1 }, 13366 13366 { { /*src1 */ { FP32_1(0), FP32_RAND_x7_V2 } }, 13367 { /* unused*/ { FP32_RAND_V1(0), FP32_RAND_x7_V6 } },13367 { /*src2 */ { FP32_RAND_V1(0), FP32_RAND_x7_V6 } }, 13368 13368 { /* => */ { FP32_V(0, 0x7ff000, RTFLOAT32U_EXP_BIAS - 1), FP32_RAND_x7_V6 } }, 13369 13369 /*mxcsr:in */ X86_MXCSR_RC_ZERO, … … 13371 13371 /*256:out */ -1 }, 13372 13372 { { /*src1 */ { FP32_V(0, 0x7fe800, RTFLOAT32U_EXP_BIAS - 2), FP32_RAND_x7_V2 } }, 13373 { /* unused*/ { FP32_RAND_V2(0), FP32_RAND_x7_V1 } },13373 { /*src2 */ { FP32_RAND_V2(0), FP32_RAND_x7_V1 } }, 13374 13374 { /* => */ { FP32_V(0, 4096, RTFLOAT32U_EXP_BIAS + 1), FP32_RAND_x7_V1 } }, 13375 13375 /*mxcsr:in */ 0, … … 13377 13377 /*256:out */ -1 }, 13378 13378 { { /*src1 */ { FP32_V(0, 0xc01, RTFLOAT32U_EXP_BIAS - 1), FP32_RAND_x7_V5 } }, 13379 { /* unused*/ { FP32_RAND_V2(0), FP32_RAND_x7_V4 } },13379 { /*src2 */ { FP32_RAND_V2(0), FP32_RAND_x7_V4 } }, 13380 13380 { /* => */ { FP32_V(0, FP32_FRAC_DENORM_MAX - 4095, RTFLOAT32U_EXP_BIAS), FP32_RAND_x7_V4 } }, 13381 13381 /*mxcsr:in */ 0, … … 13383 13383 /*256:out */ -1 }, 13384 13384 { { /*src1 */ { FP32_V(0, 0x7fe800, RTFLOAT32U_EXP_MAX - 3), FP32_RAND_x7_V5 } }, 13385 { /* unused*/ { FP32_RAND_V1(1), FP32_RAND_x7_V6 } },13385 { /*src2 */ { FP32_RAND_V1(1), FP32_RAND_x7_V6 } }, 13386 13386 { /* => */ { FP32_V(0, 4096, 1), FP32_RAND_x7_V6 } }, 13387 13387 /*mxcsr:in */ 0, … … 13389 13389 /*256:out */ -1 }, 13390 13390 { { /*src1 */ { FP32_V(0, 0x7fe800, RTFLOAT32U_EXP_MAX - 3), FP32_RAND_x7_V5 } }, 13391 { /* unused*/ { FP32_RAND_V1(1), FP32_RAND_x7_V6 } },13391 { /*src2 */ { FP32_RAND_V1(1), FP32_RAND_x7_V6 } }, 13392 13392 { /* => */ { FP32_V(0, 4096, 1), FP32_RAND_x7_V6 } }, 13393 13393 /*mxcsr:in */ X86_MXCSR_RC_UP, … … 13395 13395 /*256:out */ -1 }, 13396 13396 { { /*src1 */ { FP32_V(0, 0x7fe800, RTFLOAT32U_EXP_MAX - 3), FP32_RAND_x7_V5 } }, 13397 { /* unused*/ { FP32_RAND_V1(1), FP32_RAND_x7_V6 } },13397 { /*src2 */ { FP32_RAND_V1(1), FP32_RAND_x7_V6 } }, 13398 13398 { /* => */ { FP32_V(0, 4096, 1), FP32_RAND_x7_V6 } }, 13399 13399 /*mxcsr:in */ X86_MXCSR_RC_DOWN, … … 13401 13401 /*256:out */ -1 }, 13402 13402 { { /*src1 */ { FP32_V(0, 0xc01, RTFLOAT32U_EXP_MAX - 2), FP32_RAND_x7_V1 } }, 13403 { /* unused*/ { FP32_RAND_V2(1), FP32_RAND_x7_V1 } },13403 { /*src2 */ { FP32_RAND_V2(1), FP32_RAND_x7_V1 } }, 13404 13404 { /* => */ { FP32_0(0), FP32_RAND_x7_V1 } }, 13405 13405 /*mxcsr:in */ 0, … … 13407 13407 /*256:out */ -1 }, 13408 13408 { { /*src1 */ { FP32_V(0, 0xc01, RTFLOAT32U_EXP_MAX - 3), FP32_RAND_x7_V1 } }, 13409 { /* unused*/ { FP32_RAND_V2(1), FP32_RAND_x7_V6 } },13409 { /*src2 */ { FP32_RAND_V2(1), FP32_RAND_x7_V6 } }, 13410 13410 { /* => */ { FP32_V(0, 0x7ff000, 1), FP32_RAND_x7_V6 } }, 13411 13411 /*mxcsr:in */ 0, … … 13413 13413 /*256:out */ -1 }, 13414 13414 { { /*src1 */ { FP32_V(0, 0xc00, RTFLOAT32U_EXP_MAX - 2), FP32_RAND_x7_V0 } }, 13415 { /* unused*/ { FP32_RAND_V1(1), FP32_RAND_x7_V3 } },13415 { /*src2 */ { FP32_RAND_V1(1), FP32_RAND_x7_V3 } }, 13416 13416 { /* => */ { FP32_0(0), FP32_RAND_x7_V3 } }, 13417 13417 /*mxcsr:in */ 0, … … 13419 13419 /*256:out */ -1 }, 13420 13420 { { /*src1 */ { FP32_V(0, 0xc00, RTFLOAT32U_EXP_MAX - 2), FP32_RAND_x7_V0 } }, 13421 { /* unused*/ { FP32_RAND_V2(1), FP32_RAND_x7_V1 } },13421 { /*src2 */ { FP32_RAND_V2(1), FP32_RAND_x7_V1 } }, 13422 13422 { /* => */ { FP32_0(0), FP32_RAND_x7_V1 } }, 13423 13423 /*mxcsr:in */ X86_MXCSR_RC_DOWN, … … 13425 13425 /*256:out */ -1 }, 13426 13426 { { /*src1 */ { FP32_V(0, 0xc00, RTFLOAT32U_EXP_MAX - 2), FP32_RAND_x7_V2 } }, 13427 { /* unused*/ { FP32_RAND_V4(1), FP32_RAND_x7_V4 } },13427 { /*src2 */ { FP32_RAND_V4(1), FP32_RAND_x7_V4 } }, 13428 13428 { /* => */ { FP32_0(0), FP32_RAND_x7_V4 } }, 13429 13429 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, … … 13431 13431 /*256:out */ -1 }, 13432 13432 { { /*src1 */ { FP32_V(0, 0xc02, RTFLOAT32U_EXP_MAX - 2), FP32_RAND_x7_V3 } }, 13433 { /* unused*/ { FP32_RAND_V6(1), FP32_RAND_x7_V5 } },13433 { /*src2 */ { FP32_RAND_V6(1), FP32_RAND_x7_V5 } }, 13434 13434 { /* => */ { FP32_0(0), FP32_RAND_x7_V5 } }, 13435 13435 /*mxcsr:in */ 0, … … 13437 13437 /*256:out */ -1 }, 13438 13438 { { /*src1 */ { FP32_V(0, 0xc02, RTFLOAT32U_EXP_MAX - 2), FP32_RAND_x7_V1 } }, 13439 { /* unused*/ { FP32_RAND_V2(0), FP32_RAND_x7_V2 } },13439 { /*src2 */ { FP32_RAND_V2(0), FP32_RAND_x7_V2 } }, 13440 13440 { /* => */ { FP32_0(0), FP32_RAND_x7_V2 } }, 13441 13441 /*mxcsr:in */ X86_MXCSR_RC_DOWN, … … 13443 13443 /*256:out */ -1 }, 13444 13444 { { /*src1 */ { FP32_V(0, 0xc02, RTFLOAT32U_EXP_MAX - 2), FP32_RAND_x7_V0 } }, 13445 { /* unused*/ { FP32_RAND_V3(1), FP32_RAND_x7_V6 } },13445 { /*src2 */ { FP32_RAND_V3(1), FP32_RAND_x7_V6 } }, 13446 13446 { /* => */ { FP32_0(0), FP32_RAND_x7_V6 } }, 13447 13447 /*mxcsr:in */ X86_MXCSR_RC_UP, … … 13449 13449 /*256:out */ -1 }, 13450 13450 { { /*src1 */ { FP32_V(0, 0xc02, RTFLOAT32U_EXP_MAX - 2), FP32_RAND_x7_V3 } }, 13451 { /* unused*/ { FP32_RAND_V5(1), FP32_RAND_x7_V5 } },13451 { /*src2 */ { FP32_RAND_V5(1), FP32_RAND_x7_V5 } }, 13452 13452 { /* => */ { FP32_0(0), FP32_RAND_x7_V5 } }, 13453 13453 /*mxcsr:in */ X86_MXCSR_RC_ZERO, … … 13455 13455 /*256:out */ -1 }, 13456 13456 { { /*src1 */ { FP32_V(0, 0x7fe801, RTFLOAT32U_EXP_MAX - 3), FP32_RAND_x7_V7 } }, 13457 { /* unused*/ { FP32_RAND_V7(1), FP32_RAND_x7_V3 } },13457 { /*src2 */ { FP32_RAND_V7(1), FP32_RAND_x7_V3 } }, 13458 13458 { /* => */ { FP32_V(0, 4096, 1), FP32_RAND_x7_V3 } }, 13459 13459 /*mxcsr:in */ 0, … … 13461 13461 /*256:out */ -1 }, 13462 13462 { { /*src1 */ { FP32_V(0, 0x7fe801, RTFLOAT32U_EXP_MAX - 3), FP32_RAND_x7_V3 } }, 13463 { /* unused*/ { FP32_RAND_V4(1), FP32_RAND_x7_V4 } },13463 { /*src2 */ { FP32_RAND_V4(1), FP32_RAND_x7_V4 } }, 13464 13464 { /* => */ { FP32_V(0, 4096, 1), FP32_RAND_x7_V4 } }, 13465 13465 /*mxcsr:in */ X86_MXCSR_RC_UP, … … 13467 13467 /*256:out */ -1 }, 13468 13468 { { /*src1 */ { FP32_V(0, 0x7fe801, RTFLOAT32U_EXP_MAX - 3), FP32_RAND_x7_V2 } }, 13469 { /* unused*/ { FP32_RAND_V3(1), FP32_RAND_x7_V6 } },13469 { /*src2 */ { FP32_RAND_V3(1), FP32_RAND_x7_V6 } }, 13470 13470 { /* => */ { FP32_V(0, 4096, 1), FP32_RAND_x7_V6 } }, 13471 13471 /*mxcsr:in */ X86_MXCSR_RC_ZERO, … … 13473 13473 /*256:out */ -1 }, 13474 13474 { { /*src1 */ { FP32_V(0, 0x7fe801, RTFLOAT32U_EXP_MAX - 3), FP32_RAND_x7_V1 } }, 13475 { /* unused*/ { FP32_RAND_V2(1), FP32_RAND_x7_V0 } },13475 { /*src2 */ { FP32_RAND_V2(1), FP32_RAND_x7_V0 } }, 13476 13476 { /* => */ { FP32_V(0, 4096, 1), FP32_RAND_x7_V0 } }, 13477 13477 /*mxcsr:in */ X86_MXCSR_RC_DOWN, … … 13479 13479 /*256:out */ -1 }, 13480 13480 { { /*src1 */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_RAND_x7_V1 } }, 13481 { /* unused*/ { FP32_RAND_V3(1), FP32_RAND_x7_V3 } },13481 { /*src2 */ { FP32_RAND_V3(1), FP32_RAND_x7_V3 } }, 13482 13482 { /* => */ { FP32_V(0, 1343488, 106), FP32_RAND_x7_V3 } }, 13483 13483 /*mxcsr:in */ 0, … … 13485 13485 /*256:out */ -1 }, 13486 13486 { { /*src1 */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_RAND_x7_V1 } }, 13487 { /* unused*/ { FP32_RAND_V3(1), FP32_RAND_x7_V3 } },13487 { /*src2 */ { FP32_RAND_V3(1), FP32_RAND_x7_V3 } }, 13488 13488 { /* => */ { FP32_V(0, 1343488, 106), FP32_RAND_x7_V3 } }, 13489 13489 /*mxcsr:in */ X86_MXCSR_RC_DOWN, … … 13491 13491 /*256:out */ -1 }, 13492 13492 { { /*src1 */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_RAND_x7_V1 } }, 13493 { /* unused*/ { FP32_RAND_V3(1), FP32_RAND_x7_V3 } },13493 { /*src2 */ { FP32_RAND_V3(1), FP32_RAND_x7_V3 } }, 13494 13494 { /* => */ { FP32_V(0, 1343488, 106), FP32_RAND_x7_V3 } }, 13495 13495 /*mxcsr:in */ X86_MXCSR_RC_UP, … … 13497 13497 /*256:out */ -1 }, 13498 13498 { { /*src1 */ { FP32_V(0, 0x1ea980, 0x8f)/*81235*/, FP32_RAND_x7_V1 } }, 13499 { /* unused*/ { FP32_RAND_V2(0), FP32_RAND_x7_V3 } },13499 { /*src2 */ { FP32_RAND_V2(0), FP32_RAND_x7_V3 } }, 13500 13500 { /* => */ { FP32_V(0, 5146624, 110), FP32_RAND_x7_V3 } }, 13501 13501 /*mxcsr:in */ 0, … … 13503 13503 /*256:out */ -1 }, 13504 13504 { { /*src1 */ { FP32_V(0, 0x253468, 0x93)/*1353357*/, FP32_RAND_x7_V2 } }, 13505 { /* unused*/ { FP32_RAND_V3(0), FP32_RAND_x7_V0 } },13505 { /*src2 */ { FP32_RAND_V3(0), FP32_RAND_x7_V0 } }, 13506 13506 { /* => */ { FP32_V(0, 4610048, 106), FP32_RAND_x7_V0 } }, 13507 13507 /*mxcsr:in */ 0, … … 13509 13509 /*256:out */ -1 }, 13510 13510 { { /*src1 */ { FP32_V(0, 0x620b2d, 0x92)/*925874.8*/, FP32_RAND_x7_V4 } }, 13511 { /* unused*/ { FP32_RAND_V2(0), FP32_RAND_x7_V3 } },13511 { /*src2 */ { FP32_RAND_V2(0), FP32_RAND_x7_V3 } }, 13512 13512 { /* => */ { FP32_V(0, 1112064, 107), FP32_RAND_x7_V3 } }, 13513 13513 /*mxcsr:in */ 0, … … 13515 13515 /*256:out */ -1 }, 13516 13516 { { /*src1 */ { FP32_V(0, 0x620b2d, 0x92)/*925874.8*/, FP32_RAND_x7_V4 } }, 13517 { /* unused*/ { FP32_RAND_V2(0), FP32_RAND_x7_V3 } },13517 { /*src2 */ { FP32_RAND_V2(0), FP32_RAND_x7_V3 } }, 13518 13518 { /* => */ { FP32_V(0, 1112064, 107), FP32_RAND_x7_V3 } }, 13519 13519 /*mxcsr:in */ X86_MXCSR_RC_ZERO, … … 13521 13521 /*256:out */ -1 }, 13522 13522 { { /*src1 */ { FP32_V(0, 0x600000, 0x7e)/*0.875*/, FP32_RAND_x7_V4 } }, 13523 { /* unused*/ { FP32_RAND_V3(0), FP32_RAND_x7_V0 } },13523 { /*src2 */ { FP32_RAND_V3(0), FP32_RAND_x7_V0 } }, 13524 13524 { /* => */ { FP32_V(0, 1196032, 127), FP32_RAND_x7_V0 } }, 13525 13525 /*mxcsr:in */ 0, … … 13527 13527 /*256:out */ -1 }, 13528 13528 { { /*src1 */ { FP32_V(0, 0x490fda, 0x80)/*3.1415926*/, FP32_RAND_x7_V2 } }, 13529 { /* unused*/ { FP32_RAND_V1(0), FP32_RAND_x7_V3 } },13529 { /*src2 */ { FP32_RAND_V1(0), FP32_RAND_x7_V3 } }, 13530 13530 { /* => */ { FP32_V(0, 2293760, 125), FP32_RAND_x7_V3 } }, 13531 13531 /*mxcsr:in */ 0, … … 13533 13533 /*256:out */ -1 }, 13534 13534 { { /*src1 */ { FP32_V(0, 0x490fda, 0x80)/*3.1415926*/, FP32_RAND_x7_V2 } }, 13535 { /* unused*/ { FP32_RAND_V1(0), FP32_RAND_x7_V3 } },13535 { /*src2 */ { FP32_RAND_V1(0), FP32_RAND_x7_V3 } }, 13536 13536 { /* => */ { FP32_V(0, 2293760, 125), FP32_RAND_x7_V3 } }, 13537 13537 /*mxcsr:in */ X86_MXCSR_RC_UP, … … 13539 13539 /*256:out */ -1 }, 13540 13540 { { /*src1 */ { FP32_V(0, 0x490fda, 0x80)/*3.1415926*/, FP32_RAND_x7_V2 } }, 13541 { /* unused*/ { FP32_RAND_V1(0), FP32_RAND_x7_V0 } },13541 { /*src2 */ { FP32_RAND_V1(0), FP32_RAND_x7_V0 } }, 13542 13542 { /* => */ { FP32_V(0, 2293760, 125), FP32_RAND_x7_V0 } }, 13543 13543 /*mxcsr:in */ X86_MXCSR_RC_DOWN, … … 13545 13545 /*256:out */ -1 }, 13546 13546 { { /*src1 */ { FP32_V(1, 0, 0x7d)/*-0.250*/, FP32_RAND_x7_V6 } }, 13547 { /* unused*/ { FP32_RAND_V6(0), FP32_RAND_x7_V1 } },13547 { /*src2 */ { FP32_RAND_V6(0), FP32_RAND_x7_V1 } }, 13548 13548 { /* => */ { FP32_V(1, 8384512, 128), FP32_RAND_x7_V1 } }, 13549 13549 /*mxcsr:in */ 0, … … 13551 13551 /*256:out */ -1 }, 13552 13552 { { /*src1 */ { FP32_V(1, 0, 0x7d)/*-0.250*/, FP32_RAND_x7_V6 } }, 13553 { /* unused*/ { FP32_RAND_V3(1), FP32_RAND_x7_V1 } },13553 { /*src2 */ { FP32_RAND_V3(1), FP32_RAND_x7_V1 } }, 13554 13554 { /* => */ { FP32_V(1, 8384512, 128), FP32_RAND_x7_V1 } }, 13555 13555 /*mxcsr:in */ X86_MXCSR_RC_DOWN, … … 13557 13557 /*256:out */ -1 }, 13558 13558 { { /*src1 */ { FP32_V(1, 0x534000, 0x86)/*-211.25*/, FP32_RAND_x7_V2 } }, 13559 { /* unused*/ { FP32_RAND_V3(1), FP32_RAND_x7_V3 } },13559 { /*src2 */ { FP32_RAND_V3(1), FP32_RAND_x7_V3 } }, 13560 13560 { /* => */ { FP32_V(1, 1775616, 119), FP32_RAND_x7_V3 } }, 13561 13561 /*mxcsr:in */ 0, … … 13563 13563 /*256:out */ -1 }, 13564 13564 { { /*src1 */ { FP32_V(1, 0x534000, 0x86)/*-211.25*/, FP32_RAND_x7_V2 } }, 13565 { /* unused*/ { FP32_RAND_V3(1), FP32_RAND_x7_V3 } },13565 { /*src2 */ { FP32_RAND_V3(1), FP32_RAND_x7_V3 } }, 13566 13566 { /* => */ { FP32_V(1, 1775616, 119), FP32_RAND_x7_V3 } }, 13567 13567 /*mxcsr:in */ X86_MXCSR_RC_ZERO, … … 13572 13572 */ 13573 13573 /*15*/{ { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V7 } }, 13574 { /* unused*/ { FP32_RAND_V7(1), FP32_RAND_x7_V1 } },13574 { /*src2 */ { FP32_RAND_V7(1), FP32_RAND_x7_V1 } }, 13575 13575 { /* => */ { FP32_INF(0), FP32_RAND_x7_V1 } }, 13576 13576 /*mxcsr:in */ X86_MXCSR_XCPT_MASK, … … 13578 13578 /*256:out */ -1 }, 13579 13579 { { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V7 } }, 13580 { /* unused*/ { FP32_RAND_V7(1), FP32_RAND_x7_V1 } },13580 { /*src2 */ { FP32_RAND_V7(1), FP32_RAND_x7_V1 } }, 13581 13581 { /* => */ { FP32_INF(0), FP32_RAND_x7_V1 } }, 13582 13582 /*mxcsr:in */ X86_MXCSR_RC_UP, … … 13584 13584 /*256:out */ -1 }, 13585 13585 { { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V7 } }, 13586 { /* unused*/ { FP32_RAND_V7(1), FP32_RAND_x7_V1 } },13586 { /*src2 */ { FP32_RAND_V7(1), FP32_RAND_x7_V1 } }, 13587 13587 { /* => */ { FP32_INF(0), FP32_RAND_x7_V1 } }, 13588 13588 /*mxcsr:in */ X86_MXCSR_RC_DOWN, … … 13590 13590 /*256:out */ -1 }, 13591 13591 { { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V7 } }, 13592 { /* unused*/ { FP32_RAND_V7(1), FP32_RAND_x7_V1 } },13592 { /*src2 */ { FP32_RAND_V7(1), FP32_RAND_x7_V1 } }, 13593 13593 { /* => */ { FP32_INF(0), FP32_RAND_x7_V1 } }, 13594 13594 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, … … 13596 13596 /*256:out */ -1 }, 13597 13597 { { /*src1 */ { FP32_DENORM_MAX(1), FP32_RAND_x7_V6 } }, 13598 { /* unused*/ { FP32_RAND_V6(0), FP32_RAND_x7_V7 } },13598 { /*src2 */ { FP32_RAND_V6(0), FP32_RAND_x7_V7 } }, 13599 13599 { /* => */ { FP32_INF(1), FP32_RAND_x7_V7 } }, 13600 13600 /*mxcsr:in */ X86_MXCSR_RC_DOWN, … … 13602 13602 /*256:out */ -1 }, 13603 13603 { { /*src1 */ { FP32_DENORM_MAX(1), FP32_RAND_x7_V6 } }, 13604 { /* unused*/ { FP32_RAND_V6(0), FP32_RAND_x7_V7 } },13604 { /*src2 */ { FP32_RAND_V6(0), FP32_RAND_x7_V7 } }, 13605 13605 { /* => */ { FP32_INF(1), FP32_RAND_x7_V7 } }, 13606 13606 /*mxcsr:in */ X86_MXCSR_RC_UP, … … 13608 13608 /*256:out */ -1 }, 13609 13609 { { /*src1 */ { FP32_DENORM_MAX(1), FP32_RAND_x7_V6 } }, 13610 { /* unused*/ { FP32_RAND_V6(0), FP32_RAND_x7_V7 } },13610 { /*src2 */ { FP32_RAND_V6(0), FP32_RAND_x7_V7 } }, 13611 13611 { /* => */ { FP32_INF(1), FP32_RAND_x7_V7 } }, 13612 13612 /*mxcsr:in */ X86_MXCSR_RC_ZERO, … … 13614 13614 /*256:out */ -1 }, 13615 13615 { { /*src1 */ { FP32_DENORM_MIN(0), FP32_RAND_x7_V5 } }, 13616 { /* unused*/ { FP32_RAND_V5(0), FP32_RAND_x7_V6 } },13616 { /*src2 */ { FP32_RAND_V5(0), FP32_RAND_x7_V6 } }, 13617 13617 { /* => */ { FP32_INF(0), FP32_RAND_x7_V6 } }, 13618 13618 /*mxcsr:in */ X86_MXCSR_RC_ZERO, … … 13620 13620 /*256:out */ -1 }, 13621 13621 { { /*src1 */ { FP32_DENORM_MIN(0), FP32_RAND_x7_V4 } }, 13622 { /* unused*/ { FP32_RAND_V4(1), FP32_RAND_x7_V5 } },13622 { /*src2 */ { FP32_RAND_V4(1), FP32_RAND_x7_V5 } }, 13623 13623 { /* => */ { FP32_INF(0), FP32_RAND_x7_V5 } }, 13624 13624 /*mxcsr:in */ X86_MXCSR_RC_UP | X86_MXCSR_FZ, … … 13626 13626 /*256:out */ -1 }, 13627 13627 { { /*src1 */ { FP32_DENORM_MIN(1), FP32_RAND_x7_V5 } }, 13628 { /* unused*/ { FP32_RAND_V3(0), FP32_RAND_x7_V2 } },13628 { /*src2 */ { FP32_RAND_V3(0), FP32_RAND_x7_V2 } }, 13629 13629 { /* => */ { FP32_INF(1), FP32_RAND_x7_V2 } }, 13630 13630 /*mxcsr:in */ X86_MXCSR_RC_ZERO, … … 13632 13632 /*256:out */ -1 }, 13633 13633 { { /*src1 */ { FP32_DENORM_MIN(1), FP32_RAND_x7_V5 } }, 13634 { /* unused*/ { FP32_RAND_V3(0), FP32_RAND_x7_V2 } },13634 { /*src2 */ { FP32_RAND_V3(0), FP32_RAND_x7_V2 } }, 13635 13635 { /* => */ { FP32_INF(1), FP32_RAND_x7_V2 } }, 13636 13636 /*mxcsr:in */ X86_MXCSR_RC_UP, … … 13638 13638 /*256:out */ -1 }, 13639 13639 { { /*src1 */ { FP32_DENORM_MIN(1), FP32_RAND_x7_V5 } }, 13640 { /* unused*/ { FP32_RAND_V3(0), FP32_RAND_x7_V2 } },13640 { /*src2 */ { FP32_RAND_V3(0), FP32_RAND_x7_V2 } }, 13641 13641 { /* => */ { FP32_INF(1), FP32_RAND_x7_V2 } }, 13642 13642 /*mxcsr:in */ X86_MXCSR_RC_DOWN, … … 13644 13644 /*256:out */ -1 }, 13645 13645 { { /*src1 */ { FP32_DENORM_V0(0), FP32_RAND_x7_V3 } }, 13646 { /* unused*/ { FP32_RAND_V3(1), FP32_RAND_x7_V4 } },13646 { /*src2 */ { FP32_RAND_V3(1), FP32_RAND_x7_V4 } }, 13647 13647 { /* => */ { FP32_INF(0), FP32_RAND_x7_V4 } }, 13648 13648 /*mxcsr:in */ X86_MXCSR_RC_UP, … … 13650 13650 /*256:out */ -1 }, 13651 13651 { { /*src1 */ { FP32_DENORM_V0(1), FP32_RAND_x7_V2 } }, 13652 { /* unused*/ { FP32_RAND_V2(1), FP32_RAND_x7_V3 } },13652 { /*src2 */ { FP32_RAND_V2(1), FP32_RAND_x7_V3 } }, 13653 13653 { /* => */ { FP32_INF(1), FP32_RAND_x7_V3 } }, 13654 13654 /*mxcsr:in */ X86_MXCSR_RC_ZERO, … … 13656 13656 /*256:out */ -1 }, 13657 13657 { { /*src1 */ { FP32_DENORM_V7(1), FP32_RAND_x7_V1 } }, 13658 { /* unused*/ { FP32_RAND_V1(0), FP32_RAND_x7_V2 } },13658 { /*src2 */ { FP32_RAND_V1(0), FP32_RAND_x7_V2 } }, 13659 13659 { /* => */ { FP32_INF(1), FP32_RAND_x7_V2 } }, 13660 13660 /*mxcsr:in */ X86_MXCSR_RC_DOWN, … … 13662 13662 /*256:out */ -1 }, 13663 13663 { { /*src1 */ { FP32_DENORM_V7(1), FP32_RAND_x7_V1 } }, 13664 { /* unused*/ { FP32_RAND_V1(0), FP32_RAND_x7_V2 } },13664 { /*src2 */ { FP32_RAND_V1(0), FP32_RAND_x7_V2 } }, 13665 13665 { /* => */ { FP32_INF(1), FP32_RAND_x7_V2 } }, 13666 13666 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, … … 13668 13668 /*256:out */ -1 }, 13669 13669 { { /*src1 */ { FP32_DENORM_V7(1), FP32_RAND_x7_V0 } }, 13670 { /* unused*/ { FP32_RAND_V0(0), FP32_RAND_x7_V1 } },13670 { /*src2 */ { FP32_RAND_V0(0), FP32_RAND_x7_V1 } }, 13671 13671 { /* => */ { FP32_INF(1), FP32_RAND_x7_V1 } }, 13672 13672 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_DAZ, … … 13674 13674 /*256:out */ -1 }, 13675 13675 { { /*src1 */ { FP32_DENORM_V5(0), FP32_RAND_x7_V4 } }, 13676 { /* unused*/ { FP32_RAND_V0(0), FP32_RAND_x7_V3 } },13676 { /*src2 */ { FP32_RAND_V0(0), FP32_RAND_x7_V3 } }, 13677 13677 { /* => */ { FP32_INF(0), FP32_RAND_x7_V3 } }, 13678 13678 /*mxcsr:in */ X86_MXCSR_RC_ZERO, … … 13680 13680 /*256:out */ -1 }, 13681 13681 { { /*src1 */ { FP32_DENORM_V5(0), FP32_RAND_x7_V4 } }, 13682 { /* unused*/ { FP32_RAND_V0(0), FP32_RAND_x7_V2 } },13682 { /*src2 */ { FP32_RAND_V0(0), FP32_RAND_x7_V2 } }, 13683 13683 { /* => */ { FP32_INF(0), FP32_RAND_x7_V2 } }, 13684 13684 /*mxcsr:in */ X86_MXCSR_RC_DOWN, … … 13688 13688 * Invalids. 13689 13689 */ 13690 /* 23*/{ { /*src1 */ { FP32_SNAN(0), FP32_RAND_x7_V7 } },13691 { /* unused*/ { FP32_RAND_V0(0), FP32_RAND_x7_V0 } },13690 /*34*/{ { /*src1 */ { FP32_SNAN(0), FP32_RAND_x7_V7 } }, 13691 { /*src2 */ { FP32_RAND_V0(0), FP32_RAND_x7_V0 } }, 13692 13692 { /* => */ { FP32_QNAN_V(0, 1), FP32_RAND_x7_V0 } }, 13693 13693 /*mxcsr:in */ 0, … … 13695 13695 /*256:out */ -1 }, 13696 13696 { { /*src1 */ { FP32_SNAN(0), FP32_RAND_x7_V6 } }, 13697 { /* unused*/ { FP32_RAND_V1(0), FP32_RAND_x7_V1 } },13697 { /*src2 */ { FP32_RAND_V1(0), FP32_RAND_x7_V1 } }, 13698 13698 { /* => */ { FP32_QNAN_V(0, 1), FP32_RAND_x7_V1 } }, 13699 13699 /*mxcsr:in */ X86_MXCSR_RC_ZERO, … … 13701 13701 /*256:out */ -1 }, 13702 13702 { { /*src1 */ { FP32_SNAN(0), FP32_RAND_x7_V5 } }, 13703 { /* unused*/ { FP32_RAND_V2(0), FP32_RAND_x7_V2 } },13703 { /*src2 */ { FP32_RAND_V2(0), FP32_RAND_x7_V2 } }, 13704 13704 { /* => */ { FP32_QNAN_V(0, 1), FP32_RAND_x7_V2 } }, 13705 13705 /*mxcsr:in */ X86_MXCSR_RC_UP, … … 13707 13707 /*256:out */ -1 }, 13708 13708 { { /*src1 */ { FP32_SNAN(0), FP32_RAND_x7_V4 } }, 13709 { /* unused*/ { FP32_RAND_V3(0), FP32_RAND_x7_V3 } },13709 { /*src2 */ { FP32_RAND_V3(0), FP32_RAND_x7_V3 } }, 13710 13710 { /* => */ { FP32_QNAN_V(0, 1), FP32_RAND_x7_V3 } }, 13711 13711 /*mxcsr:in */ X86_MXCSR_RC_DOWN, … … 13713 13713 /*256:out */ -1 }, 13714 13714 { { /*src1 */ { FP32_SNAN(0), FP32_RAND_x7_V3 } }, 13715 { /* unused*/ { FP32_RAND_V4(0), FP32_RAND_x7_V4 } },13715 { /*src2 */ { FP32_RAND_V4(0), FP32_RAND_x7_V4 } }, 13716 13716 { /* => */ { FP32_QNAN_V(0, 1), FP32_RAND_x7_V4 } }, 13717 13717 /*mxcsr:in */ X86_MXCSR_DAZ, … … 13719 13719 /*256:out */ -1 }, 13720 13720 { { /*src1 */ { FP32_SNAN(0), FP32_RAND_x7_V2 } }, 13721 { /* unused*/ { FP32_RAND_V5(0), FP32_RAND_x7_V5 } },13721 { /*src2 */ { FP32_RAND_V5(0), FP32_RAND_x7_V5 } }, 13722 13722 { /* => */ { FP32_QNAN_V(0, 1), FP32_RAND_x7_V5 } }, 13723 13723 /*mxcsr:in */ X86_MXCSR_FZ, … … 13725 13725 /*256:out */ -1 }, 13726 13726 { { /*src1 */ { FP32_SNAN_V0(0), FP32_RAND_x7_V1 } }, 13727 { /* unused*/ { FP32_RAND_V6(0), FP32_RAND_x7_V6 } },13727 { /*src2 */ { FP32_RAND_V6(0), FP32_RAND_x7_V6 } }, 13728 13728 { /* => */ { FP32_QNAN_V0(0), FP32_RAND_x7_V6 } }, 13729 13729 /*mxcsr:in */ 0, … … 13731 13731 /*256:out */ -1 }, 13732 13732 { { /*src1 */ { FP32_SNAN(1), FP32_RAND_x7_V0 } }, 13733 { /* unused*/ { FP32_RAND_V7(0), FP32_RAND_x7_V7 } },13733 { /*src2 */ { FP32_RAND_V7(0), FP32_RAND_x7_V7 } }, 13734 13734 { /* => */ { FP32_QNAN_V(1, 1), FP32_RAND_x7_V7 } }, 13735 13735 /*mxcsr:in */ 0, … … 13737 13737 /*256:out */ -1 }, 13738 13738 { { /*src1 */ { FP32_SNAN_V1(0), FP32_RAND_x7_V1 } }, 13739 { /* unused*/ { FP32_RAND_V0(0), FP32_RAND_x7_V0 } },13739 { /*src2 */ { FP32_RAND_V0(0), FP32_RAND_x7_V0 } }, 13740 13740 { /* => */ { FP32_QNAN_V1(0), FP32_RAND_x7_V0 } }, 13741 13741 /*mxcsr:in */ X86_MXCSR_RC_ZERO, … … 13743 13743 /*256:out */ -1 }, 13744 13744 { { /*src1 */ { FP32_SNAN_V2(1), FP32_RAND_x7_V2 } }, 13745 { /* unused*/ { FP32_RAND_V1(1), FP32_RAND_x7_V1 } },13745 { /*src2 */ { FP32_RAND_V1(1), FP32_RAND_x7_V1 } }, 13746 13746 { /* => */ { FP32_QNAN_V2(1), FP32_RAND_x7_V1 } }, 13747 13747 /*mxcsr:in */ X86_MXCSR_RC_DOWN, … … 13749 13749 /*256:out */ -1 }, 13750 13750 { { /*src1 */ { FP32_SNAN_V3(1), FP32_RAND_x7_V3 } }, 13751 { /* unused*/ { FP32_RAND_V2(1), FP32_RAND_x7_V2 } },13751 { /*src2 */ { FP32_RAND_V2(1), FP32_RAND_x7_V2 } }, 13752 13752 { /* => */ { FP32_QNAN_V3(1), FP32_RAND_x7_V2 } }, 13753 13753 /*mxcsr:in */ X86_MXCSR_RC_UP, … … 13755 13755 /*256:out */ -1 }, 13756 13756 { { /*src1 */ { FP32_SNAN_V4(0), FP32_RAND_x7_V4 } }, 13757 { /* unused*/ { FP32_RAND_V3(1), FP32_RAND_x7_V3 } },13757 { /*src2 */ { FP32_RAND_V3(1), FP32_RAND_x7_V3 } }, 13758 13758 { /* => */ { FP32_QNAN_V4(0), FP32_RAND_x7_V3 } }, 13759 13759 /*mxcsr:in */ X86_MXCSR_RC_ZERO, … … 13761 13761 /*256:out */ -1 }, 13762 13762 { { /*src1 */ { FP32_SNAN_V5(1), FP32_RAND_x7_V5 } }, 13763 { /* unused*/ { FP32_RAND_V4(1), FP32_RAND_x7_V4 } },13763 { /*src2 */ { FP32_RAND_V4(1), FP32_RAND_x7_V4 } }, 13764 13764 { /* => */ { FP32_QNAN_V5(1), FP32_RAND_x7_V4 } }, 13765 13765 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, … … 13767 13767 /*256:out */ -1 }, 13768 13768 { { /*src1 */ { FP32_QNAN_V1(0), FP32_RAND_x7_V6 } }, 13769 { /* unused*/ { FP32_RAND_V5(1), FP32_RAND_x7_V6 } },13769 { /*src2 */ { FP32_RAND_V5(1), FP32_RAND_x7_V6 } }, 13770 13770 { /* => */ { FP32_QNAN_V1(0), FP32_RAND_x7_V6 } }, 13771 13771 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, … … 13773 13773 /*256:out */ -1 }, 13774 13774 { { /*src1 */ { FP32_QNAN_V2(1), FP32_RAND_x7_V7 } }, 13775 { /* unused*/ { FP32_RAND_V6(1), FP32_RAND_x7_V7 } },13775 { /*src2 */ { FP32_RAND_V6(1), FP32_RAND_x7_V7 } }, 13776 13776 { /* => */ { FP32_QNAN_V2(1), FP32_RAND_x7_V7 } }, 13777 13777 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, … … 13779 13779 /*256:out */ -1 }, 13780 13780 { { /*src1 */ { FP32_QNAN_V3(1), FP32_RAND_x7_V0 } }, 13781 { /* unused*/ { FP32_RAND_V7(1), FP32_RAND_x7_V0 } },13781 { /*src2 */ { FP32_RAND_V7(1), FP32_RAND_x7_V0 } }, 13782 13782 { /* => */ { FP32_QNAN_V3(1), FP32_RAND_x7_V0 } }, 13783 13783 /*mxcsr:in */ X86_MXCSR_DAZ, … … 13785 13785 /*256:out */ -1 }, 13786 13786 { { /*src1 */ { FP32_QNAN_V4(1), FP32_RAND_x7_V0 } }, 13787 { /* unused*/ { FP32_RAND_V7(1), FP32_RAND_x7_V0 } },13787 { /*src2 */ { FP32_RAND_V7(1), FP32_RAND_x7_V0 } }, 13788 13788 { /* => */ { FP32_QNAN_V4(1), FP32_RAND_x7_V0 } }, 13789 13789 /*mxcsr:in */ X86_MXCSR_RC_DOWN, … … 13792 13792 }; 13793 13793 13794 #define PASS_s_aValues RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues 13794 /* Sanity-check subset for 'same register' instruction variants */ 13795 static BS3CPUINSTR4_TEST1_VALUES_SS_T const s_aValuesSR[] = 13796 { 13797 /* 13798 * Zero. 13799 */ 13800 /* 0*/{ { /*src1 */ { FP32_0(0), FP32_RAND_x7_V7 } }, 13801 { /*unused */ { FP32_ROW_UNUSED } }, 13802 { /* => */ { FP32_INF(0), FP32_RAND_x7_V7 } }, 13803 /*mxcsr:in */ 0, 13804 /*128:out */ 0, 13805 /*256:out */ -1 }, 13806 { { /*src1 */ { FP32_0(1), FP32_RAND_x7_V0 } }, 13807 { /*unused */ { FP32_ROW_UNUSED } }, 13808 { /* => */ { FP32_INF(1), FP32_RAND_x7_V0 } }, 13809 /*mxcsr:in */ 0, 13810 /*128:out */ 0, 13811 /*256:out */ -1 }, 13812 /* 13813 * Infinity. 13814 */ 13815 /* 2*/{ { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V1 } }, 13816 { /*unused */ { FP32_ROW_UNUSED } }, 13817 { /* => */ { FP32_0(0), FP32_RAND_x7_V1 } }, 13818 /*mxcsr:in */ 0, 13819 /*128:out */ 0, 13820 /*256:out */ -1 }, 13821 { { /*src1 */ { FP32_INF(1), FP32_RAND_x7_V3 } }, 13822 { /*unused */ { FP32_ROW_UNUSED } }, 13823 { /* => */ { FP32_0(1), FP32_RAND_x7_V3 } }, 13824 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 13825 /*128:out */ X86_MXCSR_RC_ZERO, 13826 /*256:out */ -1 }, 13827 /* 13828 * Normals. 13829 */ 13830 /* 4*/{ { /*src1 */ { FP32_1(0), FP32_RAND_x7_V3 } }, 13831 { /*unused */ { FP32_ROW_UNUSED } }, 13832 { /* => */ { FP32_V(0, 0x7ff000, RTFLOAT32U_EXP_BIAS - 1), FP32_RAND_x7_V3 } }, 13833 /*mxcsr:in */ 0, 13834 /*128:out */ 0, 13835 /*256:out */ -1 }, 13836 { { /*src1 */ { FP32_1(1), FP32_RAND_x7_V2 } }, 13837 { /*unused */ { FP32_ROW_UNUSED } }, 13838 { /* => */ { FP32_V(1, 0x7ff000, RTFLOAT32U_EXP_BIAS - 1), FP32_RAND_x7_V2 } }, 13839 /*mxcsr:in */ 0, 13840 /*128:out */ 0, 13841 /*256:out */ -1 }, 13842 { { /*src1 */ { FP32_V(0, 0xc01, RTFLOAT32U_EXP_BIAS - 1), FP32_RAND_x7_V4 } }, 13843 { /*unused */ { FP32_ROW_UNUSED } }, 13844 { /* => */ { FP32_V(0, FP32_FRAC_DENORM_MAX - 4095, RTFLOAT32U_EXP_BIAS), FP32_RAND_x7_V4 } }, 13845 /*mxcsr:in */ 0, 13846 /*128:out */ 0, 13847 /*256:out */ -1 }, 13848 { { /*src1 */ { FP32_V(0, 0xc01, RTFLOAT32U_EXP_BIAS - 1), FP32_RAND_x7_V4 } }, 13849 { /*unused */ { FP32_ROW_UNUSED } }, 13850 { /* => */ { FP32_V(0, FP32_FRAC_DENORM_MAX - 4095, RTFLOAT32U_EXP_BIAS), FP32_RAND_x7_V4 } }, 13851 /*mxcsr:in */ X86_MXCSR_RC_UP, 13852 /*128:out */ X86_MXCSR_RC_UP, 13853 /*256:out */ -1 }, 13854 { { /*src1 */ { FP32_V(0, 0x7fe800, RTFLOAT32U_EXP_MAX - 3), FP32_RAND_x7_V5 } }, 13855 { /*unused */ { FP32_ROW_UNUSED } }, 13856 { /* => */ { FP32_V(0, 4096, 1), FP32_RAND_x7_V5 } }, 13857 /*mxcsr:in */ 0, 13858 /*128:out */ 0, 13859 /*256:out */ -1 }, 13860 { { /*src1 */ { FP32_V(0, 0x7fe800, RTFLOAT32U_EXP_MAX - 3), FP32_RAND_x7_V6 } }, 13861 { /*unused */ { FP32_ROW_UNUSED } }, 13862 { /* => */ { FP32_V(0, 4096, 1), FP32_RAND_x7_V6 } }, 13863 /*mxcsr:in */ X86_MXCSR_RC_UP, 13864 /*128:out */ X86_MXCSR_RC_UP, 13865 /*256:out */ -1 }, 13866 { { /*src1 */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_RAND_x7_V1 } }, 13867 { /*unused */ { FP32_ROW_UNUSED } }, 13868 { /* => */ { FP32_V(0, 1343488, 106), FP32_RAND_x7_V1 } }, 13869 /*mxcsr:in */ 0, 13870 /*128:out */ 0, 13871 /*256:out */ -1 }, 13872 { { /*src1 */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543*/, FP32_RAND_x7_V5 } }, 13873 { /*unused */ { FP32_ROW_UNUSED } }, 13874 { /* => */ { FP32_V(0, 1343488, 106), FP32_RAND_x7_V5 } }, 13875 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 13876 /*128:out */ X86_MXCSR_RC_DOWN, 13877 /*256:out */ -1 }, 13878 { { /*src1 */ { FP32_V(0, 0x620b2d, 0x92)/*925874.8*/, FP32_RAND_x7_V4 } }, 13879 { /*unused */ { FP32_ROW_UNUSED } }, 13880 { /* => */ { FP32_V(0, 1112064, 107), FP32_RAND_x7_V4 } }, 13881 /*mxcsr:in */ 0, 13882 /*128:out */ 0, 13883 /*256:out */ -1 }, 13884 { { /*src1 */ { FP32_V(0, 0x620b2d, 0x92)/*925874.8*/, FP32_RAND_x7_V4 } }, 13885 { /*unused */ { FP32_ROW_UNUSED } }, 13886 { /* => */ { FP32_V(0, 1112064, 107), FP32_RAND_x7_V4 } }, 13887 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 13888 /*128:out */ X86_MXCSR_RC_ZERO, 13889 /*256:out */ -1 }, 13890 { { /*src1 */ { FP32_V(0, 0x490fda, 0x80)/*3.1415926*/, FP32_RAND_x7_V0 } }, 13891 { /*unused */ { FP32_ROW_UNUSED } }, 13892 { /* => */ { FP32_V(0, 2293760, 125), FP32_RAND_x7_V0 } }, 13893 /*mxcsr:in */ X86_MXCSR_RC_UP, 13894 /*128:out */ X86_MXCSR_RC_UP, 13895 /*256:out */ -1 }, 13896 { { /*src1 */ { FP32_V(0, 0x490fda, 0x80)/*3.1415926*/, FP32_RAND_x7_V0 } }, 13897 { /*unused */ { FP32_ROW_UNUSED } }, 13898 { /* => */ { FP32_V(0, 2293760, 125), FP32_RAND_x7_V0 } }, 13899 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 13900 /*128:out */ X86_MXCSR_RC_DOWN, 13901 /*256:out */ -1 }, 13902 { { /*src1 */ { FP32_V(0, 0x490fda, 0x80)/*3.1415926*/, FP32_RAND_x7_V0 } }, 13903 { /*unused */ { FP32_ROW_UNUSED } }, 13904 { /* => */ { FP32_V(0, 2293760, 125), FP32_RAND_x7_V0 } }, 13905 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 13906 /*128:out */ X86_MXCSR_RC_ZERO, 13907 /*256:out */ -1 }, 13908 { { /*src1 */ { FP32_V(1, 0x534000, 0x86)/*-211.25*/, FP32_RAND_x7_V7 } }, 13909 { /*unused */ { FP32_ROW_UNUSED } }, 13910 { /* => */ { FP32_V(1, 1775616, 119), FP32_RAND_x7_V7 } }, 13911 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 13912 /*128:out */ X86_MXCSR_RC_ZERO, 13913 /*256:out */ -1 }, 13914 { { /*src1 */ { FP32_V(1, 0x534000, 0x86)/*-211.25*/, FP32_RAND_x7_V1 } }, 13915 { /*unused */ { FP32_ROW_UNUSED } }, 13916 { /* => */ { FP32_V(1, 1775616, 119), FP32_RAND_x7_V1 } }, 13917 /*mxcsr:in */ X86_MXCSR_RC_UP, 13918 /*128:out */ X86_MXCSR_RC_UP, 13919 /*256:out */ -1 }, 13920 { { /*src1 */ { FP32_V(1, 0x534000, 0x86)/*-211.25*/, FP32_RAND_x7_V2 } }, 13921 { /*unused */ { FP32_ROW_UNUSED } }, 13922 { /* => */ { FP32_V(1, 1775616, 119), FP32_RAND_x7_V2 } }, 13923 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 13924 /*128:out */ X86_MXCSR_RC_DOWN, 13925 /*256:out */ -1 }, 13926 { { /*src1 */ { FP32_V(1, 0x534000, 0x86)/*-211.25*/, FP32_RAND_x7_V2 } }, 13927 { /*unused */ { FP32_ROW_UNUSED } }, 13928 { /* => */ { FP32_V(1, 1775616, 119), FP32_RAND_x7_V2 } }, 13929 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 13930 /*128:out */ X86_MXCSR_RC_ZERO, 13931 /*256:out */ -1 }, 13932 /* 13933 * Denormals. 13934 */ 13935 /*21*/{ { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V7 } }, 13936 { /*unused */ { FP32_ROW_UNUSED } }, 13937 { /* => */ { FP32_INF(0), FP32_RAND_x7_V7 } }, 13938 /*mxcsr:in */ 0, 13939 /*128:out */ 0, 13940 /*256:out */ -1 }, 13941 { { /*src1 */ { FP32_DENORM_MAX(0), FP32_RAND_x7_V4 } }, 13942 { /*unused */ { FP32_ROW_UNUSED } }, 13943 { /* => */ { FP32_INF(0), FP32_RAND_x7_V4 } }, 13944 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 13945 /*128:out */ X86_MXCSR_RC_ZERO, 13946 /*256:out */ -1 }, 13947 { { /*src1 */ { FP32_DENORM_MAX(1), FP32_RAND_x7_V7 } }, 13948 { /*unused */ { FP32_ROW_UNUSED } }, 13949 { /* => */ { FP32_INF(1), FP32_RAND_x7_V7 } }, 13950 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 13951 /*128:out */ X86_MXCSR_RC_DOWN, 13952 /*256:out */ -1 }, 13953 { { /*src1 */ { FP32_DENORM_MAX(1), FP32_RAND_x7_V7 } }, 13954 { /*unused */ { FP32_ROW_UNUSED } }, 13955 { /* => */ { FP32_INF(1), FP32_RAND_x7_V7 } }, 13956 /*mxcsr:in */ 0, 13957 /*128:out */ 0, 13958 /*256:out */ -1 }, 13959 { { /*src1 */ { FP32_DENORM_MIN(0), FP32_RAND_x7_V6 } }, 13960 { /*unused */ { FP32_ROW_UNUSED } }, 13961 { /* => */ { FP32_INF(0), FP32_RAND_x7_V6 } }, 13962 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 13963 /*128:out */ X86_MXCSR_RC_ZERO, 13964 /*256:out */ -1 }, 13965 { { /*src1 */ { FP32_DENORM_MIN(0), FP32_RAND_x7_V6 } }, 13966 { /*unused */ { FP32_ROW_UNUSED } }, 13967 { /* => */ { FP32_INF(0), FP32_RAND_x7_V6 } }, 13968 /*mxcsr:in */ X86_MXCSR_RC_UP | X86_MXCSR_FZ, 13969 /*128:out */ X86_MXCSR_RC_UP | X86_MXCSR_FZ, 13970 /*256:out */ -1 }, 13971 { { /*src1 */ { FP32_DENORM_MIN(1), FP32_RAND_x7_V5 } }, 13972 { /*unused */ { FP32_ROW_UNUSED } }, 13973 { /* => */ { FP32_INF(1), FP32_RAND_x7_V5 } }, 13974 /*mxcsr:in */ X86_MXCSR_DAZ, 13975 /*128:out */ X86_MXCSR_DAZ, 13976 /*256:out */ -1 }, 13977 { { /*src1 */ { FP32_DENORM_MIN(1), FP32_RAND_x7_V5 } }, 13978 { /*unused */ { FP32_ROW_UNUSED } }, 13979 { /* => */ { FP32_INF(1), FP32_RAND_x7_V5 } }, 13980 /*mxcsr:in */ X86_MXCSR_RC_UP, 13981 /*128:out */ X86_MXCSR_RC_UP, 13982 /*256:out */ -1 }, 13983 { { /*src1 */ { FP32_DENORM_V0(0), FP32_RAND_x7_V4 } }, 13984 { /*unused */ { FP32_ROW_UNUSED } }, 13985 { /* => */ { FP32_INF(0), FP32_RAND_x7_V4 } }, 13986 /*mxcsr:in */ X86_MXCSR_RC_UP, 13987 /*128:out */ X86_MXCSR_RC_UP, 13988 /*256:out */ -1 }, 13989 { { /*src1 */ { FP32_DENORM_V0(1), FP32_RAND_x7_V3 } }, 13990 { /*unused */ { FP32_ROW_UNUSED } }, 13991 { /* => */ { FP32_INF(1), FP32_RAND_x7_V3 } }, 13992 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 13993 /*128:out */ X86_MXCSR_RC_ZERO, 13994 /*256:out */ -1 }, 13995 { { /*src1 */ { FP32_DENORM_V7(1), FP32_RAND_x7_V1 } }, 13996 { /*unused */ { FP32_ROW_UNUSED } }, 13997 { /* => */ { FP32_INF(1), FP32_RAND_x7_V1 } }, 13998 /*mxcsr:in */ X86_MXCSR_DAZ, 13999 /*128:out */ X86_MXCSR_DAZ, 14000 /*256:out */ -1 }, 14001 { { /*src1 */ { FP32_DENORM_V7(1), FP32_RAND_x7_V2 } }, 14002 { /*unused */ { FP32_ROW_UNUSED } }, 14003 { /* => */ { FP32_INF(1), FP32_RAND_x7_V2 } }, 14004 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 14005 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 14006 /*256:out */ -1 }, 14007 { { /*src1 */ { FP32_DENORM_V7(1), FP32_RAND_x7_V0 } }, 14008 { /*unused */ { FP32_ROW_UNUSED } }, 14009 { /* => */ { FP32_INF(1), FP32_RAND_x7_V0 } }, 14010 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_DAZ, 14011 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_DAZ, 14012 /*256:out */ -1 }, 14013 /* 14014 * Invalids. 14015 */ 14016 /*34*/{ { /*src1 */ { FP32_SNAN(0), FP32_RAND_x7_V7 } }, 14017 { /*unused */ { FP32_ROW_UNUSED } }, 14018 { /* => */ { FP32_QNAN_V(0, 1), FP32_RAND_x7_V7 } }, 14019 /*mxcsr:in */ 0, 14020 /*128:out */ 0, 14021 /*256:out */ -1 }, 14022 { { /*src1 */ { FP32_SNAN(1), FP32_RAND_x7_V2 } }, 14023 { /*unused */ { FP32_ROW_UNUSED } }, 14024 { /* => */ { FP32_QNAN_V(1, 1), FP32_RAND_x7_V2 } }, 14025 /*mxcsr:in */ X86_MXCSR_FZ, 14026 /*128:out */ X86_MXCSR_FZ, 14027 /*256:out */ -1 }, 14028 { { /*src1 */ { FP32_SNAN_V0(0), FP32_RAND_x7_V1 } }, 14029 { /*unused */ { FP32_ROW_UNUSED } }, 14030 { /* => */ { FP32_QNAN_V0(0), FP32_RAND_x7_V1 } }, 14031 /*mxcsr:in */ 0, 14032 /*128:out */ 0, 14033 /*256:out */ -1 }, 14034 { { /*src1 */ { FP32_SNAN_V5(1), FP32_RAND_x7_V5 } }, 14035 { /*unused */ { FP32_ROW_UNUSED } }, 14036 { /* => */ { FP32_QNAN_V5(1), FP32_RAND_x7_V5 } }, 14037 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 14038 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 14039 /*256:out */ -1 }, 14040 { { /*src1 */ { FP32_QNAN_V2(1), FP32_RAND_x7_V7 } }, 14041 { /*unused */ { FP32_ROW_UNUSED } }, 14042 { /* => */ { FP32_QNAN_V2(1), FP32_RAND_x7_V7 } }, 14043 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 14044 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, 14045 /*256:out */ -1 }, 14046 { { /*src1 */ { FP32_QNAN_V3(0), FP32_RAND_x7_V0 } }, 14047 { /*unused */ { FP32_ROW_UNUSED } }, 14048 { /* => */ { FP32_QNAN_V3(0), FP32_RAND_x7_V0 } }, 14049 /*mxcsr:in */ X86_MXCSR_DAZ, 14050 /*128:out */ X86_MXCSR_DAZ, 14051 /*256:out */ -1 }, 14052 }; 14053 14054 #define PASS_s_aValues RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues 14055 #define PASS_s_aValuesSR RT_ELEMENTS(s_aValuesSR), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValuesSR 13795 14056 static BS3CPUINSTR4_TEST1_T const s_aTests16[] = 13796 14057 { … … 13800 14061 { bs3CpuInstr4_vrcpss_XMM1_XMM2_XMM3_icebp_c16, X86_XCPT_AC, RM_REG, T_AVX_128, 1, 2, 3, PASS_s_aValues }, 13801 14062 { bs3CpuInstr4_vrcpss_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, PASS_s_aValues }, 14063 14064 { bs3CpuInstr4_rcpss_XMM1_XMM1_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 1, PASS_s_aValuesSR }, 14065 { bs3CpuInstr4_vrcpss_XMM1_XMM1_XMM1_icebp_c16, X86_XCPT_AC, RM_REG, T_AVX_128, 1, 1, 1, PASS_s_aValuesSR }, 14066 { bs3CpuInstr4_vrcpss_XMM1_XMM1_XMM2_icebp_c16, X86_XCPT_AC, RM_REG, T_AVX_128, 1, 1, 2, PASS_s_aValues }, 14067 { bs3CpuInstr4_vrcpss_XMM1_XMM2_XMM2_icebp_c16, X86_XCPT_AC, RM_REG, T_AVX_128, 1, 2, 2, PASS_s_aValuesSR }, 14068 { bs3CpuInstr4_vrcpss_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 1, 255, PASS_s_aValues }, 13802 14069 }; 13803 14070 static BS3CPUINSTR4_TEST1_T const s_aTests32[] = … … 13808 14075 { bs3CpuInstr4_vrcpss_XMM1_XMM2_XMM3_icebp_c32, X86_XCPT_AC, RM_REG, T_AVX_128, 1, 2, 3, PASS_s_aValues }, 13809 14076 { bs3CpuInstr4_vrcpss_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, PASS_s_aValues }, 14077 14078 { bs3CpuInstr4_rcpss_XMM1_XMM1_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 1, PASS_s_aValuesSR }, 14079 { bs3CpuInstr4_vrcpss_XMM1_XMM1_XMM1_icebp_c32, X86_XCPT_AC, RM_REG, T_AVX_128, 1, 1, 1, PASS_s_aValuesSR }, 14080 { bs3CpuInstr4_vrcpss_XMM1_XMM1_XMM2_icebp_c32, X86_XCPT_AC, RM_REG, T_AVX_128, 1, 1, 2, PASS_s_aValues }, 14081 { bs3CpuInstr4_vrcpss_XMM1_XMM2_XMM2_icebp_c32, X86_XCPT_AC, RM_REG, T_AVX_128, 1, 2, 2, PASS_s_aValuesSR }, 14082 { bs3CpuInstr4_vrcpss_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 1, 255, PASS_s_aValues }, 13810 14083 }; 13811 14084 static BS3CPUINSTR4_TEST1_T const s_aTests64[] = … … 13817 14090 { bs3CpuInstr4_rcpss_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 8, 8, 255, PASS_s_aValues }, 13818 14091 14092 { bs3CpuInstr4_rcpss_XMM1_XMM1_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 1, PASS_s_aValuesSR }, 14093 13819 14094 { bs3CpuInstr4_vrcpss_XMM1_XMM2_XMM3_icebp_c64, X86_XCPT_AC, RM_REG, T_AVX_128, 1, 2, 3, PASS_s_aValues }, 13820 14095 { bs3CpuInstr4_vrcpss_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, PASS_s_aValues }, … … 13822 14097 { bs3CpuInstr4_vrcpss_XMM13_XMM14_XMM15_icebp_c64, X86_XCPT_AC, RM_REG, T_AVX_128, 13, 14, 15, PASS_s_aValues }, 13823 14098 { bs3CpuInstr4_vrcpss_XMM13_XMM14_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 13, 14, 255, PASS_s_aValues }, 14099 14100 { bs3CpuInstr4_rcpss_XMM1_XMM1_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 1, PASS_s_aValuesSR }, 14101 { bs3CpuInstr4_vrcpss_XMM1_XMM1_XMM1_icebp_c64, X86_XCPT_AC, RM_REG, T_AVX_128, 1, 1, 1, PASS_s_aValuesSR }, 14102 { bs3CpuInstr4_vrcpss_XMM1_XMM1_XMM2_icebp_c64, X86_XCPT_AC, RM_REG, T_AVX_128, 1, 1, 2, PASS_s_aValues }, 14103 { bs3CpuInstr4_vrcpss_XMM1_XMM2_XMM2_icebp_c64, X86_XCPT_AC, RM_REG, T_AVX_128, 1, 2, 2, PASS_s_aValuesSR }, 14104 { bs3CpuInstr4_vrcpss_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 1, 255, PASS_s_aValues }, 14105 { bs3CpuInstr4_vrcpss_XMM15_XMM15_XMM15_icebp_c64, X86_XCPT_AC, RM_REG, T_AVX_128, 15, 15, 15, PASS_s_aValuesSR }, 14106 { bs3CpuInstr4_vrcpss_XMM15_XMM15_XMM13_icebp_c64, X86_XCPT_AC, RM_REG, T_AVX_128, 15, 15, 13, PASS_s_aValues }, 14107 { bs3CpuInstr4_vrcpss_XMM13_XMM14_XMM14_icebp_c64, X86_XCPT_AC, RM_REG, T_AVX_128, 13, 14, 14, PASS_s_aValuesSR }, 13824 14108 }; 13825 14109 #undef PASS_s_aValues 14110 #undef PASS_s_aValuesSR 13826 14111 13827 14112 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
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