Changeset 106332 in vbox for trunk/src/VBox/ValidationKit/bootsectors
- Timestamp:
- Oct 16, 2024 2:25:51 AM (7 months ago)
- svn:sync-xref-src-repo-rev:
- 165145
- Location:
- trunk/src/VBox/ValidationKit/bootsectors
- Files:
-
- 2 edited
-
bs3-cpu-instr-4-template.mac (modified) (1 diff)
-
bs3-cpu-instr-4.c32 (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4-template.mac
r106330 r106332 774 774 EMIT_INSTR_PLUS_ICEBP vrsqrtps, YMM1, YMM1 775 775 776 ; 777 ;; [v]rsqrtss 778 ; 779 EMIT_INSTR_PLUS_ICEBP rsqrtss, XMM1, XMM2 780 EMIT_INSTR_PLUS_ICEBP rsqrtss, XMM1, FSxBX 781 EMIT_INSTR_PLUS_ICEBP_C64 rsqrtss, XMM8, XMM9 782 EMIT_INSTR_PLUS_ICEBP_C64 rsqrtss, XMM8, FSxBX 783 784 EMIT_INSTR_PLUS_ICEBP vrsqrtss, XMM1, XMM2, XMM3 785 EMIT_INSTR_PLUS_ICEBP vrsqrtss, XMM1, XMM2, FSxBX 786 EMIT_INSTR_PLUS_ICEBP_C64 vrsqrtss, XMM8, XMM9, XMM10 787 EMIT_INSTR_PLUS_ICEBP_C64 vrsqrtss, XMM8, XMM9, FSxBX 788 789 EMIT_INSTR_PLUS_ICEBP rsqrtss, XMM1, XMM1 790 EMIT_INSTR_PLUS_ICEBP vrsqrtss, XMM1, XMM1, XMM1 791 EMIT_INSTR_PLUS_ICEBP vrsqrtss, XMM1, XMM1, XMM2 792 EMIT_INSTR_PLUS_ICEBP vrsqrtss, XMM1, XMM2, XMM2 793 EMIT_INSTR_PLUS_ICEBP vrsqrtss, XMM1, XMM1, FSxBX 794 EMIT_INSTR_PLUS_ICEBP_C64 vrsqrtss, XMM8, XMM8, XMM8 795 776 796 %endif ; BS3_INSTANTIATING_CMN 777 797 -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32
r106330 r106332 15813 15813 15814 15814 15815 /* 15816 * [V]RSQRTSS. 15817 */ 15818 /** @todo this fails entirely under IEM: the instructions rcpps, rcpss, rsqrtps, rsqrtss are all implemented with too much precision & attention to exceptions! */ 15819 BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_rsqrtss(uint8_t bMode) 15820 { 15821 static BS3CPUINSTR4_TEST1_VALUES_SS_T const s_aValues[] = 15822 { 15823 /* 15824 * Zero. 15825 */ 15826 /* 0*/{ { /*src1 */ { FP32_0(0), FP32_RAND_x7_V7 } }, 15827 { /*src2 */ { FP32_RAND_V2(0), FP32_RAND_x7_V2 } }, 15828 { /* => */ { FP32_INF(0), FP32_RAND_x7_V2 } }, 15829 /*mxcsr:in */ 0, 15830 /*128:out */ 0, 15831 /*256:out */ -1 }, 15832 { { /*src1 */ { FP32_0(1), FP32_RAND_x7_V0 } }, 15833 { /*src2 */ { FP32_RAND_V3(1), FP32_RAND_x7_V1 } }, 15834 { /* => */ { FP32_INF(1), FP32_RAND_x7_V1 } }, 15835 /*mxcsr:in */ 0, 15836 /*128:out */ 0, 15837 /*256:out */ -1 }, 15838 { { /*src1 */ { FP32_0(1), FP32_RAND_x7_V2 } }, 15839 { /*src2 */ { FP32_RAND_V5(0), FP32_RAND_x7_V1 } }, 15840 { /* => */ { FP32_INF(1), FP32_RAND_x7_V1 } }, 15841 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 15842 /*128:out */ X86_MXCSR_RC_ZERO, 15843 /*256:out */ -1 }, 15844 { { /*src1 */ { FP32_0(1), FP32_RAND_x7_V0 } }, 15845 { /*src2 */ { FP32_SNAN(0), FP32_RAND_x7_V3 } }, 15846 { /* => */ { FP32_INF(1), FP32_RAND_x7_V3 } }, 15847 /*mxcsr:in */ X86_MXCSR_RC_UP, 15848 /*128:out */ X86_MXCSR_RC_UP, 15849 /*256:out */ -1 }, 15850 { { /*src1 */ { FP32_0(1), FP32_RAND_x7_V0 } }, 15851 { /*src2 */ { FP32_QNAN(1), FP32_RAND_x7_V3 } }, 15852 { /* => */ { FP32_INF(1), FP32_RAND_x7_V3 } }, 15853 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 15854 /*128:out */ X86_MXCSR_RC_DOWN, 15855 /*256:out */ -1 }, 15856 { { /*src1 */ { FP32_0(0), FP32_RAND_x7_V0 } }, 15857 { /*src2 */ { FP32_RAND_V0(1), FP32_RAND_x7_V3 } }, 15858 { /* => */ { FP32_INF(0), FP32_RAND_x7_V3 } }, 15859 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 15860 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 15861 /*256:out */ -1 }, 15862 /* 15863 * Infinity. 15864 */ 15865 /* 6*/{ { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V1 } }, 15866 { /*src2 */ { FP32_RAND_V2(0), FP32_RAND_x7_V0 } }, 15867 { /* => */ { FP32_0(0), FP32_RAND_x7_V0 } }, 15868 /*mxcsr:in */ 0, 15869 /*128:out */ 0, 15870 /*256:out */ -1 }, 15871 { { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V3 } }, 15872 { /*src2 */ { FP32_2(1), FP32_RAND_x7_V1 } }, 15873 { /* => */ { FP32_0(0), FP32_RAND_x7_V1 } }, 15874 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 15875 /*128:out */ X86_MXCSR_RC_ZERO, 15876 /*256:out */ -1 }, 15877 { { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V5 } }, 15878 { /*src2 */ { FP32_RAND_V2(0), FP32_RAND_x7_V3 } }, 15879 { /* => */ { FP32_0(0), FP32_RAND_x7_V3 } }, 15880 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 15881 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 15882 /*256:out */ -1 }, 15883 { { /*src1 */ { FP32_INF(0), FP32_RAND_x7_V6 } }, 15884 { /*src2 */ { FP32_SNAN(0), FP32_RAND_x7_V0 } }, 15885 { /* => */ { FP32_0(0), FP32_RAND_x7_V0 } }, 15886 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 15887 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 15888 /*256:out */ -1 }, 15889 { { /*src1 */ { FP32_INF(1), FP32_RAND_x7_V6 } }, 15890 { /*src2 */ { FP32_RAND_V2(0), FP32_RAND_x7_V2 } }, 15891 { /* => */ { FP32_QNAN(1), FP32_RAND_x7_V2 } }, 15892 /*mxcsr:in */ 0, 15893 /*128:out */ 0, 15894 /*256:out */ -1 }, 15895 { { /*src1 */ { FP32_INF(1), FP32_RAND_x7_V5 } }, 15896 { /*src2 */ { FP32_RAND_V2(0), FP32_RAND_x7_V1 } }, 15897 { /* => */ { FP32_QNAN(1), FP32_RAND_x7_V1 } }, 15898 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 15899 /*128:out */ X86_MXCSR_RC_ZERO, 15900 /*256:out */ -1 }, 15901 { { /*src1 */ { FP32_INF(1), FP32_RAND_x7_V6 } }, 15902 { /*src2 */ { FP32_QNAN(0), FP32_RAND_x7_V2 } }, 15903 { /* => */ { FP32_QNAN(1), FP32_RAND_x7_V2 } }, 15904 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 15905 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 15906 /*256:out */ -1 }, 15907 { { /*src1 */ { FP32_INF(1), FP32_RAND_x7_V3 } }, 15908 { /*src2 */ { FP32_RAND_V4(0), FP32_RAND_x7_V1 } }, 15909 { /* => */ { FP32_QNAN(1), FP32_RAND_x7_V1 } }, 15910 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 15911 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 15912 /*256:out */ -1 }, 15913 /* 15914 * Normals & Precision (Overflow, Underflow not possible). 15915 */ 15916 /*14*/{ { /*src1 */ { FP32_NORM_V0(0), FP32_RAND_x7_V3 } }, 15917 { /*src2 */ { FP32_NORM_V4(0), FP32_RAND_x7_V0 } }, 15918 { /* => */ { FP32_RSQRT_NORM_V0, FP32_RAND_x7_V0 } }, 15919 /*mxcsr:in */ 0, 15920 /*128:out */ 0, 15921 /*256:out */ -1 }, 15922 15923 { { /*src1 */ { FP32_NORM_V2(0), FP32_RAND_x7_V6 } }, 15924 { /*src2 */ { FP32_1(1), FP32_RAND_x7_V3 } }, 15925 { /* => */ { FP32_RSQRT_NORM_V2, FP32_RAND_x7_V3 } }, 15926 /*mxcsr:in */ X86_MXCSR_FZ, 15927 /*128:out */ X86_MXCSR_FZ, 15928 /*256:out */ -1 }, 15929 { { /*src1 */ { FP32_NORM_V3(0), FP32_0_x7(0) } }, 15930 { /*src2 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_x7_V1 } }, 15931 { /* => */ { FP32_RSQRT_NORM_V3, FP32_RAND_x7_V1 } }, 15932 /*mxcsr:in */ X86_MXCSR_DAZ, 15933 /*128:out */ X86_MXCSR_DAZ, 15934 /*256:out */ -1 }, 15935 { { /*src1 */ { FP32_NORM_MAX(0), FP32_RAND_x7_V4 } }, 15936 { /*src2 */ { FP32_NORM_MAX(1), FP32_RAND_x7_V2 } }, 15937 { /* => */ { FP32_RSQRT_NORM_MAX, FP32_RAND_x7_V2 } }, 15938 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_DAZ, 15939 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_DAZ, 15940 /*256:out */ -1 }, 15941 { { /*src1 */ { FP32_NORM_MIN(0), FP32_RAND_x7_V7 } }, 15942 { /*src2 */ { FP32_INF(1), FP32_RAND_x7_V6 } }, 15943 { /* => */ { FP32_RSQRT_NORM_MIN, FP32_RAND_x7_V6 } }, 15944 /*mxcsr:in */ 0, 15945 /*128:out */ 0, 15946 /*256:out */ -1 }, 15947 { { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V2 } }, 15948 { /*src2 */ { FP32_RAND_V1(1), FP32_RAND_x7_V5 } }, 15949 { /* => */ { FP32_RSQRT_NS_INT_MAX, FP32_RAND_x7_V5 } }, 15950 /*mxcsr:in */ 0, 15951 /*128:out */ 0, 15952 /*256:out */ -1 }, 15953 { { /*src1 */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_x7_V5 } }, 15954 { /*src2 */ { FP32_RAND_V0(0), FP32_RAND_x7_V7 } }, 15955 { /* => */ { FP32_RSQRT_NS_INT_MIN, FP32_RAND_x7_V7 } }, 15956 /*mxcsr:in */ 0, 15957 /*128:out */ 0, 15958 /*256:out */ -1 }, 15959 { { /*src1 */ { FP32_VAL_256_0, FP32_RAND_x7_V0 } }, 15960 { /*src2 */ { FP32_2(0), FP32_RAND_x7_V4 } }, 15961 { /* => */ { FP32_RSQRT_256_0, FP32_RAND_x7_V4 } }, 15962 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 15963 /*128:out */ X86_MXCSR_RC_ZERO, 15964 /*256:out */ -1 }, 15965 { { /*src1 */ { FP32_VAL_256_0, FP32_RAND_x7_V3 } }, 15966 { /*src2 */ { FP32_DENORM_V3(0), FP32_RAND_x7_V4 } }, 15967 { /* => */ { FP32_RSQRT_256_0, FP32_RAND_x7_V4 } }, 15968 /*mxcsr:in */ X86_MXCSR_RC_UP, 15969 /*128:out */ X86_MXCSR_RC_UP, 15970 /*256:out */ -1 }, 15971 { { /*src1 */ { FP32_VAL_528_0, FP32_RAND_x7_V6 } }, 15972 { /*src2 */ { FP32_NORM_SAFE_INT_MAX(1), FP32_RAND_x7_V7 } }, 15973 { /* => */ { FP32_RSQRT_528_0, FP32_RAND_x7_V7 } }, 15974 /*mxcsr:in */ 0, 15975 /*128:out */ 0, 15976 /*256:out */ -1 }, 15977 { { /*src1 */ { FP32_VAL_528_0, FP32_RAND_x7_V6 } }, 15978 { /*src2 */ { FP32_NORM_SAFE_INT_MAX(1), FP32_RAND_x7_V7 } }, 15979 { /* => */ { FP32_RSQRT_528_0, FP32_RAND_x7_V7 } }, 15980 /*mxcsr:in */ X86_MXCSR_RC_UP, 15981 /*128:out */ X86_MXCSR_RC_UP, 15982 /*256:out */ -1 }, 15983 /** @todo Invalids. */ 15984 /*25*/ /* FP32_TABLE_D10_SS_INVALIDS */ 15985 }; 15986 #define PASS_s_aValues RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues 15987 15988 /* Sanity-check subset for 'same register' instruction variants */ 15989 static BS3CPUINSTR4_TEST1_VALUES_SS_T const s_aValuesSR[] = 15990 { 15991 /* 15992 * Zero. 15993 */ 15994 /* 0*/{ { /*src1 */ { FP32_0(0), FP32_RAND_x7_V7 } }, 15995 { /*src2 */ { FP32_0(0), FP32_RAND_x7_V7 } }, 15996 { /* => */ { FP32_INF(0), FP32_RAND_x7_V7 } }, 15997 /*mxcsr:in */ 0, 15998 /*128:out */ 0, 15999 /*256:out */ -1 }, 16000 { { /*src1 */ { FP32_INF(1), FP32_RAND_x7_V6 } }, 16001 { /*src2 */ { FP32_INF(1), FP32_RAND_x7_V6 } }, 16002 { /* => */ { FP32_QNAN(1), FP32_RAND_x7_V6 } }, 16003 /*mxcsr:in */ 0, 16004 /*128:out */ 0, 16005 /*256:out */ -1 }, 16006 { { /*src1 */ { FP32_NORM_V3(0), FP32_0_x7(0) } }, 16007 { /*src2 */ { FP32_NORM_V3(0), FP32_0_x7(0) } }, 16008 { /* => */ { FP32_RSQRT_NORM_V3, FP32_0_x7(0) } }, 16009 /*mxcsr:in */ X86_MXCSR_DAZ, 16010 /*128:out */ X86_MXCSR_DAZ, 16011 /*256:out */ -1 }, 16012 }; 16013 #define PASS_s_aValuesSR RT_ELEMENTS(s_aValuesSR), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValuesSR 16014 static BS3CPUINSTR4_TEST1_T const s_aTests16[] = 16015 { 16016 { bs3CpuInstr4_rsqrtss_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, PASS_s_aValues }, 16017 { bs3CpuInstr4_rsqrtss_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, PASS_s_aValues }, 16018 16019 { bs3CpuInstr4_vrsqrtss_XMM1_XMM2_XMM3_icebp_c16, X86_XCPT_AC, RM_REG, T_AVX_128, 1, 2, 3, PASS_s_aValues }, 16020 { bs3CpuInstr4_vrsqrtss_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, PASS_s_aValues }, 16021 16022 { bs3CpuInstr4_rsqrtss_XMM1_XMM1_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 1, PASS_s_aValuesSR }, 16023 { bs3CpuInstr4_vrsqrtss_XMM1_XMM1_XMM1_icebp_c16, X86_XCPT_AC, RM_REG, T_AVX_128, 1, 1, 1, PASS_s_aValuesSR }, 16024 { bs3CpuInstr4_vrsqrtss_XMM1_XMM1_XMM2_icebp_c16, X86_XCPT_AC, RM_REG, T_AVX_128, 1, 1, 2, PASS_s_aValues }, 16025 { bs3CpuInstr4_vrsqrtss_XMM1_XMM2_XMM2_icebp_c16, X86_XCPT_AC, RM_REG, T_AVX_128, 1, 2, 2, PASS_s_aValuesSR }, 16026 { bs3CpuInstr4_vrsqrtss_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 1, 255, PASS_s_aValuesSR }, 16027 }; 16028 static BS3CPUINSTR4_TEST1_T const s_aTests32[] = 16029 { 16030 { bs3CpuInstr4_rsqrtss_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, PASS_s_aValues }, 16031 { bs3CpuInstr4_rsqrtss_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, PASS_s_aValues }, 16032 16033 { bs3CpuInstr4_vrsqrtss_XMM1_XMM2_XMM3_icebp_c32, X86_XCPT_AC, RM_REG, T_AVX_128, 1, 2, 3, PASS_s_aValues }, 16034 { bs3CpuInstr4_vrsqrtss_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, PASS_s_aValues }, 16035 16036 { bs3CpuInstr4_rsqrtss_XMM1_XMM1_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 1, PASS_s_aValuesSR }, 16037 { bs3CpuInstr4_vrsqrtss_XMM1_XMM1_XMM1_icebp_c32, X86_XCPT_AC, RM_REG, T_AVX_128, 1, 1, 1, PASS_s_aValuesSR }, 16038 { bs3CpuInstr4_vrsqrtss_XMM1_XMM1_XMM2_icebp_c32, X86_XCPT_AC, RM_REG, T_AVX_128, 1, 1, 2, PASS_s_aValues }, 16039 { bs3CpuInstr4_vrsqrtss_XMM1_XMM2_XMM2_icebp_c32, X86_XCPT_AC, RM_REG, T_AVX_128, 1, 2, 2, PASS_s_aValuesSR }, 16040 { bs3CpuInstr4_vrsqrtss_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 1, 255, PASS_s_aValuesSR }, 16041 }; 16042 static BS3CPUINSTR4_TEST1_T const s_aTests64[] = 16043 { 16044 { bs3CpuInstr4_rsqrtss_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, PASS_s_aValues }, 16045 { bs3CpuInstr4_rsqrtss_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, PASS_s_aValues }, 16046 16047 { bs3CpuInstr4_rsqrtss_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, PASS_s_aValues }, 16048 { bs3CpuInstr4_rsqrtss_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 8, 8, 255, PASS_s_aValues }, 16049 16050 { bs3CpuInstr4_vrsqrtss_XMM1_XMM2_XMM3_icebp_c64, X86_XCPT_AC, RM_REG, T_AVX_128, 1, 2, 3, PASS_s_aValues }, 16051 { bs3CpuInstr4_vrsqrtss_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, PASS_s_aValues }, 16052 16053 { bs3CpuInstr4_vrsqrtss_XMM8_XMM9_XMM10_icebp_c64, X86_XCPT_AC, RM_REG, T_AVX_128, 8, 9, 10, PASS_s_aValues }, 16054 { bs3CpuInstr4_vrsqrtss_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 8, 9, 255, PASS_s_aValues }, 16055 16056 { bs3CpuInstr4_rsqrtss_XMM1_XMM1_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 1, PASS_s_aValuesSR }, 16057 { bs3CpuInstr4_vrsqrtss_XMM1_XMM1_XMM1_icebp_c64, X86_XCPT_AC, RM_REG, T_AVX_128, 1, 1, 1, PASS_s_aValuesSR }, 16058 { bs3CpuInstr4_vrsqrtss_XMM1_XMM1_XMM2_icebp_c64, X86_XCPT_AC, RM_REG, T_AVX_128, 1, 1, 2, PASS_s_aValues }, 16059 { bs3CpuInstr4_vrsqrtss_XMM1_XMM2_XMM2_icebp_c64, X86_XCPT_AC, RM_REG, T_AVX_128, 1, 2, 2, PASS_s_aValuesSR }, 16060 { bs3CpuInstr4_vrsqrtss_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 1, 255, PASS_s_aValuesSR }, 16061 { bs3CpuInstr4_vrsqrtss_XMM8_XMM8_XMM8_icebp_c64, X86_XCPT_AC, RM_REG, T_AVX_128, 8, 8, 8, PASS_s_aValuesSR }, 16062 }; 16063 #undef PASS_s_aValues 16064 #undef PASS_s_aValuesSR 16065 16066 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 16067 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode); 16068 return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 16069 g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5)); 16070 } 16071 16072 15815 16073 /** 15816 16074 * The 32-bit protected mode main function. … … 15869 16127 { "[v]sqrtsd", bs3CpuInstr4_v_sqrtsd, 0 }, 15870 16128 { "[v]rsqrtps", bs3CpuInstr4_v_rsqrtps, 0 }, 16129 { "[v]rsqrtss", bs3CpuInstr4_v_rsqrtss, 0 }, 15871 16130 #endif 15872 16131 };
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