Index: trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4-template.mac
===================================================================
--- trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4-template.mac	(revision 106330)
+++ trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4-template.mac	(revision 106332)
@@ -774,4 +774,24 @@
 EMIT_INSTR_PLUS_ICEBP       vrsqrtps, YMM1, YMM1
 
+;
+;; [v]rsqrtss
+;
+EMIT_INSTR_PLUS_ICEBP       rsqrtss,  XMM1, XMM2
+EMIT_INSTR_PLUS_ICEBP       rsqrtss,  XMM1, FSxBX
+EMIT_INSTR_PLUS_ICEBP_C64   rsqrtss,  XMM8, XMM9
+EMIT_INSTR_PLUS_ICEBP_C64   rsqrtss,  XMM8, FSxBX
+
+EMIT_INSTR_PLUS_ICEBP       vrsqrtss, XMM1, XMM2, XMM3
+EMIT_INSTR_PLUS_ICEBP       vrsqrtss, XMM1, XMM2, FSxBX
+EMIT_INSTR_PLUS_ICEBP_C64   vrsqrtss, XMM8, XMM9, XMM10
+EMIT_INSTR_PLUS_ICEBP_C64   vrsqrtss, XMM8, XMM9, FSxBX
+
+EMIT_INSTR_PLUS_ICEBP       rsqrtss,  XMM1, XMM1
+EMIT_INSTR_PLUS_ICEBP       vrsqrtss, XMM1, XMM1, XMM1
+EMIT_INSTR_PLUS_ICEBP       vrsqrtss, XMM1, XMM1, XMM2
+EMIT_INSTR_PLUS_ICEBP       vrsqrtss, XMM1, XMM2, XMM2
+EMIT_INSTR_PLUS_ICEBP       vrsqrtss, XMM1, XMM1, FSxBX
+EMIT_INSTR_PLUS_ICEBP_C64   vrsqrtss, XMM8, XMM8, XMM8
+
 %endif ; BS3_INSTANTIATING_CMN
 
Index: trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32
===================================================================
--- trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32	(revision 106330)
+++ trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32	(revision 106332)
@@ -15813,4 +15813,262 @@
 
 
+/*
+ * [V]RSQRTSS.
+ */
+/** @todo this fails entirely under IEM: the instructions rcpps, rcpss, rsqrtps, rsqrtss are all implemented with too much precision & attention to exceptions! */
+BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_rsqrtss(uint8_t bMode)
+{
+    static BS3CPUINSTR4_TEST1_VALUES_SS_T const s_aValues[] =
+    {
+    /*
+     * Zero.
+     */
+    /* 0*/{ { /*src1     */ { FP32_0(0),       FP32_RAND_x7_V7 } },
+            { /*src2     */ { FP32_RAND_V2(0), FP32_RAND_x7_V2 } },
+            { /* =>      */ { FP32_INF(0),     FP32_RAND_x7_V2 } },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ -1 },
+          { { /*src1     */ { FP32_0(1),       FP32_RAND_x7_V0 } },
+            { /*src2     */ { FP32_RAND_V3(1), FP32_RAND_x7_V1 } },
+            { /* =>      */ { FP32_INF(1),     FP32_RAND_x7_V1 } },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ -1 },
+          { { /*src1     */ { FP32_0(1),       FP32_RAND_x7_V2 } },
+            { /*src2     */ { FP32_RAND_V5(0), FP32_RAND_x7_V1 } },
+            { /* =>      */ { FP32_INF(1),     FP32_RAND_x7_V1 } },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
+              /*256:out  */ -1 },
+          { { /*src1     */ { FP32_0(1),       FP32_RAND_x7_V0 } },
+            { /*src2     */ { FP32_SNAN(0),    FP32_RAND_x7_V3 } },
+            { /* =>      */ { FP32_INF(1),     FP32_RAND_x7_V3 } },
+              /*mxcsr:in */ X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_RC_UP,
+              /*256:out  */ -1 },
+          { { /*src1     */ { FP32_0(1),       FP32_RAND_x7_V0 } },
+            { /*src2     */ { FP32_QNAN(1),    FP32_RAND_x7_V3 } },
+            { /* =>      */ { FP32_INF(1),     FP32_RAND_x7_V3 } },
+              /*mxcsr:in */ X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_RC_DOWN,
+              /*256:out  */ -1 },
+          { { /*src1     */ { FP32_0(0),       FP32_RAND_x7_V0 } },
+            { /*src2     */ { FP32_RAND_V0(1), FP32_RAND_x7_V3 } },
+            { /* =>      */ { FP32_INF(0),     FP32_RAND_x7_V3 } },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ,
+              /*256:out  */ -1 },
+    /*
+     * Infinity.
+     */
+    /* 6*/{ { /*src1     */ { FP32_INF(0),     FP32_RAND_x7_V1 } },
+            { /*src2     */ { FP32_RAND_V2(0), FP32_RAND_x7_V0 } },
+            { /* =>      */ { FP32_0(0),       FP32_RAND_x7_V0 } },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ -1 },
+          { { /*src1     */ { FP32_INF(0),     FP32_RAND_x7_V3 } },
+            { /*src2     */ { FP32_2(1),       FP32_RAND_x7_V1 } },
+            { /* =>      */ { FP32_0(0),       FP32_RAND_x7_V1 } },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
+              /*256:out  */ -1 },
+          { { /*src1     */ { FP32_INF(0),     FP32_RAND_x7_V5 } },
+            { /*src2     */ { FP32_RAND_V2(0), FP32_RAND_x7_V3 } },
+            { /* =>      */ { FP32_0(0),       FP32_RAND_x7_V3 } },
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ -1 },
+          { { /*src1     */ { FP32_INF(0),     FP32_RAND_x7_V6 } },
+            { /*src2     */ { FP32_SNAN(0),    FP32_RAND_x7_V0 } },
+            { /* =>      */ { FP32_0(0),       FP32_RAND_x7_V0 } },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
+              /*256:out  */ -1 },
+          { { /*src1     */ { FP32_INF(1),     FP32_RAND_x7_V6 } },
+            { /*src2     */ { FP32_RAND_V2(0), FP32_RAND_x7_V2 } },
+            { /* =>      */ { FP32_QNAN(1),    FP32_RAND_x7_V2 } },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ -1 },
+          { { /*src1     */ { FP32_INF(1),     FP32_RAND_x7_V5 } },
+            { /*src2     */ { FP32_RAND_V2(0), FP32_RAND_x7_V1 } },
+            { /* =>      */ { FP32_QNAN(1),    FP32_RAND_x7_V1 } },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
+              /*256:out  */ -1 },
+          { { /*src1     */ { FP32_INF(1),     FP32_RAND_x7_V6 } },
+            { /*src2     */ { FP32_QNAN(0),    FP32_RAND_x7_V2 } },
+            { /* =>      */ { FP32_QNAN(1),    FP32_RAND_x7_V2 } },
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*256:out  */ -1 },
+          { { /*src1     */ { FP32_INF(1),     FP32_RAND_x7_V3 } },
+            { /*src2     */ { FP32_RAND_V4(0), FP32_RAND_x7_V1 } },
+            { /* =>      */ { FP32_QNAN(1),    FP32_RAND_x7_V1 } },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
+              /*256:out  */ -1 },
+    /*
+     * Normals & Precision (Overflow, Underflow not possible).
+     */
+    /*14*/{ { /*src1     */ { FP32_NORM_V0(0),    FP32_RAND_x7_V3 } },
+            { /*src2     */ { FP32_NORM_V4(0),    FP32_RAND_x7_V0 } },
+            { /* =>      */ { FP32_RSQRT_NORM_V0, FP32_RAND_x7_V0 } },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ -1 },
+
+          { { /*src1     */ { FP32_NORM_V2(0),    FP32_RAND_x7_V6 } },
+            { /*src2     */ { FP32_1(1),          FP32_RAND_x7_V3 } },
+            { /* =>      */ { FP32_RSQRT_NORM_V2, FP32_RAND_x7_V3 } },
+              /*mxcsr:in */ X86_MXCSR_FZ,
+              /*128:out  */ X86_MXCSR_FZ,
+              /*256:out  */ -1 },
+          { { /*src1     */ { FP32_NORM_V3(0),           FP32_0_x7(0)    } },
+            { /*src2     */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_x7_V1 } },
+            { /* =>      */ { FP32_RSQRT_NORM_V3,        FP32_RAND_x7_V1 } },
+              /*mxcsr:in */ X86_MXCSR_DAZ,
+              /*128:out  */ X86_MXCSR_DAZ,
+              /*256:out  */ -1 },
+          { { /*src1     */ { FP32_NORM_MAX(0),    FP32_RAND_x7_V4 } },
+            { /*src2     */ { FP32_NORM_MAX(1),    FP32_RAND_x7_V2 } },
+            { /* =>      */ { FP32_RSQRT_NORM_MAX, FP32_RAND_x7_V2 } },
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_DAZ,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_DAZ,
+              /*256:out  */ -1 },
+          { { /*src1     */ { FP32_NORM_MIN(0),    FP32_RAND_x7_V7 } },
+            { /*src2     */ { FP32_INF(1),         FP32_RAND_x7_V6 } },
+            { /* =>      */ { FP32_RSQRT_NORM_MIN, FP32_RAND_x7_V6 } },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ -1 },
+          { { /*src1     */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V2 } },
+            { /*src2     */ { FP32_RAND_V1(1),           FP32_RAND_x7_V5 } },
+            { /* =>      */ { FP32_RSQRT_NS_INT_MAX,     FP32_RAND_x7_V5 } },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ -1 },
+          { { /*src1     */ { FP32_NORM_SAFE_INT_MIN(0), FP32_RAND_x7_V5 } },
+            { /*src2     */ { FP32_RAND_V0(0),           FP32_RAND_x7_V7 } },
+            { /* =>      */ { FP32_RSQRT_NS_INT_MIN,     FP32_RAND_x7_V7 } },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ -1 },
+          { { /*src1     */ { FP32_VAL_256_0,   FP32_RAND_x7_V0 } },
+            { /*src2     */ { FP32_2(0),        FP32_RAND_x7_V4 } },
+            { /* =>      */ { FP32_RSQRT_256_0, FP32_RAND_x7_V4 } },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO,
+              /*256:out  */ -1 },
+          { { /*src1     */ { FP32_VAL_256_0,    FP32_RAND_x7_V3 } },
+            { /*src2     */ { FP32_DENORM_V3(0), FP32_RAND_x7_V4 } },
+            { /* =>      */ { FP32_RSQRT_256_0,  FP32_RAND_x7_V4 } },
+              /*mxcsr:in */ X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_RC_UP,
+              /*256:out  */ -1 },
+          { { /*src1     */ { FP32_VAL_528_0,            FP32_RAND_x7_V6 } },
+            { /*src2     */ { FP32_NORM_SAFE_INT_MAX(1), FP32_RAND_x7_V7 } },
+            { /* =>      */ { FP32_RSQRT_528_0,          FP32_RAND_x7_V7 } },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ -1 },
+          { { /*src1     */ { FP32_VAL_528_0,            FP32_RAND_x7_V6 } },
+            { /*src2     */ { FP32_NORM_SAFE_INT_MAX(1), FP32_RAND_x7_V7 } },
+            { /* =>      */ { FP32_RSQRT_528_0,          FP32_RAND_x7_V7 } },
+              /*mxcsr:in */ X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_RC_UP,
+              /*256:out  */ -1 },
+    /** @todo Invalids. */
+    /*25*/ /* FP32_TABLE_D10_SS_INVALIDS */
+    };
+#define PASS_s_aValues RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues
+
+    /* Sanity-check subset for 'same register' instruction variants */
+    static BS3CPUINSTR4_TEST1_VALUES_SS_T const s_aValuesSR[] =
+    {
+    /*
+     * Zero.
+     */
+    /* 0*/{ { /*src1     */ { FP32_0(0),   FP32_RAND_x7_V7 } },
+            { /*src2     */ { FP32_0(0),   FP32_RAND_x7_V7 } },
+            { /* =>      */ { FP32_INF(0), FP32_RAND_x7_V7 } },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ -1 },
+          { { /*src1     */ { FP32_INF(1),  FP32_RAND_x7_V6 } },
+            { /*src2     */ { FP32_INF(1),  FP32_RAND_x7_V6 } },
+            { /* =>      */ { FP32_QNAN(1), FP32_RAND_x7_V6 } },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ -1 },
+          { { /*src1     */ { FP32_NORM_V3(0),    FP32_0_x7(0) } },
+            { /*src2     */ { FP32_NORM_V3(0),    FP32_0_x7(0) } },
+            { /* =>      */ { FP32_RSQRT_NORM_V3, FP32_0_x7(0) } },
+              /*mxcsr:in */ X86_MXCSR_DAZ,
+              /*128:out  */ X86_MXCSR_DAZ,
+              /*256:out  */ -1 },
+    };
+#define PASS_s_aValuesSR RT_ELEMENTS(s_aValuesSR), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValuesSR
+    static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
+    {
+        { bs3CpuInstr4_rsqrtss_XMM1_XMM2_icebp_c16,        255,         RM_REG, T_SSE,     1, 1, 2,   PASS_s_aValues   },
+        { bs3CpuInstr4_rsqrtss_XMM1_FSxBX_icebp_c16,       255,         RM_MEM, T_SSE,     1, 1, 255, PASS_s_aValues   },
+
+        { bs3CpuInstr4_vrsqrtss_XMM1_XMM2_XMM3_icebp_c16,  X86_XCPT_AC, RM_REG, T_AVX_128, 1, 2, 3,   PASS_s_aValues   },
+        { bs3CpuInstr4_vrsqrtss_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, PASS_s_aValues   },
+
+        { bs3CpuInstr4_rsqrtss_XMM1_XMM1_icebp_c16,        255,         RM_REG, T_SSE,     1, 1, 1,   PASS_s_aValuesSR },
+        { bs3CpuInstr4_vrsqrtss_XMM1_XMM1_XMM1_icebp_c16,  X86_XCPT_AC, RM_REG, T_AVX_128, 1, 1, 1,   PASS_s_aValuesSR },
+        { bs3CpuInstr4_vrsqrtss_XMM1_XMM1_XMM2_icebp_c16,  X86_XCPT_AC, RM_REG, T_AVX_128, 1, 1, 2,   PASS_s_aValues   },
+        { bs3CpuInstr4_vrsqrtss_XMM1_XMM2_XMM2_icebp_c16,  X86_XCPT_AC, RM_REG, T_AVX_128, 1, 2, 2,   PASS_s_aValuesSR },
+        { bs3CpuInstr4_vrsqrtss_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 1, 255, PASS_s_aValuesSR },
+    };
+    static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
+    {
+        { bs3CpuInstr4_rsqrtss_XMM1_XMM2_icebp_c32,        255,         RM_REG, T_SSE,     1, 1, 2,   PASS_s_aValues   },
+        { bs3CpuInstr4_rsqrtss_XMM1_FSxBX_icebp_c32,       255,         RM_MEM, T_SSE,     1, 1, 255, PASS_s_aValues   },
+
+        { bs3CpuInstr4_vrsqrtss_XMM1_XMM2_XMM3_icebp_c32,  X86_XCPT_AC, RM_REG, T_AVX_128, 1, 2, 3,   PASS_s_aValues   },
+        { bs3CpuInstr4_vrsqrtss_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, PASS_s_aValues   },
+
+        { bs3CpuInstr4_rsqrtss_XMM1_XMM1_icebp_c32,        255,         RM_REG, T_SSE,     1, 1, 1,   PASS_s_aValuesSR },
+        { bs3CpuInstr4_vrsqrtss_XMM1_XMM1_XMM1_icebp_c32,  X86_XCPT_AC, RM_REG, T_AVX_128, 1, 1, 1,   PASS_s_aValuesSR },
+        { bs3CpuInstr4_vrsqrtss_XMM1_XMM1_XMM2_icebp_c32,  X86_XCPT_AC, RM_REG, T_AVX_128, 1, 1, 2,   PASS_s_aValues   },
+        { bs3CpuInstr4_vrsqrtss_XMM1_XMM2_XMM2_icebp_c32,  X86_XCPT_AC, RM_REG, T_AVX_128, 1, 2, 2,   PASS_s_aValuesSR },
+        { bs3CpuInstr4_vrsqrtss_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 1, 255, PASS_s_aValuesSR },
+    };
+    static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
+    {
+        { bs3CpuInstr4_rsqrtss_XMM1_XMM2_icebp_c64,        255,         RM_REG, T_SSE,     1, 1, 2,   PASS_s_aValues   },
+        { bs3CpuInstr4_rsqrtss_XMM1_FSxBX_icebp_c64,       255,         RM_MEM, T_SSE,     1, 1, 255, PASS_s_aValues   },
+
+        { bs3CpuInstr4_rsqrtss_XMM8_XMM9_icebp_c64,        255,         RM_REG, T_SSE,     8, 8, 9,   PASS_s_aValues   },
+        { bs3CpuInstr4_rsqrtss_XMM8_FSxBX_icebp_c64,       255,         RM_MEM, T_SSE,     8, 8, 255, PASS_s_aValues   },
+
+        { bs3CpuInstr4_vrsqrtss_XMM1_XMM2_XMM3_icebp_c64,  X86_XCPT_AC, RM_REG, T_AVX_128, 1, 2, 3,   PASS_s_aValues   },
+        { bs3CpuInstr4_vrsqrtss_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 2, 255, PASS_s_aValues   },
+
+        { bs3CpuInstr4_vrsqrtss_XMM8_XMM9_XMM10_icebp_c64, X86_XCPT_AC, RM_REG, T_AVX_128, 8, 9, 10,  PASS_s_aValues   },
+        { bs3CpuInstr4_vrsqrtss_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 8, 9, 255, PASS_s_aValues   },
+
+        { bs3CpuInstr4_rsqrtss_XMM1_XMM1_icebp_c64,        255,         RM_REG, T_SSE,     1, 1, 1,   PASS_s_aValuesSR },
+        { bs3CpuInstr4_vrsqrtss_XMM1_XMM1_XMM1_icebp_c64,  X86_XCPT_AC, RM_REG, T_AVX_128, 1, 1, 1,   PASS_s_aValuesSR },
+        { bs3CpuInstr4_vrsqrtss_XMM1_XMM1_XMM2_icebp_c64,  X86_XCPT_AC, RM_REG, T_AVX_128, 1, 1, 2,   PASS_s_aValues   },
+        { bs3CpuInstr4_vrsqrtss_XMM1_XMM2_XMM2_icebp_c64,  X86_XCPT_AC, RM_REG, T_AVX_128, 1, 2, 2,   PASS_s_aValuesSR },
+        { bs3CpuInstr4_vrsqrtss_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 1, 255, PASS_s_aValuesSR },
+        { bs3CpuInstr4_vrsqrtss_XMM8_XMM8_XMM8_icebp_c64,  X86_XCPT_AC, RM_REG, T_AVX_128, 8, 8, 8,   PASS_s_aValuesSR },
+    };
+#undef PASS_s_aValues
+#undef PASS_s_aValuesSR
+
+    static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
+    unsigned const                         iTest       = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
+    return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+                                        g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5));
+}
+
+
 /**
  * The 32-bit protected mode main function.
@@ -15869,4 +16127,5 @@
         { "[v]sqrtsd",      bs3CpuInstr4_v_sqrtsd,   0 },
         { "[v]rsqrtps",     bs3CpuInstr4_v_rsqrtps,  0 },
+        { "[v]rsqrtss",     bs3CpuInstr4_v_rsqrtss,  0 },
 #endif
     };
