Changeset 106333 in vbox for trunk/src/VBox/ValidationKit/bootsectors

Timestamp:

Oct 16, 2024 2:38:27 AM (7 months ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

165146

Message:

ValidationKit/bootsectors: Additional same-register testcases for [v]sqrtp[sd], [v]sqrts[sd], [v]rsqrtps; bugref:10658

Location:

trunk/src/VBox/ValidationKit/bootsectors

Files:

• bs3-cpu-instr-4-template.mac (modified) (5 diffs)
• bs3-cpu-instr-4.c32 (modified) (8 diffs)

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4-template.mac

@@ -689 +689 @@
 
 EMIT_INSTR_PLUS_ICEBP       sqrtps,  XMM1, XMM1
+EMIT_INSTR_PLUS_ICEBP_C64   sqrtps,  XMM8, XMM8
 EMIT_INSTR_PLUS_ICEBP       vsqrtps, XMM1, XMM1
 EMIT_INSTR_PLUS_ICEBP       vsqrtps, YMM1, YMM1
+EMIT_INSTR_PLUS_ICEBP_C64   vsqrtps, YMM8, YMM8
 
 ;
@@ -711 +713 @@
 
 EMIT_INSTR_PLUS_ICEBP       sqrtpd,  XMM1, XMM1
+EMIT_INSTR_PLUS_ICEBP_C64   sqrtpd,  XMM8, XMM8
 EMIT_INSTR_PLUS_ICEBP       vsqrtpd, XMM1, XMM1
 EMIT_INSTR_PLUS_ICEBP       vsqrtpd, YMM1, YMM1
+EMIT_INSTR_PLUS_ICEBP_C64   vsqrtpd, YMM8, YMM8
 
 ;
@@ -728 +732 @@
 
 EMIT_INSTR_PLUS_ICEBP       sqrtss,  XMM1, XMM1
+EMIT_INSTR_PLUS_ICEBP_C64   sqrtss,  XMM8, XMM8
 EMIT_INSTR_PLUS_ICEBP       vsqrtss, XMM1, XMM1, XMM1
 EMIT_INSTR_PLUS_ICEBP       vsqrtss, XMM1, XMM1, XMM2
 EMIT_INSTR_PLUS_ICEBP       vsqrtss, XMM1, XMM2, XMM2
+EMIT_INSTR_PLUS_ICEBP_C64   vsqrtss, XMM8, XMM8, XMM8
 EMIT_INSTR_PLUS_ICEBP       vsqrtss, XMM1, XMM1, FSxBX
 
@@ -747 +753 @@
 
 EMIT_INSTR_PLUS_ICEBP       sqrtsd,  XMM1, XMM1
+EMIT_INSTR_PLUS_ICEBP_C64   sqrtsd,  XMM8, XMM8
 EMIT_INSTR_PLUS_ICEBP       vsqrtsd, XMM1, XMM1, XMM1
 EMIT_INSTR_PLUS_ICEBP       vsqrtsd, XMM1, XMM1, XMM2
 EMIT_INSTR_PLUS_ICEBP       vsqrtsd, XMM1, XMM2, XMM2
+EMIT_INSTR_PLUS_ICEBP_C64   vsqrtsd, XMM8, XMM8, XMM8
 EMIT_INSTR_PLUS_ICEBP       vsqrtsd, XMM1, XMM1, FSxBX
 
@@ -771 +779 @@
 
 EMIT_INSTR_PLUS_ICEBP       rsqrtps,  XMM1, XMM1
+EMIT_INSTR_PLUS_ICEBP_C64   rsqrtps,  XMM8, XMM8
 EMIT_INSTR_PLUS_ICEBP       vrsqrtps, XMM1, XMM1
 EMIT_INSTR_PLUS_ICEBP       vrsqrtps, YMM1, YMM1
+EMIT_INSTR_PLUS_ICEBP_C64   vrsqrtps, YMM8, YMM8
 
 ;

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32

@@ -12911 +12911 @@
  * [V]RCPPS.
  */
+/** @todo this fails entirely under IEM: the instructions rcpps, rcpss, rsqrtps, rsqrtss are all implemented with too much precision & attention to exceptions! */
 BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_rcpps(uint8_t bMode)
 {
@@ -13243 +13244 @@
  * [V]RCPSS.
  */
+/** @todo this fails entirely under IEM: the instructions rcpps, rcpss, rsqrtps, rsqrtss are all implemented with too much precision & attention to exceptions! */
 BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_rcpss(uint8_t bMode)
 {
@@ -14415 +14417 @@
 
         { bs3CpuInstr4_sqrtps_XMM1_XMM1_icebp_c64,   255, RM_REG, T_SSE,     1, 1, 1,   PASS_s_aValues },
+        { bs3CpuInstr4_sqrtps_XMM8_XMM8_icebp_c64,   255, RM_REG, T_SSE,     8, 8, 8,   PASS_s_aValues },
         { bs3CpuInstr4_vsqrtps_XMM1_XMM1_icebp_c64,  255, RM_REG, T_AVX_128, 1, 1, 1,   PASS_s_aValues },
         { bs3CpuInstr4_vsqrtps_YMM1_YMM1_icebp_c64,  255, RM_REG, T_AVX_256, 1, 1, 1,   PASS_s_aValues },
+        { bs3CpuInstr4_vsqrtps_YMM8_YMM8_icebp_c64,  255, RM_REG, T_AVX_256, 8, 8, 8,   PASS_s_aValues },
     };
 #undef PASS_s_aValues
@@ -14681 +14685 @@
 
         { bs3CpuInstr4_sqrtpd_XMM1_XMM1_icebp_c64,   255, RM_REG, T_SSE,     1, 1, 1,   PASS_s_aValues },
+        { bs3CpuInstr4_sqrtpd_XMM8_XMM8_icebp_c64,   255, RM_REG, T_SSE,     8, 8, 8,   PASS_s_aValues },
         { bs3CpuInstr4_vsqrtpd_XMM1_XMM1_icebp_c64,  255, RM_REG, T_AVX_128, 1, 1, 1,   PASS_s_aValues },
         { bs3CpuInstr4_vsqrtpd_YMM1_YMM1_icebp_c64,  255, RM_REG, T_AVX_256, 1, 1, 1,   PASS_s_aValues },
+        { bs3CpuInstr4_vsqrtpd_YMM8_YMM8_icebp_c64,  255, RM_REG, T_AVX_256, 8, 8, 8,   PASS_s_aValues },
     };
 #undef PASS_s_aValues
@@ -15110 +15116 @@
 
         { bs3CpuInstr4_sqrtss_XMM1_XMM1_icebp_c64,        255,         RM_REG, T_SSE,     1, 1, 1,   PASS_s_aValuesSR },
+        { bs3CpuInstr4_sqrtss_XMM8_XMM8_icebp_c64,        255,         RM_REG, T_SSE,     8, 8, 8,   PASS_s_aValuesSR },
         { bs3CpuInstr4_vsqrtss_XMM1_XMM1_XMM1_icebp_c64,  X86_XCPT_AC, RM_REG, T_AVX_128, 1, 1, 1,   PASS_s_aValuesSR },
         { bs3CpuInstr4_vsqrtss_XMM1_XMM1_XMM2_icebp_c64,  X86_XCPT_AC, RM_REG, T_AVX_128, 1, 1, 2,   PASS_s_aValues   },
         { bs3CpuInstr4_vsqrtss_XMM1_XMM2_XMM2_icebp_c64,  X86_XCPT_AC, RM_REG, T_AVX_128, 1, 2, 2,   PASS_s_aValuesSR },
+        { bs3CpuInstr4_vsqrtss_XMM8_XMM8_XMM8_icebp_c64,  X86_XCPT_AC, RM_REG, T_AVX_128, 8, 8, 8,   PASS_s_aValuesSR },
         { bs3CpuInstr4_vsqrtss_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 1, 255, PASS_s_aValues   },
     };
@@ -15542 +15550 @@
 
         { bs3CpuInstr4_sqrtsd_XMM1_XMM1_icebp_c64,        255,         RM_REG, T_SSE,     1, 1, 1,   PASS_s_aValuesSR },
+        { bs3CpuInstr4_sqrtsd_XMM8_XMM8_icebp_c64,        255,         RM_REG, T_SSE,     8, 8, 8,   PASS_s_aValuesSR },
         { bs3CpuInstr4_vsqrtsd_XMM1_XMM1_XMM1_icebp_c64,  X86_XCPT_AC, RM_REG, T_AVX_128, 1, 1, 1,   PASS_s_aValuesSR },
         { bs3CpuInstr4_vsqrtsd_XMM1_XMM1_XMM2_icebp_c64,  X86_XCPT_AC, RM_REG, T_AVX_128, 1, 1, 2,   PASS_s_aValues   },
         { bs3CpuInstr4_vsqrtsd_XMM1_XMM2_XMM2_icebp_c64,  X86_XCPT_AC, RM_REG, T_AVX_128, 1, 2, 2,   PASS_s_aValuesSR },
+        { bs3CpuInstr4_vsqrtsd_XMM8_XMM8_XMM8_icebp_c64,  X86_XCPT_AC, RM_REG, T_AVX_128, 8, 8, 8,   PASS_s_aValuesSR },
         { bs3CpuInstr4_vsqrtsd_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 1, 255, PASS_s_aValues   },
     };
@@ -15560 +15570 @@
  * [V]RSQRTPS.
  */
-/** @todo this fails entirely under IEM: the instructions rcpps, rcpss, rsqrtps, rsqrtss, are all implemented with too much precision! */
+/** @todo this fails entirely under IEM: the instructions rcpps, rcpss, rsqrtps, rsqrtss are all implemented with too much precision & attention to exceptions! */
 BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_rsqrtps(uint8_t bMode)
 {
@@ -15801 +15811 @@
 
         { bs3CpuInstr4_rsqrtps_XMM1_XMM1_icebp_c64,   255, RM_REG, T_SSE,     1, 1, 1,   PASS_s_aValues },
+        { bs3CpuInstr4_rsqrtps_XMM8_XMM8_icebp_c64,   255, RM_REG, T_SSE,     8, 8, 8,   PASS_s_aValues },
         { bs3CpuInstr4_vrsqrtps_XMM1_XMM1_icebp_c64,  255, RM_REG, T_AVX_128, 1, 1, 1,   PASS_s_aValues },
         { bs3CpuInstr4_vrsqrtps_YMM1_YMM1_icebp_c64,  255, RM_REG, T_AVX_256, 1, 1, 1,   PASS_s_aValues },
+        { bs3CpuInstr4_vrsqrtps_YMM8_YMM8_icebp_c64,  255, RM_REG, T_AVX_256, 8, 8, 8,   PASS_s_aValues },
     };
 #undef PASS_s_aValues