Changeset 106334 in vbox for trunk/src/VBox/ValidationKit

Timestamp:

Oct 16, 2024 3:01:44 AM (3 months ago)

Author:

vboxsync

Message:

ValidationKit/bootsectors: SIMD FP testcases: clean up PASS_s_aValues macros; bugref:10658

File:

• trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32 (modified) (80 diffs)

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32

@@ -2485 +2485 @@
     { { a_aTests16, RT_ELEMENTS(a_aTests16) }, { a_aTests32, RT_ELEMENTS(a_aTests32) }, { a_aTests64, RT_ELEMENTS(a_aTests64) } }
 
+/** Utility macros for inserting value table references into test arrays. */
+#define PASS_s_aArray(s_aValues)  RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues
+#define PASS_s_aValues            PASS_s_aArray(s_aValues)
+#define PASS_s_aValuesSR          PASS_s_aArray(s_aValuesSR)
+
 typedef struct BS3CPUINSTR4_TEST1_CTX_T
 {
@@ -3364 +3369 @@
     };
 
-#define PASS_s_aValues RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues
     static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
     {
@@ -3406 +3410 @@
         { bs3CpuInstr4_vaddps_YMM8_YMM9_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 8, 9, 255, PASS_s_aValues },
     };
-#undef PASS_s_aValues
 
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
@@ -3635 +3638 @@
     };
 
-#define PASS_s_aValues RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues
     static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
     {
@@ -3677 +3679 @@
         { bs3CpuInstr4_vaddpd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_256, 8, 9, 255, PASS_s_aValues },
     };
-#undef PASS_s_aValues
 
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
@@ -3941 +3942 @@
     };
 
-#define PASS_s_aValues RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues
     static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
     {
@@ -3972 +3972 @@
         { bs3CpuInstr4_vaddss_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 8, 9, 255, PASS_s_aValues },
     };
-#undef PASS_s_aValues
 
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
@@ -4250 +4249 @@
     };
 
-#define PASS_s_aValues RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues
     static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
     {
@@ -4281 +4279 @@
         { bs3CpuInstr4_vaddsd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 8, 9, 255, PASS_s_aValues },
     };
-#undef PASS_s_aValues
 
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
@@ -4572 +4569 @@
     };
 
-#define PASS_s_aValues RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues
     static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
     {
@@ -4614 +4610 @@
         { bs3CpuInstr4_vhaddps_YMM8_YMM9_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 8, 9, 255, PASS_s_aValues },
     };
-#undef PASS_s_aValues
 
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
@@ -4875 +4870 @@
     };
 
-#define PASS_s_aValues RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues
     static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
     {
@@ -4917 +4911 @@
         { bs3CpuInstr4_vhaddpd_YMM8_YMM9_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 8, 9, 255, PASS_s_aValues },
     };
-#undef PASS_s_aValues
 
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
@@ -5252 +5245 @@
     };
 
-#define PASS_s_aValues RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues
     static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
     {
@@ -5294 +5286 @@
         { bs3CpuInstr4_vsubps_YMM8_YMM9_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 8, 9, 255, PASS_s_aValues },
     };
-#undef PASS_s_aValues
 
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
@@ -5539 +5530 @@
     };
 
-#define PASS_s_aValues RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues
     static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
     {
@@ -5581 +5571 @@
         { bs3CpuInstr4_vsubpd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_256, 8, 9, 255, PASS_s_aValues },
     };
-#undef PASS_s_aValues
 
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
@@ -5851 +5840 @@
     };
 
-#define PASS_s_aValues RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues
     static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
     {
@@ -5882 +5870 @@
         { bs3CpuInstr4_vsubss_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 8, 9, 255, PASS_s_aValues },
     };
-#undef PASS_s_aValues
 
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
@@ -6181 +6168 @@
     };
 
-#define PASS_s_aValues RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues
     static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
     {
@@ -6212 +6198 @@
         { bs3CpuInstr4_vsubsd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 8, 9, 255, PASS_s_aValues },
     };
-#undef PASS_s_aValues
 
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
@@ -6503 +6488 @@
     };
 
-#define PASS_s_aValues RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues
     static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
     {
@@ -6545 +6529 @@
         { bs3CpuInstr4_vhsubps_YMM8_YMM9_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 8, 9, 255, PASS_s_aValues },
     };
-#undef PASS_s_aValues
 
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
@@ -6778 +6761 @@
     };
 
-#define PASS_s_aValues RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues
     static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
     {
@@ -6820 +6802 @@
         { bs3CpuInstr4_vhsubpd_YMM8_YMM9_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 8, 9, 255, PASS_s_aValues },
     };
-#undef PASS_s_aValues
 
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
@@ -7179 +7160 @@
     };
 
-#define PASS_s_aValues RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues
     static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
     {
@@ -7221 +7201 @@
         { bs3CpuInstr4_vmulps_YMM8_YMM9_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 8, 9, 255, PASS_s_aValues },
     };
-#undef PASS_s_aValues
 
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
@@ -7458 +7437 @@
     };
 
-#define PASS_s_aValues RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues
     static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
     {
@@ -7500 +7478 @@
         { bs3CpuInstr4_vmulpd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_256, 8, 9, 255, PASS_s_aValues },
     };
-#undef PASS_s_aValues
 
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
@@ -7699 +7676 @@
     };
 
-#define PASS_s_aValues RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues
     static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
     {
@@ -7730 +7706 @@
         { bs3CpuInstr4_vmulss_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 8, 9, 255, PASS_s_aValues },
     };
-#undef PASS_s_aValues
 
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
@@ -7995 +7970 @@
     };
 
-#define PASS_s_aValues RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues
     static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
     {
@@ -8026 +8000 @@
         { bs3CpuInstr4_vmulsd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 8, 9, 255, PASS_s_aValues },
     };
-#undef PASS_s_aValues
 
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
@@ -8342 +8315 @@
     };
 
-#define PASS_s_aValues RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues
     static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
     {
@@ -8384 +8356 @@
         { bs3CpuInstr4_vdivps_YMM8_YMM9_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 8, 9, 255, PASS_s_aValues },
     };
-#undef PASS_s_aValues
 
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
@@ -8679 +8650 @@
     };
 
-#define PASS_s_aValues RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues
     static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
     {
@@ -8721 +8691 @@
         { bs3CpuInstr4_vdivpd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_256, 8, 9, 255, PASS_s_aValues },
     };
-#undef PASS_s_aValues
 
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
@@ -8922 +8891 @@
 /** @todo Make cdefs.h 'RT_ELEMENTS(arr), arr' macro?  But extra cast, here. */
 /** @todo Do this to existing instr-4 tests?  instr-3?  Beyond? */
-#define PASS_s_aValues RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues
     static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
     {
@@ -8953 +8921 @@
         { bs3CpuInstr4_vdivss_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 8, 9, 255, PASS_s_aValues },
     };
-#undef PASS_s_aValues
 
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
@@ -9298 +9265 @@
     };
 
-#define PASS_s_aValues RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues
     static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
     {
@@ -9329 +9295 @@
         { bs3CpuInstr4_vdivsd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 8, 9, 255, PASS_s_aValues },
     };
-#undef PASS_s_aValues
 
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
@@ -9655 +9620 @@
     };
 
-#define PASS_s_aValues RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues
     static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
     {
@@ -9697 +9661 @@
         { bs3CpuInstr4_vaddsubps_YMM13_YMM14_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 13, 14, 255, PASS_s_aValues },
     };
-#undef PASS_s_aValues
 
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
@@ -10105 +10068 @@
     };
 
-#define PASS_s_aValues RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues
     static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
     {
@@ -10147 +10109 @@
         { bs3CpuInstr4_vaddsubpd_YMM13_YMM14_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 13, 14, 255, PASS_s_aValues },
     };
-#undef PASS_s_aValues
 
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
@@ -10390 +10351 @@
     };
 
-#define PASS_s_aValues RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues
     static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
     {
@@ -10432 +10392 @@
         { bs3CpuInstr4_vmaxps_YMM8_YMM9_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 8, 9, 255, PASS_s_aValues },
     };
-#undef PASS_s_aValues
 
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
@@ -10677 +10636 @@
     };
 
-#define PASS_s_aValues RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues
     static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
     {
@@ -10719 +10677 @@
         { bs3CpuInstr4_vmaxpd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_256, 8, 9, 255, PASS_s_aValues },
     };
-#undef PASS_s_aValues
 
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
@@ -11089 +11046 @@
     };
 
-#define PASS_s_aValues RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues
     static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
     {
@@ -11120 +11076 @@
         { bs3CpuInstr4_vmaxss_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 8, 9, 255, PASS_s_aValues },
     };
-#undef PASS_s_aValues
 
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
@@ -11492 +11447 @@
     };
 
-#define PASS_s_aValues RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues
     static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
     {
@@ -11523 +11477 @@
         { bs3CpuInstr4_vmaxsd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 8, 9, 255, PASS_s_aValues },
     };
-#undef PASS_s_aValues
 
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
@@ -11766 +11719 @@
     };
 
-#define PASS_s_aValues RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues
     static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
     {
@@ -11808 +11760 @@
         { bs3CpuInstr4_vminps_YMM8_YMM9_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 8, 9, 255, PASS_s_aValues },
     };
-#undef PASS_s_aValues
 
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
@@ -12053 +12004 @@
     };
 
-#define PASS_s_aValues RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues
     static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
     {
@@ -12095 +12045 @@
         { bs3CpuInstr4_vminpd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_256, 8, 9, 255, PASS_s_aValues },
     };
-#undef PASS_s_aValues
 
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
@@ -12465 +12414 @@
     };
 
-#define PASS_s_aValues RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues
     static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
     {
@@ -12496 +12444 @@
         { bs3CpuInstr4_vminss_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 8, 9, 255, PASS_s_aValues },
     };
-#undef PASS_s_aValues
 
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
@@ -12868 +12815 @@
     };
 
-#define PASS_s_aValues RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues
     static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
     {
@@ -12899 +12845 @@
         { bs3CpuInstr4_vminsd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 8, 9, 255, PASS_s_aValues },
     };
-#undef PASS_s_aValues
 
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
@@ -13190 +13135 @@
     };
 
-#define PASS_s_aValues RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues
     static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
     {
@@ -13232 +13176 @@
         { bs3CpuInstr4_vrcpps_YMM8_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 8, 8, 255, PASS_s_aValues },
     };
-#undef PASS_s_aValues
 
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
@@ -14054 +13997 @@
     };
 
-#define PASS_s_aValues   RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues
-#define PASS_s_aValuesSR RT_ELEMENTS(s_aValuesSR), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValuesSR
     static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
     {
@@ -14109 +14050 @@
         { bs3CpuInstr4_vrcpss_XMM13_XMM14_XMM14_icebp_c64, X86_XCPT_AC, RM_REG, T_AVX_128, 13, 14, 14,  PASS_s_aValuesSR },
     };
-#undef PASS_s_aValues
-#undef PASS_s_aValuesSR
 
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
@@ -14366 +14305 @@
     };
 
-#define PASS_s_aValues RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues
     static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
     {
@@ -14422 +14360 @@
         { bs3CpuInstr4_vsqrtps_YMM8_YMM8_icebp_c64,  255, RM_REG, T_AVX_256, 8, 8, 8,   PASS_s_aValues },
     };
-#undef PASS_s_aValues
 
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
@@ -14634 +14571 @@
     };
 
-#define PASS_s_aValues RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues
     static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
     {
@@ -14690 +14626 @@
         { bs3CpuInstr4_vsqrtpd_YMM8_YMM8_icebp_c64,  255, RM_REG, T_AVX_256, 8, 8, 8,   PASS_s_aValues },
     };
-#undef PASS_s_aValues
 
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
@@ -14985 +14920 @@
     /*44*/ /* FP64_TABLE_D10_SS_INVALIDS */
     };
-#define PASS_s_aValues RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues
 
     /* Sanity-check subset for 'same register' instruction variants */
@@ -15071 +15005 @@
     /*11*/ /* FP64_TABLE_D10_SS_INVALIDS // or excerpt? */
     };
-#define PASS_s_aValuesSR RT_ELEMENTS(s_aValuesSR), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValuesSR
 
     static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
@@ -15123 +15056 @@
         { bs3CpuInstr4_vsqrtss_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 1, 255, PASS_s_aValues   },
     };
-#undef PASS_s_aValues
-#undef PASS_s_aValuesSR
 
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
@@ -15419 +15350 @@
     /*44*/ /* FP64_TABLE_D10_SD_INVALIDS */
     };
-#define PASS_s_aValues RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues
 
     /* Sanity-check subset for 'same register' instruction variants */
@@ -15505 +15435 @@
     /*11*/ /* FP64_TABLE_D10_SD_INVALIDS // or excerpt? */
     };
-#define PASS_s_aValuesSR RT_ELEMENTS(s_aValuesSR), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValuesSR
 
     static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
@@ -15557 +15486 @@
         { bs3CpuInstr4_vsqrtsd_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 1, 255, PASS_s_aValues   },
     };
-#undef PASS_s_aValues
-#undef PASS_s_aValuesSR
 
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
@@ -15760 +15687 @@
     };
 
-#define PASS_s_aValues RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues
     static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
     {
@@ -15816 +15742 @@
         { bs3CpuInstr4_vrsqrtps_YMM8_YMM8_icebp_c64,  255, RM_REG, T_AVX_256, 8, 8, 8,   PASS_s_aValues },
     };
-#undef PASS_s_aValues
 
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
@@ -15996 +15921 @@
     /*25*/ /* FP32_TABLE_D10_SS_INVALIDS */
     };
-#define PASS_s_aValues RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues
 
     /* Sanity-check subset for 'same register' instruction variants */
@@ -16023 +15947 @@
               /*256:out  */ -1 },
     };
-#define PASS_s_aValuesSR RT_ELEMENTS(s_aValuesSR), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValuesSR
     static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
     {
@@ -16073 +15996 @@
         { bs3CpuInstr4_vrsqrtss_XMM8_XMM8_XMM8_icebp_c64,  X86_XCPT_AC, RM_REG, T_AVX_128, 8, 8, 8,   PASS_s_aValuesSR },
     };
-#undef PASS_s_aValues
-#undef PASS_s_aValuesSR
 
     static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);