Changeset 106382 in vbox for trunk/src/VBox/VMM

Timestamp:

Oct 16, 2024 1:53:23 PM (3 months ago)

Author:

vboxsync

Message:

VMM/PGM-armv8.cpp: Sketch some page table walking code for the debugger, nowhere near complete, bugref:10388 bugref:10393

Location:

trunk/src/VBox/VMM/VMMR3

Files:

• PGM-armv8.cpp (modified) (3 diffs)
• PGMDbg.cpp (modified) (4 diffs)

trunk/src/VBox/VMM/VMMR3/PGM-armv8.cpp

@@ -743 +743 @@
 
 
+DECLINLINE(int) pgmGstWalkReturnNotPresent(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint8_t uLevel)
+{
+    NOREF(pVCpu);
+    pWalk->fNotPresent     = true;
+    pWalk->uLevel          = uLevel;
+    pWalk->fFailed         = PGM_WALKFAIL_NOT_PRESENT
+                           | ((uint32_t)uLevel << PGM_WALKFAIL_LEVEL_SHIFT);
+    return VERR_PAGE_TABLE_NOT_PRESENT;
+}
+
+DECLINLINE(int) pgmGstWalkReturnBadPhysAddr(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint8_t uLevel, int rc)
+{
+    AssertMsg(rc == VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS, ("%Rrc\n", rc)); NOREF(rc); NOREF(pVCpu);
+    pWalk->fBadPhysAddr    = true;
+    pWalk->uLevel          = uLevel;
+    pWalk->fFailed         = PGM_WALKFAIL_BAD_PHYSICAL_ADDRESS
+                           | ((uint32_t)uLevel << PGM_WALKFAIL_LEVEL_SHIFT);
+    return VERR_PAGE_TABLE_NOT_PRESENT;
+}
+
+
+DECLINLINE(int) pgmGstWalkReturnRsvdError(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint8_t uLevel)
+{
+    NOREF(pVCpu);
+    pWalk->fRsvdError      = true;
+    pWalk->uLevel          = uLevel;
+    pWalk->fFailed         = PGM_WALKFAIL_RESERVED_BITS
+                           | ((uint32_t)uLevel << PGM_WALKFAIL_LEVEL_SHIFT);
+    return VERR_PAGE_TABLE_NOT_PRESENT;
+}
+
+
 VMMDECL(int) PGMGstGetPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk)
 {
     VMCPU_ASSERT_EMT(pVCpu);
     Assert(pWalk);
-    //AssertReleaseFailed();
+#ifndef DEBUG_aeichner
+    AssertReleaseFailed();
     RT_NOREF(pVCpu, GCPtr, pWalk);
     return VERR_NOT_IMPLEMENTED;
+#else
+    pWalk->fSucceeded = false;
+
+    RTGCPHYS GCPhysPt = CPUMGetEffectiveTtbr(pVCpu, GCPtr);
+    if (GCPhysPt == RTGCPHYS_MAX) /* MMU disabled? */
+    {
+        pWalk->GCPtr      = GCPtr;
+        pWalk->fSucceeded = true;
+        pWalk->GCPhys     = GCPtr;
+        return VINF_SUCCESS;
+    }
+
+    /* Do the translation. */
+    /** @todo This is just a sketch to get something working for debugging, assumes 4KiB granules and 48-bit output address.
+     *        Needs to be moved to PGMAllGst like on x86 and implemented for 16KiB and 64KiB granule sizes. */
+    uint64_t u64TcrEl1 = CPUMGetTcrEl1(pVCpu);
+    uint8_t u8TxSz =   (GCPtr & RT_BIT_64(55))
+                     ? ARMV8_TCR_EL1_AARCH64_T1SZ_GET(u64TcrEl1)
+                     : ARMV8_TCR_EL1_AARCH64_T0SZ_GET(u64TcrEl1);
+    uint8_t uLookupLvl;
+    RTGCPHYS fLookupMask;
+
+    /*
+     * From: https://github.com/codingbelief/arm-architecture-reference-manual-for-armv8-a/blob/master/en/chapter_d4/d42_2_controlling_address_translation_stages.md
+     * For all translation stages
+     * The maximum TxSZ value is 39. If TxSZ is programmed to a value larger than 39 then it is IMPLEMENTATION DEFINED whether:
+     *     - The implementation behaves as if the field is programmed to 39 for all purposes other than reading back the value of the field.
+     *     - Any use of the TxSZ value generates a Level 0 Translation fault for the stage of translation at which TxSZ is used.
+     *
+     * For a stage 1 translation
+     * The minimum TxSZ value is 16. If TxSZ is programmed to a value smaller than 16 then it is IMPLEMENTATION DEFINED whether:
+     *     - The implementation behaves as if the field were programmed to 16 for all purposes other than reading back the value of the field.
+     *     - Any use of the TxSZ value generates a stage 1 Level 0 Translation fault.
+     *
+     * We currently choose the former for both.
+     */
+    if (/*u8TxSz >= 16 &&*/ u8TxSz <= 24)
+    {
+        uLookupLvl = 0;
+        fLookupMask = RT_BIT_64(24 - u8TxSz + 1) - 1;
+    }
+    else if (u8TxSz >= 25 && u8TxSz <= 33)
+    {
+        uLookupLvl = 1;
+        fLookupMask = RT_BIT_64(33 - u8TxSz + 1) - 1;
+    }
+    else /*if (u8TxSz >= 34 && u8TxSz <= 39)*/
+    {
+        uLookupLvl = 2;
+        fLookupMask = RT_BIT_64(39 - u8TxSz + 1) - 1;
+    }
+    /*else
+        return pgmGstWalkReturnBadPhysAddr(pVCpu, pWalk, 0, VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS);*/ /** @todo Better status (Invalid TCR config). */
+
+    uint64_t *pu64Pt = NULL;
+    uint64_t uPt;
+    int rc;
+    if (uLookupLvl == 0)
+    {
+        rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhysPt, &pu64Pt);
+        if (RT_SUCCESS(rc)) { /* probable */ }
+        else return pgmGstWalkReturnBadPhysAddr(pVCpu, pWalk, 0, rc);
+
+        uPt = pu64Pt[(GCPtr >> 39) & fLookupMask];
+        if (uPt & RT_BIT_64(0)) { /* probable */ }
+        else return pgmGstWalkReturnNotPresent(pVCpu, pWalk, 0);
+
+        if (uPt & RT_BIT_64(1)) { /* probable */ }
+        else return pgmGstWalkReturnRsvdError(pVCpu, pWalk, 0); /** @todo Only supported if TCR_EL1.DS is set. */
+
+        /* All nine bits from now on. */
+        fLookupMask = RT_BIT_64(9) - 1;
+        GCPhysPt = (RTGCPHYS)(uPt & UINT64_C(0xfffffffff000));
+    }
+
+    if (uLookupLvl <= 1)
+    {
+        rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhysPt, &pu64Pt);
+        if (RT_SUCCESS(rc)) { /* probable */ }
+        else return pgmGstWalkReturnBadPhysAddr(pVCpu, pWalk, 1, rc);
+
+        uPt = pu64Pt[(GCPtr >> 30) & fLookupMask];
+        if (uPt & RT_BIT_64(0)) { /* probable */ }
+        else return pgmGstWalkReturnNotPresent(pVCpu, pWalk, 1);
+
+        if (uPt & RT_BIT_64(1)) { /* probable */ }
+        else
+        {
+            /* Block descriptor (1G page). */
+            pWalk->GCPtr       = GCPtr;
+            pWalk->fSucceeded  = true;
+            pWalk->GCPhys      = (RTGCPHYS)(uPt & UINT64_C(0xffffc0000000)) | (GCPtr & (RTGCPTR)(_1G - 1));
+            pWalk->fGigantPage = true;
+            return VINF_SUCCESS;
+        }
+
+        /* All nine bits from now on. */
+        fLookupMask = RT_BIT_64(9) - 1;
+        GCPhysPt = (RTGCPHYS)(uPt & UINT64_C(0xfffffffff000));
+    }
+
+    if (uLookupLvl <= 2)
+    {
+        rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhysPt, &pu64Pt);
+        if (RT_SUCCESS(rc)) { /* probable */ }
+        else return pgmGstWalkReturnBadPhysAddr(pVCpu, pWalk, 2, rc);
+
+        uPt = pu64Pt[(GCPtr >> 21) & fLookupMask];
+        if (uPt & RT_BIT_64(0)) { /* probable */ }
+        else return pgmGstWalkReturnNotPresent(pVCpu, pWalk, 2);
+
+        if (uPt & RT_BIT_64(1)) { /* probable */ }
+        else
+        {
+            /* Block descriptor (2M page). */
+            pWalk->GCPtr      = GCPtr;
+            pWalk->fSucceeded = true;
+            pWalk->GCPhys     = (RTGCPHYS)(uPt & UINT64_C(0xffffffe00000)) | (GCPtr & (RTGCPTR)(_2M - 1));
+            pWalk->fBigPage = true;
+            return VINF_SUCCESS;
+        }
+
+        /* All nine bits from now on. */
+        fLookupMask = RT_BIT_64(9) - 1;
+        GCPhysPt = (RTGCPHYS)(uPt & UINT64_C(0xfffffffff000));
+    }
+
+    Assert(uLookupLvl <= 3);
+
+    /* Next level. */
+    rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhysPt, &pu64Pt);
+    if (RT_SUCCESS(rc)) { /* probable */ }
+    else return pgmGstWalkReturnBadPhysAddr(pVCpu, pWalk, 3, rc);
+
+    uPt = pu64Pt[(GCPtr & UINT64_C(0x1ff000)) >> 12];
+    if (uPt & RT_BIT_64(0)) { /* probable */ }
+    else return pgmGstWalkReturnNotPresent(pVCpu, pWalk, 3);
+
+    if (uPt & RT_BIT_64(1)) { /* probable */ }
+    else return pgmGstWalkReturnRsvdError(pVCpu, pWalk, 3); /** No block descriptors. */
+
+    pWalk->GCPtr      = GCPtr;
+    pWalk->fSucceeded = true;
+    pWalk->GCPhys     = (RTGCPHYS)(uPt & UINT64_C(0xfffffffff000)) | (GCPtr & (RTGCPTR)(_4K - 1));
+    return VINF_SUCCESS;
+#endif
 }
 
@@ -816 +995 @@
 {
     VMCPU_ASSERT_EMT(pVCpu);
-    AssertReleaseFailed();
-    RT_NOREF(pVCpu, GCPtr, pWalk, pGstWalk);
-    return VERR_NOT_IMPLEMENTED;
+    RT_NOREF(pGstWalk);
+    return PGMGstGetPage(pVCpu, GCPtr, pWalk);
 }
 
@@ -825 +1003 @@
 {
     VMCPU_ASSERT_EMT(pVCpu);
-    AssertReleaseFailed();
-    RT_NOREF(pVCpu, GCPtr, pWalk, pGstWalk);
-    return VERR_NOT_IMPLEMENTED;
-}
+    return pgmGstPtWalk(pVCpu, GCPtr, pWalk, pGstWalk); /** @todo Always do full walk for now. */
+}

trunk/src/VBox/VMM/VMMR3/PGMDbg.cpp

@@ -1084 +1084 @@
         else
         {
+#ifndef VBOX_VMM_TARGET_ARMV8
             Assert(WalkGst.enmType != PGMPTWALKGSTTYPE_INVALID);
+#endif
             Assert(!Walk.fSucceeded);
             cbPrev = 0; /* ignore error. */
@@ -1093 +1095 @@
              */
             uint64_t cPagesCanSkip;
+#ifndef VBOX_VMM_TARGET_ARMV8
             switch (Walk.uLevel)
             {
@@ -1141 +1144 @@
                 continue;
             }
+#else
+            /** @todo Sketch, needs creating proper defines for constants in armv8.h and using these
+             * instead of hardcoding these here. */
+            switch (Walk.uLevel)
+            {
+                case 0:
+                case 1:
+                    cPagesCanSkip = (512 - ((GCPtr >> 21) & 0x1ff)) * 512
+                                  - ((GCPtr >> 12) & 0x1ff);
+                    Assert(!((GCPtr + ((RTGCPTR)cPagesCanSkip << 12)) & (RT_BIT_64(21) - 1)));
+                    break;
+                case 2:
+                    cPagesCanSkip = 512 - ((GCPtr >> 12) & 0x1ff);
+                    Assert(!((GCPtr + ((RTGCPTR)cPagesCanSkip << 12)) & (RT_BIT_64(12) - 1)));
+                    break;
+                case 3:
+                    /* page level, use cIncPages */
+                    cPagesCanSkip = 1;
+                    break;
+                default:
+                    AssertMsgFailed(("%d\n", Walk.uLevel));
+                    cPagesCanSkip = 0;
+                    break;
+            }
+
+            if (cPages <= cPagesCanSkip)
+                break;
+            fFullWalk = true;
+            if (cPagesCanSkip >= cIncPages)
+            {
+                cPages -= cPagesCanSkip;
+                GCPtr += (RTGCPTR)cPagesCanSkip << 12;
+                continue;
+            }
+#endif
         }
 
@@ -1147 +1185 @@
             break;
         cPages -= cIncPages;
+#ifndef VBOX_VMM_TARGET_ARMV8
         GCPtr += (RTGCPTR)cIncPages << X86_PT_PAE_SHIFT;
+#else
+        GCPtr += (RTGCPTR)cIncPages << 12;
+#endif
 
         /* Yield the PGM lock every now and then. */