Index: trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompFuncs.h
===================================================================
--- trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompFuncs.h	(revision 106445)
+++ trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompFuncs.h	(revision 106453)
@@ -80,8 +80,4 @@
 #endif
 
-#if defined(IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS) && !defined(IEMNATIVE_WITH_SIMD_REG_ALLOCATOR)
-# error "IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS requires IEMNATIVE_WITH_SIMD_REG_ALLOCATOR"
-#endif
-
 
 /*********************************************************************************************************************************
@@ -190,6 +186,7 @@
  * RIP updates, since these are the most common ones.
  */
-DECL_INLINE_THROW(uint32_t)
-iemNativeRegFlushPendingSpecificWrite(PIEMRECOMPILERSTATE pReNative, uint32_t off, IEMNATIVEGSTREGREF enmClass, uint8_t idxReg)
+template<IEMNATIVEGSTREGREF a_enmClass>
+DECL_INLINE_THROW(uint32_t)
+iemNativeRegFlushPendingSpecificWrite(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxReg)
 {
 #ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING
@@ -198,30 +195,29 @@
 
 #ifdef IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
-#if 0 /** @todo r=aeichner EFLAGS writeback delay. */
-    if (   enmClass == kIemNativeGstRegRef_EFlags
-        && pReNative->Core.bmGstRegShadowDirty & RT_BIT_64(kIemNativeGstReg_EFlags))
-        off = iemNativeRegFlushPendingWrite(pReNative, off, kIemNativeGstReg_EFlags);
-#else
+# if 0 /** @todo r=aeichner EFLAGS writeback delay. */
+    if RT_CONSTEXPR_IF(a_enmClass == kIemNativeGstRegRef_EFlags)
+        if (pReNative->Core.bmGstRegShadowDirty & RT_BIT_64(kIemNativeGstReg_EFlags))
+            off = iemNativeRegFlushPendingWrite(pReNative, off, kIemNativeGstReg_EFlags);
+# else
     Assert(!(pReNative->Core.bmGstRegShadowDirty & RT_BIT_64(kIemNativeGstReg_EFlags)));
-#endif
-
-    if (   enmClass == kIemNativeGstRegRef_Gpr
-        && pReNative->Core.bmGstRegShadowDirty & RT_BIT_64(idxReg))
-        off = iemNativeRegFlushPendingWrite(pReNative, off, IEMNATIVEGSTREG_GPR(idxReg));
-#endif
-
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
-    if (   enmClass == kIemNativeGstRegRef_XReg
-        && pReNative->Core.bmGstSimdRegShadows & RT_BIT_64(idxReg))
-    {
-        off = iemNativeSimdRegFlushPendingWrite(pReNative, off, IEMNATIVEGSTSIMDREG_SIMD(idxReg));
-        /* Flush the shadows as the register needs to be reloaded (there is no guarantee right now, that the referenced register doesn't change). */
-        uint8_t const idxHstSimdReg = pReNative->Core.aidxGstSimdRegShadows[idxReg];
-
-        iemNativeSimdRegClearGstSimdRegShadowing(pReNative, idxHstSimdReg, off);
-        iemNativeSimdRegFlushGuestShadows(pReNative, RT_BIT_64(IEMNATIVEGSTSIMDREG_SIMD(idxReg)));
-    }
-#endif
-    RT_NOREF(pReNative, enmClass, idxReg);
+# endif
+
+    if RT_CONSTEXPR_IF(a_enmClass == kIemNativeGstRegRef_Gpr)
+        if (pReNative->Core.bmGstRegShadowDirty & RT_BIT_64(idxReg))
+            off = iemNativeRegFlushPendingWrite(pReNative, off, IEMNATIVEGSTREG_GPR(idxReg));
+#endif
+
+    if RT_CONSTEXPR_IF(a_enmClass == kIemNativeGstRegRef_XReg)
+        if (pReNative->Core.bmGstSimdRegShadows & RT_BIT_64(idxReg))
+        {
+            off = iemNativeSimdRegFlushPendingWrite(pReNative, off, IEMNATIVEGSTSIMDREG_SIMD(idxReg));
+            /* Flush the shadows as the register needs to be reloaded (there is no
+               guarantee right now, that the referenced register doesn't change). */
+            uint8_t const idxHstSimdReg = pReNative->Core.aidxGstSimdRegShadows[idxReg];
+
+            iemNativeSimdRegClearGstSimdRegShadowing(pReNative, idxHstSimdReg, off);
+            iemNativeSimdRegFlushGuestShadows(pReNative, RT_BIT_64(IEMNATIVEGSTSIMDREG_SIMD(idxReg)));
+        }
+
     return off;
 }
@@ -2555,10 +2551,8 @@
 iemNativeEmitMaybeRaiseDeviceNotAvailable(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxInstr)
 {
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
     STAM_COUNTER_INC(&pReNative->pVCpu->iem.s.StatNativeMaybeDeviceNotAvailXcptCheckPotential);
 
     if (!(pReNative->fSimdRaiseXcptChecksEmitted & IEMNATIVE_SIMD_RAISE_XCPT_CHECKS_EMITTED_MAYBE_DEVICE_NOT_AVAILABLE))
     {
-#endif
         /*
          * Make sure we don't have any outstanding guest register writes as we may
@@ -2589,10 +2583,8 @@
         iemNativeRegFreeTmp(pReNative, idxCr0Reg);
 
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
         pReNative->fSimdRaiseXcptChecksEmitted |= IEMNATIVE_SIMD_RAISE_XCPT_CHECKS_EMITTED_MAYBE_DEVICE_NOT_AVAILABLE;
     }
     else
         STAM_COUNTER_INC(&pReNative->pVCpu->iem.s.StatNativeMaybeDeviceNotAvailXcptCheckOmitted);
-#endif
 
     return off;
@@ -2614,10 +2606,8 @@
 iemNativeEmitMaybeRaiseWaitDeviceNotAvailable(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxInstr)
 {
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
     STAM_COUNTER_INC(&pReNative->pVCpu->iem.s.StatNativeMaybeWaitDeviceNotAvailXcptCheckPotential);
 
     if (!(pReNative->fSimdRaiseXcptChecksEmitted & IEMNATIVE_SIMD_RAISE_XCPT_CHECKS_EMITTED_MAYBE_WAIT_DEVICE_NOT_AVAILABLE))
     {
-#endif
         /*
          * Make sure we don't have any outstanding guest register writes as we may
@@ -2648,10 +2638,8 @@
         iemNativeRegFreeTmp(pReNative, idxCr0Reg);
 
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
         pReNative->fSimdRaiseXcptChecksEmitted |= IEMNATIVE_SIMD_RAISE_XCPT_CHECKS_EMITTED_MAYBE_WAIT_DEVICE_NOT_AVAILABLE;
     }
     else
         STAM_COUNTER_INC(&pReNative->pVCpu->iem.s.StatNativeMaybeWaitDeviceNotAvailXcptCheckOmitted);
-#endif
 
     return off;
@@ -2718,10 +2706,8 @@
 iemNativeEmitMaybeRaiseSseRelatedXcpt(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxInstr)
 {
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
     STAM_COUNTER_INC(&pReNative->pVCpu->iem.s.StatNativeMaybeSseXcptCheckPotential);
 
     if (!(pReNative->fSimdRaiseXcptChecksEmitted & IEMNATIVE_SIMD_RAISE_XCPT_CHECKS_EMITTED_MAYBE_SSE))
     {
-#endif
         /*
          * Make sure we don't have any outstanding guest register writes as we may
@@ -2790,10 +2776,8 @@
         iemNativeRegFreeTmp(pReNative, idxCr4Reg);
 
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
         pReNative->fSimdRaiseXcptChecksEmitted |= IEMNATIVE_SIMD_RAISE_XCPT_CHECKS_EMITTED_MAYBE_SSE;
     }
     else
         STAM_COUNTER_INC(&pReNative->pVCpu->iem.s.StatNativeMaybeSseXcptCheckOmitted);
-#endif
 
     return off;
@@ -2815,10 +2799,8 @@
 iemNativeEmitMaybeRaiseAvxRelatedXcpt(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxInstr)
 {
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
     STAM_COUNTER_INC(&pReNative->pVCpu->iem.s.StatNativeMaybeAvxXcptCheckPotential);
 
     if (!(pReNative->fSimdRaiseXcptChecksEmitted & IEMNATIVE_SIMD_RAISE_XCPT_CHECKS_EMITTED_MAYBE_AVX))
     {
-#endif
         /*
          * Make sure we don't have any outstanding guest register writes as we may
@@ -2898,10 +2880,9 @@
         iemNativeRegFreeTmp(pReNative, idxCr4Reg);
         iemNativeRegFreeTmp(pReNative, idxXcr0Reg);
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
+
         pReNative->fSimdRaiseXcptChecksEmitted |= IEMNATIVE_SIMD_RAISE_XCPT_CHECKS_EMITTED_MAYBE_AVX;
     }
     else
         STAM_COUNTER_INC(&pReNative->pVCpu->iem.s.StatNativeMaybeAvxXcptCheckOmitted);
-#endif
 
     return off;
@@ -4122,8 +4103,7 @@
     IEMNATIVE_STRICT_EFLAGS_SKIPPING_EMIT_CHECK(pReNative, off, X86_EFL_STATUS_BITS);
 
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
     /* Clear the appropriate IEMNATIVE_SIMD_RAISE_XCPT_CHECKS_EMITTED_XXX flags
        when a calls clobber any of the relevant control registers. */
-# if 1
+#if 1
     if (!(fGstShwFlush & (RT_BIT_64(kIemNativeGstReg_Cr0) | RT_BIT_64(kIemNativeGstReg_Cr4) | RT_BIT_64(kIemNativeGstReg_Xcr0))))
     {
@@ -4142,5 +4122,5 @@
                                                     | IEMNATIVE_SIMD_RAISE_XCPT_CHECKS_EMITTED_MAYBE_DEVICE_NOT_AVAILABLE);
 
-# else
+#else
     if (pfnCImpl == (uintptr_t)iemCImpl_xsetbv) /* Modifies xcr0 which only the AVX check uses. */
         pReNative->fSimdRaiseXcptChecksEmitted &= ~IEMNATIVE_SIMD_RAISE_XCPT_CHECKS_EMITTED_MAYBE_AVX;
@@ -4154,11 +4134,10 @@
                                                     | IEMNATIVE_SIMD_RAISE_XCPT_CHECKS_EMITTED_MAYBE_SSE
                                                     | IEMNATIVE_SIMD_RAISE_XCPT_CHECKS_EMITTED_MAYBE_DEVICE_NOT_AVAILABLE);
-# endif
-
-# ifdef IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS
+#endif
+
+#ifdef IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS
     /* Mark the host floating point control register as not synced if MXCSR is modified. */
     if (fGstShwFlush & RT_BIT_64(kIemNativeGstReg_MxCsr))
         pReNative->fSimdRaiseXcptChecksEmitted &= ~IEMNATIVE_SIMD_HOST_FP_CTRL_REG_SYNCED;
-# endif
 #endif
 
@@ -4734,5 +4713,4 @@
 
 
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
 #define IEM_MC_FETCH_GREG_PAIR_U64(a_u128Dst, a_iGRegLo, a_iGRegHi) \
     off = iemNativeEmitFetchGregPairU64(pReNative, off, a_u128Dst, a_iGRegLo, a_iGRegHi)
@@ -4761,5 +4739,4 @@
     return off;
 }
-#endif
 
 
@@ -5197,5 +5174,4 @@
 
 
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
 #define IEM_MC_STORE_GREG_PAIR_U64(a_iGRegLo, a_iGRegHi, a_u128Value) \
     off = iemNativeEmitStoreGregPairU64(pReNative, off, a_iGRegLo, a_iGRegHi, a_u128Value)
@@ -5224,5 +5200,4 @@
     return off;
 }
-#endif
 
 
@@ -6185,5 +6160,5 @@
 
     /* If we've delayed writing back the register value, flush it now. */
-    off = iemNativeRegFlushPendingSpecificWrite(pReNative, off, kIemNativeGstRegRef_Gpr, iGRegEx & 15);
+    off = iemNativeRegFlushPendingSpecificWrite<kIemNativeGstRegRef_Gpr>(pReNative, off, iGRegEx & 15);
 
     /* If it's not a const reference we need to flush the shadow copy of the register now. */
@@ -6233,5 +6208,5 @@
 
     /* If we've delayed writing back the register value, flush it now. */
-    off = iemNativeRegFlushPendingSpecificWrite(pReNative, off, kIemNativeGstRegRef_Gpr, iGReg);
+    off = iemNativeRegFlushPendingSpecificWrite<kIemNativeGstRegRef_Gpr>(pReNative, off, iGReg);
 
     /* If it's not a const reference we need to flush the shadow copy of the register now. */
@@ -6281,5 +6256,5 @@
 
     /* If we've delayed writing back the register value, flush it now. */
-    off = iemNativeRegFlushPendingSpecificWrite(pReNative, off, kIemNativeGstRegRef_EFlags, 0);
+    off = iemNativeRegFlushPendingSpecificWrite<kIemNativeGstRegRef_EFlags>(pReNative, off, 0);
 
     /* If there is a shadow copy of guest EFLAGS, flush it now. */
@@ -6308,12 +6283,11 @@
     off = iemNativeEmitRefXregXxx(pReNative, off, a_pXmmDst, a_iXReg, true /*fConst*/)
 
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
 /* Just being paranoid here. */
-# ifndef _MSC_VER /* MSC can't compile this, doesn't like [0]. Added reduced version afterwards. */
+#ifndef _MSC_VER /* MSC can't compile this, doesn't like [0]. Added reduced version afterwards. */
 AssertCompile2MemberOffsets(CPUMCTX, XState.x87.aXMM[0], XState.x87.aXMM[0].au64[0]);
 AssertCompile2MemberOffsets(CPUMCTX, XState.x87.aXMM[0], XState.x87.aXMM[0].au32[0]);
 AssertCompile2MemberOffsets(CPUMCTX, XState.x87.aXMM[0], XState.x87.aXMM[0].ar64[0]);
 AssertCompile2MemberOffsets(CPUMCTX, XState.x87.aXMM[0], XState.x87.aXMM[0].ar32[0]);
-# endif
+#endif
 AssertCompileMemberOffset(X86XMMREG, au64, 0);
 AssertCompileMemberOffset(X86XMMREG, au32, 0);
@@ -6321,13 +6295,12 @@
 AssertCompileMemberOffset(X86XMMREG, ar32, 0);
 
-# define IEM_MC_REF_XREG_U32_CONST(a_pu32Dst, a_iXReg) \
+#define IEM_MC_REF_XREG_U32_CONST(a_pu32Dst, a_iXReg) \
     off = iemNativeEmitRefXregXxx(pReNative, off, a_pu32Dst, a_iXReg, true /*fConst*/)
-# define IEM_MC_REF_XREG_U64_CONST(a_pu64Dst, a_iXReg) \
+#define IEM_MC_REF_XREG_U64_CONST(a_pu64Dst, a_iXReg) \
     off = iemNativeEmitRefXregXxx(pReNative, off, a_pu64Dst, a_iXReg, true /*fConst*/)
-# define IEM_MC_REF_XREG_R32_CONST(a_pr32Dst, a_iXReg) \
+#define IEM_MC_REF_XREG_R32_CONST(a_pr32Dst, a_iXReg) \
     off = iemNativeEmitRefXregXxx(pReNative, off, a_pr32Dst, a_iXReg, true /*fConst*/)
-# define IEM_MC_REF_XREG_R64_CONST(a_pr64Dst, a_iXReg) \
+#define IEM_MC_REF_XREG_R64_CONST(a_pr64Dst, a_iXReg) \
     off = iemNativeEmitRefXregXxx(pReNative, off, a_pr64Dst, a_iXReg, true /*fConst*/)
-#endif
 
 /** Handles IEM_MC_REF_XREG_xxx[_CONST]. */
@@ -6340,13 +6313,9 @@
 
     /* If we've delayed writing back the register value, flush it now. */
-    off = iemNativeRegFlushPendingSpecificWrite(pReNative, off, kIemNativeGstRegRef_XReg, iXReg);
-
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
+    off = iemNativeRegFlushPendingSpecificWrite<kIemNativeGstRegRef_XReg>(pReNative, off, iXReg);
+
     /* If it's not a const reference we need to flush the shadow copy of the register now. */
     if (!fConst)
         iemNativeSimdRegFlushGuestShadows(pReNative, RT_BIT_64(IEMNATIVEGSTSIMDREG_SIMD(iXReg)));
-#else
-    RT_NOREF(fConst);
-#endif
 
     return off;
@@ -7178,10 +7147,6 @@
                IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_UNEXPECTED_KIND));
     Assert(!a_fFlat ? iSegReg < 6 : iSegReg == UINT8_MAX);
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
     AssertCompile(   a_cbMem == 1 || a_cbMem == 2 || a_cbMem == 4 || a_cbMem == 8
                   || a_cbMem == sizeof(RTUINT128U) || a_cbMem == sizeof(RTUINT256U));
-#else
-    AssertCompile(a_cbMem == 1 || a_cbMem == 2 || a_cbMem == 4 || a_cbMem == 8);
-#endif
     AssertCompile(!(a_fAlignMaskAndCtl & ~(UINT32_C(0xff) | IEM_MEMMAP_F_ALIGN_GP | IEM_MEMMAP_F_ALIGN_SSE)));
     AssertCompile(IEMNATIVE_CALL_ARG_GREG_COUNT >= 4);
@@ -7234,5 +7199,4 @@
                 Assert(a_fAlignMaskAndCtl <= 7);
                 break;
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
             case sizeof(RTUINT128U):
                 Assert(   (   a_enmOp == kIemNativeEmitMemOp_Fetch
@@ -7260,5 +7224,4 @@
                        : a_fAlignMaskAndCtl <= 31);
                 break;
-#endif
         }
     }
@@ -7308,5 +7271,4 @@
                 Assert(a_fAlignMaskAndCtl <= 7);
                 break;
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
             case sizeof(RTUINT128U):
                 Assert(   (   a_enmOp == kIemNativeEmitMemOp_Fetch
@@ -7334,5 +7296,4 @@
                        : a_fAlignMaskAndCtl <= 31);
                 break;
-#endif
         }
     }
@@ -7374,45 +7335,20 @@
      */
     uint16_t const uTlbSeqNo         = pReNative->uTlbSeqNo++;
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
-    uint8_t        idxRegValueFetch;
-    if RT_CONSTEXPR_IF(a_cbMem == sizeof(RTUINT128U) || a_cbMem == sizeof(RTUINT256U))
-        idxRegValueFetch = a_enmOp == kIemNativeEmitMemOp_Store ? UINT8_MAX
-                         : iemNativeVarSimdRegisterAcquire(pReNative, idxVarValue, &off);
-    else
-        idxRegValueFetch = a_enmOp == kIemNativeEmitMemOp_Store ? UINT8_MAX
-                         : !(pReNative->Core.bmHstRegs & RT_BIT_32(IEMNATIVE_CALL_RET_GREG))
-                         ? iemNativeVarRegisterSetAndAcquire(pReNative, idxVarValue, IEMNATIVE_CALL_RET_GREG, &off)
-                         : iemNativeVarRegisterAcquire(pReNative, idxVarValue, &off);
-#else
-    uint8_t  const idxRegValueFetch  = a_enmOp == kIemNativeEmitMemOp_Store ? UINT8_MAX
+    RT_CONSTEXPR
+    bool const     fSimdRegValues    = a_cbMem == sizeof(RTUINT128U) || a_cbMem == sizeof(RTUINT256U);
+    uint8_t const  idxRegValueFetch  = a_enmOp == kIemNativeEmitMemOp_Store ? UINT8_MAX
+                                     : fSimdRegValues
+                                     ? iemNativeVarSimdRegisterAcquire(pReNative, idxVarValue, &off)
                                      : !(pReNative->Core.bmHstRegs & RT_BIT_32(IEMNATIVE_CALL_RET_GREG))
                                      ? iemNativeVarRegisterSetAndAcquire(pReNative, idxVarValue, IEMNATIVE_CALL_RET_GREG, &off)
                                      : iemNativeVarRegisterAcquire(pReNative, idxVarValue, &off);
-#endif
     IEMNATIVEEMITTLBSTATE const TlbState(pReNative, &off, idxVarGCPtrMem, iSegReg, a_fFlat, a_cbMem, offDisp);
-
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
-    uint8_t  idxRegValueStore = UINT8_MAX;
-
-    if RT_CONSTEXPR_IF(a_cbMem == sizeof(RTUINT128U) || a_cbMem == sizeof(RTUINT256U))
-        idxRegValueStore =    a_enmOp == kIemNativeEmitMemOp_Store
-                           && !TlbState.fSkip
-                           && pVarValue->enmKind != kIemNativeVarKind_Immediate
-                         ? iemNativeVarSimdRegisterAcquire(pReNative, idxVarValue, &off, true /*fInitialized*/)
-                         : UINT8_MAX;
-    else
-        idxRegValueStore  =    a_enmOp == kIemNativeEmitMemOp_Store
-                            && !TlbState.fSkip
-                            && pVarValue->enmKind != kIemNativeVarKind_Immediate
-                          ? iemNativeVarRegisterAcquireInited(pReNative, idxVarValue, &off)
-                          : UINT8_MAX;
-
-#else
-    uint8_t  const idxRegValueStore  =    a_enmOp == kIemNativeEmitMemOp_Store
-                                       && !TlbState.fSkip
-                                       && pVarValue->enmKind != kIemNativeVarKind_Immediate
-                                     ? iemNativeVarRegisterAcquireInited(pReNative, idxVarValue, &off)
-                                     : UINT8_MAX;
-#endif
+    uint8_t const  idxRegValueStore =     a_enmOp != kIemNativeEmitMemOp_Store
+                                       || TlbState.fSkip
+                                       || pVarValue->enmKind == kIemNativeVarKind_Immediate
+                                     ? UINT8_MAX
+                                     : fSimdRegValues
+                                     ? iemNativeVarSimdRegisterAcquire(pReNative, idxVarValue, &off, true /*fInitialized*/)
+                                     : iemNativeVarRegisterAcquireInited(pReNative, idxVarValue, &off);
     uint32_t const idxRegMemResult   = !TlbState.fSkip ? iemNativeRegAllocTmp(pReNative, &off) : UINT8_MAX;
     uint32_t const idxLabelTlbLookup = !TlbState.fSkip
@@ -7468,14 +7404,17 @@
 #ifndef IEMNATIVE_WITH_FREE_AND_FLUSH_VOLATILE_REGS_AT_TLB_LOOKUP
     /* Save variables in volatile registers. */
-    uint32_t const fHstRegsNotToSave = TlbState.getRegsNotToSave()
-                                     | (idxRegMemResult  != UINT8_MAX ? RT_BIT_32(idxRegMemResult)  : 0)
-                                     | (idxRegValueFetch != UINT8_MAX ? RT_BIT_32(idxRegValueFetch) : 0);
-    off = iemNativeVarSaveVolatileRegsPreHlpCall(pReNative, off, fHstRegsNotToSave);
+    uint32_t const fHstGprsNotToSave = TlbState.getRegsNotToSave()
+                                     | (idxRegMemResult  < 32                    ? RT_BIT_32(idxRegMemResult)        : 0)
+#ifdef _MSC_VER /* Workaround for stupid compiler (2019). */
+                                     | (idxRegValueFetch < 32 && !fSimdRegValues ? RT_BIT_32(idxRegValueFetch & 0x1f) : 0);
+#else
+                                     | (idxRegValueFetch < 32 && !fSimdRegValues ? RT_BIT_32(idxRegValueFetch)        : 0);
+#endif
+    off = iemNativeVarSaveVolatileRegsPreHlpCall(pReNative, off, fHstGprsNotToSave);
 #endif
 
     /* IEMNATIVE_CALL_ARG2/3_GREG = uValue (idxVarValue) - if store */
     uint32_t fVolGregMask = IEMNATIVE_CALL_VOLATILE_GREG_MASK;
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
-    if RT_CONSTEXPR_IF(a_cbMem == sizeof(RTUINT128U) || a_cbMem == sizeof(RTUINT256U))
+    if RT_CONSTEXPR_IF(fSimdRegValues)
     {
         /*
@@ -7494,7 +7433,5 @@
         fVolGregMask &= ~RT_BIT_32(idxRegArgValue);
     }
-    else
-#endif
-    if RT_CONSTEXPR_IF(a_enmOp == kIemNativeEmitMemOp_Store)
+    else if RT_CONSTEXPR_IF(a_enmOp == kIemNativeEmitMemOp_Store)
     {
         uint8_t const idxRegArgValue = a_fFlat ? IEMNATIVE_CALL_ARG2_GREG : IEMNATIVE_CALL_ARG3_GREG;
@@ -7525,23 +7462,23 @@
 #ifdef IEMNATIVE_WITH_EFLAGS_POSTPONING
     /* Do delayed EFLAGS calculations. */
-    if RT_CONSTEXPR_IF(a_enmOp == kIemNativeEmitMemOp_Store || a_cbMem == sizeof(RTUINT128U) || a_cbMem == sizeof(RTUINT256U))
+    if RT_CONSTEXPR_IF(a_enmOp == kIemNativeEmitMemOp_Store || fSimdRegValues)
     {
         if RT_CONSTEXPR_IF(a_fFlat)
             off = iemNativeDoPostponedEFlagsAtTlbMiss<  RT_BIT_32(IEMNATIVE_CALL_ARG1_GREG)
                                                       | RT_BIT_32(IEMNATIVE_CALL_ARG2_GREG)>(pReNative, off, &TlbState,
-                                                                                             fHstRegsNotToSave);
+                                                                                             fHstGprsNotToSave);
         else
             off = iemNativeDoPostponedEFlagsAtTlbMiss<  RT_BIT_32(IEMNATIVE_CALL_ARG1_GREG)
                                                       | RT_BIT_32(IEMNATIVE_CALL_ARG2_GREG)
                                                       | RT_BIT_32(IEMNATIVE_CALL_ARG3_GREG)>(pReNative, off, &TlbState,
-                                                                                             fHstRegsNotToSave);
+                                                                                             fHstGprsNotToSave);
     }
     else if RT_CONSTEXPR_IF(a_fFlat)
         off = iemNativeDoPostponedEFlagsAtTlbMiss<  RT_BIT_32(IEMNATIVE_CALL_ARG1_GREG)>(pReNative, off, &TlbState,
-                                                                                         fHstRegsNotToSave);
+                                                                                         fHstGprsNotToSave);
     else
         off = iemNativeDoPostponedEFlagsAtTlbMiss<  RT_BIT_32(IEMNATIVE_CALL_ARG1_GREG)
                                                   | RT_BIT_32(IEMNATIVE_CALL_ARG2_GREG)>(pReNative, off, &TlbState,
-                                                                                         fHstRegsNotToSave);
+                                                                                         fHstGprsNotToSave);
 #endif
 
@@ -7557,6 +7494,5 @@
     if RT_CONSTEXPR_IF(a_enmOp != kIemNativeEmitMemOp_Store)
     {
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
-        if RT_CONSTEXPR_IF(a_cbMem == sizeof(RTUINT128U) || a_cbMem == sizeof(RTUINT256U))
+        if RT_CONSTEXPR_IF(fSimdRegValues)
         {
             Assert(a_enmOp == kIemNativeEmitMemOp_Fetch);
@@ -7566,5 +7502,4 @@
         }
         else
-#endif
         {
             Assert(idxRegValueFetch == pVarValue->idxReg);
@@ -7576,5 +7511,5 @@
 #ifndef IEMNATIVE_WITH_FREE_AND_FLUSH_VOLATILE_REGS_AT_TLB_LOOKUP
     /* Restore variables and guest shadow registers to volatile registers. */
-    off = iemNativeVarRestoreVolatileRegsPostHlpCall(pReNative, off, fHstRegsNotToSave);
+    off = iemNativeVarRestoreVolatileRegsPostHlpCall(pReNative, off, fHstGprsNotToSave);
     off = iemNativeRegRestoreGuestShadowsInVolatileRegs(pReNative, off, TlbState.getActiveRegsWithShadows());
 #endif
@@ -7644,5 +7579,4 @@
                             off = iemNativeEmitStoreGpr64ByGprEx(pCodeBuf, off, idxRegValueStore, idxRegMemResult);
                             break;
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
                         case sizeof(RTUINT128U):
                             off = iemNativeEmitStoreVecRegByGprU128Ex(pCodeBuf, off, idxRegValueStore, idxRegMemResult);
@@ -7651,5 +7585,4 @@
                             off = iemNativeEmitStoreVecRegByGprU256Ex(pCodeBuf, off, idxRegValueStore, idxRegMemResult);
                             break;
-#endif
                         default:
                             AssertFailed();
@@ -7700,5 +7633,4 @@
                         off = iemNativeEmitLoadGprByGprU64Ex(pCodeBuf, off, idxRegValueFetch, idxRegMemResult);
                         break;
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
                     case sizeof(RTUINT128U):
                         /*
@@ -7715,5 +7647,4 @@
                         off = iemNativeEmitLoadVecRegByGprU256Ex(pCodeBuf, off, idxRegValueFetch, idxRegMemResult);
                         break;
-#endif
                     default:
                         AssertFailed();
@@ -8000,5 +7931,5 @@
             pReNative, off, a_r64Dst, UINT8_MAX, a_GCPtrMem, (uintptr_t)iemNativeHlpMemFlatFetchDataU64, pCallEntry->idxInstr)
 
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
+
 /* 128-bit segmented: */
 #define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
@@ -8092,5 +8023,4 @@
             pReNative, off, a_uYmmDst, UINT8_MAX, a_GCPtrMem, (uintptr_t)iemNativeHlpMemFlatFetchDataU256NoAc, pCallEntry->idxInstr)
 
-#endif
 
 
@@ -8187,6 +8117,5 @@
 
 
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
-# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
+#define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
     off = iemNativeEmitMemFetchStoreDataCommon<sizeof(RTUINT128U), \
                                                (sizeof(RTUINT128U) - 1U) | IEM_MEMMAP_F_ALIGN_GP | IEM_MEMMAP_F_ALIGN_SSE, \
@@ -8194,13 +8123,13 @@
             pReNative, off, a_u128Value, a_iSeg, a_GCPtrMem, (uintptr_t)iemNativeHlpMemStoreDataU128AlignedSse, pCallEntry->idxInstr)
 
-# define IEM_MC_STORE_MEM_U128_NO_AC(a_iSeg, a_GCPtrMem, a_u128Value) \
+#define IEM_MC_STORE_MEM_U128_NO_AC(a_iSeg, a_GCPtrMem, a_u128Value) \
     off = iemNativeEmitMemFetchStoreDataCommon<sizeof(RTUINT128U), sizeof(RTUINT128U) - 1, kIemNativeEmitMemOp_Store>(\
             pReNative, off, a_u128Value, a_iSeg, a_GCPtrMem, (uintptr_t)iemNativeHlpMemStoreDataU128NoAc, pCallEntry->idxInstr)
 
-# define IEM_MC_STORE_MEM_U256_NO_AC(a_iSeg, a_GCPtrMem, a_u256Value) \
+#define IEM_MC_STORE_MEM_U256_NO_AC(a_iSeg, a_GCPtrMem, a_u256Value) \
     off = iemNativeEmitMemFetchStoreDataCommon<sizeof(RTUINT256U), sizeof(RTUINT256U) - 1, kIemNativeEmitMemOp_Store>(\
             pReNative, off, a_u256Value, a_iSeg, a_GCPtrMem, (uintptr_t)iemNativeHlpMemStoreDataU256NoAc, pCallEntry->idxInstr)
 
-# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
+#define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
     off = iemNativeEmitMemFetchStoreDataCommon<sizeof(RTUINT256U), \
                                                (sizeof(RTUINT256U) - 1U) | IEM_MEMMAP_F_ALIGN_GP, \
@@ -8209,5 +8138,5 @@
 
 
-# define IEM_MC_STORE_MEM_FLAT_U128_ALIGN_SSE(a_GCPtrMem, a_u128Value) \
+#define IEM_MC_STORE_MEM_FLAT_U128_ALIGN_SSE(a_GCPtrMem, a_u128Value) \
     off = iemNativeEmitMemFetchStoreDataCommon<sizeof(RTUINT128U), \
                                                (sizeof(RTUINT128U) - 1U) | IEM_MEMMAP_F_ALIGN_GP | IEM_MEMMAP_F_ALIGN_SSE, \
@@ -8216,18 +8145,17 @@
             pCallEntry->idxInstr)
 
-# define IEM_MC_STORE_MEM_FLAT_U128_NO_AC(a_GCPtrMem, a_u128Value) \
+#define IEM_MC_STORE_MEM_FLAT_U128_NO_AC(a_GCPtrMem, a_u128Value) \
     off = iemNativeEmitMemFetchStoreDataCommon<sizeof(RTUINT128U), sizeof(RTUINT128U) - 1, kIemNativeEmitMemOp_Store, true>(\
             pReNative, off, a_u128Value, UINT8_MAX, a_GCPtrMem, (uintptr_t)iemNativeHlpMemFlatStoreDataU128NoAc, pCallEntry->idxInstr)
 
-# define IEM_MC_STORE_MEM_FLAT_U256_NO_AC(a_GCPtrMem, a_u256Value) \
+#define IEM_MC_STORE_MEM_FLAT_U256_NO_AC(a_GCPtrMem, a_u256Value) \
     off = iemNativeEmitMemFetchStoreDataCommon<sizeof(RTUINT256U), sizeof(RTUINT256U) - 1, kIemNativeEmitMemOp_Store, true>(\
             pReNative, off, a_u256Value, UINT8_MAX, a_GCPtrMem, (uintptr_t)iemNativeHlpMemFlatStoreDataU256NoAc, pCallEntry->idxInstr)
 
-# define IEM_MC_STORE_MEM_FLAT_U256_ALIGN_AVX(a_GCPtrMem, a_u256Value) \
+#define IEM_MC_STORE_MEM_FLAT_U256_ALIGN_AVX(a_GCPtrMem, a_u256Value) \
     off = iemNativeEmitMemFetchStoreDataCommon<sizeof(RTUINT256U), \
                                                (sizeof(RTUINT256U) - 1U) | IEM_MEMMAP_F_ALIGN_GP, kIemNativeEmitMemOp_Store, \
                                                true>(\
             pReNative, off, a_u256Value, UINT8_MAX, a_GCPtrMem, (uintptr_t)iemNativeHlpMemFlatStoreDataU256AlignedAvx, pCallEntry->idxInstr)
-#endif
 
 
@@ -9808,7 +9736,4 @@
 
 
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
-
-
 /*********************************************************************************************************************************
 *   Emitters for SSE/AVX specific operations.                                                                                    *
@@ -11102,6 +11027,4 @@
 
 
-#endif /* IEMNATIVE_WITH_SIMD_REG_ALLOCATOR */
-
 
 /*********************************************************************************************************************************
Index: trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompiler.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompiler.cpp	(revision 106445)
+++ trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompiler.cpp	(revision 106453)
@@ -711,5 +711,4 @@
 
 
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
 /**
  * Used by TB code to load 128-bit data w/ segmentation.
@@ -775,5 +774,4 @@
 #endif
 }
-#endif
 
 
@@ -830,5 +828,4 @@
 
 
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
 /**
  * Used by TB code to store unsigned 128-bit data w/ segmentation.
@@ -881,6 +878,4 @@
 #endif
 }
-#endif
-
 
 
@@ -1127,5 +1122,4 @@
 
 
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
 /**
  * Used by TB code to load unsigned 128-bit data w/ flat address.
@@ -1191,5 +1185,4 @@
 #endif
 }
-#endif
 
 
@@ -1246,5 +1239,4 @@
 
 
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
 /**
  * Used by TB code to store unsigned 128-bit data w/ flat address.
@@ -1297,6 +1289,4 @@
 #endif
 }
-#endif
-
 
 
@@ -2087,7 +2077,5 @@
 # endif
 #endif
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
     pReNative->fSimdRaiseXcptChecksEmitted = 0;
-#endif
     pReNative->Core.bmHstRegs              = IEMNATIVE_REG_FIXED_MASK
 #if IEMNATIVE_HST_GREG_COUNT < 32
@@ -2175,9 +2163,8 @@
 #endif
 
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
     pReNative->Core.bmHstSimdRegs          = IEMNATIVE_SIMD_REG_FIXED_MASK
-# if IEMNATIVE_HST_SIMD_REG_COUNT < 32
+#if IEMNATIVE_HST_SIMD_REG_COUNT < 32
                                            | ~(RT_BIT(IEMNATIVE_HST_SIMD_REG_COUNT) - 1U)
-# endif
+#endif
                                            ;
     pReNative->Core.bmHstSimdRegsWithGstShadow   = 0;
@@ -2204,6 +2191,4 @@
 #ifdef IEMNATIVE_SIMD_REG_FIXED_TMP0
     pReNative->Core.aHstSimdRegs[IEMNATIVE_SIMD_REG_FIXED_TMP0].enmWhat = kIemNativeWhat_FixedTmp;
-#endif
-
 #endif
 
@@ -2688,12 +2673,11 @@
     pEntry->GuestRegShadowing.idxHstReg     = idxHstReg;
     pEntry->GuestRegShadowing.idxHstRegPrev = idxHstRegPrev;
-#ifdef IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
+# ifdef IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
     Assert(   idxHstReg != UINT8_MAX
            || !(pReNative->Core.bmGstRegShadowDirty & RT_BIT_64(enmGstReg)));
-#endif
-}
-
-
-# ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
+# endif
+}
+
+
 /**
  * Debug Info: Record info about guest register shadowing.
@@ -2710,5 +2694,4 @@
     pEntry->GuestSimdRegShadowing.idxHstSimdRegPrev = idxHstSimdRegPrev;
 }
-# endif
 
 
@@ -2726,5 +2709,4 @@
 # endif
 
-# if defined(IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK) || defined(IEMNATIVE_WITH_SIMD_REG_ALLOCATOR)
 
 /**
@@ -2788,5 +2770,4 @@
 }
 
-# endif /* defined(IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK) || defined(IEMNATIVE_WITH_SIMD_REG_ALLOCATOR) */
 
 # ifdef IEMNATIVE_WITH_EFLAGS_POSTPONING
@@ -3284,40 +3265,38 @@
         {
             uint32_t const idxVar = ASMBitFirstSetU32(fVars) - 1;
-            uint8_t const  idxReg = pReNative->Core.aVars[idxVar].idxReg;
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
-            if (pReNative->Core.aVars[idxVar].fSimdReg) /* Need to ignore SIMD variables here or we end up freeing random registers. */
-                continue;
-#endif
-
-            if (   idxReg < RT_ELEMENTS(pReNative->Core.aHstRegs)
-                && (RT_BIT_32(idxReg) & fRegMask)
-                && (  iLoop == 0
-                    ? pReNative->Core.aVars[idxVar].enmKind != kIemNativeVarKind_Stack
-                    : pReNative->Core.aVars[idxVar].enmKind == kIemNativeVarKind_Stack)
-                && !pReNative->Core.aVars[idxVar].fRegAcquired)
+            if (!pReNative->Core.aVars[idxVar].fSimdReg) /* (this is the GPR allocator) */
             {
-                Assert(pReNative->Core.bmHstRegs & RT_BIT_32(idxReg));
-                Assert(   (pReNative->Core.bmGstRegShadows & pReNative->Core.aHstRegs[idxReg].fGstRegShadows)
-                       == pReNative->Core.aHstRegs[idxReg].fGstRegShadows);
-                Assert(pReNative->Core.bmGstRegShadows < RT_BIT_64(kIemNativeGstReg_End));
-                Assert(   RT_BOOL(pReNative->Core.bmHstRegsWithGstShadow & RT_BIT_32(idxReg))
-                       == RT_BOOL(pReNative->Core.aHstRegs[idxReg].fGstRegShadows));
+                uint8_t const  idxReg = pReNative->Core.aVars[idxVar].idxReg;
+                if (   idxReg < RT_ELEMENTS(pReNative->Core.aHstRegs)
+                    && (RT_BIT_32(idxReg) & fRegMask)
+                    && (  iLoop == 0
+                        ? pReNative->Core.aVars[idxVar].enmKind != kIemNativeVarKind_Stack
+                        : pReNative->Core.aVars[idxVar].enmKind == kIemNativeVarKind_Stack)
+                    && !pReNative->Core.aVars[idxVar].fRegAcquired)
+                {
+                    Assert(pReNative->Core.bmHstRegs & RT_BIT_32(idxReg));
+                    Assert(   (pReNative->Core.bmGstRegShadows & pReNative->Core.aHstRegs[idxReg].fGstRegShadows)
+                           == pReNative->Core.aHstRegs[idxReg].fGstRegShadows);
+                    Assert(pReNative->Core.bmGstRegShadows < RT_BIT_64(kIemNativeGstReg_End));
+                    Assert(   RT_BOOL(pReNative->Core.bmHstRegsWithGstShadow & RT_BIT_32(idxReg))
+                           == RT_BOOL(pReNative->Core.aHstRegs[idxReg].fGstRegShadows));
 #ifdef IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
-                Assert(!(pReNative->Core.aHstRegs[idxReg].fGstRegShadows & pReNative->Core.bmGstRegShadowDirty));
-#endif
-
-                if (pReNative->Core.aVars[idxVar].enmKind == kIemNativeVarKind_Stack)
-                {
-                    uint8_t const idxStackSlot = iemNativeVarGetStackSlot(pReNative, IEMNATIVE_VAR_IDX_PACK(idxVar));
-                    *poff = iemNativeEmitStoreGprByBp(pReNative, *poff, iemNativeStackCalcBpDisp(idxStackSlot), idxReg);
+                    Assert(!(pReNative->Core.aHstRegs[idxReg].fGstRegShadows & pReNative->Core.bmGstRegShadowDirty));
+#endif
+
+                    if (pReNative->Core.aVars[idxVar].enmKind == kIemNativeVarKind_Stack)
+                    {
+                        uint8_t const idxStackSlot = iemNativeVarGetStackSlot(pReNative, IEMNATIVE_VAR_IDX_PACK(idxVar));
+                        *poff = iemNativeEmitStoreGprByBp(pReNative, *poff, iemNativeStackCalcBpDisp(idxStackSlot), idxReg);
+                    }
+
+                    pReNative->Core.aVars[idxVar].idxReg    = UINT8_MAX;
+                    pReNative->Core.bmHstRegs              &= ~RT_BIT_32(idxReg);
+
+                    pReNative->Core.bmHstRegsWithGstShadow &= ~RT_BIT_32(idxReg);
+                    pReNative->Core.bmGstRegShadows        &= ~pReNative->Core.aHstRegs[idxReg].fGstRegShadows;
+                    pReNative->Core.aHstRegs[idxReg].fGstRegShadows = 0;
+                    return idxReg;
                 }
-
-                pReNative->Core.aVars[idxVar].idxReg    = UINT8_MAX;
-                pReNative->Core.bmHstRegs              &= ~RT_BIT_32(idxReg);
-
-                pReNative->Core.bmHstRegsWithGstShadow &= ~RT_BIT_32(idxReg);
-                pReNative->Core.bmGstRegShadows        &= ~pReNative->Core.aHstRegs[idxReg].fGstRegShadows;
-                pReNative->Core.aHstRegs[idxReg].fGstRegShadows = 0;
-                return idxReg;
             }
             fVars &= ~RT_BIT_32(idxVar);
@@ -3345,7 +3324,5 @@
     IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVar);
     Assert(pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)].idxReg == idxRegOld);
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
     Assert(!pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)].fSimdReg);
-#endif
     RT_NOREF(pszCaller);
 
@@ -4201,7 +4178,5 @@
                                    IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_REG_IPE_5));
                         Assert(pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)].idxReg == idxReg);
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
                         Assert(!pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)].fSimdReg);
-#endif
 
                         if (pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)].enmKind != kIemNativeVarKind_Stack)
@@ -4325,7 +4300,5 @@
     IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVar);
     Assert(pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)].idxReg == idxHstReg);
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
     Assert(!pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)].fSimdReg);
-#endif
 
     pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)].idxReg = UINT8_MAX;
@@ -4358,19 +4331,18 @@
 
 
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
-# if defined(LOG_ENABLED) || defined(IEMNATIVE_WITH_TB_DEBUG_INFO)
+#if defined(LOG_ENABLED) || defined(IEMNATIVE_WITH_TB_DEBUG_INFO)
 /** Host CPU SIMD register names. */
 DECL_HIDDEN_CONST(const char * const) g_apszIemNativeHstSimdRegNames[] =
 {
-#  ifdef RT_ARCH_AMD64
+# ifdef RT_ARCH_AMD64
     "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15"
-#  elif RT_ARCH_ARM64
+# elif RT_ARCH_ARM64
     "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",  "v8",  "v9",  "v10", "v11", "v12", "v13", "v14", "v15",
     "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
-#  else
-#   error "port me"
-#  endif
+# else
+#  error "port me"
+# endif
 };
-# endif
+#endif
 
 
@@ -4691,5 +4663,4 @@
     return off;
 }
-#endif
 
 
@@ -4751,7 +4722,5 @@
                     PIEMNATIVEVAR const pVar   = &pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)];
                     Assert(pVar->idxReg == idxReg);
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
                     Assert(!pVar->fSimdReg);
-#endif
                     if (!(RT_BIT_32(IEMNATIVE_VAR_IDX_UNPACK(idxVar)) & fKeepVars))
                     {
@@ -4829,8 +4798,8 @@
     }
 
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
-    /* Now for the SIMD registers, no argument support for now. */
+    /*
+     * Now for the SIMD registers, no argument support for now.
+     */
     off = iemNativeSimdRegMoveAndFreeAndFlushAtCall(pReNative, off, 0 /*cArgs*/, fKeepVars);
-#endif
 
     return off;
@@ -5031,5 +5000,4 @@
 *   SIMD register allocator (largely code duplication of the GPR allocator for now but might diverge)                            *
 *********************************************************************************************************************************/
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
 
 /**
@@ -5295,35 +5263,35 @@
         {
             uint32_t const idxVar = ASMBitFirstSetU32(fVars) - 1;
-            uint8_t const  idxReg = pReNative->Core.aVars[idxVar].idxReg;
-            if (!pReNative->Core.aVars[idxVar].fSimdReg) /* Ignore non SIMD variables here. */
-                continue;
-
-            if (   idxReg < RT_ELEMENTS(pReNative->Core.aHstSimdRegs)
-                && (RT_BIT_32(idxReg) & fRegMask)
-                && (  iLoop == 0
-                    ? pReNative->Core.aVars[idxVar].enmKind != kIemNativeVarKind_Stack
-                    : pReNative->Core.aVars[idxVar].enmKind == kIemNativeVarKind_Stack)
-                && !pReNative->Core.aVars[idxVar].fRegAcquired)
+            if (pReNative->Core.aVars[idxVar].fSimdReg) /* (this is the SIMD allocator) */
             {
-                Assert(pReNative->Core.bmHstSimdRegs & RT_BIT_32(idxReg));
-                Assert(   (pReNative->Core.bmGstSimdRegShadows & pReNative->Core.aHstSimdRegs[idxReg].fGstRegShadows)
-                       == pReNative->Core.aHstSimdRegs[idxReg].fGstRegShadows);
-                Assert(pReNative->Core.bmGstSimdRegShadows < RT_BIT_64(kIemNativeGstSimdReg_End));
-                Assert(   RT_BOOL(pReNative->Core.bmHstSimdRegsWithGstShadow & RT_BIT_32(idxReg))
-                       == RT_BOOL(pReNative->Core.aHstSimdRegs[idxReg].fGstRegShadows));
-
-                if (pReNative->Core.aVars[idxVar].enmKind == kIemNativeVarKind_Stack)
+                uint8_t const idxReg = pReNative->Core.aVars[idxVar].idxReg;
+                if (   idxReg < RT_ELEMENTS(pReNative->Core.aHstSimdRegs)
+                    && (RT_BIT_32(idxReg) & fRegMask)
+                    && (  iLoop == 0
+                        ? pReNative->Core.aVars[idxVar].enmKind != kIemNativeVarKind_Stack
+                        : pReNative->Core.aVars[idxVar].enmKind == kIemNativeVarKind_Stack)
+                    && !pReNative->Core.aVars[idxVar].fRegAcquired)
                 {
-                    uint8_t const idxStackSlot = iemNativeVarGetStackSlot(pReNative, IEMNATIVE_VAR_IDX_PACK(idxVar));
-                    *poff = iemNativeEmitStoreGprByBp(pReNative, *poff, iemNativeStackCalcBpDisp(idxStackSlot), idxReg);
+                    Assert(pReNative->Core.bmHstSimdRegs & RT_BIT_32(idxReg));
+                    Assert(   (pReNative->Core.bmGstSimdRegShadows & pReNative->Core.aHstSimdRegs[idxReg].fGstRegShadows)
+                           == pReNative->Core.aHstSimdRegs[idxReg].fGstRegShadows);
+                    Assert(pReNative->Core.bmGstSimdRegShadows < RT_BIT_64(kIemNativeGstSimdReg_End));
+                    Assert(   RT_BOOL(pReNative->Core.bmHstSimdRegsWithGstShadow & RT_BIT_32(idxReg))
+                           == RT_BOOL(pReNative->Core.aHstSimdRegs[idxReg].fGstRegShadows));
+
+                    if (pReNative->Core.aVars[idxVar].enmKind == kIemNativeVarKind_Stack)
+                    {
+                        uint8_t const idxStackSlot = iemNativeVarGetStackSlot(pReNative, IEMNATIVE_VAR_IDX_PACK(idxVar));
+                        *poff = iemNativeEmitStoreGprByBp(pReNative, *poff, iemNativeStackCalcBpDisp(idxStackSlot), idxReg);
+                    }
+
+                    pReNative->Core.aVars[idxVar].idxReg        = UINT8_MAX;
+                    pReNative->Core.bmHstSimdRegs              &= ~RT_BIT_32(idxReg);
+
+                    pReNative->Core.bmHstSimdRegsWithGstShadow &= ~RT_BIT_32(idxReg);
+                    pReNative->Core.bmGstSimdRegShadows        &= ~pReNative->Core.aHstRegs[idxReg].fGstRegShadows;
+                    pReNative->Core.aHstSimdRegs[idxReg].fGstRegShadows = 0;
+                    return idxReg;
                 }
-
-                pReNative->Core.aVars[idxVar].idxReg        = UINT8_MAX;
-                pReNative->Core.bmHstSimdRegs              &= ~RT_BIT_32(idxReg);
-
-                pReNative->Core.bmHstSimdRegsWithGstShadow &= ~RT_BIT_32(idxReg);
-                pReNative->Core.bmGstSimdRegShadows        &= ~pReNative->Core.aHstRegs[idxReg].fGstRegShadows;
-                pReNative->Core.aHstSimdRegs[idxReg].fGstRegShadows = 0;
-                return idxReg;
             }
             fVars &= ~RT_BIT_32(idxVar);
@@ -5546,8 +5514,8 @@
         || pReNative->Core.aHstSimdRegs[idxHstSimdRegSrc].enmLoaded == kIemNativeGstSimdRegLdStSz_256)
     {
-# ifdef RT_ARCH_ARM64
+#ifdef RT_ARCH_ARM64
         /* ASSUMES that there are two adjacent 128-bit registers available for the 256-bit value. */
         Assert(!(idxHstSimdRegDst & 0x1)); Assert(!(idxHstSimdRegSrc & 0x1));
-# endif
+#endif
 
         if (idxHstSimdRegDst != idxHstSimdRegSrc)
@@ -5756,8 +5724,8 @@
             || enmIntendedUse == kIemNativeGstRegUse_ForUpdate)
         {
-# if defined(IEMNATIVE_WITH_TB_DEBUG_INFO) && defined(IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK)
+#if defined(IEMNATIVE_WITH_TB_DEBUG_INFO) && defined(IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK)
             iemNativeDbgInfoAddNativeOffset(pReNative, *poff);
             iemNativeDbgInfoAddGuestRegDirty(pReNative, true /*fSimdReg*/, enmGstSimdReg, idxSimdReg);
-# endif
+#endif
 
             if (enmLoadSz == kIemNativeGstSimdRegLdStSz_Low128)
@@ -5792,8 +5760,8 @@
         || enmIntendedUse == kIemNativeGstRegUse_ForUpdate)
     {
-# if defined(IEMNATIVE_WITH_TB_DEBUG_INFO) && defined(IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK)
+#if defined(IEMNATIVE_WITH_TB_DEBUG_INFO) && defined(IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK)
         iemNativeDbgInfoAddNativeOffset(pReNative, *poff);
         iemNativeDbgInfoAddGuestRegDirty(pReNative, true /*fSimdReg*/, enmGstSimdReg, idxRegNew);
-# endif
+#endif
 
         if (enmLoadSz == kIemNativeGstSimdRegLdStSz_Low128)
@@ -5880,5 +5848,4 @@
     }
 }
-#endif /* IEMNATIVE_WITH_SIMD_REG_ALLOCATOR */
 
 
@@ -5972,9 +5939,5 @@
 #endif
 
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
-    off = iemNativeSimdRegFlushDirtyGuest(pReNative, off, ~fGstSimdShwExcept);
-#endif
-
-    return off;
+    return iemNativeSimdRegFlushDirtyGuest(pReNative, off, ~fGstSimdShwExcept);
 }
 
@@ -6175,5 +6138,4 @@
 
 
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
 /**
  * Loads the guest shadow SIMD register @a enmGstSimdReg into host SIMD reg @a idxHstSimdReg.
@@ -6209,5 +6171,4 @@
     }
 }
-#endif /* IEMNATIVE_WITH_SIMD_REG_ALLOCATOR */
 
 #ifdef VBOX_STRICT
@@ -6403,10 +6364,10 @@
 }
 
-# ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
-#  ifdef RT_ARCH_AMD64
+# ifdef RT_ARCH_AMD64
 /**
  * Helper for AMD64 to emit code which checks the low 128-bits of the given SIMD register against the given vCPU offset.
  */
-DECL_FORCE_INLINE_THROW(uint32_t) iemNativeEmitGuestSimdRegValueCheckVCpuU128(uint8_t * const pbCodeBuf, uint32_t off, uint8_t idxSimdReg, uint32_t offVCpu)
+DECL_FORCE_INLINE_THROW(uint32_t)
+iemNativeEmitGuestSimdRegValueCheckVCpuU128(uint8_t * const pbCodeBuf, uint32_t off, uint8_t idxSimdReg, uint32_t offVCpu)
 {
     /* pcmpeqq vectmp0, [gstreg] (ASSUMES SSE4.1) */
@@ -6469,5 +6430,5 @@
     return off;
 }
-#  endif
+# endif /* RT_ARCH_AMD64 */
 
 
@@ -6494,5 +6455,5 @@
         return off;
 
-#  ifdef RT_ARCH_AMD64
+# ifdef RT_ARCH_AMD64
     if (enmLoadSz == kIemNativeGstSimdRegLdStSz_Low128 || enmLoadSz == kIemNativeGstSimdRegLdStSz_256)
     {
@@ -6525,5 +6486,6 @@
                                                           g_aGstSimdShadowInfo[enmGstSimdReg].offYmm);
     }
-#  elif defined(RT_ARCH_ARM64)
+
+# elif defined(RT_ARCH_ARM64)
     /* mov vectmp0, [gstreg] */
     off = iemNativeEmitLoadSimdRegWithGstShadowSimdReg(pReNative, off, IEMNATIVE_SIMD_REG_FIXED_TMP0, enmGstSimdReg, enmLoadSz);
@@ -6561,12 +6523,11 @@
     }
 
-#  else
-#   error "Port me!"
-#  endif
+# else
+#  error "Port me!"
+# endif
 
     IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
     return off;
 }
-# endif /* IEMNATIVE_WITH_SIMD_REG_ALLOCATOR */
 
 
@@ -6586,5 +6547,5 @@
     off = iemNativeEmitCmpGpr32WithImm(pReNative, off, idxRegTmp, fExec & IEMTB_F_KEY_MASK);
 
-#ifdef RT_ARCH_AMD64
+# ifdef RT_ARCH_AMD64
     uint8_t * const pbCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 3);
 
@@ -7152,7 +7113,5 @@
     pReNative->Core.aVars[idxVar].fRegAcquired   = false;
     pReNative->Core.aVars[idxVar].u.uValue       = 0;
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
     pReNative->Core.aVars[idxVar].fSimdReg       = false;
-#endif
     return idxVar;
 }
@@ -7580,9 +7539,6 @@
     }
     iemNativeRegMarkAllocated(pReNative, idxReg, kIemNativeWhat_Var, idxVar);
-    pVar->idxReg = idxReg;
-
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
+    pVar->idxReg   = idxReg;
     pVar->fSimdReg = false;
-#endif
 
     /*
@@ -7667,5 +7623,4 @@
 
 
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
 /**
  * Makes sure variable @a idxVar has a SIMD register assigned to it and that it stays
@@ -7683,4 +7638,6 @@
  * @param  idxRegPref   Preferred SIMD register number or UINT8_MAX.
  */
+/** @todo Create variants for the last two params like we've done for the
+ *        GPR variant? */
 DECL_HIDDEN_THROW(uint8_t) iemNativeVarSimdRegisterAcquire(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar, uint32_t *poff,
                                                            bool fInitialized /*= false*/, uint8_t idxRegPref /*= UINT8_MAX*/)
@@ -7692,4 +7649,5 @@
     Assert(!pVar->fRegAcquired);
 
+/** @todo inline this bit?   */
     uint8_t idxReg = pVar->idxReg;
     if (idxReg < RT_ELEMENTS(pReNative->Core.aHstSimdRegs))
@@ -7762,7 +7720,6 @@
     }
     iemNativeSimdRegMarkAllocated(pReNative, idxReg, kIemNativeWhat_Var, idxVar);
-
+    pVar->idxReg   = idxReg;
     pVar->fSimdReg = true;
-    pVar->idxReg = idxReg;
 
     /*
@@ -7789,5 +7746,4 @@
     return idxReg;
 }
-#endif
 
 
@@ -7929,10 +7885,10 @@
  * @param   pReNative           The recompiler state.
  * @param   off                 The code buffer position.
- * @param   fHstRegsNotToSave   Set of registers not to save & restore.
+ * @param   fHstGprNotToSave    Set of GPRs not to save & restore.
  */
 DECL_HIDDEN_THROW(uint32_t)
-iemNativeVarSaveVolatileRegsPreHlpCall(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t fHstRegsNotToSave)
-{
-    uint32_t fHstRegs = pReNative->Core.bmHstRegs & IEMNATIVE_CALL_VOLATILE_NOTMP_GREG_MASK & ~fHstRegsNotToSave;
+iemNativeVarSaveVolatileRegsPreHlpCall(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t fHstGprNotToSave)
+{
+    uint32_t fHstRegs = pReNative->Core.bmHstRegs & IEMNATIVE_CALL_VOLATILE_NOTMP_GREG_MASK & ~fHstGprNotToSave;
     if (fHstRegs)
     {
@@ -7991,5 +7947,4 @@
         } while (fHstRegs);
     }
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
 
     /*
@@ -8055,5 +8010,4 @@
         } while (fHstRegs);
     }
-#endif
     return off;
 }
@@ -8066,12 +8020,15 @@
  * @param   pReNative           The recompiler state.
  * @param   off                 The code buffer position.
- * @param   fHstRegsNotToSave   Set of registers not to save & restore.
+ * @param   fHstGprNotToSave   Set of registers not to save & restore.
  * @see     iemNativeVarSaveVolatileRegsPreHlpCall(),
  *          iemNativeRegRestoreGuestShadowsInVolatileRegs()
  */
 DECL_HIDDEN_THROW(uint32_t)
-iemNativeVarRestoreVolatileRegsPostHlpCall(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t fHstRegsNotToSave)
-{
-    uint32_t fHstRegs = pReNative->Core.bmHstRegs & IEMNATIVE_CALL_VOLATILE_NOTMP_GREG_MASK & ~fHstRegsNotToSave;
+iemNativeVarRestoreVolatileRegsPostHlpCall(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t fHstGprNotToSave)
+{
+    /*
+     * GPRs
+     */
+    uint32_t fHstRegs = pReNative->Core.bmHstRegs & IEMNATIVE_CALL_VOLATILE_NOTMP_GREG_MASK & ~fHstGprNotToSave;
     if (fHstRegs)
     {
@@ -8128,5 +8085,8 @@
         } while (fHstRegs);
     }
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
+
+    /*
+     * SIMD registers.
+     */
     fHstRegs = pReNative->Core.bmHstSimdRegs & (IEMNATIVE_CALL_VOLATILE_SIMD_REG_MASK & ~IEMNATIVE_SIMD_REG_FIXED_MASK);
     if (fHstRegs)
@@ -8181,5 +8141,4 @@
         } while (fHstRegs);
     }
-#endif
     return off;
 }
@@ -8227,20 +8186,20 @@
     /* Free the host register first if any assigned. */
     uint8_t const idxHstReg = pReNative->Core.aVars[idxVar].idxReg;
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
-    if (   idxHstReg != UINT8_MAX
-        && pReNative->Core.aVars[idxVar].fSimdReg)
-    {
-        Assert(idxHstReg < RT_ELEMENTS(pReNative->Core.aHstSimdRegs));
-        Assert(pReNative->Core.aHstSimdRegs[idxHstReg].idxVar == IEMNATIVE_VAR_IDX_PACK(idxVar));
-        pReNative->Core.aHstSimdRegs[idxHstReg].idxVar = UINT8_MAX;
-        pReNative->Core.bmHstSimdRegs &= ~RT_BIT_32(idxHstReg);
-    }
-    else
-#endif
-    if (idxHstReg < RT_ELEMENTS(pReNative->Core.aHstRegs))
-    {
-        Assert(pReNative->Core.aHstRegs[idxHstReg].idxVar == IEMNATIVE_VAR_IDX_PACK(idxVar));
-        pReNative->Core.aHstRegs[idxHstReg].idxVar = UINT8_MAX;
-        pReNative->Core.bmHstRegs &= ~RT_BIT_32(idxHstReg);
+    if (idxHstReg != UINT8_MAX)
+    {
+        if (!pReNative->Core.aVars[idxVar].fSimdReg)
+        {
+            Assert(idxHstReg < RT_ELEMENTS(pReNative->Core.aHstRegs));
+            Assert(pReNative->Core.aHstRegs[idxHstReg].idxVar == IEMNATIVE_VAR_IDX_PACK(idxVar));
+            pReNative->Core.aHstRegs[idxHstReg].idxVar = UINT8_MAX;
+            pReNative->Core.bmHstRegs &= ~RT_BIT_32(idxHstReg);
+        }
+        else
+        {
+            Assert(idxHstReg < RT_ELEMENTS(pReNative->Core.aHstSimdRegs));
+            Assert(pReNative->Core.aHstSimdRegs[idxHstReg].idxVar == IEMNATIVE_VAR_IDX_PACK(idxVar));
+            pReNative->Core.aHstSimdRegs[idxHstReg].idxVar = UINT8_MAX;
+            pReNative->Core.bmHstSimdRegs &= ~RT_BIT_32(idxHstReg);
+        }
     }
 
@@ -8446,44 +8405,48 @@
             {
                 uint8_t const idxRegOld = pReNative->Core.aVars[idxVar].idxReg;
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
-                if (   idxRegOld != UINT8_MAX
-                    && pReNative->Core.aVars[idxVar].fSimdReg)
+                if (idxRegOld != UINT8_MAX)
                 {
-                    Assert(idxRegOld < RT_ELEMENTS(pReNative->Core.aHstSimdRegs));
-                    Assert(pReNative->Core.aVars[idxVar].cbVar == sizeof(RTUINT128U) || pReNative->Core.aVars[idxVar].cbVar == sizeof(RTUINT256U));
-
-                    uint8_t const idxStackSlot = iemNativeVarGetStackSlot(pReNative, IEMNATIVE_VAR_IDX_PACK(idxVar));
-                    Log12(("iemNativeEmitCallCommon: spilling idxVar=%d/%#x/idxReg=%d (referred to by %d) onto the stack (slot %#x bp+%d, off=%#x)\n",
-                           idxVar, IEMNATIVE_VAR_IDX_PACK(idxVar), idxRegOld, pReNative->Core.aVars[idxVar].idxReferrerVar,
-                           idxStackSlot, iemNativeStackCalcBpDisp(idxStackSlot), off));
-                    if (pReNative->Core.aVars[idxVar].cbVar == sizeof(RTUINT128U))
-                        off = iemNativeEmitStoreVecRegByBpU128(pReNative, off, iemNativeStackCalcBpDisp(idxStackSlot), idxRegOld);
+                    if (!pReNative->Core.aVars[idxVar].fSimdReg)
+                    {
+                        Assert(idxRegOld < RT_ELEMENTS(pReNative->Core.aHstRegs));
+
+                        uint8_t const idxStackSlot = iemNativeVarGetStackSlot(pReNative, IEMNATIVE_VAR_IDX_PACK(idxVar));
+                        Log12(("iemNativeEmitCallCommon: spilling idxVar=%d/%#x/idxReg=%d (referred to by %d) onto the stack (slot %#x bp+%d, off=%#x)\n",
+                               idxVar, IEMNATIVE_VAR_IDX_PACK(idxVar), idxRegOld, pReNative->Core.aVars[idxVar].idxReferrerVar,
+                               idxStackSlot, iemNativeStackCalcBpDisp(idxStackSlot), off));
+                        off = iemNativeEmitStoreGprByBp(pReNative, off, iemNativeStackCalcBpDisp(idxStackSlot), idxRegOld);
+
+                        pReNative->Core.aVars[idxVar].idxReg    = UINT8_MAX;
+                        pReNative->Core.bmHstRegs              &= ~RT_BIT_32(idxRegOld);
+                        pReNative->Core.bmHstRegsWithGstShadow &= ~RT_BIT_32(idxRegOld);
+                        pReNative->Core.bmGstRegShadows        &= ~pReNative->Core.aHstRegs[idxRegOld].fGstRegShadows;
+                        pReNative->Core.aHstRegs[idxRegOld].fGstRegShadows = 0;
+                    }
                     else
-                        off = iemNativeEmitStoreVecRegByBpU256(pReNative, off, iemNativeStackCalcBpDisp(idxStackSlot), idxRegOld);
-
-                    Assert(!(   (pReNative->Core.bmGstSimdRegShadowDirtyLo128 | pReNative->Core.bmGstSimdRegShadowDirtyHi128)
-                              & pReNative->Core.aHstSimdRegs[idxRegOld].fGstRegShadows));
-
-                    pReNative->Core.aVars[idxVar].idxReg       = UINT8_MAX;
-                    pReNative->Core.bmHstSimdRegs              &= ~RT_BIT_32(idxRegOld);
-                    pReNative->Core.bmHstSimdRegsWithGstShadow &= ~RT_BIT_32(idxRegOld);
-                    pReNative->Core.bmGstSimdRegShadows        &= ~pReNative->Core.aHstSimdRegs[idxRegOld].fGstRegShadows;
-                    pReNative->Core.aHstSimdRegs[idxRegOld].fGstRegShadows = 0;
-                }
-                else
-#endif
-                if (idxRegOld < RT_ELEMENTS(pReNative->Core.aHstRegs))
-                {
-                    uint8_t const idxStackSlot = iemNativeVarGetStackSlot(pReNative, IEMNATIVE_VAR_IDX_PACK(idxVar));
-                    Log12(("iemNativeEmitCallCommon: spilling idxVar=%d/%#x/idxReg=%d (referred to by %d) onto the stack (slot %#x bp+%d, off=%#x)\n",
-                           idxVar, IEMNATIVE_VAR_IDX_PACK(idxVar), idxRegOld, pReNative->Core.aVars[idxVar].idxReferrerVar,
-                           idxStackSlot, iemNativeStackCalcBpDisp(idxStackSlot), off));
-                    off = iemNativeEmitStoreGprByBp(pReNative, off, iemNativeStackCalcBpDisp(idxStackSlot), idxRegOld);
-
-                    pReNative->Core.aVars[idxVar].idxReg    = UINT8_MAX;
-                    pReNative->Core.bmHstRegs              &= ~RT_BIT_32(idxRegOld);
-                    pReNative->Core.bmHstRegsWithGstShadow &= ~RT_BIT_32(idxRegOld);
-                    pReNative->Core.bmGstRegShadows        &= ~pReNative->Core.aHstRegs[idxRegOld].fGstRegShadows;
-                    pReNative->Core.aHstRegs[idxRegOld].fGstRegShadows = 0;
+                    {
+                        Assert(idxRegOld < RT_ELEMENTS(pReNative->Core.aHstSimdRegs));
+                        Assert(   pReNative->Core.aVars[idxVar].cbVar == sizeof(RTUINT128U)
+                               || pReNative->Core.aVars[idxVar].cbVar == sizeof(RTUINT256U));
+
+                        uint8_t const idxStackSlot = iemNativeVarGetStackSlot(pReNative, IEMNATIVE_VAR_IDX_PACK(idxVar));
+                        Log12(("iemNativeEmitCallCommon: spilling idxVar=%d/%#x/idxReg=%d (referred to by %d) onto the stack (slot %#x bp+%d, off=%#x)\n",
+                               idxVar, IEMNATIVE_VAR_IDX_PACK(idxVar), idxRegOld, pReNative->Core.aVars[idxVar].idxReferrerVar,
+                               idxStackSlot, iemNativeStackCalcBpDisp(idxStackSlot), off));
+                        if (pReNative->Core.aVars[idxVar].cbVar == sizeof(RTUINT128U))
+                            off = iemNativeEmitStoreVecRegByBpU128(pReNative, off,
+                                                                   iemNativeStackCalcBpDisp(idxStackSlot), idxRegOld);
+                        else
+                            off = iemNativeEmitStoreVecRegByBpU256(pReNative, off,
+                                                                   iemNativeStackCalcBpDisp(idxStackSlot), idxRegOld);
+
+                        Assert(!(   (pReNative->Core.bmGstSimdRegShadowDirtyLo128 | pReNative->Core.bmGstSimdRegShadowDirtyHi128)
+                                  & pReNative->Core.aHstSimdRegs[idxRegOld].fGstRegShadows));
+
+                        pReNative->Core.aVars[idxVar].idxReg       = UINT8_MAX;
+                        pReNative->Core.bmHstSimdRegs              &= ~RT_BIT_32(idxRegOld);
+                        pReNative->Core.bmHstSimdRegsWithGstShadow &= ~RT_BIT_32(idxRegOld);
+                        pReNative->Core.bmGstSimdRegShadows        &= ~pReNative->Core.aHstSimdRegs[idxRegOld].fGstRegShadows;
+                        pReNative->Core.aHstSimdRegs[idxRegOld].fGstRegShadows = 0;
+                    }
                 }
             }
@@ -8621,25 +8584,23 @@
                         int32_t const offBpDispOther = iemNativeStackCalcBpDisp(idxStackSlot);
                         uint8_t const idxRegOther    = pReNative->Core.aVars[idxOtherVar].idxReg;
-# ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
-                        bool    const fSimdReg       = pReNative->Core.aVars[idxOtherVar].fSimdReg;
-                        uint8_t const cbVar          = pReNative->Core.aVars[idxOtherVar].cbVar;
-                        if (   fSimdReg
-                            && idxRegOther != UINT8_MAX)
+                        if (idxRegOther != UINT8_MAX)
                         {
-                            Assert(idxRegOther < RT_ELEMENTS(pReNative->Core.aHstSimdRegs));
-                            if (cbVar == sizeof(RTUINT128U))
-                                off = iemNativeEmitStoreVecRegByBpU128(pReNative, off, offBpDispOther, idxRegOther);
+                            if (!pReNative->Core.aVars[idxOtherVar].fSimdReg)
+                            {
+                                Assert(idxRegOther < RT_ELEMENTS(pReNative->Core.aHstRegs));
+                                off = iemNativeEmitStoreGprByBp(pReNative, off, offBpDispOther, idxRegOther);
+                                iemNativeRegFreeVar(pReNative, idxRegOther, true); /** @todo const ref? */
+                                Assert(pReNative->Core.aVars[idxOtherVar].idxReg == UINT8_MAX);
+                            }
                             else
-                                off = iemNativeEmitStoreVecRegByBpU256(pReNative, off, offBpDispOther, idxRegOther);
-                            iemNativeSimdRegFreeVar(pReNative, idxRegOther, true); /** @todo const ref? */
-                            Assert(pReNative->Core.aVars[idxOtherVar].idxReg == UINT8_MAX);
-                        }
-                        else
-# endif
-                        if (idxRegOther < RT_ELEMENTS(pReNative->Core.aHstRegs))
-                        {
-                            off = iemNativeEmitStoreGprByBp(pReNative, off, offBpDispOther, idxRegOther);
-                            iemNativeRegFreeVar(pReNative, idxRegOther, true); /** @todo const ref? */
-                            Assert(pReNative->Core.aVars[idxOtherVar].idxReg == UINT8_MAX);
+                            {
+                                Assert(idxRegOther < RT_ELEMENTS(pReNative->Core.aHstSimdRegs));
+                                if (pReNative->Core.aVars[idxOtherVar].cbVar == sizeof(RTUINT128U))
+                                    off = iemNativeEmitStoreVecRegByBpU128(pReNative, off, offBpDispOther, idxRegOther);
+                                else
+                                    off = iemNativeEmitStoreVecRegByBpU256(pReNative, off, offBpDispOther, idxRegOther);
+                                iemNativeSimdRegFreeVar(pReNative, idxRegOther, true); /** @todo const ref? */
+                                Assert(pReNative->Core.aVars[idxOtherVar].idxReg == UINT8_MAX);
+                            }
                         }
                         Assert(   pReNative->Core.aVars[idxOtherVar].idxStackSlot != UINT8_MAX
@@ -8723,25 +8684,23 @@
                             int32_t const offBpDispOther = iemNativeStackCalcBpDisp(idxStackSlot);
                             uint8_t const idxRegOther    = pReNative->Core.aVars[idxOtherVar].idxReg;
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
-                            bool    const fSimdReg       = pReNative->Core.aVars[idxOtherVar].fSimdReg;
-                            uint8_t const cbVar          = pReNative->Core.aVars[idxOtherVar].cbVar;
-                            if (   fSimdReg
-                                && idxRegOther != UINT8_MAX)
+                            if (idxRegOther != UINT8_MAX)
                             {
-                                Assert(idxRegOther < RT_ELEMENTS(pReNative->Core.aHstSimdRegs));
-                                if (cbVar == sizeof(RTUINT128U))
-                                    off = iemNativeEmitStoreVecRegByBpU128(pReNative, off, offBpDispOther, idxRegOther);
+                                if (!pReNative->Core.aVars[idxOtherVar].fSimdReg)
+                                {
+                                    Assert(idxRegOther < RT_ELEMENTS(pReNative->Core.aHstRegs));
+                                    off = iemNativeEmitStoreGprByBp(pReNative, off, offBpDispOther, idxRegOther);
+                                    iemNativeRegFreeVar(pReNative, idxRegOther, true); /** @todo const ref? */
+                                    Assert(pReNative->Core.aVars[idxOtherVar].idxReg == UINT8_MAX);
+                                }
                                 else
-                                    off = iemNativeEmitStoreVecRegByBpU256(pReNative, off, offBpDispOther, idxRegOther);
-                                iemNativeSimdRegFreeVar(pReNative, idxRegOther, true); /** @todo const ref? */
-                                Assert(pReNative->Core.aVars[idxOtherVar].idxReg == UINT8_MAX);
-                            }
-                            else
-#endif
-                            if (idxRegOther < RT_ELEMENTS(pReNative->Core.aHstRegs))
-                            {
-                                off = iemNativeEmitStoreGprByBp(pReNative, off, offBpDispOther, idxRegOther);
-                                iemNativeRegFreeVar(pReNative, idxRegOther, true); /** @todo const ref? */
-                                Assert(pReNative->Core.aVars[idxOtherVar].idxReg == UINT8_MAX);
+                                {
+                                    Assert(idxRegOther < RT_ELEMENTS(pReNative->Core.aHstSimdRegs));
+                                    if (pReNative->Core.aVars[idxOtherVar].cbVar == sizeof(RTUINT128U))
+                                        off = iemNativeEmitStoreVecRegByBpU128(pReNative, off, offBpDispOther, idxRegOther);
+                                    else
+                                        off = iemNativeEmitStoreVecRegByBpU256(pReNative, off, offBpDispOther, idxRegOther);
+                                    iemNativeSimdRegFreeVar(pReNative, idxRegOther, true); /** @todo const ref? */
+                                    Assert(pReNative->Core.aVars[idxOtherVar].idxReg == UINT8_MAX);
+                                }
                             }
                             Assert(   pReNative->Core.aVars[idxOtherVar].idxStackSlot != UINT8_MAX
@@ -8985,5 +8944,4 @@
         ENTRY(cpum.GstCtx.aXcr[0]),
         ENTRY(cpum.GstCtx.aXcr[1]),
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
         ENTRY(cpum.GstCtx.XState.x87.MXCSR),
         ENTRY(cpum.GstCtx.XState.x87.aXMM[0]),
@@ -9019,5 +8977,4 @@
         ENTRY(cpum.GstCtx.XState.u.YmmHi.aYmmHi[14]),
         ENTRY(cpum.GstCtx.XState.u.YmmHi.aYmmHi[15])
-#endif
 #undef ENTRY
     };
@@ -9494,5 +9451,4 @@
                         }
 
-# ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
                         case kIemTbDbgEntryType_GuestSimdRegShadowing:
                         {
@@ -9511,5 +9467,4 @@
                             continue;
                         }
-# endif
 
                         case kIemTbDbgEntryType_Label:
Index: trunk/src/VBox/VMM/VMMAll/IEMAllThrdRecompiler.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMAll/IEMAllThrdRecompiler.cpp	(revision 106445)
+++ trunk/src/VBox/VMM/VMMAll/IEMAllThrdRecompiler.cpp	(revision 106453)
@@ -114,7 +114,4 @@
 #endif
 
-#if defined(IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS) && !defined(IEMNATIVE_WITH_SIMD_REG_ALLOCATOR)
-# error "IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS requires IEMNATIVE_WITH_SIMD_REG_ALLOCATOR"
-#endif
 
 
Index: trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllN8veEmit-x86.h
===================================================================
--- trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllN8veEmit-x86.h	(revision 106445)
+++ trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllN8veEmit-x86.h	(revision 106453)
@@ -2233,5 +2233,4 @@
 
 
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
 /*********************************************************************************************************************************
 *   SIMD emitters.                                                                                                               *
@@ -3218,5 +3217,4 @@
 IEMNATIVE_NATIVE_EMIT_FP_3OP_U128(subps, kArmv8VecInstrFpOp_Sub, kArmv8VecInstrFpSz_4x_Single, 0, 0x5c);
 
-#endif /* IEMNATIVE_WITH_SIMD_REG_ALLOCATOR */
 
 #endif /* !VMM_INCLUDED_SRC_VMMAll_target_x86_IEMAllN8veEmit_x86_h */
