VirtualBox

Changeset 106453 in vbox for trunk/src/VBox/VMM/include


Ignore:
Timestamp:
Oct 17, 2024 1:54:35 PM (7 months ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
165272
Message:

VMM/IEM: Eliminated the IEMNATIVE_WITH_SIMD_REG_ALLOCATOR define. Fixed bug in iemNativeEmitMemFetchStoreDataCommon where a SIMD register was masked in calls to iemNativeVarSaveVolatileRegsPreHlpCall and friends. Fixed theoretical loop-forever bugs in iemNativeSimdRegAllocFindFree & iemNativeRegAllocFindFree. bugref:10720

Location:
trunk/src/VBox/VMM/include
Files:
3 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/VMM/include/IEMInternal.h

    r106406 r106453  
    120120#endif
    121121
    122 /** Enables the SIMD register allocator @bugref{10614}.  */
    123 #if defined(DOXYGEN_RUNNING) || 1
    124 # define IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
    125 #endif
    126122/** Enables access to even callee saved registers. */
    127 //# define IEMNATIVE_WITH_SIMD_REG_ACCESS_ALL_REGISTERS
     123/*# define IEMNATIVE_WITH_SIMD_REG_ACCESS_ALL_REGISTERS*/
    128124
    129125#if defined(DOXYGEN_RUNNING) || 1
    … …  
    22772273    STAMCOUNTER             StatNativeEndIfOtherBranchDirty;
    22782274
    2279 //#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
    22802275    /** Native recompiler: Number of calls to iemNativeSimdRegAllocFindFree. */
    22812276    STAMCOUNTER             StatNativeSimdRegFindFree;
    … …  
    23102305    /** Native recompiler: Number of IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() checks omitted. */
    23112306    STAMCOUNTER             StatNativeMaybeAvxXcptCheckOmitted;
    2312 //#endif
    23132307
    23142308    /** Native recompiler: The TB finished executing completely without jumping to a an exit label.

  • trunk/src/VBox/VMM/include/IEMN8veRecompiler.h

    r106408 r106453  
    204204 * Mask GPRs with fixes assignments, either by us or dictated by the CPU/OS
    205205 * architecture. */
    206 #ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
    207206/** @def IEMNATIVE_SIMD_REG_FIXED_TMP0
    208207 * Mask SIMD registers with fixes assignments, either by us or dictated by the CPU/OS
    … …  
    210209/** @def IEMNATIVE_SIMD_REG_FIXED_TMP0
    211210 * Dedicated temporary SIMD register. */
    212 #endif
    213211#if defined(RT_ARCH_ARM64) || defined(DOXYGEN_RUNNING) /* arm64 goes first because of doxygen */
    214212# define IEMNATIVE_REG_FIXED_PVMCPU         ARMV8_A64_REG_X28
    … …  
    234232                                             | IEMNATIVE_REG_FIXED_MASK_ADD)
    235233
    236 # ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
    237234# define IEMNATIVE_SIMD_REG_FIXED_TMP0      ARMV8_A64_REG_Q30
    238 #  if defined(IEMNATIVE_WITH_SIMD_REG_ACCESS_ALL_REGISTERS)
    239 #   define IEMNATIVE_SIMD_REG_FIXED_MASK    RT_BIT_32(ARMV8_A64_REG_Q30)
    240 #  else
     235# if defined(IEMNATIVE_WITH_SIMD_REG_ACCESS_ALL_REGISTERS)
     236#  define IEMNATIVE_SIMD_REG_FIXED_MASK     RT_BIT_32(ARMV8_A64_REG_Q30)
     237# else
    241238/** @note
    242239 * ARM64 has 32 registers, but they are only 128-bit wide.  So, in order to
    … …  
    251248 * prologue/epilogue.
    252249 */
    253 #   define IEMNATIVE_SIMD_REG_FIXED_MASK    (  UINT32_C(0xff00) \
     250#  define IEMNATIVE_SIMD_REG_FIXED_MASK     (  UINT32_C(0xff00) \
    254251                                             | RT_BIT_32(ARMV8_A64_REG_Q31) \
    255252                                             | RT_BIT_32(ARMV8_A64_REG_Q30) \
    … …  
    269266                                             | RT_BIT_32(ARMV8_A64_REG_Q3) \
    270267                                             | RT_BIT_32(ARMV8_A64_REG_Q1))
    271 #  endif
    272268# endif
    273269
    … …  
    281277                                             | RT_BIT_32(X86_GREG_xBP) )
    282278
    283 # ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
    284 #  define IEMNATIVE_SIMD_REG_FIXED_TMP0     5 /* xmm5/ymm5 */
    285 #  ifndef IEMNATIVE_WITH_SIMD_REG_ACCESS_ALL_REGISTERS
    286 #   ifndef _MSC_VER
    287 #    define IEMNATIVE_WITH_SIMD_REG_ACCESS_ALL_REGISTERS
    288 #   endif
     279# define IEMNATIVE_SIMD_REG_FIXED_TMP0      5 /* xmm5/ymm5 */
     280# ifndef IEMNATIVE_WITH_SIMD_REG_ACCESS_ALL_REGISTERS
     281#  ifndef _MSC_VER
     282#   define IEMNATIVE_WITH_SIMD_REG_ACCESS_ALL_REGISTERS
    289283#  endif
    290 #  ifdef IEMNATIVE_WITH_SIMD_REG_ACCESS_ALL_REGISTERS
    291 #   define IEMNATIVE_SIMD_REG_FIXED_MASK    (RT_BIT_32(IEMNATIVE_SIMD_REG_FIXED_TMP0))
    292 #  else
     284# endif
     285# ifdef IEMNATIVE_WITH_SIMD_REG_ACCESS_ALL_REGISTERS
     286#  define IEMNATIVE_SIMD_REG_FIXED_MASK     (RT_BIT_32(IEMNATIVE_SIMD_REG_FIXED_TMP0))
     287# else
    293288/** @note On Windows/AMD64 xmm6 through xmm15 are marked as callee saved. */
    294 #   define IEMNATIVE_SIMD_REG_FIXED_MASK    (  UINT32_C(0xffc0) \
     289#  define IEMNATIVE_SIMD_REG_FIXED_MASK     (  UINT32_C(0xffc0) \
    295290                                             | RT_BIT_32(IEMNATIVE_SIMD_REG_FIXED_TMP0))
    296 #  endif
    297291# endif
    298292
    … …  
    338332                                             | RT_BIT_32(X86_GREG_x10) \
    339333                                             | RT_BIT_32(X86_GREG_x11) )
    340 #  ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
    341334/* xmm0 - xmm5 are marked as volatile. */
    342 #   define IEMNATIVE_CALL_VOLATILE_SIMD_REG_MASK (UINT32_C(0x3f))
    343 #  endif
     335#  define IEMNATIVE_CALL_VOLATILE_SIMD_REG_MASK (UINT32_C(0x3f))
    344336
    345337# else  /* !RT_OS_WINDOWS */
    … …  
    366358                                             | RT_BIT_32(X86_GREG_x10) \
    367359                                             | RT_BIT_32(X86_GREG_x11) )
    368 #  ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
    369360/* xmm0 - xmm15 are marked as volatile. */
    370 #   define IEMNATIVE_CALL_VOLATILE_SIMD_REG_MASK (UINT32_C(0xffff))
    371 #  endif
     361#  define IEMNATIVE_CALL_VOLATILE_SIMD_REG_MASK (UINT32_C(0xffff))
    372362# endif /* !RT_OS_WINDOWS */
    373363
    … …  
    409399                                             | RT_BIT_32(ARMV8_A64_REG_X16) \
    410400                                             | RT_BIT_32(ARMV8_A64_REG_X17) )
    411 # ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
    412401/* The low 64 bits of v8 - v15 marked as callee saved but the rest is volatile,
    413402 * so to simplify our life a bit we just mark everything as volatile. */
    414 #  define IEMNATIVE_CALL_VOLATILE_SIMD_REG_MASK (UINT32_C(0xffffffff))
    415 # endif
     403# define IEMNATIVE_CALL_VOLATILE_SIMD_REG_MASK UINT32_C(0xffffffff)
    416404
    417405#endif
    … …  
    453441 * Mask corresponding to IEMNATIVE_HST_GREG_COUNT that can be applied to
    454442 * inverted register masks and such to get down to a correct set of regs. */
    455 #ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
    456443/** @def IEMNATIVE_HST_SIMD_REG_COUNT
    457444 * Number of host SIMD registers we track. */
    … …  
    459446 * Mask corresponding to IEMNATIVE_HST_SIMD_REG_COUNT that can be applied to
    460447 * inverted register masks and such to get down to a correct set of regs. */
    461 #endif
    462448#ifdef RT_ARCH_AMD64
    463449# define IEMNATIVE_HST_GREG_COUNT           16
    464450# define IEMNATIVE_HST_GREG_MASK            UINT32_C(0xffff)
    465451
    466 # ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
    467 #  define IEMNATIVE_HST_SIMD_REG_COUNT      16
    468 #  define IEMNATIVE_HST_SIMD_REG_MASK       UINT32_C(0xffff)
    469 # endif
     452# define IEMNATIVE_HST_SIMD_REG_COUNT       16
     453# define IEMNATIVE_HST_SIMD_REG_MASK        UINT32_C(0xffff)
    470454
    471455#elif defined(RT_ARCH_ARM64)
    … …  
    473457# define IEMNATIVE_HST_GREG_MASK            UINT32_MAX
    474458
    475 # ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
    476 #  define IEMNATIVE_HST_SIMD_REG_COUNT      32
    477 #  define IEMNATIVE_HST_SIMD_REG_MASK       UINT32_MAX
    478 # endif
     459# define IEMNATIVE_HST_SIMD_REG_COUNT       32
     460# define IEMNATIVE_HST_SIMD_REG_MASK        UINT32_MAX
    479461
    480462#else
    … …  
    12481230    /** Info about a host register shadowing a guest register. */
    12491231    kIemTbDbgEntryType_GuestRegShadowing,
    1250 #ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
    12511232    /** Info about a host SIMD register shadowing a guest SIMD register. */
    12521233    kIemTbDbgEntryType_GuestSimdRegShadowing,
    1253 #endif
    12541234#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING
    12551235    /** Info about a delayed RIP update. */
    12561236    kIemTbDbgEntryType_DelayedPcUpdate,
    12571237#endif
    1258 #if defined(IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK) || defined(IEMNATIVE_WITH_SIMD_REG_ALLOCATOR)
    12591238    /** Info about a shadowed guest register becoming dirty. */
    12601239    kIemTbDbgEntryType_GuestRegDirty,
    12611240    /** Info about register writeback/flush oepration. */
    12621241    kIemTbDbgEntryType_GuestRegWriteback,
    1263 #endif
    12641242#ifdef IEMNATIVE_WITH_EFLAGS_POSTPONING
    12651243    /** Info about a delayed EFLAGS calculation. */
    … …  
    13381316    } GuestRegShadowing;
    13391317
    1340 #ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
    13411318    struct
    13421319    {
    … …  
    13511328        uint32_t    idxHstSimdRegPrev : 8;
    13521329    } GuestSimdRegShadowing;
    1353 #endif
    13541330
    13551331#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING
    … …  
    13651341#endif
    13661342
    1367 #if defined(IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK) || defined(IEMNATIVE_WITH_SIMD_REG_ALLOCATOR)
    13681343    struct
    13691344    {
    … …  
    13901365        uint32_t    fGstReg       : 25;
    13911366    } GuestRegWriteback;
    1392 #endif
    13931367
    13941368#ifdef IEMNATIVE_WITH_EFLAGS_POSTPONING
    … …  
    14801454/** @} */
    14811455
    1482 #ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
    14831456
    14841457/**
    … …  
    15171490} IEMNATIVEGSTSIMDREGLDSTSZ;
    15181491
    1519 #endif /* IEMNATIVE_WITH_SIMD_REG_ALLOCATOR */
    15201492
    15211493/**
    … …  
    16021574     * @todo not sure what this really is for...   */
    16031575    IEMNATIVEGSTREG     enmGstReg;
    1604 #ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
    16051576    /** Flag whether this variable is held in a SIMD register (only supported for 128-bit and 256-bit variables),
    16061577     * only valid when idxReg is not UINT8_MAX. */
    … …  
    16091580     *  variable is idle and the register can be grabbed. */
    16101581    bool                fRegAcquired : 1;
    1611 #else
    1612     /** Set if the registered is currently used exclusively, false if the
    1613      *  variable is idle and the register can be grabbed. */
    1614     bool                fRegAcquired;
    1615 #endif
    16161582
    16171583    union
    … …  
    17071673
    17081674
    1709 #ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
    17101675/**
    17111676 * Host SIMD register entry - this tracks a virtual 256-bit register split into two 128-bit
    … …  
    17361701    uint8_t                   abAlign[5];
    17371702} IEMNATIVEHSTSIMDREG;
    1738 #endif
    17391703
    17401704
    … …  
    17691733#endif
    17701734
    1771 #ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
    17721735    /** Allocation bitmap for aHstSimdRegs. */
    17731736    uint32_t                    bmHstSimdRegs;
    … …  
    17821745    /** Bitmap marking whether the high 128-bit of the shadowed guest register are dirty and need writeback. */
    17831746    uint64_t                    bmGstSimdRegShadowDirtyHi128;
    1784 #endif
    17851747
    17861748    union
    … …  
    18021764     * there are no duplicate copies or ambiguities like that). */
    18031765    uint8_t                     aidxGstRegShadows[kIemNativeGstReg_End];
    1804 #ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
    18051766    /** Maps a guest SIMD register to a host SIMD register (index by IEMNATIVEGSTSIMDREG).
    18061767     * Entries are only valid if the corresponding bit in bmGstSimdRegShadows is set.
    … …  
    18081769     * there are no duplicate copies or ambiguities like that). */
    18091770    uint8_t                     aidxGstSimdRegShadows[kIemNativeGstSimdReg_End];
    1810 #endif
    18111771
    18121772    /** Host register allocation tracking. */
    18131773    IEMNATIVEHSTREG             aHstRegs[IEMNATIVE_HST_GREG_COUNT];
    1814 #ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
    18151774    /** Host SIMD register allocation tracking. */
    18161775    IEMNATIVEHSTSIMDREG         aHstSimdRegs[IEMNATIVE_HST_SIMD_REG_COUNT];
    1817 #endif
    18181776
    18191777    /** Variables and arguments. */
    … …  
    18451803
    18461804
    1847 #ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
    18481805/** Clear the dirty state of the given guest SIMD register. */
    1849 # define IEMNATIVE_SIMD_REG_STATE_CLR_DIRTY(a_pReNative, a_iSimdReg) \
     1806#define IEMNATIVE_SIMD_REG_STATE_CLR_DIRTY(a_pReNative, a_iSimdReg) \
    18501807    do { \
    18511808        (a_pReNative)->Core.bmGstSimdRegShadowDirtyLo128 &= ~RT_BIT_64(a_iSimdReg); \
    … …  
    18541811
    18551812/** Returns whether the low 128-bits of the given guest SIMD register are dirty. */
    1856 # define IEMNATIVE_SIMD_REG_STATE_IS_DIRTY_LO_U128(a_pReNative, a_iSimdReg) \
     1813#define IEMNATIVE_SIMD_REG_STATE_IS_DIRTY_LO_U128(a_pReNative, a_iSimdReg) \
    18571814    RT_BOOL((a_pReNative)->Core.bmGstSimdRegShadowDirtyLo128 & RT_BIT_64(a_iSimdReg))
    18581815/** Returns whether the high 128-bits of the given guest SIMD register are dirty. */
    1859 # define IEMNATIVE_SIMD_REG_STATE_IS_DIRTY_HI_U128(a_pReNative, a_iSimdReg) \
     1816#define IEMNATIVE_SIMD_REG_STATE_IS_DIRTY_HI_U128(a_pReNative, a_iSimdReg) \
    18601817    RT_BOOL((a_pReNative)->Core.bmGstSimdRegShadowDirtyHi128 & RT_BIT_64(a_iSimdReg))
    18611818/** Returns whether the given guest SIMD register is dirty. */
    1862 # define IEMNATIVE_SIMD_REG_STATE_IS_DIRTY_U256(a_pReNative, a_iSimdReg) \
     1819#define IEMNATIVE_SIMD_REG_STATE_IS_DIRTY_U256(a_pReNative, a_iSimdReg) \
    18631820    RT_BOOL(((a_pReNative)->Core.bmGstSimdRegShadowDirtyLo128 | (a_pReNative)->Core.bmGstSimdRegShadowDirtyHi128) & RT_BIT_64(a_iSimdReg))
    18641821
    18651822/** Set the low 128-bits of the given guest SIMD register to the dirty state. */
    1866 # define IEMNATIVE_SIMD_REG_STATE_SET_DIRTY_LO_U128(a_pReNative, a_iSimdReg) \
     1823#define IEMNATIVE_SIMD_REG_STATE_SET_DIRTY_LO_U128(a_pReNative, a_iSimdReg) \
    18671824    ((a_pReNative)->Core.bmGstSimdRegShadowDirtyLo128 |= RT_BIT_64(a_iSimdReg))
    18681825/** Set the high 128-bits of the given guest SIMD register to the dirty state. */
    1869 # define IEMNATIVE_SIMD_REG_STATE_SET_DIRTY_HI_U128(a_pReNative, a_iSimdReg) \
     1826#define IEMNATIVE_SIMD_REG_STATE_SET_DIRTY_HI_U128(a_pReNative, a_iSimdReg) \
    18701827    ((a_pReNative)->Core.bmGstSimdRegShadowDirtyHi128 |= RT_BIT_64(a_iSimdReg))
    18711828
    18721829/** Flag for indicating that IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() has emitted code in the current TB. */
    1873 # define IEMNATIVE_SIMD_RAISE_XCPT_CHECKS_EMITTED_MAYBE_DEVICE_NOT_AVAILABLE        RT_BIT_32(0)
     1830#define IEMNATIVE_SIMD_RAISE_XCPT_CHECKS_EMITTED_MAYBE_DEVICE_NOT_AVAILABLE         RT_BIT_32(0)
    18741831    /** Flag for indicating that IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() has emitted code in the current TB. */
    1875 # define IEMNATIVE_SIMD_RAISE_XCPT_CHECKS_EMITTED_MAYBE_WAIT_DEVICE_NOT_AVAILABLE   RT_BIT_32(1)
     1832#define IEMNATIVE_SIMD_RAISE_XCPT_CHECKS_EMITTED_MAYBE_WAIT_DEVICE_NOT_AVAILABLE    RT_BIT_32(1)
    18761833/** Flag for indicating that IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() has emitted code in the current TB. */
    1877 # define IEMNATIVE_SIMD_RAISE_XCPT_CHECKS_EMITTED_MAYBE_SSE                         RT_BIT_32(2)
     1834#define IEMNATIVE_SIMD_RAISE_XCPT_CHECKS_EMITTED_MAYBE_SSE                          RT_BIT_32(2)
    18781835/** Flag for indicating that IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() has emitted code in the current TB. */
    1879 # define IEMNATIVE_SIMD_RAISE_XCPT_CHECKS_EMITTED_MAYBE_AVX                         RT_BIT_32(3)
     1836#define IEMNATIVE_SIMD_RAISE_XCPT_CHECKS_EMITTED_MAYBE_AVX                          RT_BIT_32(3)
    18801837# ifdef IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS
    18811838/** Flag indicating that the guest MXCSR was synced to the host floating point control register. */
    1882 #  define IEMNATIVE_SIMD_HOST_FP_CTRL_REG_SYNCED                                    RT_BIT_32(4)
     1839# define IEMNATIVE_SIMD_HOST_FP_CTRL_REG_SYNCED                                     RT_BIT_32(4)
    18831840/** Flag indicating whether the host floating point control register was saved before overwriting it. */
    1884 #  define IEMNATIVE_SIMD_HOST_FP_CTRL_REG_SAVED                                     RT_BIT_32(5)
    1885 # endif
     1841# define IEMNATIVE_SIMD_HOST_FP_CTRL_REG_SAVED                                      RT_BIT_32(5)
    18861842#endif
    18871843
    … …  
    20201976    /** The expected IEMCPU::fExec value for the current call/instruction. */
    20211977    uint32_t                    fExec;
    2022 #ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
    20231978    /** IEMNATIVE_SIMD_RAISE_XCPT_CHECKS_EMITTED_XXX flags for exception flags
    20241979     * we only emit once per TB (or when the cr0/cr4/xcr0 register changes).
    … …  
    20291984     */
    20301985    uint32_t                    fSimdRaiseXcptChecksEmitted;
    2031 #endif
    20321986    /** The call number of the last CheckIrq, UINT32_MAX if not seen. */
    20331987    uint32_t                    idxLastCheckIrqCallNo;
    … …  
    21952149DECL_HIDDEN_THROW(void)     iemNativeDbgInfoAddGuestRegShadowing(PIEMRECOMPILERSTATE pReNative, IEMNATIVEGSTREG enmGstReg,
    21962150                                                                 uint8_t idxHstReg = UINT8_MAX, uint8_t idxHstRegPrev = UINT8_MAX);
    2197 # ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
    21982151DECL_HIDDEN_THROW(void)     iemNativeDbgInfoAddGuestSimdRegShadowing(PIEMRECOMPILERSTATE pReNative,
    21992152                                                                     IEMNATIVEGSTSIMDREG enmGstSimdReg,
    22002153                                                                     uint8_t idxHstSimdReg = UINT8_MAX,
    22012154                                                                     uint8_t idxHstSimdRegPrev = UINT8_MAX);
    2202 # endif
    2203 # if defined(IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK) || defined(IEMNATIVE_WITH_SIMD_REG_ALLOCATOR)
    22042155DECL_HIDDEN_THROW(void)     iemNativeDbgInfoAddGuestRegDirty(PIEMRECOMPILERSTATE pReNative, bool fSimdReg,
    22052156                                                             uint8_t idxGstReg, uint8_t idxHstReg);
    22062157DECL_HIDDEN_THROW(void)     iemNativeDbgInfoAddGuestRegWriteback(PIEMRECOMPILERSTATE pReNative, bool fSimdReg,
    22072158                                                                 uint64_t fGstReg);
    2208 # endif
    22092159DECL_HIDDEN_THROW(void)     iemNativeDbgInfoAddDelayedPcUpdate(PIEMRECOMPILERSTATE pReNative,
    22102160                                                               uint64_t offPc, uint32_t cInstrSkipped);
    … …  
    22692219DECL_HIDDEN_THROW(uint32_t) iemNativeRegMoveOrSpillStackVar(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxVar,
    22702220                                                            uint32_t fForbiddenRegs = IEMNATIVE_CALL_VOLATILE_GREG_MASK);
    2271 # ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
    22722221DECL_HIDDEN_THROW(uint32_t) iemNativeSimdRegMoveOrSpillStackVar(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxVar,
    22732222                                                                uint32_t fForbiddenRegs = IEMNATIVE_CALL_VOLATILE_SIMD_REG_MASK);
    2274 # endif
    22752223#endif
    22762224DECLHIDDEN(void)            iemNativeRegFree(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg) RT_NOEXCEPT;
    … …  
    22782226DECLHIDDEN(void)            iemNativeRegFreeTmpImm(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg) RT_NOEXCEPT;
    22792227DECLHIDDEN(void)            iemNativeRegFreeVar(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg, bool fFlushShadows) RT_NOEXCEPT;
    2280 #ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
    22812228DECLHIDDEN(void)            iemNativeSimdRegFreeVar(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstSimdReg, bool fFlushShadows) RT_NOEXCEPT;
    2282 # ifdef IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
     2229#ifdef IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
    22832230DECL_HIDDEN_THROW(uint32_t) iemNativeSimdRegFlushDirtyGuestByHostSimdRegShadow(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxHstReg);
    2284 # endif
    22852231#endif
    22862232DECLHIDDEN(void)            iemNativeRegFreeAndFlushMask(PIEMRECOMPILERSTATE pReNative, uint32_t fHstRegMask) RT_NOEXCEPT;
    … …  
    23142260
    23152261
    2316 #ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
    23172262DECL_HIDDEN_THROW(uint8_t)  iemNativeSimdRegAllocTmp(PIEMRECOMPILERSTATE pReNative, uint32_t *poff, bool fPreferVolatile = true);
    23182263DECL_HIDDEN_THROW(uint8_t)  iemNativeSimdRegAllocTmpEx(PIEMRECOMPILERSTATE pReNative, uint32_t *poff, uint32_t fRegMask,
    … …  
    23302275                                                                         uint8_t idxHstSimdReg, IEMNATIVEGSTSIMDREG enmGstSimdReg,
    23312276                                                                         IEMNATIVEGSTSIMDREGLDSTSZ enmLoadSz);
    2332 #endif
    23332277
    23342278DECL_HIDDEN_THROW(uint8_t)  iemNativeArgAlloc(PIEMRECOMPILERSTATE pReNative, uint8_t iArgNo, uint8_t cbType);
    … …  
    23492293DECL_HIDDEN_THROW(uint8_t)  iemNativeVarRegisterAcquireInitedWithPrefSlow(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar,
    23502294                                                                          uint32_t *poff, uint8_t idxRegPref);
    2351 #ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
    23522295DECL_HIDDEN_THROW(uint8_t)  iemNativeVarSimdRegisterAcquire(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar, uint32_t *poff,
    23532296                                                            bool fInitialized = false, uint8_t idxRegPref = UINT8_MAX);
    2354 #endif
    23552297DECL_HIDDEN_THROW(uint8_t)  iemNativeVarRegisterAcquireForGuestReg(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar,
    23562298                                                                   IEMNATIVEGSTREG enmGstReg, uint32_t *poff);
    23572299DECL_HIDDEN_THROW(uint32_t) iemNativeVarSaveVolatileRegsPreHlpCall(PIEMRECOMPILERSTATE pReNative, uint32_t off,
    2358                                                                    uint32_t fHstRegsNotToSave);
     2300                                                                   uint32_t fHstGprNotToSave);
    23592301DECL_HIDDEN_THROW(uint32_t) iemNativeVarRestoreVolatileRegsPostHlpCall(PIEMRECOMPILERSTATE pReNative, uint32_t off,
    2360                                                                        uint32_t fHstRegsNotToSave);
     2302                                                                       uint32_t fHstGprNotToSave);
    23612303DECLHIDDEN(void)            iemNativeVarFreeOneWorker(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar);
    23622304DECLHIDDEN(void)            iemNativeVarFreeAllSlow(PIEMRECOMPILERSTATE pReNative, uint32_t bmVars);
    … …  
    23722314DECL_HIDDEN_THROW(uint32_t) iemNativeEmitGuestRegValueCheckEx(PIEMRECOMPILERSTATE pReNative, PIEMNATIVEINSTR pCodeBuf,
    23732315                                                              uint32_t off, uint8_t idxReg, IEMNATIVEGSTREG enmGstReg);
    2374 # ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
    23752316DECL_HIDDEN_THROW(uint32_t) iemNativeEmitGuestSimdRegValueCheck(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxSimdReg,
    23762317                                                                IEMNATIVEGSTSIMDREG enmGstSimdReg,
    23772318                                                                IEMNATIVEGSTSIMDREGLDSTSZ enmLoadSz);
    2378 # endif
    23792319DECL_HIDDEN_THROW(uint32_t) iemNativeEmitExecFlagsCheck(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t fExec);
    23802320#endif
    … …  
    24182358IEM_DECL_NATIVE_HLP_PROTO(uint64_t, iemNativeHlpMemFetchDataU32_Sx_U64,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg));
    24192359IEM_DECL_NATIVE_HLP_PROTO(uint64_t, iemNativeHlpMemFetchDataU64,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg));
    2420 #ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
    24212360IEM_DECL_NATIVE_HLP_PROTO(void,     iemNativeHlpMemFetchDataU128,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg, PRTUINT128U pu128Dst));
    24222361IEM_DECL_NATIVE_HLP_PROTO(void,     iemNativeHlpMemFetchDataU128AlignedSse,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg, PRTUINT128U pu128Dst));
    … …  
    24242363IEM_DECL_NATIVE_HLP_PROTO(void,     iemNativeHlpMemFetchDataU256NoAc,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg, PRTUINT256U pu256Dst));
    24252364IEM_DECL_NATIVE_HLP_PROTO(void,     iemNativeHlpMemFetchDataU256AlignedAvx,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg, PRTUINT256U pu256Dst));
    2426 #endif
    24272365IEM_DECL_NATIVE_HLP_PROTO(void,     iemNativeHlpMemStoreDataU8,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg, uint8_t u8Value));
    24282366IEM_DECL_NATIVE_HLP_PROTO(void,     iemNativeHlpMemStoreDataU16,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg, uint16_t u16Value));
    24292367IEM_DECL_NATIVE_HLP_PROTO(void,     iemNativeHlpMemStoreDataU32,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg, uint32_t u32Value));
    24302368IEM_DECL_NATIVE_HLP_PROTO(void,     iemNativeHlpMemStoreDataU64,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg, uint64_t u64Value));
    2431 #ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
    24322369IEM_DECL_NATIVE_HLP_PROTO(void,     iemNativeHlpMemStoreDataU128AlignedSse,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg, PCRTUINT128U pu128Src));
    24332370IEM_DECL_NATIVE_HLP_PROTO(void,     iemNativeHlpMemStoreDataU128NoAc,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg, PCRTUINT128U pu128Src));
    24342371IEM_DECL_NATIVE_HLP_PROTO(void,     iemNativeHlpMemStoreDataU256NoAc,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg, PCRTUINT256U pu256Src));
    24352372IEM_DECL_NATIVE_HLP_PROTO(void,     iemNativeHlpMemStoreDataU256AlignedAvx,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg, PCRTUINT256U pu256Src));
    2436 #endif
    24372373IEM_DECL_NATIVE_HLP_PROTO(void,     iemNativeHlpStackStoreU16,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint16_t u16Value));
    24382374IEM_DECL_NATIVE_HLP_PROTO(void,     iemNativeHlpStackStoreU32,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t u32Value));
    … …  
    24532389IEM_DECL_NATIVE_HLP_PROTO(uint64_t, iemNativeHlpMemFlatFetchDataU32_Sx_U64,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem));
    24542390IEM_DECL_NATIVE_HLP_PROTO(uint64_t, iemNativeHlpMemFlatFetchDataU64,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem));
    2455 #ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
    24562391IEM_DECL_NATIVE_HLP_PROTO(void,     iemNativeHlpMemFlatFetchDataU128,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, PRTUINT128U pu128Dst));
    24572392IEM_DECL_NATIVE_HLP_PROTO(void,     iemNativeHlpMemFlatFetchDataU128AlignedSse,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, PRTUINT128U pu128Dst));
    … …  
    24592394IEM_DECL_NATIVE_HLP_PROTO(void,     iemNativeHlpMemFlatFetchDataU256NoAc,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, PRTUINT256U pu256Dst));
    24602395IEM_DECL_NATIVE_HLP_PROTO(void,     iemNativeHlpMemFlatFetchDataU256AlignedAvx,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, PRTUINT256U pu256Dst));
    2461 #endif
    24622396IEM_DECL_NATIVE_HLP_PROTO(void,     iemNativeHlpMemFlatStoreDataU8,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t u8Value));
    24632397IEM_DECL_NATIVE_HLP_PROTO(void,     iemNativeHlpMemFlatStoreDataU16,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint16_t u16Value));
    24642398IEM_DECL_NATIVE_HLP_PROTO(void,     iemNativeHlpMemFlatStoreDataU32,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t u32Value));
    24652399IEM_DECL_NATIVE_HLP_PROTO(void,     iemNativeHlpMemFlatStoreDataU64,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint64_t u64Value));
    2466 #ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
    24672400IEM_DECL_NATIVE_HLP_PROTO(void,     iemNativeHlpMemFlatStoreDataU128AlignedSse,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, PCRTUINT128U pu128Src));
    24682401IEM_DECL_NATIVE_HLP_PROTO(void,     iemNativeHlpMemFlatStoreDataU128NoAc,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, PCRTUINT128U pu128Src));
    24692402IEM_DECL_NATIVE_HLP_PROTO(void,     iemNativeHlpMemFlatStoreDataU256NoAc,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, PCRTUINT256U pu256Src));
    24702403IEM_DECL_NATIVE_HLP_PROTO(void,     iemNativeHlpMemFlatStoreDataU256AlignedAvx,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, PCRTUINT256U pu256Src));
    2471 #endif
    24722404IEM_DECL_NATIVE_HLP_PROTO(void,     iemNativeHlpStackFlatStoreU16,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint16_t u16Value));
    24732405IEM_DECL_NATIVE_HLP_PROTO(void,     iemNativeHlpStackFlatStoreU32,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t u32Value));
    … …  
    26682600
    26692601
    2670 #ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
    26712602DECL_INLINE_THROW(void) iemNativeVarSimdRegisterRelease(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar)
    26722603{
    … …  
    26742605    iemNativeVarRegisterRelease(pReNative, idxVar);
    26752606}
    2676 #endif
    26772607
    26782608
    … …  
    28442774
    28452775
    2846 #ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
    28472776/** Number of hidden arguments for SSE_AIMPL calls. */
    2848 # define IEM_SSE_AIMPL_HIDDEN_ARGS 1
     2777#define IEM_SSE_AIMPL_HIDDEN_ARGS  1
    28492778/** Number of hidden arguments for AVX_AIMPL calls. */
    2850 # define IEM_AVX_AIMPL_HIDDEN_ARGS 1
    2851 #endif
     2779#define IEM_AVX_AIMPL_HIDDEN_ARGS   1
    28522780
    28532781
    … …  
    31943122    uint64_t const bmGstRegShadowDirty     = 0;
    31953123#endif
    3196 #ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
    31973124    uint64_t const bmGstSimdRegShadowDirty = (  pReNative->Core.bmGstSimdRegShadowDirtyLo128
    31983125                                              | pReNative->Core.bmGstSimdRegShadowDirtyHi128)
    31993126                                           & ~fGstSimdShwExcept;
    3200 #else
    3201     uint64_t const bmGstSimdRegShadowDirty = 0;
    3202 #endif
    32033127    if (bmGstRegShadowDirty | bmGstSimdRegShadowDirty | fWritebackPc)
    32043128        return iemNativeRegFlushPendingWritesSlow(pReNative, off, fGstShwExcept, fGstSimdShwExcept);
    … …  
    32833207*********************************************************************************************************************************/
    32843208
    3285 #ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
    3286 
    32873209DECL_FORCE_INLINE(uint8_t)
    32883210iemNativeSimdRegMarkAllocated(PIEMRECOMPILERSTATE pReNative, uint8_t idxSimdReg,
    … …  
    34043326}
    34053327
    3406 #endif /* IEMNATIVE_WITH_SIMD_REG_ALLOCATOR */
    34073328
    34083329

  • trunk/src/VBox/VMM/include/IEMN8veRecompilerEmit.h

    r106202 r106453  
    23542354
    23552355
    2356 #ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
    23572356/**
    23582357 * Emits a 128-bit vector register load instruction with an BP relative source address.
    … …  
    24022401#endif
    24032402}
    2404 
    2405 #endif
    24062403
    24072404
    … …  
    25542551}
    25552552
    2556 #ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
    25572553
    25582554/**
    … …  
    26382634}
    26392635
    2640 #endif /* IEMNATIVE_WITH_SIMD_REG_ALLOCATOR */
    26412636#if defined(RT_ARCH_ARM64)
    26422637
    … …  
    27142709}
    27152710
    2716 # ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
    27172711/**
    27182712 * Common bit of iemNativeEmitLoadVecRegByGprU128 and friends.
    … …  
    27502744    return off;
    27512745}
    2752 # endif
    27532746
    27542747
    … …  
    31763169
    31773170
    3178 #ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
    31793171/**
    31803172 * Emits a 128-bit vector register load via a GPR base address with a displacement.
    … …  
    32893281    return off;
    32903282}
    3291 #endif
    32923283
    32933284
    … …  
    36053596
    36063597
    3607 #ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
    36083598/**
    36093599 * Emits a 128-bit vector register store via a GPR base address with a displacement.
    … …  
    37183708    return off;
    37193709}
    3720 #endif
    37213710
    37223711
    … …  
    89468935
    89478936
    8948 #ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
     8937
    89498938/*********************************************************************************************************************************
    89508939*   SIMD helpers.                                                                                                                *
    89518940*********************************************************************************************************************************/
    8952 
    89538941
    89548942/**
    … …  
    1054310531}
    1054410532
    10545 #endif /* IEMNATIVE_WITH_SIMD_REG_ALLOCATOR */
    1054610533
    1054710534/** @} */
Note: See TracChangeset for help on using the changeset viewer.

© 2025 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette