VirtualBox

Changeset 106465 in vbox for trunk/src/VBox/VMM/VMMAll


Ignore:
Timestamp:
Oct 18, 2024 12:27:52 AM (4 months ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
165291
Message:

VMM/IEM: Added iemNativeEmitLoadGprWithGstReg[Ex]T and iemNativeEmitStoreGprToGstReg[Ex]T as better way of explictly loading & storing standard guest registers. bugref:10720

Location:
trunk/src/VBox/VMM/VMMAll
Files:
5 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/VMM/VMMAll/IEMAllN8veExecMem.cpp

    r106405 r106465  
    323323typedef struct IEMEXECMEMALLOCHDR
    324324{
     325    RT_GCC_EXTENSION
    325326    union
    326327    {

  • trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompBltIn.cpp

    r106443 r106465  
    13061306    if (IEM_F_MODE_X86_IS_FLAT(pReNative->fExec))
    13071307    {
    1308         off = iemNativeEmitLoadGprFromVCpuU64(pReNative, off, idxRegTmp, RT_UOFFSETOF(VMCPUCC, cpum.GstCtx.cs.u64Base));
     1308        off = iemNativeEmitLoadGprWithGstRegT<kIemNativeGstReg_CsBase>(pReNative, off, idxRegTmp);
    13091309# ifdef RT_ARCH_ARM64
    13101310        uint32_t * const pu32CodeBuf = iemNativeInstrBufEnsure(pReNative, off, 2);
    … …  
    16191619    if (IEM_F_MODE_X86_IS_FLAT(pReNative->fExec))
    16201620    {
    1621         off = iemNativeEmitLoadGprFromVCpuU64(pReNative, off, idxRegTmp, RT_UOFFSETOF(VMCPUCC, cpum.GstCtx.cs.u64Base));
     1621        off = iemNativeEmitLoadGprWithGstRegT<kIemNativeGstReg_CsBase>(pReNative, off, idxRegTmp);
    16221622# ifdef RT_ARCH_ARM64
    16231623        uint32_t * const pu32CodeBuf = iemNativeInstrBufEnsure(pReNative, off, 2);

  • trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompFuncs.h

    r106453 r106465  
    143143        Log4(("uPcUpdatingDebug=rip+%ld cBits=%d off=%#x\n", offDisp, cBits, off));
    144144        pReNative->Core.fDebugPcInitialized = true;
    145         off = iemNativeEmitLoadGprFromVCpuU64Ex(pCodeBuf, off, idxTmpReg, RT_UOFFSETOF(VMCPU, cpum.GstCtx.rip));
     145        off = iemNativeEmitLoadGprWithGstRegExT<kIemNativeGstReg_Pc>(pCodeBuf, off, idxTmpReg);
    146146    }
    147147
    … …  
    444444                                                                                    | CPUMCTX_DBG_DBGF_MASK);
    445445    off = iemNativeEmitAndGpr32ByImm(pReNative, off, idxEflReg, ~(uint32_t)(X86_EFL_RF | CPUMCTX_INHIBIT_SHADOW));
    446     off = iemNativeEmitStoreGprToVCpuU32(pReNative, off, idxEflReg, RT_UOFFSETOF(VMCPU, cpum.GstCtx.eflags));
     446    off = iemNativeEmitStoreGprToGstRegT<kIemNativeGstReg_EFlags>(pReNative, off, idxEflReg);
    447447
    448448    /* Free but don't flush the EFLAGS register. */
    … …  
    583583# if defined(IEMNATIVE_REG_FIXED_PC_DBG)
    584584    if (!pReNative->Core.offPc)
    585         off = iemNativeEmitLoadGprFromVCpuU64(pReNative, off, IEMNATIVE_REG_FIXED_PC_DBG, RT_UOFFSETOF(VMCPU, cpum.GstCtx.rip));
     585        off = iemNativeEmitLoadGprWithGstShadowRegT<kIemNativeGstReg_Pc>(pNative, off, IEMNATIVE_REG_FIXED_PC_DBG);
    586586# endif
    587587
    … …  
    591591    /* Perform the addition and store the result. */
    592592    off = iemNativeEmitAddGprImm8(pReNative, off, idxPcReg, cbInstr);
    593     off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxPcReg, RT_UOFFSETOF(VMCPU, cpum.GstCtx.rip));
     593    off = iemNativeEmitStoreGprToGstRegT<kIemNativeGstReg_Pc>(pReNative, off, idxPcReg);
    594594
    595595    /* Free but don't flush the PC register. */
    … …  
    629629# ifdef IEMNATIVE_REG_FIXED_PC_DBG
    630630    if (!pReNative->Core.offPc)
    631         off = iemNativeEmitLoadGprFromVCpuU64(pReNative, off, IEMNATIVE_REG_FIXED_PC_DBG, RT_UOFFSETOF(VMCPU, cpum.GstCtx.rip));
     631        off = iemNativeEmitLoadGprWithGstShadowRegT<kIemNativeGstReg_Pc>(pReNative, off, IEMNATIVE_REG_FIXED_PC_DBG);
    632632# endif
    633633
    … …  
    637637    /* Perform the addition and store the result. */
    638638    off = iemNativeEmitAddGpr32Imm8(pReNative, off, idxPcReg, cbInstr);
    639     off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxPcReg, RT_UOFFSETOF(VMCPU, cpum.GstCtx.rip));
     639    off = iemNativeEmitStoreGprToGstRegT<kIemNativeGstReg_Pc>(pReNative, off, idxPcReg);
    640640
    641641    /* Free but don't flush the PC register. */
    … …  
    675675# if defined(IEMNATIVE_REG_FIXED_PC_DBG)
    676676    if (!pReNative->Core.offPc)
    677         off = iemNativeEmitLoadGprFromVCpuU64(pReNative, off, IEMNATIVE_REG_FIXED_PC_DBG, RT_UOFFSETOF(VMCPU, cpum.GstCtx.rip));
     677        off = iemNativeEmitLoadGprWithGstShadowRegT<kIemNativeGstReg_Pc>(pReNative, off, IEMNATIVE_REG_FIXED_PC_DBG);
    678678# endif
    679679
    … …  
    684684    off = iemNativeEmitAddGpr32Imm8(pReNative, off, idxPcReg, cbInstr);
    685685    off = iemNativeEmitClear16UpGpr(pReNative, off, idxPcReg);
    686     off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxPcReg, RT_UOFFSETOF(VMCPU, cpum.GstCtx.rip));
     686    off = iemNativeEmitStoreGprToGstRegT<kIemNativeGstReg_Pc>(pReNative, off, idxPcReg);
    687687
    688688    /* Free but don't flush the PC register. */
    … …  
    850850    /* Undo the PC adjustment and store the old PC value. */
    851851    off = iemNativeEmitSubGprImm(pReNative, off, idxAddrReg, offDisp, iTmpReg);
    852     off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxAddrReg, RT_UOFFSETOF(VMCPU, cpum.GstCtx.rip));
     852    off = iemNativeEmitStoreGprToGstRegT<kIemNativeGstReg_Pc>(pReNative, off, idxAddrReg);
    853853
    854854    off = iemNativeEmitTbExit<kIemNativeLabelType_RaiseGp0, false /*a_fActuallyExitingTb*/>(pReNative, off);
    … …  
    943943        {
    944944            idxOldPcReg = iTmpReg;
    945             off = iemNativeEmitLoadGprFromVCpuU64(pReNative, off, idxOldPcReg, RT_UOFFSETOF(VMCPU, cpum.GstCtx.rip));
     945            off = iemNativeEmitLoadGprWithGstRegT<kIemNativeGstReg_Pc>(pReNative, off, idxOldPcReg);
    946946        }
    947947        off = iemNativeEmitAddGprImm(pReNative, off, idxOldPcReg, pReNative->Core.offPc);
    948         off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxOldPcReg, RT_UOFFSETOF(VMCPU, cpum.GstCtx.rip));
     948        off = iemNativeEmitStoreGprToGstRegT<kIemNativeGstReg_Pc>(pReNative, off, idxOldPcReg);
    949949
    950950        off = iemNativeEmitTbExit<kIemNativeLabelType_RaiseGp0, false /*a_fActuallyExitingTb*/>(pReNative, off);
    … …  
    10491049        {
    10501050            idxOldPcReg = idxAddrReg;
    1051             off = iemNativeEmitLoadGprFromVCpuU64(pReNative, off, idxOldPcReg, RT_UOFFSETOF(VMCPU, cpum.GstCtx.rip));
     1051            off = iemNativeEmitLoadGprWithGstRegT<kIemNativeGstReg_Pc>(pReNative, off, idxOldPcReg);
    10521052        }
    10531053        off = iemNativeEmitAddGprImm(pReNative, off, idxOldPcReg, pReNative->Core.offPc);
    1054         off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxOldPcReg, RT_UOFFSETOF(VMCPU, cpum.GstCtx.rip));
     1054        off = iemNativeEmitStoreGprToGstRegT<kIemNativeGstReg_Pc>(pReNative, off, idxOldPcReg);
    10551055# ifdef IEMNATIVE_WITH_INSTRUCTION_COUNTING
    10561056        off = iemNativeEmitStoreImmToVCpuU8(pReNative, off, idxInstr, RT_UOFFSETOF(VMCPUCC, iem.s.idxTbCurInstr));
    … …  
    12101210#endif
    12111211
    1212         off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxPcReg, RT_UOFFSETOF(VMCPU, cpum.GstCtx.rip));
     1212        off = iemNativeEmitStoreGprToGstRegT<kIemNativeGstReg_Pc>(pReNative, off, idxPcReg);
    12131213
    12141214        /* Free but don't flush the PC register. */
    … …  
    13321332#endif
    13331333
    1334     off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxPcReg, RT_UOFFSETOF(VMCPU, cpum.GstCtx.rip));
     1334    off = iemNativeEmitStoreGprToGstRegT<kIemNativeGstReg_Pc>(pReNative, off, idxPcReg);
    13351335#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING
    13361336    pReNative->Core.offPc = 0;
    … …  
    13951395    off = iemNativeEmitPcDebugCheckWithReg(pReNative, off, idxPcReg);
    13961396#endif
    1397     off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxPcReg, RT_UOFFSETOF(VMCPU, cpum.GstCtx.rip));
     1397    off = iemNativeEmitStoreGprToGstRegT<kIemNativeGstReg_Pc>(pReNative, off, idxPcReg);
    13981398
    13991399    /* Free but don't flush the PC register. */
    … …  
    15101510
    15111511    /* Store the result. */
    1512     off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxPcReg, RT_UOFFSETOF(VMCPU, cpum.GstCtx.rip));
     1512    off = iemNativeEmitStoreGprToGstRegT<kIemNativeGstReg_Pc>(pReNative, off, idxPcReg);
    15131513
    15141514#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING
    … …  
    18081808
    18091809#if !defined(IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK)
    1810     off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxRegRsp, RT_UOFFSETOF_DYN(VMCPU, cpum.GstCtx.rsp));
     1810    off = iemNativeEmitStoreGprToGstRegT<kIemNativeGstReg_Rsp>(pReNative, off, idxRegRsp);
    18111811#endif
    18121812    iemNativeRegFreeTmp(pReNative, idxRegRsp);
    … …  
    18881888    /* Get a register with the new PC loaded from idxVarPc.
    18891889       Note! This ASSUMES that the high bits of the GPR is zeroed. */
    1890     uint8_t const idxNewPcReg = iemNativeVarRegisterAcquire(pReNative, idxVarPc, &off);
     1890    uint8_t const idxPcRegNew = iemNativeVarRegisterAcquire(pReNative, idxVarPc, &off);
    18911891
    18921892    /* Check limit (may #GP(0) + exit TB). */
    18931893    if (!f64Bit)
    18941894/** @todo we can skip this test in FLAT 32-bit mode. */
    1895         off = iemNativeEmitCheckGpr32AgainstCsSegLimitMaybeRaiseGp0(pReNative, off, idxNewPcReg, idxInstr);
     1895        off = iemNativeEmitCheckGpr32AgainstCsSegLimitMaybeRaiseGp0(pReNative, off, idxPcRegNew, idxInstr);
    18961896    /* Check that the address is canonical, raising #GP(0) + exit TB if it isn't. */
    18971897    else if (cbVar > sizeof(uint32_t))
    1898         off = iemNativeEmitCheckGprCanonicalMaybeRaiseGp0(pReNative, off, idxNewPcReg, idxInstr);
     1898        off = iemNativeEmitCheckGprCanonicalMaybeRaiseGp0(pReNative, off, idxPcRegNew, idxInstr);
    18991899
    19001900#if 1
    … …  
    19351935
    19361936    /* Store the result. */
    1937     off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxNewPcReg, RT_UOFFSETOF(VMCPU, cpum.GstCtx.rip));
     1937    off = iemNativeEmitStoreGprToGstRegT<kIemNativeGstReg_Pc>(pReNative, off, idxPcRegNew);
    19381938#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING_DEBUG
    1939     off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxNewPcReg, RT_UOFFSETOF(VMCPU, iem.s.uPcUpdatingDebug));
     1939    off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxPcRegNew, RT_UOFFSETOF(VMCPU, iem.s.uPcUpdatingDebug));
    19401940    pReNative->Core.fDebugPcInitialized = true;
    19411941    Log4(("uPcUpdatingDebug=rip/indirect-call off=%#x\n", off));
    … …  
    19441944#if 1
    19451945    /* Need to transfer the shadow information to the new RIP register. */
    1946     iemNativeRegClearAndMarkAsGstRegShadow(pReNative, idxNewPcReg, kIemNativeGstReg_Pc, off);
     1946    iemNativeRegClearAndMarkAsGstRegShadow(pReNative, idxPcRegNew, kIemNativeGstReg_Pc, off);
    19471947#else
    19481948    /* Sync the new PC. */
    1949     off = iemNativeEmitLoadGprFromGpr(pReNative, off, idxPcReg, idxNewPcReg);
     1949    off = iemNativeEmitLoadGprFromGpr(pReNative, off, idxPcReg, idxPcRegNew);
    19501950#endif
    19511951    iemNativeVarRegisterRelease(pReNative, idxVarPc);
    … …  
    20342034
    20352035    /* Store the result. */
    2036     off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxPcRegNew, RT_UOFFSETOF(VMCPU, cpum.GstCtx.rip));
     2036    off = iemNativeEmitStoreGprToGstRegT<kIemNativeGstReg_Pc>(pReNative, off, idxPcRegNew);
    20372037#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING_DEBUG
    20382038    off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxPcRegNew, RT_UOFFSETOF(VMCPU, iem.s.uPcUpdatingDebug));
    … …  
    21002100
    21012101    /* Store the result. */
    2102     off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxPcRegNew, RT_UOFFSETOF(VMCPU, cpum.GstCtx.rip));
     2102    off = iemNativeEmitStoreGprToGstRegT<kIemNativeGstReg_Pc>(pReNative, off, idxPcRegNew);
    21032103#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING_DEBUG
    21042104    off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxPcRegNew, RT_UOFFSETOF(VMCPU, iem.s.uPcUpdatingDebug));
    … …  
    21642164
    21652165    /* Store the result. */
    2166     off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxPcRegNew, RT_UOFFSETOF(VMCPU, cpum.GstCtx.rip));
     2166    off = iemNativeEmitStoreGprToGstRegT<kIemNativeGstReg_Pc>(pReNative, off, idxPcRegNew);
    21672167#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING_DEBUG
    21682168    off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxPcRegNew, RT_UOFFSETOF(VMCPU, iem.s.uPcUpdatingDebug));
    … …  
    25122512
    25132513    /* Commit the result and clear any current guest shadows for RIP. */
    2514     off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxRegRsp,       RT_UOFFSETOF(VMCPU, cpum.GstCtx.rsp));
    2515     off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxRegMemResult, RT_UOFFSETOF(VMCPU, cpum.GstCtx.rip));
     2514    off = iemNativeEmitStoreGprToGstRegT<kIemNativeGstReg_Rsp>(pReNative, off, idxRegRsp);
     2515    off = iemNativeEmitStoreGprToGstRegT<kIemNativeGstReg_Pc>( pReNative, off, idxRegMemResult);
    25162516    iemNativeRegClearAndMarkAsGstRegShadow(pReNative, idxRegMemResult, kIemNativeGstReg_Pc, off);
    25172517#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING_DEBUG
    … …  
    59245924        }
    59255925        else
    5926             off = iemNativeEmitLoadGprFromVCpuU32(pReNative, off, idxVarReg, RT_UOFFSETOF(VMCPUCC, cpum.GstCtx.eflags));
     5926            off = iemNativeEmitLoadGprWithGstRegT<kIemNativeGstReg_EFlags>(pReNative, off, idxVarReg);
    59275927        iemNativeVarRegisterRelease(pReNative, idxVarEFlags);
    59285928    }
    … …  
    60236023
    60246024    iemNativeRegClearAndMarkAsGstRegShadow(pReNative, idxReg, kIemNativeGstReg_EFlags, off);
    6025     off = iemNativeEmitStoreGprToVCpuU32(pReNative, off, idxReg, RT_UOFFSETOF_DYN(VMCPUCC, cpum.GstCtx.eflags));
     6025    off = iemNativeEmitStoreGprToGstRegT<kIemNativeGstReg_EFlags>(pReNative, off, idxReg);
    60266026    iemNativeVarRegisterRelease(pReNative, idxVarEFlags);
    60276027    return off;
    … …  
    60676067
    60686068    /** @todo No delayed writeback for EFLAGS right now. */
    6069     off = iemNativeEmitStoreGprToVCpuU32(pReNative, off, idxEflReg, RT_UOFFSETOF(VMCPU, cpum.GstCtx.eflags));
     6069    off = iemNativeEmitStoreGprToGstRegT<kIemNativeGstReg_EFlags>(pReNative, off, idxEflReg);
    60706070
    60716071    /* Free but don't flush the EFLAGS register. */
    … …  
    73917391        /* Perform the addition and store the result. */
    73927392        off = iemNativeEmitAddGprImm(pReNative, off, idxPcReg, pReNative->Core.offPc);
    7393         off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxPcReg, RT_UOFFSETOF(VMCPU, cpum.GstCtx.rip));
     7393        off = iemNativeEmitStoreGprToGstRegT<kIemNativeGstReg_Pc>(pReNative, off, idxPcReg);
    73947394# ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING_DEBUG
    73957395        off = iemNativeEmitPcDebugCheckWithReg(pReNative, off, idxPcReg);
    … …  
    75277527        /* Restore the original value. */
    75287528        off = iemNativeEmitSubGprImm(pReNative, off, idxPcReg, pReNative->Core.offPc);
    7529         off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxPcReg, RT_UOFFSETOF(VMCPU, cpum.GstCtx.rip));
     7529        off = iemNativeEmitStoreGprToGstRegT<kIemNativeGstReg_Pc>(pReNative, off, idxPcReg);
    75307530
    75317531        /* Free and flush the PC register. */
    … …  
    84638463                        else
    84648464                        {
    8465                             off = iemNativeEmitLoadGprFromVCpuU32(pReNative, off, TlbState.idxReg1,
    8466                                                                   RT_UOFFSETOF(VMCPUCC, cpum.GstCtx.eflags));
     8465                            off = iemNativeEmitLoadGprWithGstRegT<kIemNativeGstReg_EFlags>(pReNative, off, TlbState.idxReg1);
    84678466                            off = iemNativeEmitAndGpr32ByImm(pReNative, off, TlbState.idxReg1,
    84688467                                                             UINT32_C(0xffff0000) & ~X86_EFL_RAZ_MASK);
    … …  
    85148513
    85158514#if !defined(IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK)
    8516     off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxRegRsp, RT_UOFFSETOF_DYN(VMCPU, cpum.GstCtx.rsp));
     8515    off = iemNativeEmitStoreGprToGstRegT<kIemNativeGstReg_Rsp>(pReNative, off, idxRegRsp);
    85178516#endif
    85188517    iemNativeRegFreeTmp(pReNative, idxRegRsp);
    … …  
    88648863
    88658864#if !defined(IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK)
    8866     off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxRegRsp, RT_UOFFSETOF(VMCPU, cpum.GstCtx.rsp));
     8865    off = iemNativeEmitStoreGprToGstRegT<kIemNativeGstReg_Rsp>(pReNative, off, idxRegRsp);
    88678866#endif
    88688867
    … …  
    1092810927#ifndef IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
    1092910928    /* Writeback the MXCSR register value (there is no delayed writeback for such registers at the moment). */
    10930     off = iemNativeEmitStoreGprToVCpuU32(pReNative, off, idxRegMxCsr, RT_UOFFSETOF_DYN(VMCPU, cpum.GstCtx.XState.x87.MXCSR));
     10929    off = iemNativeEmitStoreGprToGstRegT<kIemNativeGstReg_MxCsr>(pReNative, off, idxRegMxCsr);
    1093110930#endif
    1093210931

  • trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompiler.cpp

    r106453 r106465  
    60356035    /* Perform the addition and store the result. */
    60366036    off = iemNativeEmitAddGprImm(pReNative, off, idxPcReg, pReNative->Core.offPc);
    6037     off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxPcReg, RT_UOFFSETOF(VMCPU, cpum.GstCtx.rip));
     6037    off = iemNativeEmitStoreGprToGstRegT<kIemNativeGstReg_Pc>(pReNative, off, idxPcReg);
    60386038# ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING_DEBUG
    60396039    off = iemNativeEmitPcDebugCheckWithReg(pReNative, off, idxPcReg);

  • trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllN8veEmit-x86.h

    r106453 r106465  
    198198
    199199/*********************************************************************************************************************************
     200*   Guest Register Load & Store Helpers                                                                                          *
     201*********************************************************************************************************************************/
     202
     203
     204/**
     205 * Alternative to iemNativeEmitLoadGprWithGstShadowRegEx() and
     206 * iemNativeEmitLoadGprWithGstShadowReg() which should be more efficient as it
     207 * lets the compiler do the equivalent of the g_aGstShadowInfo lookup.
     208 *
     209 * @note This does not mark @a idxHstReg as having a shadow copy of @a a_enmGstReg,
     210 *       that is something the caller needs to do if applicable.
     211 */
     212template<IEMNATIVEGSTREG const a_enmGstReg>
     213DECL_INLINE_THROW(uint32_t) iemNativeEmitLoadGprWithGstRegExT(PIEMNATIVEINSTR pCodeBuf, uint32_t off, uint8_t idxHstReg)
     214{
     215    /* 64-bit registers: */
     216    if RT_CONSTEXPR_IF(a_enmGstReg == kIemNativeGstReg_Pc)
     217        return iemNativeEmitLoadGprFromVCpuU64Ex(pCodeBuf, off, idxHstReg, RT_UOFFSETOF(VMCPU, cpum.GstCtx.rip));
     218    else if RT_CONSTEXPR_IF(a_enmGstReg == kIemNativeGstReg_Rsp)
     219        return iemNativeEmitLoadGprFromVCpuU64Ex(pCodeBuf, off, idxHstReg, RT_UOFFSETOF(VMCPU, cpum.GstCtx.rsp));
     220    else if RT_CONSTEXPR_IF(a_enmGstReg == kIemNativeGstReg_CsBase)
     221        return iemNativeEmitLoadGprFromVCpuU64Ex(pCodeBuf, off, idxHstReg, RT_UOFFSETOF(VMCPU, cpum.GstCtx.cs.u64Base));
     222    //else if RT_CONSTEXPR_IF(a_enmGstReg == kIemNativeGstReg_Cr0)
     223    //    return iemNativeEmitLoadGprFromVCpuU64Ex(pCodeBuf, off, idxHstReg, RT_UOFFSETOF(VMCPU, cpum.GstCtx.cr0));
     224    //else if RT_CONSTEXPR_IF(a_enmGstReg == kIemNativeGstReg_Cr4)
     225    //    return iemNativeEmitLoadGprFromVCpuU64Ex(pCodeBuf, off, idxHstReg, RT_UOFFSETOF(VMCPU, cpum.GstCtx.cr4));
     226    //else if RT_CONSTEXPR_IF(a_enmGstReg == kIemNativeGstReg_Xcr0)
     227    //    return iemNativeEmitLoadGprFromVCpuU64Ex(pCodeBuf, off, idxHstReg, RT_UOFFSETOF(VMCPU, cpum.GstCtx.aXcr[0]));
     228
     229    /* 32-bit registers:   */
     230    else if RT_CONSTEXPR_IF(a_enmGstReg == kIemNativeGstReg_EFlags)
     231        return iemNativeEmitLoadGprFromVCpuU64Ex(pCodeBuf, off, idxHstReg, RT_UOFFSETOF(VMCPU, cpum.GstCtx.eflags));
     232    else if RT_CONSTEXPR_IF(a_enmGstReg == kIemNativeGstReg_MxCsr)
     233        return iemNativeEmitLoadGprFromVCpuU64Ex(pCodeBuf, off, idxHstReg, RT_UOFFSETOF(VMCPU, cpum.GstCtx.XState.x87.MXCSR));
     234
     235    /* 16-bit registers */
     236    else if RT_CONSTEXPR_IF(a_enmGstReg == kIemNativeGstReg_FpuFcw)
     237        return iemNativeEmitLoadGprFromVCpuU16Ex(pCodeBuf, off, idxHstReg, RT_UOFFSETOF(VMCPU, cpum.GstCtx.XState.x87.FCW));
     238    else if RT_CONSTEXPR_IF(a_enmGstReg == kIemNativeGstReg_FpuFsw)
     239        return iemNativeEmitLoadGprFromVCpuU16Ex(pCodeBuf, off, idxHstReg, RT_UOFFSETOF(VMCPU, cpum.GstCtx.XState.x87.FSW));
     240#if RT_CPLUSPLUS_PREREQ(201700) && !defined(__clang_major__)
     241    else
     242    {
     243        AssertCompile(false);
     244        return off;
     245    }
     246#endif
     247}
     248
     249
     250/** See iemNativeEmitLoadGprWithGstRegExT(). */
     251template<IEMNATIVEGSTREG const a_enmGstReg>
     252DECL_INLINE_THROW(uint32_t) iemNativeEmitLoadGprWithGstRegT(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxHstReg)
     253{
     254#ifdef RT_ARCH_AMD64
     255    PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 16);
     256#elif defined(RT_ARCH_ARM64)
     257    PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 6);
     258#else
     259# error "port me"
     260#endif
     261    off = iemNativeEmitLoadGprWithGstRegExT<a_enmGstReg>(pCodeBuf, off, idxHstReg);
     262    IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
     263    return off;
     264}
     265
     266
     267/**
     268 * Store companion to iemNativeEmitLoadGprWithGstRegExT().
     269 */
     270template<IEMNATIVEGSTREG const a_enmGstReg>
     271DECL_INLINE_THROW(uint32_t) iemNativeEmitStoreGprToGstRegExT(PIEMNATIVEINSTR pCodeBuf, uint32_t off, uint8_t idxHstReg,
     272                                                             uint8_t idxTmpReg = IEMNATIVE_REG_FIXED_TMP0)
     273{
     274    /* 64-bit registers: */
     275    if RT_CONSTEXPR_IF(a_enmGstReg == kIemNativeGstReg_Pc)
     276        return iemNativeEmitStoreGprToVCpuU64Ex(pCodeBuf, off, idxHstReg, RT_UOFFSETOF(VMCPU, cpum.GstCtx.rip), idxTmpReg);
     277    else if RT_CONSTEXPR_IF(a_enmGstReg == kIemNativeGstReg_Rsp)
     278        return iemNativeEmitStoreGprToVCpuU64Ex(pCodeBuf, off, idxHstReg, RT_UOFFSETOF(VMCPU, cpum.GstCtx.rsp), idxTmpReg);
     279    //else if RT_CONSTEXPR_IF(a_enmGstReg == kIemNativeGstReg_Cr0)
     280    //    return iemNativeEmitStoreGprToVCpuU64Ex(pCodeBuf, off, idxHstReg, RT_UOFFSETOF(VMCPU, cpum.GstCtx.cr0), idxTmpReg);
     281    //else if RT_CONSTEXPR_IF(a_enmGstReg == kIemNativeGstReg_Cr4)
     282    //    return iemNativeEmitStoreGprToVCpuU64Ex(pCodeBuf, off, idxHstReg, RT_UOFFSETOF(VMCPU, cpum.GstCtx.cr4), idxTmpReg);
     283    //else if RT_CONSTEXPR_IF(a_enmGstReg == kIemNativeGstReg_Xcr0)
     284    //    return iemNativeEmitStoreGprToVCpuU64Ex(pCodeBuf, off, idxHstReg, RT_UOFFSETOF(VMCPU, cpum.GstCtx.aXcr[0]), idxTmpReg);
     285    /* 32-bit registers:   */
     286    else if RT_CONSTEXPR_IF(a_enmGstReg == kIemNativeGstReg_EFlags)
     287        return iemNativeEmitStoreGprToVCpuU32Ex(pCodeBuf, off, idxHstReg, RT_UOFFSETOF(VMCPU, cpum.GstCtx.eflags), idxTmpReg);
     288    else if RT_CONSTEXPR_IF(a_enmGstReg == kIemNativeGstReg_MxCsr)
     289        return iemNativeEmitStoreGprToVCpuU32Ex(pCodeBuf, off, idxHstReg, RT_UOFFSETOF(VMCPU, cpum.GstCtx.XState.x87.MXCSR), idxTmpReg);
     290    /* 16-bit registers */
     291    else if RT_CONSTEXPR_IF(a_enmGstReg == kIemNativeGstReg_FpuFcw)
     292        return iemNativeEmitStoreGprToVCpuU16Ex(pCodeBuf, off, idxHstReg, RT_UOFFSETOF(VMCPU, cpum.GstCtx.XState.x87.FCW), idxTmpReg);
     293    else if RT_CONSTEXPR_IF(a_enmGstReg == kIemNativeGstReg_FpuFsw)
     294        return iemNativeEmitStoreGprToVCpuU16Ex(pCodeBuf, off, idxHstReg, RT_UOFFSETOF(VMCPU, cpum.GstCtx.XState.x87.FSW), idxTmpReg);
     295#if RT_CPLUSPLUS_PREREQ(201700) && !defined(__clang_major__)
     296    else
     297    {
     298        AssertCompile(false);
     299        return off;
     300    }
     301#endif
     302}
     303
     304
     305/** See iemNativeEmitLoadGprWithGstRegExT(). */
     306template<IEMNATIVEGSTREG const a_enmGstReg>
     307DECL_INLINE_THROW(uint32_t) iemNativeEmitStoreGprToGstRegT(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxHstReg)
     308{
     309#ifdef RT_ARCH_AMD64
     310    PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 16);
     311#elif defined(RT_ARCH_ARM64)
     312    PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 6);
     313#else
     314# error "port me"
     315#endif
     316    off = iemNativeEmitStoreGprToGstRegExT<a_enmGstReg>(pCodeBuf, off, idxHstReg);
     317    IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
     318    return off;
     319}
     320
     321
     322
     323/*********************************************************************************************************************************
    200324*   EFLAGS                                                                                                                       *
    201325*********************************************************************************************************************************/
    … …  
    468592        idxRegEfl = ASMBitFirstSetU32(bmAvailableRegs) - 1;
    469593        bmAvailableRegs &= ~RT_BIT_32(idxRegTmp);
    470         off = iemNativeEmitLoadGprFromVCpuU32Ex(pCodeBuf, off, idxRegEfl, RT_UOFFSETOF(VMCPU, cpum.GstCtx.eflags));
     594        off = iemNativeEmitLoadGprWithGstRegExT<kIemNativeGstReg_EFlags>(pCodeBuf, off, idxRegEfl);
    471595    }
    472596    Assert(bmAvailableRegs != 0);
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