VirtualBox

Changeset 106471 in vbox


Ignore:
Timestamp:
Oct 18, 2024 11:50:05 AM (6 months ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
165298
Message:

ValidationKit/bootsectors: Implement same-register testcases for [v]haddp[sd]; bugref:10658

Location:
trunk/src/VBox/ValidationKit/bootsectors
Files:
2 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4-template.mac

    r106335 r106471  
    258258EMIT_INSTR_PLUS_ICEBP_C64   vhaddps, YMM8, YMM9, FSxBX
    259259
     260EMIT_INSTR_PLUS_ICEBP       haddps,  XMM1, XMM1
     261EMIT_INSTR_PLUS_ICEBP_C64   haddps,  XMM8, XMM8
     262EMIT_INSTR_PLUS_ICEBP       vhaddps, YMM1, YMM1, YMM1
     263EMIT_INSTR_PLUS_ICEBP       vhaddps, YMM1, YMM1, YMM2
     264EMIT_INSTR_PLUS_ICEBP_C64   vhaddps, YMM8, YMM8, YMM8
     265EMIT_INSTR_PLUS_ICEBP       vhaddps, YMM1, YMM1, FSxBX
     266
    260267;
    261268;; [v]haddpd
    … …  
    275282EMIT_INSTR_PLUS_ICEBP_C64   vhaddpd, YMM8, YMM9, YMM10
    276283EMIT_INSTR_PLUS_ICEBP_C64   vhaddpd, YMM8, YMM9, FSxBX
     284
     285EMIT_INSTR_PLUS_ICEBP       haddpd,  XMM1, XMM1
     286EMIT_INSTR_PLUS_ICEBP_C64   haddpd,  XMM8, XMM8
     287EMIT_INSTR_PLUS_ICEBP       vhaddpd, YMM1, YMM1, YMM1
     288EMIT_INSTR_PLUS_ICEBP       vhaddpd, YMM1, YMM1, YMM2
     289EMIT_INSTR_PLUS_ICEBP_C64   vhaddpd, YMM8, YMM8, YMM8
     290EMIT_INSTR_PLUS_ICEBP       vhaddpd, YMM1, YMM1, FSxBX
    277291
    278292;

  • trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32

    r106470 r106471  
    34533453    /** @todo Underflow, Precision; Rounding; FZ etc. */
    34543454    };
     3455
     3456    /* Sanity-check subset for 'same register' instruction variants */
    34553457    static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValuesSR[] =
    34563458    {
    … …  
    37543756    /** @todo Underflow, Precision; Rounding; FZ etc. */
    37553757    };
     3758
     3759    /* Sanity-check subset for 'same register' instruction variants */
    37563760    static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValuesSR[] =
    37573761    {
    … …  
    40904094    /** @todo Underflow; Precision; Rounding; FZ etc. */
    40914095    };
     4096
     4097    /* Sanity-check subset for 'same register' instruction variants */
    40924098    static BS3CPUINSTR4_TEST1_VALUES_SS_T const s_aValuesSR[] =
    40934099    {
    … …  
    44414447    /** @todo Underflow, Precision; Rounding; FZ etc. */
    44424448    };
     4449
     4450    /* Sanity-check subset for 'same register' instruction variants */
    44434451    static BS3CPUINSTR4_TEST1_VALUES_SD_T const s_aValuesSR[] =
    44444452    {
    … …  
    48064814    };
    48074815
     4816    /* Sanity-check subset for 'same register' instruction variants */
     4817    static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValuesSR[] =
     4818    {
     4819          { { /*src1     */ { FP32_V(0, 0x669050, 0x93)/*1888778.0*/, FP32_V(1, 0x1ea980, 0x8f)/*-81235.0*/,   FP32_V(0, 0x253468, 0x93)/*1353357.0*/, FP32_V(1, 0x7c9000, 0x88)/*-1010.25*/,   FP32_V(0, 0x5c0000, 0x84)/*55.0*/, FP32_V(0, 0x600000, 0x81)/*7.0*/,    FP32_V(0, 0x534000, 0x86)/*211.25*/, FP32_1(1)                           } },
     4820            { /*src1     */ { FP32_V(0, 0x669050, 0x93)/*1888778.0*/, FP32_V(1, 0x1ea980, 0x8f)/*-81235.0*/,   FP32_V(0, 0x253468, 0x93)/*1353357.0*/, FP32_V(1, 0x7c9000, 0x88)/*-1010.25*/,   FP32_V(0, 0x5c0000, 0x84)/*55.0*/, FP32_V(0, 0x600000, 0x81)/*7.0*/,    FP32_V(0, 0x534000, 0x86)/*211.25*/, FP32_1(1)                           } },
     4821            { /* =>      */ { FP32_V(0, 0x5ca5b8, 0x93)/*1807543.0*/, FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_V(0, 0x5ca5b8, 0x93)/*1807543.0*/, FP32_V(0, 0x2514d6, 0x93)/*1352346.75*/, FP32_V(0, 0x780000, 0x84)/*62.0*/, FP32_V(0, 0x524000, 0x86)/*210.25*/, FP32_V(0, 0x780000, 0x84)/*62.0*/,   FP32_V(0, 0x524000, 0x86)/*210.25*/ } },
     4822              /*mxcsr:in */ 0,
     4823              /*128:out  */ 0,
     4824              /*256:out  */ 0 },
     4825          { { /*src2     */ { FP32_V(0, 0x6423f2, 0x92)/*934463.125*/, FP32_V(1, 0x0a19f0, 0x8f)/*-70707.875*/, FP32_V(0, 0x600000, 0x7e)/*0.875*/,   FP32_V(0, 0x769b50, 0x92)/*1010101.0*/, FP32_INF(0),  FP32_INF(1),  FP32_QNAN(1), FP32_QNAN(0) } },
     4826            { /*src1     */ { FP32_V(0, 0x6423f2, 0x92)/*934463.125*/, FP32_V(1, 0x0a19f0, 0x8f)/*-70707.875*/, FP32_V(0, 0x600000, 0x7e)/*0.875*/,   FP32_V(0, 0x769b50, 0x92)/*1010101.0*/, FP32_INF(0),  FP32_INF(1),  FP32_QNAN(1), FP32_QNAN(0) } },
     4827            { /* =>      */ { FP32_V(0,0x52e0b4,0x92)/*863755.25*/,    FP32_V(0,0x769b5e,0x92)/*1010101.875*/,  FP32_V(0,0x52e0b4,0x92)/*863755.25*/, FP32_V(0,0x769b5e,0x92)/*1010101.875*/, FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1) } },
     4828              /*mxcsr:in */ 0,
     4829              /*128:out  */ 0,
     4830              /*256:out  */ X86_MXCSR_IE },
     4831    };
     4832
    48084833    static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
    48094834    {
    … …  
    48164841        { bs3CpuInstr4_vhaddps_YMM1_YMM2_YMM3_icebp_c16,  255, RM_REG, T_AVX_256, 1, 2, 3,   PASS_s_aValues },
    48174842        { bs3CpuInstr4_vhaddps_YMM1_YMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_256, 1, 2, 255, PASS_s_aValues },
     4843
     4844        { bs3CpuInstr4_haddps_XMM1_XMM1_icebp_c16,        255, RM_REG, T_SSE3,    1, 1, 1,   PASS_s_aValuesSR },
     4845        { bs3CpuInstr4_vhaddps_YMM1_YMM1_YMM1_icebp_c16,  255, RM_REG, T_AVX_256, 1, 1, 1,   PASS_s_aValuesSR },
     4846        { bs3CpuInstr4_vhaddps_YMM1_YMM1_YMM2_icebp_c16,  255, RM_REG, T_AVX_256, 1, 1, 2,   PASS_s_aValuesSR },
     4847        { bs3CpuInstr4_vhaddps_YMM1_YMM1_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_256, 1, 1, 255, PASS_s_aValuesSR },
    48184848    };
    48194849    static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
    … …  
    48274857        { bs3CpuInstr4_vhaddps_YMM1_YMM2_YMM3_icebp_c32,  255, RM_REG, T_AVX_256, 1, 2, 3,   PASS_s_aValues },
    48284858        { bs3CpuInstr4_vhaddps_YMM1_YMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_256, 1, 2, 255, PASS_s_aValues },
     4859
     4860        { bs3CpuInstr4_haddps_XMM1_XMM1_icebp_c32,        255, RM_REG, T_SSE3,    1, 1, 1,   PASS_s_aValuesSR },
     4861        { bs3CpuInstr4_vhaddps_YMM1_YMM1_YMM1_icebp_c32,  255, RM_REG, T_AVX_256, 1, 1, 1,   PASS_s_aValuesSR },
     4862        { bs3CpuInstr4_vhaddps_YMM1_YMM1_YMM2_icebp_c32,  255, RM_REG, T_AVX_256, 1, 1, 2,   PASS_s_aValuesSR },
     4863        { bs3CpuInstr4_vhaddps_YMM1_YMM1_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_256, 1, 1, 255, PASS_s_aValuesSR },
    48294864    };
    48304865    static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
    … …  
    48464881        { bs3CpuInstr4_vhaddps_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 10,  PASS_s_aValues },
    48474882        { bs3CpuInstr4_vhaddps_YMM8_YMM9_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 8, 9, 255, PASS_s_aValues },
     4883
     4884        { bs3CpuInstr4_haddps_XMM1_XMM1_icebp_c64,        255, RM_REG, T_SSE3,    1, 1, 1,   PASS_s_aValuesSR },
     4885        { bs3CpuInstr4_haddps_XMM8_XMM8_icebp_c64,        255, RM_REG, T_SSE3,    8, 8, 8,   PASS_s_aValuesSR },
     4886        { bs3CpuInstr4_vhaddps_YMM1_YMM1_YMM1_icebp_c64,  255, RM_REG, T_AVX_256, 1, 1, 1,   PASS_s_aValuesSR },
     4887        { bs3CpuInstr4_vhaddps_YMM8_YMM8_YMM8_icebp_c64,  255, RM_REG, T_AVX_256, 8, 8, 8,   PASS_s_aValuesSR },
     4888        { bs3CpuInstr4_vhaddps_YMM1_YMM1_YMM2_icebp_c64,  255, RM_REG, T_AVX_256, 1, 1, 2,   PASS_s_aValuesSR },
     4889        { bs3CpuInstr4_vhaddps_YMM1_YMM1_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 1, 1, 255, PASS_s_aValuesSR },
    48484890    };
    48494891
    … …  
    51075149    };
    51085150
     5151    /* Sanity-check subset for 'same register' instruction variants */
     5152    static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValuesSR[] =
     5153    {
     5154    /* 0*/{ { /*src2     */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_V(0, 0xd6eca42000000, 0x419)/*123450000.5*/,      FP64_V(0, 0xcf0033a34f337, 0x432)/*4072598000007579.5*/, FP64_V(0, 0x921fb54442d18, 0x400)/*3.141592653589793*/ } },
     5155            { /*src1     */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_V(0, 0xd6eca42000000, 0x419)/*123450000.5*/,      FP64_V(0, 0xcf0033a34f337, 0x432)/*4072598000007579.5*/, FP64_V(0, 0x921fb54442d18, 0x400)/*3.141592653589793*/ } },
     5156            { /* =>      */ { FP64_V(0,0xc12235db073f0,0x42d)/*123456913326543.75*/,   FP64_V(0,0xc12235db073f0,0x42d)/*123456913326543.75*/, FP64_V(0,0xcf0033a34f33d,0x432)/*4072598000007582.5*/,   FP64_V(0,0xcf0033a34f33d,0x432)/*4072598000007582.5*/  } },
     5157              /*mxcsr:in */ 0,
     5158              /*128:out  */ 0,
     5159              /*256:out  */ X86_MXCSR_PE },
     5160          { { /*src2     */ { FP64_INF(0),  FP64_QNAN(1), FP64_SNAN(1),      FP64_SNAN(0)      } },
     5161            { /*src1     */ { FP64_INF(0),  FP64_QNAN(1), FP64_SNAN(1),      FP64_SNAN(0)      } },
     5162            { /* =>      */ { FP64_QNAN(1), FP64_QNAN(1), FP64_QNAN_V(1, 1), FP64_QNAN_V(1, 1) } },
     5163              /*mxcsr:in */ 0,
     5164              /*128:out  */ 0,
     5165              /*256:out  */ X86_MXCSR_IE },
     5166    };
     5167
    51095168    static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
    51105169    {
    … …  
    51175176        { bs3CpuInstr4_vhaddpd_YMM1_YMM2_YMM3_icebp_c16,  255, RM_REG, T_AVX_256, 1, 2, 3,   PASS_s_aValues },
    51185177        { bs3CpuInstr4_vhaddpd_YMM1_YMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_256, 1, 2, 255, PASS_s_aValues },
     5178
     5179        { bs3CpuInstr4_haddpd_XMM1_XMM1_icebp_c16,        255, RM_REG, T_SSE3,    1, 1, 1,   PASS_s_aValuesSR },
     5180        { bs3CpuInstr4_vhaddpd_YMM1_YMM1_YMM1_icebp_c16,  255, RM_REG, T_AVX_256, 1, 1, 1,   PASS_s_aValuesSR },
     5181        { bs3CpuInstr4_vhaddpd_YMM1_YMM1_YMM2_icebp_c16,  255, RM_REG, T_AVX_256, 1, 1, 2,   PASS_s_aValuesSR },
     5182        { bs3CpuInstr4_vhaddpd_YMM1_YMM1_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_256, 1, 1, 255, PASS_s_aValuesSR },
    51195183    };
    51205184    static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
    … …  
    51285192        { bs3CpuInstr4_vhaddpd_YMM1_YMM2_YMM3_icebp_c32,  255, RM_REG, T_AVX_256, 1, 2, 3,   PASS_s_aValues },
    51295193        { bs3CpuInstr4_vhaddpd_YMM1_YMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_256, 1, 2, 255, PASS_s_aValues },
     5194
     5195        { bs3CpuInstr4_haddpd_XMM1_XMM1_icebp_c32,        255, RM_REG, T_SSE3,    1, 1, 1,   PASS_s_aValuesSR },
     5196        { bs3CpuInstr4_vhaddpd_YMM1_YMM1_YMM1_icebp_c32,  255, RM_REG, T_AVX_256, 1, 1, 1,   PASS_s_aValuesSR },
     5197        { bs3CpuInstr4_vhaddpd_YMM1_YMM1_YMM2_icebp_c32,  255, RM_REG, T_AVX_256, 1, 1, 2,   PASS_s_aValuesSR },
     5198        { bs3CpuInstr4_vhaddpd_YMM1_YMM1_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_256, 1, 1, 255, PASS_s_aValuesSR },
    51305199    };
    51315200    static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
    … …  
    51475216        { bs3CpuInstr4_vhaddpd_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 10,  PASS_s_aValues },
    51485217        { bs3CpuInstr4_vhaddpd_YMM8_YMM9_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 8, 9, 255, PASS_s_aValues },
     5218
     5219        { bs3CpuInstr4_haddpd_XMM1_XMM1_icebp_c64,        255, RM_REG, T_SSE3,    1, 1, 1,   PASS_s_aValuesSR },
     5220        { bs3CpuInstr4_haddpd_XMM8_XMM8_icebp_c64,        255, RM_REG, T_SSE3,    8, 8, 8,   PASS_s_aValuesSR },
     5221        { bs3CpuInstr4_vhaddpd_YMM1_YMM1_YMM1_icebp_c64,  255, RM_REG, T_AVX_256, 1, 1, 1,   PASS_s_aValuesSR },
     5222        { bs3CpuInstr4_vhaddpd_YMM8_YMM8_YMM8_icebp_c64,  255, RM_REG, T_AVX_256, 8, 8, 8,   PASS_s_aValuesSR },
     5223        { bs3CpuInstr4_vhaddpd_YMM1_YMM1_YMM2_icebp_c64,  255, RM_REG, T_AVX_256, 1, 1, 2,   PASS_s_aValuesSR },
     5224        { bs3CpuInstr4_vhaddpd_YMM1_YMM1_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 1, 1, 255, PASS_s_aValuesSR },
    51495225    };
    51505226
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