Changeset 106473 in vbox for trunk/src/VBox/ValidationKit

Timestamp:

Oct 18, 2024 11:58:31 AM (3 months ago)

Author:

vboxsync

Message:

ValidationKit/bootsectors: fix my own bracing error somehow not yelled by scm; bugref:9898

File:

• trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32 (modified) (3 diffs)

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32

@@ -8867 +8867 @@
             /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) },  /* shift too far */
     };
-    static BS3CPUINSTR3_TEST1_T const s_aTests16[] = {
+    static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
+    {
         {  bs3CpuInstr3_pslldq_XMM1_000h_icebp_c16,       255, RM_REG, T_SSE2,     1, 1, 2, RT_ELEMENTS(s_aValuesX00), s_aValuesX00  },
         {  bs3CpuInstr3_pslldq_XMM1_005h_icebp_c16,       255, RM_REG, T_SSE2,     1, 1, 2, RT_ELEMENTS(s_aValuesL05), s_aValuesL05  },
@@ -8888 +8889 @@
         {  bs3CpuInstr3_vpsrldq_YMM1_YMM2_012h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValuesX12), s_aValuesX12  },
     };
-    static BS3CPUINSTR3_TEST1_T const s_aTests32[] = {
+    static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
+    {
         {  bs3CpuInstr3_pslldq_XMM1_000h_icebp_c32,       255, RM_REG, T_SSE2,     1, 1, 2, RT_ELEMENTS(s_aValuesX00), s_aValuesX00  },
         {  bs3CpuInstr3_pslldq_XMM1_005h_icebp_c32,       255, RM_REG, T_SSE2,     1, 1, 2, RT_ELEMENTS(s_aValuesL05), s_aValuesL05  },
@@ -8909 +8911 @@
         {  bs3CpuInstr3_vpsrldq_YMM1_YMM2_012h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValuesX12), s_aValuesX12  },
     };
-    static BS3CPUINSTR3_TEST1_T const s_aTests64[] = {
+    static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
+    {
         {  bs3CpuInstr3_pslldq_XMM1_000h_icebp_c64,       255, RM_REG, T_SSE2,     1, 1, 2, RT_ELEMENTS(s_aValuesX00), s_aValuesX00  },
         {  bs3CpuInstr3_pslldq_XMM1_005h_icebp_c64,       255, RM_REG, T_SSE2,     1, 1, 2, RT_ELEMENTS(s_aValuesL05), s_aValuesL05  },