Changeset 10661 in vbox

Timestamp:

Jul 15, 2008 2:21:04 PM (16 years ago)

Author:

vboxsync

Message:

Reduce the number of world switches caused by cr8 writes by checking if we really need to be notified. (only when
an interrupt is pending and masked by the TRP value)

Location:

trunk

Files:

• include/VBox/pdmapi.h (modified) (2 diffs)
• include/VBox/pdmdev.h (modified) (2 diffs)
• src/VBox/VMM/VMMAll/EMAll.cpp (modified) (1 diff)
• src/VBox/VMM/VMMAll/PDMAll.cpp (modified) (2 diffs)
• src/VBox/VMM/VMMR0/HWSVMR0.cpp (modified) (2 diffs)
• src/VBox/VMM/VMMR0/HWVMXR0.cpp (modified) (1 diff)

trunk/include/VBox/pdmapi.h

@@ -100 +100 @@
 
 /**
- * Set the TPR (task priority register?).
+ * Set the TPR (task priority register).
  *
  * @returns VBox status code.
@@ -109 +109 @@
 
 /**
- * Get the TPR (task priority register?).
+ * Get the TPR (task priority register).
  *
  * @returns The current TPR.
  * @param   pVM             VM handle.
  * @param   pu8TPR          Where to store the TRP.
- */
-PDMDECL(int) PDMApicGetTPR(PVM pVM, uint8_t *pu8TPR);
+ * @param   pfPending       Pending state (out).
+ */
+PDMDECL(int) PDMApicGetTPR(PVM pVM, uint8_t *pu8TPR, bool *pfPending);
 
 

trunk/include/VBox/pdmdev.h

@@ -968 +968 @@
 
     /**
-     * Set the TPR (task priority register?).
+     * Set the TPR (task priority register).
      *
      * @param   pDevIns         Device instance of the APIC.
@@ -976 +976 @@
 
     /**
-     * Get the TPR (task priority register?).
+     * Get the TPR (task priority register).
      *
      * @returns The current TPR.
      * @param   pDevIns         Device instance of the APIC.
+     * @param   pfPending       Pending interrupt state (out).
      */
     DECLR3CALLBACKMEMBER(uint8_t, pfnGetTPRHC,(PPDMDEVINS pDevIns));

trunk/src/VBox/VMM/VMMAll/EMAll.cpp

@@ -1726 +1726 @@
     {
         val64 = 0;
-        rc = PDMApicGetTPR(pVM, (uint8_t *)&val64);
+        rc = PDMApicGetTPR(pVM, (uint8_t *)&val64, NULL);
         AssertMsgRCReturn(rc, ("PDMApicGetTPR failed\n"), VERR_EM_INTERPRETER);
     }

trunk/src/VBox/VMM/VMMAll/PDMAll.cpp

@@ -230 +230 @@
 
 /**
- * Get the TPR (task priority register?).
+ * Get the TPR (task priority register).
  *
  * @returns The current TPR.
  * @param   pVM             VM handle.
  * @param   pu8TPR          Where to store the TRP.
- */
-PDMDECL(int) PDMApicGetTPR(PVM pVM, uint8_t *pu8TPR)
+ * @param   pfPending       Pending interrupt state (out).
+*/
+PDMDECL(int) PDMApicGetTPR(PVM pVM, uint8_t *pu8TPR, bool *pfPending)
 {
     if (pVM->pdm.s.Apic.CTXALLSUFF(pDevIns))
@@ -243 +244 @@
         pdmLock(pVM);
         *pu8TPR = pVM->pdm.s.Apic.CTXALLSUFF(pfnGetTPR)(pVM->pdm.s.Apic.CTXALLSUFF(pDevIns));
+        if (pfPending)
+            *pfPending = pVM->pdm.s.Apic.CTXALLSUFF(pfnHasPendingIrq)(pVM->pdm.s.Apic.CTXALLSUFF(pDevIns));
         pdmUnlock(pVM);
         return VINF_SUCCESS;

trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp

@@ -269 +269 @@
      */
     if (!pVM->hwaccm.s.fNestedPaging)
-        pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4) | RT_BIT(8);
+        pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4);
     else
         pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(4) | RT_BIT(8);
@@ -861 +861 @@
     if (pCtx->msrEFER & MSR_K6_EFER_LMA)
     {
+        bool fPending;
+
         /* TPR caching in CR8 */
-        int rc = PDMApicGetTPR(pVM, &u8LastVTPR);
+        int rc = PDMApicGetTPR(pVM, &u8LastVTPR, &fPending);
         AssertRC(rc);
         pVMCB->ctrl.IntCtrl.n.u8VTPR = u8LastVTPR;
+
+        if (fPending)
+        {
+            /* A TPR change could activate a pending interrupt, so catch cr8 writes. */
+            pVMCB->ctrl.u16InterceptWrCRx |= RT_BIT(8);
+        }
+        else
+            /* No interrupts are pending, so we don't need to be explicitely notified. 
+             * There are enough world switches for detecting pending interrupts.
+             */
+            pVMCB->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
     }
 

trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp

@@ -1182 +1182 @@
         /* TPR caching in CR8 */
         uint8_t u8TPR;
-        int rc = PDMApicGetTPR(pVM, &u8TPR);
+        bool    fPending;
+
+        int rc = PDMApicGetTPR(pVM, &u8TPR, &fPending);
         AssertRC(rc);
         /* The TPR can be found at offset 0x80 in the APIC mmio page. */
         pVM->hwaccm.s.vmx.pAPIC[0x80] = u8TPR << 4; /* bits 7-4 contain the task priority */
 
-        /* CR8 updates that lower the TPR value to below the current value should cause an exit. */
-        rc  = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, u8TPR);
+        /* Two options here:
+         * - external interrupt pending, but masked by the TPR value.
+         *   -> CR8 updates that lower the TPR value to below the current value should cause an exit
+         * - no pending interrupts
+         *   -> We don't need to be explicitely notified. There are enough world switches for detecting pending interrupts.
+         */
+        rc  = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, (fPending) ? u8TPR : 0);
         AssertRC(rc);
     }