Index: /trunk/include/VBox/dis-armv8.h
===================================================================
--- /trunk/include/VBox/dis-armv8.h	(revision 106615)
+++ /trunk/include/VBox/dis-armv8.h	(revision 106616)
@@ -59,5 +59,6 @@
     kDisOpParamArmV8RegType_Simd_Scalar_64Bit,
     kDisOpParamArmV8RegType_Simd_Scalar_128Bit,
-    kDisOpParamArmV8RegType_Simd_Vector
+    kDisOpParamArmV8RegType_Simd_Vector,
+    kDisOpParamArmV8RegType_Sp
 } DISOPPARAMARMV8REGTYPE;
 
@@ -69,5 +70,5 @@
     /** The register type (DISOPPARAMARMV8REGTYPE). */
     uint8_t  enmRegType;
-    /** The register ID. */
+    /** The register ID (not applicable for kDisOpParamArmV8RegType_Sp). */
     uint8_t  idReg;
 } DISOPPARAMARMV8REG;
Index: /trunk/src/VBox/Disassembler/DisasmCore-armv8.cpp
===================================================================
--- /trunk/src/VBox/Disassembler/DisasmCore-armv8.cpp	(revision 106615)
+++ /trunk/src/VBox/Disassembler/DisasmCore-armv8.cpp	(revision 106616)
@@ -79,6 +79,7 @@
 static FNDISPARSEARMV8 disArmV8ParseImmAdr;
 static FNDISPARSEARMV8 disArmV8ParseImmZero;
-static FNDISPARSEARMV8 disArmV8ParseReg;
-static FNDISPARSEARMV8 disArmV8ParseRegOff;
+static FNDISPARSEARMV8 disArmV8ParseGprZr;
+static FNDISPARSEARMV8 disArmV8ParseGprSp;
+static FNDISPARSEARMV8 disArmV8ParseGprOff;
 static FNDISPARSEARMV8 disArmV8ParseImmsImmrN;
 static FNDISPARSEARMV8 disArmV8ParseHw;
@@ -126,6 +127,7 @@
     disArmV8ParseImmAdr,
     disArmV8ParseImmZero,
-    disArmV8ParseReg,
-    disArmV8ParseRegOff,
+    disArmV8ParseGprZr,
+    disArmV8ParseGprSp,
+    disArmV8ParseGprOff,
     disArmV8ParseImmsImmrN,
     disArmV8ParseHw,
@@ -290,5 +292,5 @@
 
 
-static int disArmV8ParseReg(PDISSTATE pDis, uint32_t u32Insn, PCDISARMV8OPCODE pOp, PCDISARMV8INSNCLASS pInsnClass, PDISOPPARAM pParam, PCDISARMV8INSNPARAM pInsnParm, bool *pf64Bit)
+static int disArmV8ParseGprZr(PDISSTATE pDis, uint32_t u32Insn, PCDISARMV8OPCODE pOp, PCDISARMV8INSNCLASS pInsnClass, PDISOPPARAM pParam, PCDISARMV8INSNPARAM pInsnParm, bool *pf64Bit)
 {
     RT_NOREF(pDis, pOp, pInsnClass);
@@ -302,10 +304,24 @@
 
 
-static int disArmV8ParseRegOff(PDISSTATE pDis, uint32_t u32Insn, PCDISARMV8OPCODE pOp, PCDISARMV8INSNCLASS pInsnClass, PDISOPPARAM pParam, PCDISARMV8INSNPARAM pInsnParm, bool *pf64Bit)
+static int disArmV8ParseGprSp(PDISSTATE pDis, uint32_t u32Insn, PCDISARMV8OPCODE pOp, PCDISARMV8INSNCLASS pInsnClass, PDISOPPARAM pParam, PCDISARMV8INSNPARAM pInsnParm, bool *pf64Bit)
+{
+    RT_NOREF(pDis, pOp, pInsnClass);
+    pParam->armv8.Op.Reg.idReg = disArmV8ExtractBitVecFromInsn(u32Insn, pInsnParm->idxBitStart, pInsnParm->cBits);
+    if (pParam->armv8.Op.Reg.idReg == 31)
+        pParam->armv8.Op.Reg.enmRegType = kDisOpParamArmV8RegType_Sp;
+    else if (*pf64Bit || (pParam->armv8.enmType == kDisArmv8OpParmAddrInGpr))
+        pParam->armv8.Op.Reg.enmRegType = kDisOpParamArmV8RegType_Gpr_64Bit;
+    else
+        pParam->armv8.Op.Reg.enmRegType = kDisOpParamArmV8RegType_Gpr_32Bit;
+    return VINF_SUCCESS;
+}
+
+
+static int disArmV8ParseGprOff(PDISSTATE pDis, uint32_t u32Insn, PCDISARMV8OPCODE pOp, PCDISARMV8INSNCLASS pInsnClass, PDISOPPARAM pParam, PCDISARMV8INSNPARAM pInsnParm, bool *pf64Bit)
 {
     RT_NOREF(pDis, pOp, pInsnClass, pf64Bit);
-    pParam->armv8.GprIndex.idReg = disArmV8ExtractBitVecFromInsn(u32Insn, pInsnParm->idxBitStart, pInsnParm->cBits);
-    pParam->armv8.Op.Reg.enmRegType = kDisOpParamArmV8RegType_Gpr_64Bit; /* Might get overwritten later on. */
-    pParam->fUse                   |= DISUSE_INDEX;
+    pParam->armv8.GprIndex.idReg      = disArmV8ExtractBitVecFromInsn(u32Insn, pInsnParm->idxBitStart, pInsnParm->cBits);
+    pParam->armv8.GprIndex.enmRegType = kDisOpParamArmV8RegType_Gpr_64Bit; /* Might get overwritten later on. */
+    pParam->fUse                     |= DISUSE_INDEX;
     return VINF_SUCCESS;
 }
Index: /trunk/src/VBox/Disassembler/DisasmFormatArmV8.cpp
===================================================================
--- /trunk/src/VBox/Disassembler/DisasmFormatArmV8.cpp	(revision 106615)
+++ /trunk/src/VBox/Disassembler/DisasmFormatArmV8.cpp	(revision 106616)
@@ -401,4 +401,9 @@
             return psz;
         }
+        case kDisOpParamArmV8RegType_Sp:
+        {
+            *pcchReg = 2;
+            return "sp";
+        }
         default:
             AssertFailed();
Index: /trunk/src/VBox/Disassembler/DisasmInternal-armv8.h
===================================================================
--- /trunk/src/VBox/Disassembler/DisasmInternal-armv8.h	(revision 106615)
+++ /trunk/src/VBox/Disassembler/DisasmInternal-armv8.h	(revision 106616)
@@ -56,6 +56,7 @@
     kDisParmParseImmAdr,
     kDisParmParseImmZero,
-    kDisParmParseReg,
-    kDisParmParseRegOff,
+    kDisParmParseGprZr,
+    kDisParmParseGprSp,
+    kDisParmParseGprOff,
     kDisParmParseImmsImmrN,
     kDisParmParseHw,
Index: /trunk/src/VBox/Disassembler/DisasmTables-armv8-a64-simd-fp.cpp.h
===================================================================
--- /trunk/src/VBox/Disassembler/DisasmTables-armv8-a64-simd-fp.cpp.h	(revision 106615)
+++ /trunk/src/VBox/Disassembler/DisasmTables-armv8-a64-simd-fp.cpp.h	(revision 106616)
@@ -87,5 +87,5 @@
     DIS_ARMV8_INSN_DECODE(kDisParmParseFpType,         22,  2, DIS_ARMV8_INSN_PARAM_UNSET),
     DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg,           0,  5, 0 /*idxParam*/),
-    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,             5,  5, 1 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr,           5,  5, 1 /*idxParam*/),
     DIS_ARMV8_INSN_DECODE(kDisParmParseFpScale,        10,  6, 2 /*idxParam*/),
 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(DataProcFpFixedPConvGpr2FpReg, 0x7f3f0000 /*fFixedInsn*/, DISARMV8INSNCLASS_F_SF /*fClass*/,
@@ -111,5 +111,5 @@
 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(DataProcFpFixedPConvFpReg2Gpr)
     DIS_ARMV8_INSN_DECODE(kDisParmParseFpType,         22,  2, DIS_ARMV8_INSN_PARAM_UNSET),
-    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,             0,  5, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr,           0,  5, 0 /*idxParam*/),
     DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg,           5,  5, 1 /*idxParam*/),
     DIS_ARMV8_INSN_DECODE(kDisParmParseFpScale,        10,  6, 2 /*idxParam*/),
Index: /trunk/src/VBox/Disassembler/DisasmTables-armv8-a64.cpp
===================================================================
--- /trunk/src/VBox/Disassembler/DisasmTables-armv8-a64.cpp	(revision 106615)
+++ /trunk/src/VBox/Disassembler/DisasmTables-armv8-a64.cpp	(revision 106616)
@@ -76,5 +76,5 @@
     DIS_ARMV8_OP(0x90000000, "adrp" ,           OP_ARMV8_A64_ADRP,      DISOPTYPE_HARMLESS)
 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Adr)
-    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,    0, 5, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr,  0, 5, 0 /*idxParam*/),
     DIS_ARMV8_INSN_DECODE(kDisParmParseImmAdr, 0, 0, 1 /*idxParam*/),
 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(Adr, 0x9f000000 /*fFixedInsn*/, DISARMV8INSNCLASS_F_FORCED_64BIT,
@@ -90,8 +90,8 @@
     DIS_ARMV8_OP(0x71000000, "subs" ,           OP_ARMV8_A64_SUBS,      DISOPTYPE_HARMLESS),
 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(AddSubImm)
-    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,    0, 5, 0 /*idxParam*/),
-    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,    5, 5, 1 /*idxParam*/),
-    DIS_ARMV8_INSN_DECODE(kDisParmParseImm,  10, 12, 2 /*idxParam*/),
-    DIS_ARMV8_INSN_DECODE(kDisParmParseSh12, 22,  1, 2 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr,  0,  5, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp,  5,  5, 1 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseImm,   10, 12, 2 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseSh12,  22,  1, 2 /*idxParam*/),
 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(AddSubImm, 0x7f800000 /*fFixedInsn*/, DISARMV8INSNCLASS_F_SF,
                                                 kDisArmV8OpcDecodeNop, RT_BIT_32(29) | RT_BIT_32(30), 29,
@@ -106,7 +106,7 @@
     DIS_ARMV8_OP(0x6b000000, "subs" ,           OP_ARMV8_A64_SUBS,      DISOPTYPE_HARMLESS),
 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(AddSubShiftReg)
-    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,            0,  5, 0 /*idxParam*/),
-    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,            5,  5, 1 /*idxParam*/),
-    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,           16,  5, 2 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr,          0,  5, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr,          5,  5, 1 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr,         16,  5, 2 /*idxParam*/),
     DIS_ARMV8_INSN_DECODE(kDisParmParseShift,         22,  2, 2 /*idxParam*/),
     DIS_ARMV8_INSN_DECODE(kDisParmParseShiftAmount,   10,  6, 2 /*idxParam*/),
@@ -123,6 +123,6 @@
     DIS_ARMV8_OP(0x72000000, "ands" ,           OP_ARMV8_A64_ANDS,      DISOPTYPE_HARMLESS),
 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LogicalImm)
-    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,            0,  5, 0 /*idxParam*/),
-    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,            5,  5, 1 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp,          0,  5, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr,          5,  5, 1 /*idxParam*/),
     DIS_ARMV8_INSN_DECODE(kDisParmParseImmsImmrN,     10, 13, 2 /*idxParam*/),
 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(LogicalImm, 0x7f800000 /*fFixedInsn*/, DISARMV8INSNCLASS_F_SF,
@@ -138,5 +138,5 @@
     DIS_ARMV8_OP(0x72800000, "movk" ,           OP_ARMV8_A64_MOVK,      DISOPTYPE_HARMLESS),
 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(MoveWide)
-    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,            0,  5, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr,          0,  5, 0 /*idxParam*/),
     DIS_ARMV8_INSN_DECODE(kDisParmParseImm,            5, 16, 1 /*idxParam*/),
     DIS_ARMV8_INSN_DECODE(kDisParmParseHw,            21,  2, 1 /*idxParam*/),
@@ -153,6 +153,6 @@
     INVALID_OPCODE,
 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Bitfield)
-    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,            0,  5, 0 /*idxParam*/),
-    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,            5,  5, 1 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr,          0,  5, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr,          5,  5, 1 /*idxParam*/),
     DIS_ARMV8_INSN_DECODE(kDisParmParseImm,           16,  6, 2 /*idxParam*/),
     DIS_ARMV8_INSN_DECODE(kDisParmParseImm,           10,  6, 3 /*idxParam*/),
@@ -223,5 +223,5 @@
     DIS_ARMV8_OP(0x54000010, "wfit" ,           OP_ARMV8_A64_WFIT,      DISOPTYPE_HARMLESS), /* FEAT_WFxT */
 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(SysReg)
-    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,            0,  5, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr,          0,  5, 0 /*idxParam*/),
 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_1(SysReg, 0xffffffe0 /*fFixedInsn*/, DISARMV8INSNCLASS_F_FORCED_64BIT,
                                                 kDisArmV8OpcDecodeNop, 0xfe0, 5,
@@ -289,5 +289,5 @@
     DIS_ARMV8_OP(0xd5233160, "ttest",           OP_ARMV8_A64_TTEST,     DISOPTYPE_HARMLESS),                         /* FEAT_TME */
 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(SysResult)
-    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,            0,  5, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr,          0,  5, 0 /*idxParam*/),
 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_1(SysResult, 0xfffffffe /*fFixedInsn*/, DISARMV8INSNCLASS_F_FORCED_64BIT,
                                                 kDisArmV8OpcDecodeNop, RT_BIT_32(8) | RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11), 8,
@@ -302,5 +302,5 @@
     DIS_ARMV8_INSN_DECODE(kDisParmParseCRnCRm,         8,  8, 1 /*idxParam*/),
     DIS_ARMV8_INSN_DECODE(kDisParmParseImm,            5,  3, 2 /*idxParam*/),
-    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,            0,  5, 3 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr,          0,  5, 3 /*idxParam*/),
 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_0(Sys, 0xfff80000 /*fFixedInsn*/, DISARMV8INSNCLASS_F_FORCED_64BIT,
                                                 kDisArmV8OpcDecodeNop, 0, 0); /** @todo */
@@ -311,5 +311,5 @@
     DIS_ARMV8_OP(0xd5280000, "sysl",            OP_ARMV8_A64_SYSL,      DISOPTYPE_HARMLESS),
 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(SysL)
-    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,            0,  5, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr,          0,  5, 0 /*idxParam*/),
     DIS_ARMV8_INSN_DECODE(kDisParmParseImm,           16,  3, 1 /*idxParam*/),
     DIS_ARMV8_INSN_DECODE(kDisParmParseCRnCRm,         8,  8, 2 /*idxParam*/),
@@ -324,5 +324,5 @@
 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Msr)
     DIS_ARMV8_INSN_DECODE(kDisParmParseSysReg,         5, 15, 0 /*idxParam*/),
-    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,            0,  5, 1 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr,          0,  5, 1 /*idxParam*/),
 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(Msr, 0xfff00000 /*fFixedInsn*/, DISARMV8INSNCLASS_F_FORCED_64BIT,
                                                 kDisArmV8OpcDecodeNop, 0, 0,
@@ -334,5 +334,5 @@
     DIS_ARMV8_OP(0xd5300000, "mrs",             OP_ARMV8_A64_MRS,       DISOPTYPE_HARMLESS | DISOPTYPE_PRIVILEGED),
 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Mrs)
-    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,            0,  5, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr,          0,  5, 0 /*idxParam*/),
     DIS_ARMV8_INSN_DECODE(kDisParmParseSysReg,         5, 15, 1 /*idxParam*/),
 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(Mrs, 0xfff00000 /*fFixedInsn*/, DISARMV8INSNCLASS_F_FORCED_64BIT,
@@ -350,5 +350,5 @@
     DIS_ARMV8_OP(0xd65f0c00, "retab",          OP_ARMV8_A64_RETAB,      DISOPTYPE_HARMLESS | DISOPTYPE_CONTROLFLOW),
 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(BrBlrRet)
-    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,            5,  5, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr,          5,  5, 0 /*idxParam*/),
 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_1(BrBlrRet, 0xfffffc1f /*fFixedInsn*/, DISARMV8INSNCLASS_F_FORCED_64BIT,
                                                 kDisArmV8OpcDecodeLookup, 0xfffffc1f, 0,
@@ -393,5 +393,5 @@
     DIS_ARMV8_OP(0x35000000, "cbnz",            OP_ARMV8_A64_CBNZ,      DISOPTYPE_HARMLESS | DISOPTYPE_CONTROLFLOW),
 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(CmpBrImm)
-    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,            0,  5, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr,          0,  5, 0 /*idxParam*/),
     DIS_ARMV8_INSN_DECODE(kDisParmParseImmRel,         5, 19, 1 /*idxParam*/),
 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(CmpBrImm, 0x7f000000 /*fFixedInsn*/, DISARMV8INSNCLASS_F_SF,
@@ -405,5 +405,5 @@
     DIS_ARMV8_OP(0x37000000, "tbnz",            OP_ARMV8_A64_TBNZ,      DISOPTYPE_HARMLESS | DISOPTYPE_CONTROLFLOW),
 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(TestBrImm)
-    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,            0,  5, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr,          0,  5, 0 /*idxParam*/),
     DIS_ARMV8_INSN_DECODE(kDisParmParseImmTbz,         0,  0, 1 /*idxParam*/), /* Hardcoded bit offsets in parser. */
     DIS_ARMV8_INSN_DECODE(kDisParmParseImmRel,         5, 14, 2 /*idxParam*/),
@@ -439,7 +439,7 @@
     DIS_ARMV8_OP(0x6a000000, "ands",            OP_ARMV8_A64_ANDS,      DISOPTYPE_HARMLESS)
 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LogShiftRegN0)
-    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,            0,  5, 0 /*idxParam*/),
-    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,            5,  5, 1 /*idxParam*/),
-    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,           16,  5, 2 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr,          0,  5, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr,          5,  5, 1 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr,         16,  5, 2 /*idxParam*/),
     DIS_ARMV8_INSN_DECODE(kDisParmParseShift,         22,  2, 2 /*idxParam*/),
     DIS_ARMV8_INSN_DECODE(kDisParmParseShiftAmount,   10,  6, 2 /*idxParam*/),
@@ -456,7 +456,7 @@
     DIS_ARMV8_OP(0x6a200000, "bics",            OP_ARMV8_A64_BICS,      DISOPTYPE_HARMLESS)
 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LogShiftRegN1)
-    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,            0,  5, 0 /*idxParam*/),
-    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,            5,  5, 1 /*idxParam*/),
-    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,           16,  5, 2 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr,          0,  5, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr,          5,  5, 1 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr,         16,  5, 2 /*idxParam*/),
     DIS_ARMV8_INSN_DECODE(kDisParmParseShift,         22,  2, 2 /*idxParam*/),
     DIS_ARMV8_INSN_DECODE(kDisParmParseShiftAmount,   10,  6, 2 /*idxParam*/),
@@ -494,6 +494,6 @@
     DIS_ARMV8_OP(0x7a400000, "ccmp",            OP_ARMV8_A64_CCMP,      DISOPTYPE_HARMLESS)
 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(CondCmpReg)
-    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,            5,  5, 0 /*idxParam*/),
-    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,           16,  5, 1 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr,          5,  5, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr,         16,  5, 1 /*idxParam*/),
     DIS_ARMV8_INSN_DECODE(kDisParmParseImm,            0,  4, 2 /*idxParam*/),
     DIS_ARMV8_INSN_DECODE(kDisParmParseCond,          12,  4, 3 /*idxParam*/),
@@ -576,6 +576,6 @@
 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegUImmGpr)
     DIS_ARMV8_INSN_DECODE(kDisParmParseSize,          30,  2, DIS_ARMV8_INSN_PARAM_UNSET),
-    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,            0,  5, 0 /*idxParam*/),
-    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,            5,  5, 1 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr,          0,  5, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp,          5,  5, 1 /*idxParam*/),
     DIS_ARMV8_INSN_DECODE(kDisParmParseImmMemOff,     10, 12, 1 /*idxParam*/),
 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(LdStRegUImmGpr, 0xffc00000 /*fFixedInsn*/, 0 /*fClass*/,
@@ -625,7 +625,7 @@
 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegOffGpr)
     DIS_ARMV8_INSN_DECODE(kDisParmParseSize,          30,  2, DIS_ARMV8_INSN_PARAM_UNSET),
-    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,            0,  5, 0 /*idxParam*/),
-    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,            5,  5, 1 /*idxParam*/),
-    DIS_ARMV8_INSN_DECODE(kDisParmParseRegOff,        16,  5, 1 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr,          0,  5, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp,          5,  5, 1 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprOff,        16,  5, 1 /*idxParam*/),
     DIS_ARMV8_INSN_DECODE(kDisParmParseOption,        13,  3, 1 /*idxParam*/),
     DIS_ARMV8_INSN_DECODE(kDisParmParseS,             12,  1, 1 /*idxParam*/),
@@ -696,6 +696,6 @@
 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegUnscaledImmGpr)
     DIS_ARMV8_INSN_DECODE(kDisParmParseSize,               30,  2, DIS_ARMV8_INSN_PARAM_UNSET),
-    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,                 0,  5, 0 /*idxParam*/),
-    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,                 5,  5, 1 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr,               0,  5, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp,               5,  5, 1 /*idxParam*/),
     DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOffUnscaled, 12,  9, 1 /*idxParam*/),
 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(LdStRegUnscaledImmGpr, 0xffe00c00 /*fFixedInsn*/, 0 /*fClass*/,
@@ -788,7 +788,7 @@
     INVALID_OPCODE,
 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegPairOff)
-    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,            0,  5, 0 /*idxParam*/),
-    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,           10,  5, 1 /*idxParam*/),
-    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,            5,  5, 2 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr,          0,  5, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr,         10,  5, 1 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp,          5,  5, 2 /*idxParam*/),
     DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOff,    15,  7, 2 /*idxParam*/),
 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(LdStRegPairOff, 0xffc00000 /*fFixedInsn*/, 0 /*fClass*/,
@@ -813,7 +813,7 @@
     INVALID_OPCODE,
 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegPairPreIndex)
-    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,            0,  5, 0 /*idxParam*/),
-    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,           10,  5, 1 /*idxParam*/),
-    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,            5,  5, 2 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr,          0,  5, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr,         10,  5, 1 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp,          5,  5, 2 /*idxParam*/),
     DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOff,    15,  7, 2 /*idxParam*/),
     DIS_ARMV8_INSN_DECODE(kDisParmParseSetPreIndexed,  0,  0, 2 /*idxParam*/),
@@ -839,7 +839,7 @@
     INVALID_OPCODE,
 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegPairPostIndex)
-    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,             0,  5, 0 /*idxParam*/),
-    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,            10,  5, 1 /*idxParam*/),
-    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,             5,  5, 2 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr,           0,  5, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr,          10,  5, 1 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp,           5,  5, 2 /*idxParam*/),
     DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOff,     15,  7, 2 /*idxParam*/),
     DIS_ARMV8_INSN_DECODE(kDisParmParseSetPostIndexed,  0,  0, 2 /*idxParam*/),
Index: /trunk/src/VBox/Disassembler/testcase/tstDisasmArmv8-1-asm.S
===================================================================
--- /trunk/src/VBox/Disassembler/testcase/tstDisasmArmv8-1-asm.S	(revision 106615)
+++ /trunk/src/VBox/Disassembler/testcase/tstDisasmArmv8-1-asm.S	(revision 106616)
@@ -303,4 +303,14 @@
         bic  w0, w1, w28, ROR #31
 
+        bic  wzr, wzr, wzr
+        bic  wzr, wzr, wzr, LSL #1
+        bic  wzr, wzr, wzr, LSL #31
+        bic  wzr, wzr, wzr, LSR #1
+        bic  wzr, wzr, wzr, LSR #31
+        bic  wzr, wzr, wzr, ASR #1
+        bic  wzr, wzr, wzr, ASR #31
+        bic  wzr, wzr, wzr, ROR #1
+        bic  wzr, wzr, wzr, ROR #31
+
         bic  x0, x0, x27
         bic  x0, x1, x28, LSL #1
@@ -313,4 +323,14 @@
         bic  x0, x1, x28, ROR #63
 
+        bic  xzr, xzr, xzr
+        bic  xzr, xzr, xzr, LSL #1
+        bic  xzr, xzr, xzr, LSL #63
+        bic  xzr, xzr, xzr, LSR #1
+        bic  xzr, xzr, xzr, LSR #63
+        bic  xzr, xzr, xzr, ASR #1
+        bic  xzr, xzr, xzr, ASR #63
+        bic  xzr, xzr, xzr, ROR #1
+        bic  xzr, xzr, xzr, ROR #63
+
         orn  w0, w0, w27
         orn  w0, w1, w28, LSL #1
@@ -323,4 +343,14 @@
         orn  w0, w1, w28, ROR #31
 
+        orn  wzr, wzr, wzr
+        orn  wzr, wzr, wzr, LSL #1
+        orn  wzr, wzr, wzr, LSL #31
+        orn  wzr, wzr, wzr, LSR #1
+        orn  wzr, wzr, wzr, LSR #31
+        orn  wzr, wzr, wzr, ASR #1
+        orn  wzr, wzr, wzr, ASR #31
+        orn  wzr, wzr, wzr, ROR #1
+        orn  wzr, wzr, wzr, ROR #31
+
         orn  x0, x0, x27
         orn  x0, x1, x28, LSL #1
@@ -333,4 +363,14 @@
         orn  x0, x1, x28, ROR #63
 
+        orn  xzr, xzr, xzr
+        orn  xzr, xzr, xzr, LSL #1
+        orn  xzr, xzr, xzr, LSL #63
+        orn  xzr, xzr, xzr, LSR #1
+        orn  xzr, xzr, xzr, LSR #63
+        orn  xzr, xzr, xzr, ASR #1
+        orn  xzr, xzr, xzr, ASR #63
+        orn  xzr, xzr, xzr, ROR #1
+        orn  xzr, xzr, xzr, ROR #63
+
         eon  w0, w0, w27
         eon  w0, w1, w28, LSL #1
@@ -343,4 +383,14 @@
         eon  w0, w1, w28, ROR #31
 
+        eon  wzr, wzr, wzr
+        eon  wzr, wzr, wzr, LSL #1
+        eon  wzr, wzr, wzr, LSL #31
+        eon  wzr, wzr, wzr, LSR #1
+        eon  wzr, wzr, wzr, LSR #31
+        eon  wzr, wzr, wzr, ASR #1
+        eon  wzr, wzr, wzr, ASR #31
+        eon  wzr, wzr, wzr, ROR #1
+        eon  wzr, wzr, wzr, ROR #31
+
         eon  x0, x0, x27
         eon  x0, x1, x28, LSL #1
@@ -353,4 +403,14 @@
         eon  x0, x1, x28, ROR #63
 
+        eon  xzr, xzr, xzr
+        eon  xzr, xzr, xzr, LSL #1
+        eon  xzr, xzr, xzr, LSL #63
+        eon  xzr, xzr, xzr, LSR #1
+        eon  xzr, xzr, xzr, LSR #63
+        eon  xzr, xzr, xzr, ASR #1
+        eon  xzr, xzr, xzr, ASR #63
+        eon  xzr, xzr, xzr, ROR #1
+        eon  xzr, xzr, xzr, ROR #63
+
         bics w0, w0, w27
         bics w0, w1, w28, LSL #1
@@ -363,4 +423,14 @@
         bics w0, w1, w28, ROR #31
 
+        bics wzr, wzr, wzr
+        bics wzr, wzr, wzr, LSL #1
+        bics wzr, wzr, wzr, LSL #31
+        bics wzr, wzr, wzr, LSR #1
+        bics wzr, wzr, wzr, LSR #31
+        bics wzr, wzr, wzr, ASR #1
+        bics wzr, wzr, wzr, ASR #31
+        bics wzr, wzr, wzr, ROR #1
+        bics wzr, wzr, wzr, ROR #31
+
         bics x0, x0, x27
         bics x0, x1, x28, LSL #1
@@ -373,4 +443,14 @@
         bics x0, x1, x28, ROR #63
 
+        bics xzr, xzr, xzr
+        bics xzr, xzr, xzr, LSL #1
+        bics xzr, xzr, xzr, LSL #63
+        bics xzr, xzr, xzr, LSR #1
+        bics xzr, xzr, xzr, LSR #63
+        bics xzr, xzr, xzr, ASR #1
+        bics xzr, xzr, xzr, ASR #63
+        bics xzr, xzr, xzr, ROR #1
+        bics xzr, xzr, xzr, ROR #63
+
         ; Memory loads
         ldrb w0, [x28]
@@ -378,71 +458,143 @@
         ldrb w0, [x28, #4095]
 
+        ldrb w0, [sp]
+        ldrb w0, [sp, #1]
+        ldrb w0, [sp, #4095]
+
         ldrsb w0, [x28]
         ldrsb w0, [x28, #1]
         ldrsb w0, [x28, #4095]
 
+        ldrsb w0, [sp]
+        ldrsb w0, [sp, #1]
+        ldrsb w0, [sp, #4095]
+
         ldrsb x0, [x28]
         ldrsb x0, [x28, #1]
         ldrsb x0, [x28, #4095]
 
+        ldrsb x0, [sp]
+        ldrsb x0, [sp, #1]
+        ldrsb x0, [sp, #4095]
+
         ldrh w0, [x28]
         ldrh w0, [x28, #2]
         ldrh w0, [x28, #1024]
 
+        ldrh w0, [sp]
+        ldrh w0, [sp, #2]
+        ldrh w0, [sp, #1024]
+
         ldrsh w0, [x28]
         ldrsh w0, [x28, #2]
         ldrsh w0, [x28, #1024]
 
+        ldrsh w0, [sp]
+        ldrsh w0, [sp, #2]
+        ldrsh w0, [sp, #1024]
+
         ldrsh x0, [x28]
         ldrsh x0, [x28, #2]
         ldrsh x0, [x28, #1024]
 
+        ldrsh x0, [sp]
+        ldrsh x0, [sp, #2]
+        ldrsh x0, [sp, #1024]
+
         ldr x0, [x28]
         ldr x0, [x28, #8]
         ldr x0, [x28, #32760]
 
+        ldr x0, [sp]
+        ldr x0, [sp, #8]
+        ldr x0, [sp, #32760]
+
         ldr w0, [x28]
         ldr w0, [x28, #4]
         ldr w0, [x28, #16380]
 
+        ldr w0, [sp]
+        ldr w0, [sp, #4]
+        ldr w0, [sp, #16380]
+
         ldrsw x0, [x28]
         ldrsw x0, [x28, #4]
         ldrsw x0, [x28, #16380]
 
+        ldrsw x0, [sp]
+        ldrsw x0, [sp, #4]
+        ldrsw x0, [sp, #16380]
+
         ldurb w0, [x28]
         ldurb w0, [x28, #-256]
         ldurb w0, [x28, #255]
 
+        ldurb w0, [sp]
+        ldurb w0, [sp, #-256]
+        ldurb w0, [sp, #255]
+
         ldursb w0, [x28]
         ldursb w0, [x28, #-256]
         ldursb w0, [x28, #255]
 
+        ldursb w0, [sp]
+        ldursb w0, [sp, #-256]
+        ldursb w0, [sp, #255]
+
         ldursb x0, [x28]
         ldursb x0, [x28, #-256]
         ldursb x0, [x28, #255]
 
+        ldursb x0, [sp]
+        ldursb x0, [sp, #-256]
+        ldursb x0, [sp, #255]
+
         ldurh w0, [x28]
         ldurh w0, [x28, #-256]
         ldurh w0, [x28, #255]
 
+        ldurh w0, [sp]
+        ldurh w0, [sp, #-256]
+        ldurh w0, [sp, #255]
+
         ldursh w0, [x28]
         ldursh w0, [x28, #-256]
         ldursh w0, [x28, #255]
 
+        ldursh w0, [sp]
+        ldursh w0, [sp, #-256]
+        ldursh w0, [sp, #255]
+
         ldursh x0, [x28]
         ldursh x0, [x28, #-256]
         ldursh x0, [x28, #255]
 
+        ldursh x0, [sp]
+        ldursh x0, [sp, #-256]
+        ldursh x0, [sp, #255]
+
         ldur x0, [x28]
         ldur x0, [x28, #-256]
         ldur x0, [x28, #255]
 
+        ldur x0, [sp]
+        ldur x0, [sp, #-256]
+        ldur x0, [sp, #255]
+
         ldur w0, [x28]
         ldur w0, [x28, #-256]
         ldur w0, [x28, #255]
 
+        ldur w0, [sp]
+        ldur w0, [sp, #-256]
+        ldur w0, [sp, #255]
+
         ldursw x0, [x28]
         ldursw x0, [x28, #-256]
         ldursw x0, [x28, #255]
+
+        ldursw x0, [sp]
+        ldursw x0, [sp, #-256]
+        ldursw x0, [sp, #255]
 
         ldp w0, w1, [x28]
@@ -451,4 +603,9 @@
         ldp w0, w1, [x28, #252]
 
+        ldp w0, w1, [sp]
+        ldp w0, w1, [sp, #4]
+        ldp w0, w1, [sp, #-256]
+        ldp w0, w1, [sp, #252]
+
         ldp x0, x1, [x28]
         ldp x0, x1, [x28, #8]
@@ -456,19 +613,40 @@
         ldp x0, x1, [x28, #504]
 
+        ldp x0, x1, [sp]
+        ldp x0, x1, [sp, #8]
+        ldp x0, x1, [sp, #-512]
+        ldp x0, x1, [sp, #504]
+
         ldp w0, w1, [x28, #4]!
         ldp w0, w1, [x28, #-256]!
         ldp w0, w1, [x28, #252]!
 
+        ldp w0, w1, [sp, #4]!
+        ldp w0, w1, [sp, #-256]!
+        ldp w0, w1, [sp, #252]!
+
         ldp x0, x1, [x28, #8]!
         ldp x0, x1, [x28, #-512]!
         ldp x0, x1, [x28, #504]!
 
+        ldp x0, x1, [sp, #8]!
+        ldp x0, x1, [sp, #-512]!
+        ldp x0, x1, [sp, #504]!
+
         ldp w0, w1, [x28], #4
         ldp w0, w1, [x28], #-256
         ldp w0, w1, [x28], #252
 
+        ldp w0, w1, [sp], #4
+        ldp w0, w1, [sp], #-256
+        ldp w0, w1, [sp], #252
+
         ldp x0, x1, [x28], #8
         ldp x0, x1, [x28], #-512
         ldp x0, x1, [x28], #504
+
+        ldp x0, x1, [sp], #8
+        ldp x0, x1, [sp], #-512
+        ldp x0, x1, [sp], #504
 
         ldr  x0, [x1, x2]
@@ -482,4 +660,14 @@
         ldr  w0, [x1, w2, SXTW #2]
 
+        ldr  x0, [sp, x2]
+        ldr  w0, [sp, x2]
+        ldr  x0, [sp, x2, SXTX #0]
+        ldr  x0, [sp, x2, LSL  #3]  ; UXTX
+        ldr  x0, [sp, x2, SXTX #3]
+        ldr  w0, [sp, w2, UXTW #0]
+        ldr  w0, [sp, w2, SXTW #0]
+        ldr  w0, [sp, w2, UXTW #2]
+        ldr  w0, [sp, w2, SXTW #2]
+
         ldrb w0, [x1, x2]
         ldrb w0, [x1, x2, LSL  #0]  ; UXTX
@@ -488,4 +676,10 @@
         ldrb w0, [x1, w2, SXTW #0]
 
+        ldrb w0, [sp, x2]
+        ldrb w0, [sp, x2, LSL  #0]  ; UXTX
+        ldrb w0, [sp, x2, SXTX #0]
+        ldrb w0, [sp, w2, UXTW #0]
+        ldrb w0, [sp, w2, SXTW #0]
+
         ldrsb w0, [x1, x2]
         ldrsb w0, [x1, x2, LSL  #0] ; UXTX
@@ -493,4 +687,10 @@
         ldrsb w0, [x1, w2, UXTW #0]
         ldrsb w0, [x1, w2, SXTW #0]
+
+        ldrsb w0, [sp, x2]
+        ldrsb w0, [sp, x2, LSL  #0] ; UXTX
+        ldrsb w0, [sp, x2, SXTX #0]
+        ldrsb w0, [sp, w2, UXTW #0]
+        ldrsb w0, [sp, w2, SXTW #0]
 
         ldrh w0, [x1, x2]
@@ -504,4 +704,14 @@
         ldrh w0, [x1, w2, SXTW #1]
 
+        ldrh w0, [sp, x2]
+        ;ldrh w0, [sp, x2, LSL  #0]  ; UXTX
+        ldrh w0, [sp, x2, SXTX #0]
+        ldrh w0, [sp, x2, LSL  #1]   ; UXTX
+        ldrh w0, [sp, x2, SXTX #1]
+        ldrh w0, [sp, w2, UXTW #0]
+        ldrh w0, [sp, w2, SXTW #0]
+        ldrh w0, [sp, w2, UXTW #1]
+        ldrh w0, [sp, w2, SXTW #1]
+
         ldrsh w0, [x1, x2]
         ;ldrsh w0, [x1, x2, LSL  #0] ; UXTX
@@ -514,4 +724,14 @@
         ldrsh w0, [x1, w2, SXTW #1]
 
+        ldrsh w0, [sp, x2]
+        ;ldrsh w0, [sp, x2, LSL  #0] ; UXTX
+        ldrsh w0, [sp, x2, SXTX #0]
+        ldrsh w0, [sp, x2, LSL  #1]   ; UXTX
+        ldrsh w0, [sp, x2, SXTX #1]
+        ldrsh w0, [sp, w2, UXTW #0]
+        ldrsh w0, [sp, w2, SXTW #0]
+        ldrsh w0, [sp, w2, UXTW #1]
+        ldrsh w0, [sp, w2, SXTW #1]
+
         ldrsw x0, [x1, x2]
         ;ldrsw x0, [x1, x2, LSL  #0] ; UXTX
@@ -524,4 +744,14 @@
         ldrsw x0, [x1, w2, SXTW #2]
 
+        ldrsw x0, [sp, x2]
+        ;ldrsw x0, [sp, x2, LSL  #0] ; UXTX
+        ldrsw x0, [sp, x2, SXTX #0]
+        ldrsw x0, [sp, x2, LSL  #2]  ; UXTX
+        ldrsw x0, [sp, x2, SXTX #2]
+        ldrsw x0, [sp, w2, UXTW #0]
+        ldrsw x0, [sp, w2, SXTW #0]
+        ldrsw x0, [sp, w2, UXTW #2]
+        ldrsw x0, [sp, w2, SXTW #2]
+
         ; Memory stores
         strb w0, [x28]
@@ -529,16 +759,31 @@
         strb w0, [x28, #4095]
 
+        strb w0, [sp]
+        strb w0, [sp, #1]
+        strb w0, [sp, #4095]
+
         strh w0, [x28]
         strh w0, [x28, #2]
         strh w0, [x28, #1024]
 
+        strh w0, [sp]
+        strh w0, [sp, #2]
+        strh w0, [sp, #1024]
+
         str x0, [x28]
         str x0, [x28, #8]
         str x0, [x28, #32760]
 
+        str x0, [sp]
+        str x0, [sp, #8]
+        str x0, [sp, #32760]
+
         str w0, [x28]
         str w0, [x28, #4]
         str w0, [x28, #16380]
 
+        str w0, [sp]
+        str w0, [sp, #4]
+        str w0, [sp, #16380]
 
         sturb w0, [x28]
@@ -546,15 +791,31 @@
         sturb w0, [x28, #255]
 
+        sturb w0, [sp]
+        sturb w0, [sp, #-256]
+        sturb w0, [sp, #255]
+
         sturh w0, [x28]
         sturh w0, [x28, #-256]
         sturh w0, [x28, #255]
 
+        sturh w0, [sp]
+        sturh w0, [sp, #-256]
+        sturh w0, [sp, #255]
+
         stur x0, [x28]
         stur x0, [x28, #-256]
         stur x0, [x28, #255]
 
+        stur x0, [sp]
+        stur x0, [sp, #-256]
+        stur x0, [sp, #255]
+
         stur w0, [x28]
         stur w0, [x28, #-256]
         stur w0, [x28, #255]
+
+        stur w0, [sp]
+        stur w0, [sp, #-256]
+        stur w0, [sp, #255]
 
         stp w0, w1, [x28]
@@ -563,4 +824,9 @@
         stp w0, w1, [x28, #252]
 
+        stp w0, w1, [sp]
+        stp w0, w1, [sp, #4]
+        stp w0, w1, [sp, #-256]
+        stp w0, w1, [sp, #252]
+
         stp x0, x1, [x28]
         stp x0, x1, [x28, #8]
@@ -568,19 +834,40 @@
         stp x0, x1, [x28, #504]
 
+        stp x0, x1, [sp]
+        stp x0, x1, [sp, #8]
+        stp x0, x1, [sp, #-512]
+        stp x0, x1, [sp, #504]
+
         stp w0, w1, [x28, #4]!
         stp w0, w1, [x28, #-256]!
         stp w0, w1, [x28, #252]!
 
+        stp w0, w1, [sp, #4]!
+        stp w0, w1, [sp, #-256]!
+        stp w0, w1, [sp, #252]!
+
         stp x0, x1, [x28, #8]!
         stp x0, x1, [x28, #-512]!
         stp x0, x1, [x28, #504]!
 
+        stp x0, x1, [sp, #8]!
+        stp x0, x1, [sp, #-512]!
+        stp x0, x1, [sp, #504]!
+
         stp w0, w1, [x28], #4
         stp w0, w1, [x28], #-256
         stp w0, w1, [x28], #252
 
+        stp w0, w1, [sp], #4
+        stp w0, w1, [sp], #-256
+        stp w0, w1, [sp], #252
+
         stp x0, x1, [x28], #8
         stp x0, x1, [x28], #-512
         stp x0, x1, [x28], #504
+
+        stp x0, x1, [sp], #8
+        stp x0, x1, [sp], #-512
+        stp x0, x1, [sp], #504
 
         str  x0, [x1, x2]
@@ -594,4 +881,14 @@
         str  w0, [x1, w2, SXTW #2]
 
+        str  x0, [sp, x2]
+        str  w0, [sp, x2]
+        str  x0, [sp, x2, SXTX #0]
+        str  x0, [sp, x2, LSL  #3]  ; UXTX
+        str  x0, [sp, x2, SXTX #3]
+        str  w0, [sp, w2, UXTW #0]
+        str  w0, [sp, w2, SXTW #0]
+        str  w0, [sp, w2, UXTW #2]
+        str  w0, [sp, w2, SXTW #2]
+
         strb w0, [x1, x2]
         strb w0, [x1, x2, LSL  #0x0]
@@ -599,4 +896,10 @@
         strb w0, [x1, w2, UXTW #0x0]
         strb w0, [x1, w2, SXTW #0x0]
+
+        strb w0, [sp, x2]
+        strb w0, [sp, x2, LSL  #0x0]
+        strb w0, [sp, x2, SXTX #0x0]
+        strb w0, [sp, w2, UXTW #0x0]
+        strb w0, [sp, w2, SXTW #0x0]
 
         strh w0, [x1, x2]
@@ -609,4 +912,14 @@
         strh w0, [x1, w2, UXTW #1]
         strh w0, [x1, w2, SXTW #1]
+
+        strh w0, [sp, x2]
+        ;strh w0, [sp, x2, LSL  #0x0] ; UXTX
+        strh w0, [sp, x2, SXTX #0x0]
+        strh w0, [sp, x2, LSL  #1]   ; UXTX
+        strh w0, [sp, x2, SXTX #1]
+        strh w0, [sp, w2, UXTW #0x0]
+        strh w0, [sp, w2, SXTW #0x0]
+        strh w0, [sp, w2, UXTW #1]
+        strh w0, [sp, w2, SXTW #1]
 
         ; Conditional compare
@@ -939,4 +1252,21 @@
         ;sqrshrn q0, q1, #64
 
+        dsb #0
+        dsb #1
+        dsb #2
+        dsb #3
+        dsb #4
+        dsb #5
+        dsb #6
+        dsb #7
+        dsb #8
+        dsb #9
+        dsb #0xa
+        dsb #0xb
+        dsb #0xc
+        dsb #0xd
+        dsb #0xe
+        dsb #0xf
+
         ;
         ; Keep last so the testcase can catch errors in
