Changeset 106631 in vbox

Timestamp:

Oct 23, 2024 5:45:19 PM (5 weeks ago)

Author:

vboxsync

Message:

Disassembler: Decode data processing 1-source instructions, bugref:10394

Location:

trunk

Files:

• include/VBox/disopcode-armv8.h (modified) (3 diffs)
• src/VBox/Disassembler/DisasmTables-armv8-a64.cpp (modified) (5 diffs)
• src/VBox/Disassembler/testcase/tstDisasmArmv8-1-asm.S (modified) (2 diffs)

trunk/include/VBox/disopcode-armv8.h

@@ -51 +51 @@
      * @{ */
     OP_ARMV8_INVALID = 0,
+    OP_ARMV8_A64_ABS,
     OP_ARMV8_A64_ADC,
     OP_ARMV8_A64_ADCS,
@@ -131 +132 @@
     OP_ARMV8_A64_CMPP,
     OP_ARMV8_A64_CNEG,
+    OP_ARMV8_A64_CNT,
     OP_ARMV8_A64_CPP,
     /** @todo FEAT_MOPS instructions (CPYFP and friends). */
@@ -147 +149 @@
     OP_ARMV8_A64_CSINC,
     OP_ARMV8_A64_CSNEG,
+    OP_ARMV8_A64_CTZ,
     OP_ARMV8_A64_DC,
     OP_ARMV8_A64_DCPS1,

trunk/src/VBox/Disassembler/DisasmTables-armv8-a64.cpp

@@ -564 +564 @@
     DIS_ARMV8_OP(0x1ac06c00, "umin",            OP_ARMV8_A64_UMIN,      DISOPTYPE_HARMLESS),
 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(Reg2Src32Bit, 0xffe0fc00 /*fFixedInsn*/, kDisArmV8OpcDecodeNop,
-                                                RT_BIT_32(10) | RT_BIT_32(11) | RT_BIT_32(12) | RT_BIT_32(13) | RT_BIT_32(14) | RT_BIT_32(14), 10,
+                                                RT_BIT_32(10) | RT_BIT_32(11) | RT_BIT_32(12) | RT_BIT_32(13) | RT_BIT_32(14) | RT_BIT_32(15), 10,
                                                 kDisArmv8OpParmReg, kDisArmv8OpParmReg, kDisArmv8OpParmReg);
 
@@ -619 +619 @@
     DIS_ARMV8_OP(           0x9ac06c00, "umin",            OP_ARMV8_A64_UMIN,      DISOPTYPE_HARMLESS)
 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(Reg2Src64Bit, 0xffe0fc00 /*fFixedInsn*/, kDisArmV8OpcDecodeNop,
-                                                RT_BIT_32(10) | RT_BIT_32(11) | RT_BIT_32(12) | RT_BIT_32(13) | RT_BIT_32(14) | RT_BIT_32(14), 10,
+                                                RT_BIT_32(10) | RT_BIT_32(11) | RT_BIT_32(12) | RT_BIT_32(13) | RT_BIT_32(14) | RT_BIT_32(15), 10,
                                                 kDisArmv8OpParmReg, kDisArmv8OpParmReg, kDisArmv8OpParmReg);
 
@@ -631 +631 @@
     DIS_ARMV8_OP(0xbac00000, "subps",           OP_ARMV8_A64_SUBPS,     DISOPTYPE_HARMLESS),
 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(Subps, 0xffe0fc00 /*fFixedInsn*/, kDisArmV8OpcDecodeNop,
-                                                RT_BIT_32(10) | RT_BIT_32(11) | RT_BIT_32(12) | RT_BIT_32(13) | RT_BIT_32(14) | RT_BIT_32(14), 10,
+                                                RT_BIT_32(10) | RT_BIT_32(11) | RT_BIT_32(12) | RT_BIT_32(13) | RT_BIT_32(14) | RT_BIT_32(15), 10,
                                                 kDisArmv8OpParmReg, kDisArmv8OpParmReg, kDisArmv8OpParmReg);
 
@@ -658 +658 @@
 
 
+/* RBIT/REV16/REV/CLZ/CLS/CTZ/CNT/ABS/REV32 */
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Reg1SrcInsn)
+    DIS_ARMV8_INSN_DECODE(kDisParmParseSf,            31,  1, DIS_ARMV8_INSN_PARAM_UNSET),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr,          0,  5, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr,          5,  5, 1 /*idxParam*/),
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Reg1SrcInsn)
+    DIS_ARMV8_OP(0x5ac00000, "rbit",            OP_ARMV8_A64_RBIT,      DISOPTYPE_HARMLESS),
+    DIS_ARMV8_OP(0x5ac00400, "rev16",           OP_ARMV8_A64_REV16,     DISOPTYPE_HARMLESS),
+    DIS_ARMV8_OP(0x5ac00800, "rev",             OP_ARMV8_A64_REV,       DISOPTYPE_HARMLESS), /** @todo REV32 if SF1 is 1 (why must this be so difficult ARM?). */
+    DIS_ARMV8_OP(0x5ac00c00, "rev",             OP_ARMV8_A64_REV,       DISOPTYPE_HARMLESS), /** @todo SF must be 1, otherwise unallocated. */
+    DIS_ARMV8_OP(0x5ac01000, "clz",             OP_ARMV8_A64_CLZ,       DISOPTYPE_HARMLESS),
+    DIS_ARMV8_OP(0x5ac01400, "cls",             OP_ARMV8_A64_CLS,       DISOPTYPE_HARMLESS),
+    DIS_ARMV8_OP(0x5ac01800, "ctz",             OP_ARMV8_A64_CTZ,       DISOPTYPE_HARMLESS),
+    DIS_ARMV8_OP(0x5ac01c00, "cnt",             OP_ARMV8_A64_CNT,       DISOPTYPE_HARMLESS),
+    DIS_ARMV8_OP(0x5ac02000, "abs",             OP_ARMV8_A64_ABS,       DISOPTYPE_HARMLESS),
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(Reg1SrcInsn, 0x7ffffc00 /*fFixedInsn*/, kDisArmV8OpcDecodeNop,
+                                                RT_BIT_32(10) | RT_BIT_32(11) | RT_BIT_32(12) | RT_BIT_32(13) | RT_BIT_32(14) | RT_BIT_32(15), 10,
+                                                kDisArmv8OpParmReg, kDisArmv8OpParmReg);
+
+
+/**
+ * C4.1.95 - Data Processing - Register - 1-source
+ *
+ * Differentiate between standard and FEAT_PAuth instructions based on opcode2 field.
+ */
+DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(Reg1Src)
+    DIS_ARMV8_DECODE_MAP_ENTRY(Reg1SrcInsn),          /* Data-processing (1-source) */
+    DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,               /* Data-processing (1-source, FEAT_PAuth) */
+DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(Reg1Src, 16);
+
+
 /**
  * C4.1.95 - Data Processing - Register - 2-source / 1-source
@@ -665 +696 @@
 DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(Reg2Src1Src)
     DIS_ARMV8_DECODE_MAP_ENTRY(Reg2SrcSubps),        /* Data-processing (2-source) */
-    DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,              /** @todo Data-processing (1-source) */
+    DIS_ARMV8_DECODE_MAP_ENTRY(Reg1Src),             /* Data-processing (1-source) */
 DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(Reg2Src1Src, 30);
 

trunk/src/VBox/Disassembler/testcase/tstDisasmArmv8-1-asm.S

@@ -1275 +1275 @@
         ;subp  x0, sp, sp - Requires FEAT_MTE
 
+        ;gmi   x0, x1, x3  - Requires FEAT_MTE
+        ;gmi   x0, sp, x3  - Requires FEAT_MTE
+
+        ;irg   x0, x1, x3  - Requires FEAT_MTE
+        ;irg   x0, x1, xzr - Requires FEAT_MTE
+        ;irg   sp, sp, x3  - Requires FEAT_MTE
+        ;irg   sp, sp, xzr - Requires FEAT_MTE
+
         udiv w0, w1, wzr
         udiv x0, x1, xzr
@@ -1318 +1326 @@
         ;smin w0, w1, wzr - Requires FEAT_CSSC
         ;smin x0, x1, xzr - Requires FEAT_CSSC
+
+        rbit w0, wzr
+        rbit w0, w1
+        rbit x0, xzr
+        rbit x0, x1
+
+        rev16 w0, wzr
+        rev16 w0, w1
+        rev16 x0, xzr
+        rev16 x0, x1
+
+        rev   w0, wzr
+        rev   w0, w1
+        rev   x0, xzr
+        rev   x0, x1
+
+        ; @todo rev32
+
+        clz   w0, wzr
+        clz   w0, w1
+        clz   x0, xzr
+        clz   x0, x1
+
+        cls   w0, wzr
+        cls   w0, w1
+        cls   x0, xzr
+        cls   x0, x1
+
+        ;ctz   w0, wzr - Requires FEAT_CSSC
+        ;ctz   w0, w1  - Requires FEAT_CSSC
+        ;ctz   x0, xzr - Requires FEAT_CSSC
+        ;ctz   x0, x1  - Requires FEAT_CSSC
+
+        ;cnt   w0, wzr - Requires FEAT_CSSC
+        ;cnt   w0, w1  - Requires FEAT_CSSC
+        ;cnt   x0, xzr - Requires FEAT_CSSC
+        ;cnt   x0, x1  - Requires FEAT_CSSC
 
         ;