Changeset 106659 in vbox for trunk/src/VBox/Disassembler

Timestamp:

Oct 24, 2024 12:55:19 PM (3 months ago)

Author:

vboxsync

Message:

Disassembler: Decode post-indexed load/store instructions, bugref:10394

Location:

trunk/src/VBox/Disassembler

Files:

• DisasmTables-armv8-a64.cpp (modified) (2 diffs)
• testcase/tstDisasmArmv8-1-asm.S (modified) (2 diffs)

trunk/src/VBox/Disassembler/DisasmTables-armv8-a64.cpp

@@ -1025 +1025 @@
 
 /*
+ * STRB/LDRB/LDRSB/STRH/LDRH/LDRSH/STR/LDR/LDRSW/STR/LDR
+ *
+ * Note: The size,opc bitfields are concatenated to form an index.
+ */
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegImmPostIndexGpr)
+    DIS_ARMV8_INSN_DECODE(kDisParmParseSize,               30,  2, DIS_ARMV8_INSN_PARAM_UNSET),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr,               0,  5, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp,           5,  5, 1 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOffUnscaled, 12,  9, 1 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseSetPostIndexed,      0,  0, 1 /*idxParam*/),
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegImmPostIndexGpr)
+    DIS_ARMV8_OP(0x38000400, "strb",            OP_ARMV8_A64_STRB,      DISOPTYPE_HARMLESS),
+    DIS_ARMV8_OP(0x38400400, "ldrb",            OP_ARMV8_A64_LDRB,      DISOPTYPE_HARMLESS),
+ DIS_ARMV8_OP_EX(0x38800400, "ldrsb",           OP_ARMV8_A64_LDRSB,     DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
+ DIS_ARMV8_OP_EX(0x38c00400, "ldrsb",           OP_ARMV8_A64_LDRSB,     DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
+    DIS_ARMV8_OP(0x78000400, "strh",            OP_ARMV8_A64_STRH,      DISOPTYPE_HARMLESS),
+    DIS_ARMV8_OP(0x78400400, "ldrh",            OP_ARMV8_A64_LDRH,      DISOPTYPE_HARMLESS),
+ DIS_ARMV8_OP_EX(0x78800400, "ldrsh",           OP_ARMV8_A64_LDURSH,    DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
+ DIS_ARMV8_OP_EX(0x78c00400, "ldrsh",           OP_ARMV8_A64_LDURSH,    DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
+    DIS_ARMV8_OP(0xb8000400, "str",             OP_ARMV8_A64_STR,       DISOPTYPE_HARMLESS),
+    DIS_ARMV8_OP(0xb8400400, "ldr",             OP_ARMV8_A64_LDR,       DISOPTYPE_HARMLESS),
+ DIS_ARMV8_OP_EX(0xb8800400, "ldrsw",           OP_ARMV8_A64_LDURSW,    DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
+    INVALID_OPCODE,
+    DIS_ARMV8_OP(0xf8000400, "str",             OP_ARMV8_A64_STR,       DISOPTYPE_HARMLESS),
+    DIS_ARMV8_OP(0xf8400400, "ldr",             OP_ARMV8_A64_LDR,       DISOPTYPE_HARMLESS),
+    INVALID_OPCODE,
+    INVALID_OPCODE,
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegImmPostIndexGpr, 0xffe00c00 /*fFixedInsn*/,
+                                       kDisArmV8OpcDecodeCollate,
+                                       RT_BIT_32(22) | RT_BIT_32(23) | RT_BIT_32(30) | RT_BIT_32(31), 22);
+
+
+/*
+ * C4.1.94.26 - Loads and Stores - Load/Store register (immediate post-indexed) variants
+ *
+ * Differentiate further based on the VR field.
+ *
+ *     Bit  26
+ *     +-------------------------------------------
+ *           0 GPR variants.
+ *           1 SIMD/FP variants
+ */
+DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegImmPostIndex)
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegImmPostIndexGpr),
+    DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,             /** @todo */
+DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegImmPostIndex, RT_BIT_32(26), 26);
+
+
+/*
  * C4.1.94 - Loads and Stores - Load/Store register variants
  *
@@ -1038 +1087 @@
 DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegOp2_11_0)
     DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegUnscaledImm),
-    DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,         /** @todo */
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegImmPostIndex),
     DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,         /** @todo */
     DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegImmPreIndex),

trunk/src/VBox/Disassembler/testcase/tstDisasmArmv8-1-asm.S

@@ -642 +642 @@
         ldrsw x0, [sp, #255]!
 
+        ldrb w0, [x28], #0
+        ldrb w0, [x28], #-256
+        ldrb w0, [x28], #255
+
+        ldrb w0, [sp], #0
+        ldrb w0, [sp], #-256
+        ldrb w0, [sp], #255
+
+        ldrsb w0, [x28], #0
+        ldrsb w0, [x28], #-256
+        ldrsb w0, [x28], #255
+
+        ldrsb w0, [sp], #0
+        ldrsb w0, [sp], #-256
+        ldrsb w0, [sp], #255
+
+        ldrsb x0, [x28], #0
+        ldrsb x0, [x28], #-256
+        ldrsb x0, [x28], #255
+
+        ldrsb x0, [sp], #0
+        ldrsb x0, [sp], #-256
+        ldrsb x0, [sp], #255
+
+        ldrh w0, [x28], #0
+        ldrh w0, [x28], #-256
+        ldrh w0, [x28], #255
+
+        ldrh w0, [sp], #0
+        ldrh w0, [sp], #-256
+        ldrh w0, [sp], #255
+
+        ldrsh w0, [x28], #0
+        ldrsh w0, [x28], #-256
+        ldrsh w0, [x28], #255
+
+        ldrsh w0, [sp], #0
+        ldrsh w0, [sp], #-256
+        ldrsh w0, [sp], #255
+
+        ldrsh x0, [x28], #0
+        ldrsh x0, [x28], #-256
+        ldrsh x0, [x28], #255
+
+        ldrsh x0, [sp], #0
+        ldrsh x0, [sp], #-256
+        ldrsh x0, [sp], #255
+
+        ldr x0, [x28], #0
+        ldr x0, [x28], #-256
+        ldr x0, [x28], #255
+
+        ldr x0, [sp], #0
+        ldr x0, [sp], #-256
+        ldr x0, [sp], #255
+
+        ldr w0, [x28], #0
+        ldr w0, [x28], #-256
+        ldr w0, [x28], #255
+
+        ldr w0, [sp], #0
+        ldr w0, [sp], #-256
+        ldr w0, [sp], #255
+
+        ldrsw x0, [x28], #0
+        ldrsw x0, [x28], #-256
+        ldrsw x0, [x28], #255
+
+        ldrsw x0, [sp], #0
+        ldrsw x0, [sp], #-256
+        ldrsw x0, [sp], #255
+
 
         ldurb w0, [x28]
@@ -903 +975 @@
         str w0, [sp, #4]
         str w0, [sp, #16380]
+
+        strb w0, [x28, #0]!
+        strb w0, [x28, #-256]!
+        strb w0, [x28, #255]!
+
+        strb w0, [sp, #0]!
+        strb w0, [sp, #-256]!
+        strb w0, [sp, #255]!
+
+        strh w0, [x28, #0]!
+        strh w0, [x28, #-256]!
+        strh w0, [x28, #255]!
+
+        strh w0, [sp, #0]!
+        strh w0, [sp, #-256]!
+        strh w0, [sp, #255]!
+
+        str x0, [x28, #0]!
+        str x0, [x28, #-256]!
+        str x0, [x28, #255]!
+
+        str x0, [sp, #0]!
+        str x0, [sp, #-256]!
+        str x0, [sp, #255]!
+
+        str w0, [x28, #0]!
+        str w0, [x28, #-256]!
+        str w0, [x28, #255]!
+
+        str w0, [sp, #0]!
+        str w0, [sp, #-256]!
+        str w0, [sp, #255]!
+
+
+        strb w0, [x28], #0
+        strb w0, [x28], #-256
+        strb w0, [x28], #255
+
+        strb w0, [sp], #0
+        strb w0, [sp], #-256
+        strb w0, [sp], #255
+
+        strh w0, [x28], #0
+        strh w0, [x28], #-256
+        strh w0, [x28], #255
+
+        strh w0, [sp], #0
+        strh w0, [sp], #-256
+        strh w0, [sp], #255
+
+        str x0, [x28], #0
+        str x0, [x28], #-256
+        str x0, [x28], #255
+
+        str x0, [sp], #0
+        str x0, [sp], #-256
+        str x0, [sp], #255
+
+        str w0, [x28], #0
+        str w0, [x28], #-256
+        str w0, [x28], #255
+
+        str w0, [sp], #0
+        str w0, [sp], #-256
+        str w0, [sp], #255
 
         sturb w0, [x28]