VirtualBox

Changeset 106676 in vbox for trunk/src/VBox/ValidationKit


Ignore:
Timestamp:
Oct 25, 2024 6:21:56 AM (4 months ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
165544
Message:

ValidationKit/bootsectors: SIMD FP testcases: emit instruction test functions for 22 'cvt' family instructions; bugref:10658; jiraref:VBP-1206

  • add instruction test variants for 22 'cvt' family instructions
  • generates 594 different functions: lots of test code to be written!
  • document FPU/MMX transitions the test code will need to implement
  • document encoding variants we ought to test if we can figure out how
  • allow forcing specific 'FSxBX' data sizes needed in some AVX cases
File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4-template.mac

    r106471 r106676  
    7171
    7272;;
     73; FSxBX and its variants allow a memory reference to be embedded into a test
     74; instruction. `xBX' adjusts automatically to the addressing model: BX, EBX,
     75; or RBX depending on the number of address bits. FSxBX_D and so on allow to
     76; force a particular memory reference size; this is necessary for some AVX
     77; instructions where the mentioned XMM/YMM/ZMM register size doesn't fully
     78; control the memory size to be used. Macros are repeatedly redefined in
     79; order to pick up the current address-model-specific `xBX' value. (Other
     80; sizes could be defined: B=byte=1, W=word=2, T=tword=10(x87), z=zword=32)
     81;
     82 %ifndef BS3CPUINSTR4_DEFINE_FSxBX_DEFINED
     83  %define BS3CPUINSTR4_DEFINE_FSxBX_DEFINED
     84  %macro BS3CPUINSTR4_DEFINE_FSxBX 0
     85   %define FSxBX [fs:xBX]           ; natural size of the instruction
     86   %define FSxBX_D dword [fs:xBX]   ; dword =  32 bits =  4 bytes =  2 words
     87   %define FSxBX_Q qword [fs:xBX]   ; qword =  64 bits =  8 bytes =  4 words
     88   %define FSxBX_O oword [fs:xBX]   ; oword = 128 bits = 16 bytes =  8 words
     89   %define FSxBX_Y yword [fs:xBX]   ; yword = 256 bits = 32 bytes = 16 words
     90  %endmacro
     91  %macro BS3CPUINSTR4_UNDEF_FSxBX 0
     92   %undef  FSxBX
     93   %undef  FSxBX_D
     94   %undef  FSxBX_Q
     95   %undef  FSxBX_O
     96   %undef  FSxBX_Y
     97  %endmacro
     98 %endif ; !BS3CPUINSTR4_DEFINE_FSxBX_DEFINED
     99
     100;;
    73101; The EMIT_INSTR_PLUS_ICEBP macros is for creating a common function for and
    74 ; named after a single instruction, followed by a looping ICEBP.
    75 ;
    76 ; This works like a prefix to the instruction invocation, only exception is that
    77 ; instead of [fs:xBX] you write FSxBS as that's what is wanted in the name.
     102; named after a single instruction & args, followed by a looping ICEBP.
    78103;
    79104 %ifndef EMIT_INSTR_PLUS_ICEBP_DEFINED
    … …  
    82107  %macro EMIT_INSTR_PLUS_ICEBP 2
    83108BS3CPUINSTR4_PROC_BEGIN_CMN bs3CpuInstr4_ %+ %1 %+ _ %+ %2 %+ _icebp
    84    %define FSxBX [fs:xBX]
     109   BS3CPUINSTR4_DEFINE_FSxBX
    85110        %1      %2
    86    %undef  FSxBX
     111   BS3CPUINSTR4_UNDEF_FSxBX
    87112.again:
    88113        icebp
    … …  
    93118  %macro EMIT_INSTR_PLUS_ICEBP 3
    94119BS3CPUINSTR4_PROC_BEGIN_CMN bs3CpuInstr4_ %+ %1 %+ _ %+ %2 %+ _ %+ %3 %+ _icebp
    95    %define FSxBX [fs:xBX]
     120   BS3CPUINSTR4_DEFINE_FSxBX
    96121        %1      %2, %3
    97    %undef  FSxBX
     122   BS3CPUINSTR4_UNDEF_FSxBX
    98123.again:
    99124        icebp
    … …  
    104129  %macro EMIT_INSTR_PLUS_ICEBP 4
    105130BS3CPUINSTR4_PROC_BEGIN_CMN bs3CpuInstr4_ %+ %1 %+ _ %+ %2 %+ _ %+ %3 %+ _ %+ %4 %+ _icebp
    106    %define FSxBX [fs:xBX]
     131   BS3CPUINSTR4_DEFINE_FSxBX
    107132        %1      %2, %3, %4
    108    %undef  FSxBX
     133   BS3CPUINSTR4_UNDEF_FSxBX
    109134.again:
    110135        icebp
    … …  
    115140  %macro EMIT_INSTR_PLUS_ICEBP 5
    116141BS3CPUINSTR4_PROC_BEGIN_CMN bs3CpuInstr4_ %+ %1 %+ _ %+ %2 %+ _ %+ %3 %+ _ %+ %4 %+ _ %+ %5 %+ _icebp
    117    %define FSxBX [fs:xBX]
     142   BS3CPUINSTR4_DEFINE_FSxBX
    118143        %1      %2, %3, %4, %5
    119    %undef  FSxBX
     144   BS3CPUINSTR4_UNDEF_FSxBX
    120145.again:
    121146        icebp
    … …  
    846871EMIT_INSTR_PLUS_ICEBP_C64   vrsqrtss, XMM8, XMM8, XMM8
    847872
     873;
     874;; cvtpi2ps
     875;
     876; SSE-128, int32 -> fp32 (packed:2; from MMX register)
     877EMIT_INSTR_PLUS_ICEBP       cvtpi2ps, XMM1, MM1
     878EMIT_INSTR_PLUS_ICEBP       cvtpi2ps, XMM1, FSxBX
     879EMIT_INSTR_PLUS_ICEBP_C64   cvtpi2ps, XMM8, MM1
     880EMIT_INSTR_PLUS_ICEBP_C64   cvtpi2ps, XMM8, FSxBX
     881; note: transition from x87 FPU to MMX; takes FPU exceptions (SDM does not mention MM forms only?)
     882;
     883;; cvtps2pi
     884;
     885; SSE-128, fp32 -> int32 (packed:2; to MMX register)
     886EMIT_INSTR_PLUS_ICEBP       cvtps2pi, MM1, XMM1
     887EMIT_INSTR_PLUS_ICEBP       cvtps2pi, MM1, FSxBX
     888EMIT_INSTR_PLUS_ICEBP_C64   cvtps2pi, MM1, XMM8
     889; note: transition from x87 FPU to MMX; takes FPU exceptions
     890
     891;
     892;; cvttps2pi
     893;
     894; SSE-128, fp32 -> int32 (packed:2; truncated; to MMX register)
     895EMIT_INSTR_PLUS_ICEBP       cvttps2pi, MM1, XMM1
     896EMIT_INSTR_PLUS_ICEBP       cvttps2pi, MM1, FSxBX
     897EMIT_INSTR_PLUS_ICEBP_C64   cvttps2pi, MM1, XMM8
     898; note: transition from x87 FPU to MMX; takes FPU exceptions
     899;
     900;; cvtsi2ss
     901;
     902; SSE-128, int32 -> fp32 (single)
     903EMIT_INSTR_PLUS_ICEBP       cvtsi2ss,  XMM1, EAX
     904EMIT_INSTR_PLUS_ICEBP       cvtsi2ss,  XMM1, FSxBX_D
     905EMIT_INSTR_PLUS_ICEBP_C64   cvtsi2ss,  XMM8, R8D
     906EMIT_INSTR_PLUS_ICEBP_C64   cvtsi2ss,  XMM8, FSxBX_D
     907; SSE-128, int64 -> fp32 (single)
     908EMIT_INSTR_PLUS_ICEBP_C64   cvtsi2ss,  XMM1, RAX
     909EMIT_INSTR_PLUS_ICEBP_C64   cvtsi2ss,  XMM1, FSxBX_Q
     910EMIT_INSTR_PLUS_ICEBP_C64   cvtsi2ss,  XMM8, R8
     911EMIT_INSTR_PLUS_ICEBP_C64   cvtsi2ss,  XMM8, FSxBX_Q
     912; AVX-128, int32 -> fp32 (single)
     913EMIT_INSTR_PLUS_ICEBP       vcvtsi2ss, XMM1, XMM2, EAX
     914EMIT_INSTR_PLUS_ICEBP       vcvtsi2ss, XMM1, XMM2, FSxBX_D
     915EMIT_INSTR_PLUS_ICEBP_C64   vcvtsi2ss, XMM8, XMM9, R8D
     916EMIT_INSTR_PLUS_ICEBP_C64   vcvtsi2ss, XMM8, XMM9, FSxBX_D
     917; AVX-128, int64 -> fp32 (single)
     918EMIT_INSTR_PLUS_ICEBP       vcvtsi2ss, XMM1, XMM2, RAX       ;; @todo this assembles in 16/32 mode; SDM says VEX.W1 ignored in non-64 bit
     919EMIT_INSTR_PLUS_ICEBP       vcvtsi2ss, XMM1, XMM2, FSxBX_Q   ;; @todo this assembles in 16/32 mode; SDM says VEX.W1 ignored in non-64 bit
     920EMIT_INSTR_PLUS_ICEBP_C64   vcvtsi2ss, XMM8, XMM9, R8
     921EMIT_INSTR_PLUS_ICEBP_C64   vcvtsi2ss, XMM8, XMM9, FSxBX_Q
     922; AVX-128, int32 -> fp32, same-reg (single)
     923EMIT_INSTR_PLUS_ICEBP       vcvtsi2ss, XMM1, XMM1, EAX
     924EMIT_INSTR_PLUS_ICEBP       vcvtsi2ss, XMM1, XMM1, FSxBX_D
     925EMIT_INSTR_PLUS_ICEBP_C64   vcvtsi2ss, XMM8, XMM8, R8D
     926EMIT_INSTR_PLUS_ICEBP_C64   vcvtsi2ss, XMM8, XMM8, FSxBX_D
     927; AVX-128, int64 -> fp32, same-reg (single)
     928EMIT_INSTR_PLUS_ICEBP       vcvtsi2ss, XMM1, XMM1, RAX       ;; @todo this assembles in 16/32 mode, but should it...?
     929EMIT_INSTR_PLUS_ICEBP       vcvtsi2ss, XMM1, XMM1, FSxBX_Q   ;; @todo this assembles in 16/32 mode, but should it...?
     930EMIT_INSTR_PLUS_ICEBP_C64   vcvtsi2ss, XMM8, XMM8, R8
     931EMIT_INSTR_PLUS_ICEBP_C64   vcvtsi2ss, XMM8, XMM8, FSxBX_Q
     932; @todo test with VEX.L=1 (as if asking for YMM)?  SDM says 'unpredictable behavior'...
     933; @todo same-reg int32 -> fp32 (SDM says W1 ignored in 32-bit modes) (see above)
     934
     935;
     936;; cvtss2si
     937;
     938; SSE-128, fp32 -> int32
     939EMIT_INSTR_PLUS_ICEBP       cvtss2si,  EAX, XMM1
     940EMIT_INSTR_PLUS_ICEBP       cvtss2si,  EAX, FSxBX
     941EMIT_INSTR_PLUS_ICEBP_C64   cvtss2si,  R8D, XMM8
     942EMIT_INSTR_PLUS_ICEBP_C64   cvtss2si,  R8D, FSxBX
     943; SSE-128, fp32 -> int64
     944EMIT_INSTR_PLUS_ICEBP_C64   cvtss2si,  RAX, XMM1
     945EMIT_INSTR_PLUS_ICEBP_C64   cvtss2si,  RAX, FSxBX
     946EMIT_INSTR_PLUS_ICEBP_C64   cvtss2si,  R8,  XMM8
     947EMIT_INSTR_PLUS_ICEBP_C64   cvtss2si,  R8,  FSxBX
     948; AVX-128, fp32 -> int32
     949EMIT_INSTR_PLUS_ICEBP       vcvtss2si, EAX, XMM1
     950EMIT_INSTR_PLUS_ICEBP       vcvtss2si, EAX, FSxBX
     951EMIT_INSTR_PLUS_ICEBP_C64   vcvtss2si, R8D, XMM8
     952EMIT_INSTR_PLUS_ICEBP_C64   vcvtss2si, R8D, FSxBX
     953; AVX-128, fp32 -> int64
     954EMIT_INSTR_PLUS_ICEBP       vcvtss2si, RAX, XMM1
     955EMIT_INSTR_PLUS_ICEBP       vcvtss2si, RAX, FSxBX
     956EMIT_INSTR_PLUS_ICEBP_C64   vcvtss2si, R8,  XMM8
     957EMIT_INSTR_PLUS_ICEBP_C64   vcvtss2si, R8,  FSxBX
     958; @todo test with VEX.W=1 in 16/32-bit modes; SDM says behaves as if W=0
     959; @todo test with VEX.L=1 (as if asking for YMM)?  SDM says 'unpredictable behavior'...
     960
     961;
     962;; cvttss2si
     963;
     964; SSE-128, fp32 -> int32 (single; truncated)
     965EMIT_INSTR_PLUS_ICEBP       cvttss2si,  EAX,  XMM1
     966EMIT_INSTR_PLUS_ICEBP       cvttss2si,  EAX,  FSxBX
     967EMIT_INSTR_PLUS_ICEBP_C64   cvttss2si,  R8D,  XMM8
     968EMIT_INSTR_PLUS_ICEBP_C64   cvttss2si,  R8D,  FSxBX
     969; SSE-128, fp32 -> int64 (single; truncated)
     970EMIT_INSTR_PLUS_ICEBP_C64   cvttss2si,  RAX,  XMM1
     971EMIT_INSTR_PLUS_ICEBP_C64   cvttss2si,  RAX,  FSxBX
     972EMIT_INSTR_PLUS_ICEBP_C64   cvttss2si,  R8,   XMM8
     973EMIT_INSTR_PLUS_ICEBP_C64   cvttss2si,  R8,   FSxBX
     974; AVX-128, fp32 -> int32 (single; truncated)
     975EMIT_INSTR_PLUS_ICEBP       vcvttss2si, EAX,  XMM1
     976EMIT_INSTR_PLUS_ICEBP       vcvttss2si, EAX,  FSxBX
     977EMIT_INSTR_PLUS_ICEBP_C64   vcvttss2si, R8D,  XMM8
     978EMIT_INSTR_PLUS_ICEBP_C64   vcvttss2si, R8D,  FSxBX
     979; AVX-128, fp32 -> int64 (single; truncated)
     980EMIT_INSTR_PLUS_ICEBP       vcvttss2si, RAX,  XMM1
     981EMIT_INSTR_PLUS_ICEBP       vcvttss2si, RAX,  FSxBX
     982EMIT_INSTR_PLUS_ICEBP_C64   vcvttss2si, R8,   XMM8
     983EMIT_INSTR_PLUS_ICEBP_C64   vcvttss2si, R8,   FSxBX
     984; @todo test with VEX.W=1 in 16/32-bit modes; SDM says behaves as if W=0
     985; @todo test with VEX.L=1 (as if asking for YMM)?  SDM says 'unpredictable behavior'...
     986
     987;
     988;; cvtpi2pd
     989;
     990; SSE-128, int32 -> fp64 (packed:2; from MMX register)
     991EMIT_INSTR_PLUS_ICEBP       cvtpi2pd, XMM1, MM1
     992EMIT_INSTR_PLUS_ICEBP       cvtpi2pd, XMM1, FSxBX
     993EMIT_INSTR_PLUS_ICEBP_C64   cvtpi2pd, XMM8, MM1
     994EMIT_INSTR_PLUS_ICEBP_C64   cvtpi2pd, XMM8, FSxBX
     995; note: transition from x87 FPU to MMX; takes FPU exceptions (MM forms only)
     996
     997;
     998;; cvtpd2pi
     999;
     1000; SSE-128, fp64 -> int32 (packed:2; to MMX register)
     1001EMIT_INSTR_PLUS_ICEBP       cvtpd2pi, MM1, XMM1
     1002EMIT_INSTR_PLUS_ICEBP       cvtpd2pi, MM1, FSxBX
     1003EMIT_INSTR_PLUS_ICEBP_C64   cvtpd2pi, MM1, XMM8
     1004; note: transition from x87 FPU to MMX; takes FPU exceptions
     1005
     1006;
     1007;; cvttpd2pi
     1008;
     1009; SSE-128, fp64 -> int32 (packed:2; truncated; to MMX register)
     1010EMIT_INSTR_PLUS_ICEBP       cvttpd2pi, MM1, XMM1
     1011EMIT_INSTR_PLUS_ICEBP       cvttpd2pi, MM1, FSxBX
     1012EMIT_INSTR_PLUS_ICEBP_C64   cvttpd2pi, MM1, XMM8
     1013; note: transition from x87 FPU to MMX; takes FPU exceptions
     1014
     1015;
     1016;; cvtsi2sd
     1017;
     1018; SSE-128, int32 -> fp64 (single)
     1019EMIT_INSTR_PLUS_ICEBP       cvtsi2sd,  XMM1, EAX
     1020EMIT_INSTR_PLUS_ICEBP       cvtsi2sd,  XMM1, FSxBX_D
     1021EMIT_INSTR_PLUS_ICEBP_C64   cvtsi2sd,  XMM8, R8D
     1022EMIT_INSTR_PLUS_ICEBP_C64   cvtsi2sd,  XMM8, FSxBX_D
     1023; SSE-128, int64 -> fp64 (single)
     1024EMIT_INSTR_PLUS_ICEBP_C64   cvtsi2sd,  XMM1, RAX
     1025EMIT_INSTR_PLUS_ICEBP_C64   cvtsi2sd,  XMM1, FSxBX_Q
     1026EMIT_INSTR_PLUS_ICEBP_C64   cvtsi2sd,  XMM8, R8
     1027EMIT_INSTR_PLUS_ICEBP_C64   cvtsi2sd,  XMM8, FSxBX_Q
     1028; AVX-128, int32 -> fp64 (single)
     1029EMIT_INSTR_PLUS_ICEBP       vcvtsi2sd, XMM1, XMM2, EAX
     1030EMIT_INSTR_PLUS_ICEBP       vcvtsi2sd, XMM1, XMM2, FSxBX_D
     1031EMIT_INSTR_PLUS_ICEBP_C64   vcvtsi2sd, XMM8, XMM9, EAX
     1032EMIT_INSTR_PLUS_ICEBP_C64   vcvtsi2sd, XMM8, XMM9, FSxBX_D
     1033; AVX-128, int64 -> fp64 (single)
     1034EMIT_INSTR_PLUS_ICEBP       vcvtsi2sd, XMM1, XMM2, RAX
     1035EMIT_INSTR_PLUS_ICEBP       vcvtsi2sd, XMM1, XMM2, FSxBX_Q
     1036EMIT_INSTR_PLUS_ICEBP_C64   vcvtsi2sd, XMM8, XMM9, RAX
     1037EMIT_INSTR_PLUS_ICEBP_C64   vcvtsi2sd, XMM8, XMM9, FSxBX_Q
     1038; AVX-128, int32 -> fp64, same-reg (single)
     1039EMIT_INSTR_PLUS_ICEBP       vcvtsi2sd, XMM1, XMM1, EAX
     1040EMIT_INSTR_PLUS_ICEBP       vcvtsi2sd, XMM1, XMM1, FSxBX_D
     1041EMIT_INSTR_PLUS_ICEBP_C64   vcvtsi2sd, XMM8, XMM8, EAX
     1042EMIT_INSTR_PLUS_ICEBP_C64   vcvtsi2sd, XMM8, XMM8, FSxBX_D
     1043; AVX-128, int64 -> fp64, same-reg (single)
     1044EMIT_INSTR_PLUS_ICEBP       vcvtsi2sd, XMM1, XMM1, RAX
     1045EMIT_INSTR_PLUS_ICEBP       vcvtsi2sd, XMM1, XMM1, FSxBX_Q
     1046EMIT_INSTR_PLUS_ICEBP_C64   vcvtsi2sd, XMM8, XMM8, RAX
     1047EMIT_INSTR_PLUS_ICEBP_C64   vcvtsi2sd, XMM8, XMM8, FSxBX_Q
     1048; @todo test with VEX.W=1 in 16/32-bit modes; SDM says behaves as if W=0
     1049; @todo test with VEX.L=1 (as if asking for YMM)?  SDM says 'unpredictable behavior'...
     1050
     1051;
     1052;; cvtsd2si
     1053;
     1054; SSE-128, fp64 -> int32 (single)
     1055EMIT_INSTR_PLUS_ICEBP       cvtsd2si,  EAX, XMM1
     1056EMIT_INSTR_PLUS_ICEBP       cvtsd2si,  EAX, FSxBX
     1057EMIT_INSTR_PLUS_ICEBP_C64   cvtsd2si,  R8D, XMM8
     1058EMIT_INSTR_PLUS_ICEBP_C64   cvtsd2si,  R8D, FSxBX
     1059; SSE-128, fp64 -> int64 (single)
     1060EMIT_INSTR_PLUS_ICEBP_C64   cvtsd2si,  RAX, XMM1
     1061EMIT_INSTR_PLUS_ICEBP_C64   cvtsd2si,  RAX, FSxBX
     1062EMIT_INSTR_PLUS_ICEBP_C64   cvtsd2si,  R8,  XMM8
     1063EMIT_INSTR_PLUS_ICEBP_C64   cvtsd2si,  R8,  FSxBX
     1064; AVX-128, fp64 -> int32 (single)
     1065EMIT_INSTR_PLUS_ICEBP       vcvtsd2si, EAX, XMM1
     1066EMIT_INSTR_PLUS_ICEBP       vcvtsd2si, EAX, FSxBX
     1067EMIT_INSTR_PLUS_ICEBP_C64   vcvtsd2si, R8D, XMM8
     1068EMIT_INSTR_PLUS_ICEBP_C64   vcvtsd2si, R8D, FSxBX
     1069; AVX-128, fp64 -> int64 (single)
     1070EMIT_INSTR_PLUS_ICEBP       vcvtsd2si, RAX, XMM1   ;; @todo this assembles in 16/32 mode; SDM says VEX.W1 ignored in non-64 bit
     1071EMIT_INSTR_PLUS_ICEBP       vcvtsd2si, RAX, FSxBX  ;; @todo this assembles in 16/32 mode; SDM says VEX.W1 ignored in non-64 bit
     1072EMIT_INSTR_PLUS_ICEBP_C64   vcvtsd2si, R8,  XMM8
     1073EMIT_INSTR_PLUS_ICEBP_C64   vcvtsd2si, R8,  FSxBX
     1074; @todo test with VEX.L=1 (as if asking for YMM)?  SDM says 'unpredictable behavior'...
     1075; @todo same-reg int32 -> fp32 (SDM says W1 ignored in 32-bit modes) (see above)
     1076
     1077;
     1078;; cvttsd2si
     1079;
     1080; SSE-128, fp64 -> int32 (single; truncated)
     1081EMIT_INSTR_PLUS_ICEBP       cvttsd2si,  EAX, XMM1
     1082EMIT_INSTR_PLUS_ICEBP       cvttsd2si,  EAX, FSxBX
     1083EMIT_INSTR_PLUS_ICEBP_C64   cvttsd2si,  R8D, XMM8
     1084EMIT_INSTR_PLUS_ICEBP_C64   cvttsd2si,  R8D, FSxBX
     1085; SSE-128, fp64 -> int64 (single; truncated)
     1086EMIT_INSTR_PLUS_ICEBP_C64   cvttsd2si,  RAX, XMM1
     1087EMIT_INSTR_PLUS_ICEBP_C64   cvttsd2si,  RAX, FSxBX
     1088EMIT_INSTR_PLUS_ICEBP_C64   cvttsd2si,  R8,  XMM8
     1089EMIT_INSTR_PLUS_ICEBP_C64   cvttsd2si,  R8,  FSxBX
     1090; AVX-128, fp64 -> int32 (single; truncated)
     1091EMIT_INSTR_PLUS_ICEBP       vcvttsd2si, EAX, XMM1
     1092EMIT_INSTR_PLUS_ICEBP       vcvttsd2si, EAX, FSxBX
     1093EMIT_INSTR_PLUS_ICEBP_C64   vcvttsd2si, R8D, XMM8
     1094EMIT_INSTR_PLUS_ICEBP_C64   vcvttsd2si, R8D, FSxBX
     1095; AVX-128, fp64 -> int64 (single; truncated)
     1096EMIT_INSTR_PLUS_ICEBP       vcvttsd2si, RAX, XMM1
     1097EMIT_INSTR_PLUS_ICEBP       vcvttsd2si, RAX, FSxBX
     1098EMIT_INSTR_PLUS_ICEBP_C64   vcvttsd2si, R8,  XMM8
     1099EMIT_INSTR_PLUS_ICEBP_C64   vcvttsd2si, R8,  FSxBX
     1100; @todo test with VEX.W=1 in 16/32-bit modes; SDM says behaves as if W=0
     1101; @todo test with VEX.L=1 (as if asking for YMM)?  SDM says 'unpredictable behavior'...
     1102
     1103;
     1104;; cvtdq2ps
     1105;
     1106; SSE-128, int32 -> fp32 (packed:4)
     1107EMIT_INSTR_PLUS_ICEBP       cvtdq2ps,  XMM1, XMM2
     1108EMIT_INSTR_PLUS_ICEBP       cvtdq2ps,  XMM1, FSxBX
     1109EMIT_INSTR_PLUS_ICEBP_C64   cvtdq2ps,  XMM8, XMM9
     1110EMIT_INSTR_PLUS_ICEBP_C64   cvtdq2ps,  XMM8, FSxBX
     1111; AVX-128, int32 -> fp32 (packed:4)
     1112EMIT_INSTR_PLUS_ICEBP       vcvtdq2ps, XMM1, XMM2
     1113EMIT_INSTR_PLUS_ICEBP       vcvtdq2ps, XMM1, FSxBX
     1114EMIT_INSTR_PLUS_ICEBP_C64   vcvtdq2ps, XMM8, XMM9
     1115EMIT_INSTR_PLUS_ICEBP_C64   vcvtdq2ps, XMM8, FSxBX
     1116; AVX-256, int32 -> fp32 (packed:8)
     1117EMIT_INSTR_PLUS_ICEBP       vcvtdq2ps, YMM1, YMM2
     1118EMIT_INSTR_PLUS_ICEBP       vcvtdq2ps, YMM1, FSxBX
     1119EMIT_INSTR_PLUS_ICEBP_C64   vcvtdq2ps, YMM8, YMM9
     1120EMIT_INSTR_PLUS_ICEBP_C64   vcvtdq2ps, YMM8, FSxBX
     1121; SSE-128, int32 -> fp32, same-reg (packed:4)
     1122EMIT_INSTR_PLUS_ICEBP       cvtdq2ps,  XMM1, XMM1
     1123EMIT_INSTR_PLUS_ICEBP_C64   cvtdq2ps,  XMM8, XMM8
     1124; AVX-128, int32 -> fp32, same-reg (packed:4)
     1125EMIT_INSTR_PLUS_ICEBP       vcvtdq2ps, XMM1, XMM1
     1126EMIT_INSTR_PLUS_ICEBP_C64   vcvtdq2ps, XMM8, XMM8
     1127; AVX-256, int32 -> fp32, same-reg (packed:8)
     1128EMIT_INSTR_PLUS_ICEBP       vcvtdq2ps, YMM1, YMM1
     1129EMIT_INSTR_PLUS_ICEBP_C64   vcvtdq2ps, YMM8, YMM8
     1130
     1131;
     1132;; cvtps2dq
     1133;
     1134; SSE-128, fp32 -> int32 (packed:4)
     1135EMIT_INSTR_PLUS_ICEBP       cvtps2dq,  XMM1, XMM2
     1136EMIT_INSTR_PLUS_ICEBP       cvtps2dq,  XMM1, FSxBX
     1137EMIT_INSTR_PLUS_ICEBP_C64   cvtps2dq,  XMM8, XMM9
     1138EMIT_INSTR_PLUS_ICEBP_C64   cvtps2dq,  XMM8, FSxBX
     1139; AVX-128, fp32 -> int32 (packed:4)
     1140EMIT_INSTR_PLUS_ICEBP       vcvtps2dq, XMM1, XMM2
     1141EMIT_INSTR_PLUS_ICEBP       vcvtps2dq, XMM1, FSxBX
     1142EMIT_INSTR_PLUS_ICEBP_C64   vcvtps2dq, XMM8, XMM9
     1143EMIT_INSTR_PLUS_ICEBP_C64   vcvtps2dq, XMM8, FSxBX
     1144; AVX-256, fp32 -> int32 (packed:8)
     1145EMIT_INSTR_PLUS_ICEBP       vcvtps2dq, YMM1, YMM2
     1146EMIT_INSTR_PLUS_ICEBP       vcvtps2dq, YMM1, FSxBX
     1147EMIT_INSTR_PLUS_ICEBP_C64   vcvtps2dq, YMM8, YMM9
     1148EMIT_INSTR_PLUS_ICEBP_C64   vcvtps2dq, YMM8, FSxBX
     1149; SSE-128, fp32 -> int32, same-reg (packed:4)
     1150EMIT_INSTR_PLUS_ICEBP       cvtps2dq,  XMM1, XMM1
     1151EMIT_INSTR_PLUS_ICEBP_C64   cvtps2dq,  XMM8, XMM8
     1152; AVX-128, fp32 -> int32, same-reg (packed:4)
     1153EMIT_INSTR_PLUS_ICEBP       vcvtps2dq, XMM1, XMM1
     1154EMIT_INSTR_PLUS_ICEBP_C64   vcvtps2dq, XMM8, XMM8
     1155; AVX-256, fp32 -> int32, same-reg (packed:8)
     1156EMIT_INSTR_PLUS_ICEBP       vcvtps2dq, YMM1, YMM1
     1157EMIT_INSTR_PLUS_ICEBP_C64   vcvtps2dq, YMM8, YMM8
     1158
     1159;
     1160;; cvttps2dq
     1161;
     1162; SSE-128, fp32 -> int32 (packed:4; truncated)
     1163EMIT_INSTR_PLUS_ICEBP       cvttps2dq,  XMM1, XMM2
     1164EMIT_INSTR_PLUS_ICEBP       cvttps2dq,  XMM1, FSxBX_O
     1165EMIT_INSTR_PLUS_ICEBP_C64   cvttps2dq,  XMM8, XMM9
     1166EMIT_INSTR_PLUS_ICEBP_C64   cvttps2dq,  XMM8, FSxBX_O
     1167; AVX-128, fp32 -> int32 (packed:4; truncated)
     1168EMIT_INSTR_PLUS_ICEBP       vcvttps2dq, XMM1, XMM2
     1169EMIT_INSTR_PLUS_ICEBP       vcvttps2dq, XMM1, FSxBX_O
     1170EMIT_INSTR_PLUS_ICEBP_C64   vcvttps2dq, XMM8, XMM9
     1171EMIT_INSTR_PLUS_ICEBP_C64   vcvttps2dq, XMM8, FSxBX_O
     1172; AVX-256, fp32 -> int32 (packed:8; truncated)
     1173EMIT_INSTR_PLUS_ICEBP       vcvttps2dq, YMM1, YMM2
     1174EMIT_INSTR_PLUS_ICEBP       vcvttps2dq, YMM1, FSxBX_Y
     1175EMIT_INSTR_PLUS_ICEBP_C64   vcvttps2dq, YMM8, YMM9
     1176EMIT_INSTR_PLUS_ICEBP_C64   vcvttps2dq, YMM8, FSxBX_Y
     1177; AVX-128, fp32 -> int32, same-reg (packed:4; truncated)
     1178EMIT_INSTR_PLUS_ICEBP       cvttps2dq,  XMM1, XMM1
     1179EMIT_INSTR_PLUS_ICEBP_C64   cvttps2dq,  XMM8, XMM8
     1180; AVX-128, fp32 -> int32, same-reg (packed:4; truncated)
     1181EMIT_INSTR_PLUS_ICEBP       vcvttps2dq, XMM1, XMM1
     1182EMIT_INSTR_PLUS_ICEBP_C64   vcvttps2dq, XMM8, XMM8
     1183; AVX-256, fp32 -> int32, same-reg (packed:8; truncated)
     1184EMIT_INSTR_PLUS_ICEBP       vcvttps2dq, YMM1, YMM1
     1185EMIT_INSTR_PLUS_ICEBP_C64   vcvttps2dq, YMM8, YMM8
     1186
     1187;
     1188;; cvtdq2pd
     1189;
     1190; SSE-128, int32 -> fp64 (packed:2)
     1191EMIT_INSTR_PLUS_ICEBP       cvtdq2pd,  XMM1, XMM2
     1192EMIT_INSTR_PLUS_ICEBP       cvtdq2pd,  XMM1, FSxBX
     1193EMIT_INSTR_PLUS_ICEBP_C64   cvtdq2pd,  XMM8, XMM9
     1194EMIT_INSTR_PLUS_ICEBP_C64   cvtdq2pd,  XMM8, FSxBX
     1195; AVX-128, int32 -> fp64 (packed:2)
     1196EMIT_INSTR_PLUS_ICEBP       vcvtdq2pd, XMM1, XMM2
     1197EMIT_INSTR_PLUS_ICEBP       vcvtdq2pd, XMM1, FSxBX
     1198EMIT_INSTR_PLUS_ICEBP_C64   vcvtdq2pd, XMM8, XMM9
     1199EMIT_INSTR_PLUS_ICEBP_C64   vcvtdq2pd, XMM8, FSxBX
     1200; AVX-256, int32 -> fp64 (packed:4)
     1201EMIT_INSTR_PLUS_ICEBP       vcvtdq2pd, YMM1, XMM2
     1202EMIT_INSTR_PLUS_ICEBP       vcvtdq2pd, YMM1, FSxBX
     1203EMIT_INSTR_PLUS_ICEBP_C64   vcvtdq2pd, YMM8, XMM9
     1204EMIT_INSTR_PLUS_ICEBP_C64   vcvtdq2pd, YMM8, FSxBX
     1205; SSE-128, int32 -> fp64, same-reg (packed:2)
     1206EMIT_INSTR_PLUS_ICEBP       cvtdq2pd,  XMM1, XMM1
     1207EMIT_INSTR_PLUS_ICEBP_C64   cvtdq2pd,  XMM8, XMM8
     1208; AVX-128, int32 -> fp64, same-reg (packed:2)
     1209EMIT_INSTR_PLUS_ICEBP       vcvtdq2pd, XMM1, XMM1
     1210EMIT_INSTR_PLUS_ICEBP_C64   vcvtdq2pd, XMM8, XMM8
     1211; AVX-256, int32 -> fp64, same-reg (packed:4)
     1212EMIT_INSTR_PLUS_ICEBP       vcvtdq2pd, YMM1, XMM1
     1213EMIT_INSTR_PLUS_ICEBP_C64   vcvtdq2pd, YMM8, XMM8
     1214
     1215;
     1216;; cvtpd2dq
     1217;
     1218; SSE-128, fp64 -> int32 (packed:2)
     1219EMIT_INSTR_PLUS_ICEBP       cvtpd2dq,  XMM1, XMM2
     1220EMIT_INSTR_PLUS_ICEBP       cvtpd2dq,  XMM1, FSxBX
     1221EMIT_INSTR_PLUS_ICEBP_C64   cvtpd2dq,  XMM8, XMM9
     1222EMIT_INSTR_PLUS_ICEBP_C64   cvtpd2dq,  XMM8, FSxBX
     1223; AVX-128, fp64 -> int32 (packed:2)
     1224EMIT_INSTR_PLUS_ICEBP       vcvtpd2dq, XMM1, XMM2
     1225EMIT_INSTR_PLUS_ICEBP       vcvtpd2dq, XMM1, FSxBX
     1226EMIT_INSTR_PLUS_ICEBP_C64   vcvtpd2dq, XMM8, XMM9
     1227EMIT_INSTR_PLUS_ICEBP_C64   vcvtpd2dq, XMM8, FSxBX
     1228; AVX-256, fp64 -> int32 (packed:4)
     1229EMIT_INSTR_PLUS_ICEBP       vcvtpd2dq, XMM1, YMM2
     1230EMIT_INSTR_PLUS_ICEBP       vcvtpd2dq, YMM1, FSxBX
     1231EMIT_INSTR_PLUS_ICEBP_C64   vcvtpd2dq, XMM8, YMM9
     1232EMIT_INSTR_PLUS_ICEBP_C64   vcvtpd2dq, YMM8, FSxBX
     1233; SSE-128, fp64 -> int32, same-reg (packed:2)
     1234EMIT_INSTR_PLUS_ICEBP       cvtpd2dq,  XMM1, XMM1
     1235EMIT_INSTR_PLUS_ICEBP_C64   cvtpd2dq,  XMM8, XMM8
     1236; AVX-128, fp64 -> int32, same-reg (packed:2)
     1237EMIT_INSTR_PLUS_ICEBP       vcvtpd2dq, XMM1, XMM1
     1238EMIT_INSTR_PLUS_ICEBP_C64   vcvtpd2dq, XMM8, XMM8
     1239; AVX-256, fp64 -> int32, same-reg (packed:4)
     1240EMIT_INSTR_PLUS_ICEBP       vcvtpd2dq, XMM1, YMM1
     1241EMIT_INSTR_PLUS_ICEBP_C64   vcvtpd2dq, XMM8, YMM8
     1242
     1243;
     1244;; cvttpd2dq
     1245;
     1246; SSE-128, fp64 -> int32 (packed:2; truncated)
     1247EMIT_INSTR_PLUS_ICEBP       cvttpd2dq,  XMM1, XMM2
     1248EMIT_INSTR_PLUS_ICEBP       cvttpd2dq,  XMM1, FSxBX_O
     1249EMIT_INSTR_PLUS_ICEBP_C64   cvttpd2dq,  XMM8, XMM9
     1250EMIT_INSTR_PLUS_ICEBP_C64   cvttpd2dq,  XMM8, FSxBX_O
     1251; AVX-128, fp64 -> int32 (packed:2; truncated)
     1252EMIT_INSTR_PLUS_ICEBP       vcvttpd2dq, XMM1, XMM2
     1253EMIT_INSTR_PLUS_ICEBP       vcvttpd2dq, XMM1, FSxBX_O
     1254EMIT_INSTR_PLUS_ICEBP_C64   vcvttpd2dq, XMM8, XMM9
     1255EMIT_INSTR_PLUS_ICEBP_C64   vcvttpd2dq, XMM8, FSxBX_O
     1256; AVX-256, fp64 -> int32 (packed:4; truncated)
     1257EMIT_INSTR_PLUS_ICEBP       vcvttpd2dq, XMM1, YMM2
     1258EMIT_INSTR_PLUS_ICEBP       vcvttpd2dq, XMM1, FSxBX_Y
     1259EMIT_INSTR_PLUS_ICEBP_C64   vcvttpd2dq, XMM8, YMM9
     1260EMIT_INSTR_PLUS_ICEBP_C64   vcvttpd2dq, XMM8, FSxBX_Y
     1261; AVX-128, fp64 -> int32, same-reg (packed:2; truncated)
     1262EMIT_INSTR_PLUS_ICEBP       cvttpd2dq,  XMM1, XMM1
     1263EMIT_INSTR_PLUS_ICEBP_C64   cvttpd2dq,  XMM8, XMM8
     1264; AVX-128, fp64 -> int32, same-reg (packed:2; truncated)
     1265EMIT_INSTR_PLUS_ICEBP       vcvttpd2dq, XMM1, XMM1
     1266EMIT_INSTR_PLUS_ICEBP_C64   vcvttpd2dq, XMM8, XMM8
     1267; AVX-256, fp64 -> int32, same-reg (packed:4; truncated)
     1268EMIT_INSTR_PLUS_ICEBP       vcvttpd2dq, XMM1, YMM1
     1269EMIT_INSTR_PLUS_ICEBP_C64   vcvttpd2dq, XMM8, YMM8
     1270
     1271;
     1272;; cvtpd2ps
     1273;
     1274; SSE-128, fp64 -> fp32 (packed:2)
     1275EMIT_INSTR_PLUS_ICEBP       cvtpd2ps,  XMM1, XMM2
     1276EMIT_INSTR_PLUS_ICEBP       cvtpd2ps,  XMM1, FSxBX
     1277EMIT_INSTR_PLUS_ICEBP_C64   cvtpd2ps,  XMM8, XMM9
     1278EMIT_INSTR_PLUS_ICEBP_C64   cvtpd2ps,  XMM8, FSxBX
     1279; AVX-128, fp64 -> fp32 (packed:2)
     1280EMIT_INSTR_PLUS_ICEBP       vcvtpd2ps, XMM1, XMM2
     1281EMIT_INSTR_PLUS_ICEBP       vcvtpd2ps, XMM1, FSxBX_O
     1282EMIT_INSTR_PLUS_ICEBP_C64   vcvtpd2ps, XMM8, XMM9
     1283EMIT_INSTR_PLUS_ICEBP_C64   vcvtpd2ps, XMM8, FSxBX_O
     1284; AVX-256, fp64 -> fp32 (packed:4)
     1285EMIT_INSTR_PLUS_ICEBP       vcvtpd2ps, XMM1, YMM2
     1286EMIT_INSTR_PLUS_ICEBP       vcvtpd2ps, XMM1, FSxBX_Y
     1287EMIT_INSTR_PLUS_ICEBP_C64   vcvtpd2ps, XMM8, YMM9
     1288EMIT_INSTR_PLUS_ICEBP_C64   vcvtpd2ps, XMM8, FSxBX_Y
     1289; SSE-128, fp64 -> fp32, same-reg (packed:2)
     1290EMIT_INSTR_PLUS_ICEBP       cvtpd2ps,  XMM1, XMM1
     1291EMIT_INSTR_PLUS_ICEBP_C64   cvtpd2ps,  XMM8, XMM8
     1292; AVX-128, fp64 -> fp32, same-reg (packed:2)
     1293EMIT_INSTR_PLUS_ICEBP       vcvtpd2ps, XMM1, XMM1
     1294EMIT_INSTR_PLUS_ICEBP_C64   vcvtpd2ps, XMM8, XMM8
     1295; AVX-256, fp64 -> fp32, same-reg (packed:4)
     1296EMIT_INSTR_PLUS_ICEBP       vcvtpd2ps, XMM1, YMM1
     1297EMIT_INSTR_PLUS_ICEBP_C64   vcvtpd2ps, XMM8, YMM8
     1298
     1299;
     1300;; cvtps2pd
     1301;
     1302; SSE-128, fp32 -> fp64 (packed:2)
     1303EMIT_INSTR_PLUS_ICEBP       cvtps2pd,  XMM1, XMM2
     1304EMIT_INSTR_PLUS_ICEBP       cvtps2pd,  XMM1, FSxBX
     1305EMIT_INSTR_PLUS_ICEBP_C64   cvtps2pd,  XMM8, XMM9
     1306EMIT_INSTR_PLUS_ICEBP_C64   cvtps2pd,  XMM8, FSxBX
     1307; AVX-128, fp32 -> fp64 (packed:2)
     1308EMIT_INSTR_PLUS_ICEBP       vcvtps2pd, XMM1, XMM2
     1309EMIT_INSTR_PLUS_ICEBP       vcvtps2pd, XMM1, FSxBX
     1310EMIT_INSTR_PLUS_ICEBP_C64   vcvtps2pd, XMM8, XMM9
     1311EMIT_INSTR_PLUS_ICEBP_C64   vcvtps2pd, XMM8, FSxBX
     1312; AVX-256, fp32 -> fp64 (packed:4)
     1313EMIT_INSTR_PLUS_ICEBP       vcvtps2pd, YMM1, XMM2
     1314EMIT_INSTR_PLUS_ICEBP       vcvtps2pd, YMM1, FSxBX_O
     1315EMIT_INSTR_PLUS_ICEBP_C64   vcvtps2pd, YMM8, XMM9
     1316EMIT_INSTR_PLUS_ICEBP_C64   vcvtps2pd, YMM8, FSxBX_O
     1317; SSE-128, fp32 -> fp64, same-reg (packed:2)
     1318EMIT_INSTR_PLUS_ICEBP       cvtps2pd,  XMM1, XMM1
     1319EMIT_INSTR_PLUS_ICEBP_C64   cvtps2pd,  XMM8, XMM8
     1320; AVX-128, fp32 -> fp64, same-reg (packed:2)
     1321EMIT_INSTR_PLUS_ICEBP       vcvtps2pd, XMM1, XMM1
     1322EMIT_INSTR_PLUS_ICEBP_C64   vcvtps2pd, XMM8, XMM8
     1323; AVX-256, fp32 -> fp64, same-reg (packed:4)
     1324EMIT_INSTR_PLUS_ICEBP       vcvtps2pd, YMM1, XMM1
     1325EMIT_INSTR_PLUS_ICEBP_C64   vcvtps2pd, YMM8, XMM8
     1326
     1327;
     1328;; cvtsd2ss
     1329;
     1330; SSE-128, fp64 -> fp32 (single)
     1331EMIT_INSTR_PLUS_ICEBP       cvtsd2ss,  XMM1, XMM2
     1332EMIT_INSTR_PLUS_ICEBP       cvtsd2ss,  XMM1, FSxBX
     1333EMIT_INSTR_PLUS_ICEBP_C64   cvtsd2ss,  XMM8, XMM9
     1334EMIT_INSTR_PLUS_ICEBP_C64   cvtsd2ss,  XMM8, FSxBX
     1335; AVX-128, fp64 -> fp32 (single)
     1336EMIT_INSTR_PLUS_ICEBP       vcvtsd2ss, XMM1, XMM2, XMM3
     1337EMIT_INSTR_PLUS_ICEBP       vcvtsd2ss, XMM1, XMM2, FSxBX
     1338EMIT_INSTR_PLUS_ICEBP_C64   vcvtsd2ss, XMM8, XMM9, XMM10
     1339EMIT_INSTR_PLUS_ICEBP_C64   vcvtsd2ss, XMM8, XMM9, FSxBX
     1340; SSE-128, fp64 -> fp32, same-reg (single)
     1341EMIT_INSTR_PLUS_ICEBP       cvtsd2ss,  XMM1, XMM1
     1342EMIT_INSTR_PLUS_ICEBP_C64   cvtsd2ss,  XMM8, XMM8
     1343; AVX-128, fp64 -> fp32, same-reg (single)
     1344EMIT_INSTR_PLUS_ICEBP       vcvtsd2ss, XMM1, XMM1, XMM1
     1345EMIT_INSTR_PLUS_ICEBP_C64   vcvtsd2ss, XMM1, XMM1, XMM8
     1346EMIT_INSTR_PLUS_ICEBP_C64   vcvtsd2ss, XMM1, XMM8, XMM8
     1347EMIT_INSTR_PLUS_ICEBP_C64   vcvtsd2ss, XMM1, XMM8, XMM1
     1348EMIT_INSTR_PLUS_ICEBP       vcvtsd2ss, XMM1, XMM1, FSxBX
     1349EMIT_INSTR_PLUS_ICEBP_C64   vcvtsd2ss, XMM8, XMM8, XMM8
     1350EMIT_INSTR_PLUS_ICEBP_C64   vcvtsd2ss, XMM8, XMM8, FSxBX
     1351; @todo test with VEX.L=1 (as if asking for YMM)?  SDM says 'unpredictable behavior'...
     1352
     1353;
     1354;; cvtss2sd
     1355;
     1356; SSE-128, fp32 -> fp64 (single)
     1357EMIT_INSTR_PLUS_ICEBP       cvtss2sd,  XMM1, XMM2
     1358EMIT_INSTR_PLUS_ICEBP       cvtss2sd,  XMM1, FSxBX
     1359EMIT_INSTR_PLUS_ICEBP_C64   cvtss2sd,  XMM8, XMM9
     1360EMIT_INSTR_PLUS_ICEBP_C64   cvtss2sd,  XMM8, FSxBX
     1361; AVX-128, fp32 -> fp64 (single)
     1362EMIT_INSTR_PLUS_ICEBP       vcvtss2sd, XMM1, XMM2, XMM3
     1363EMIT_INSTR_PLUS_ICEBP       vcvtss2sd, XMM1, XMM2, FSxBX
     1364EMIT_INSTR_PLUS_ICEBP_C64   vcvtss2sd, XMM8, XMM9, XMM10
     1365EMIT_INSTR_PLUS_ICEBP_C64   vcvtss2sd, XMM8, XMM9, FSxBX
     1366; SSE-128, fp32 -> fp64, same-reg (single)
     1367EMIT_INSTR_PLUS_ICEBP       cvtss2sd,  XMM1, XMM1
     1368EMIT_INSTR_PLUS_ICEBP_C64   cvtss2sd,  XMM8, XMM8
     1369; AVX-128, fp32 -> fp64, same-reg (single)
     1370EMIT_INSTR_PLUS_ICEBP       vcvtss2sd, XMM1, XMM1, XMM1
     1371EMIT_INSTR_PLUS_ICEBP_C64   vcvtss2sd, XMM1, XMM1, XMM8
     1372EMIT_INSTR_PLUS_ICEBP_C64   vcvtss2sd, XMM1, XMM8, XMM8
     1373EMIT_INSTR_PLUS_ICEBP_C64   vcvtss2sd, XMM1, XMM8, XMM1
     1374EMIT_INSTR_PLUS_ICEBP       vcvtss2sd, XMM1, XMM1, FSxBX
     1375EMIT_INSTR_PLUS_ICEBP_C64   vcvtss2sd, XMM8, XMM8, XMM8
     1376EMIT_INSTR_PLUS_ICEBP_C64   vcvtss2sd, XMM8, XMM8, FSxBX
     1377; @todo test with VEX.L=1 (as if asking for YMM)?  SDM says 'unpredictable behavior'...
     1378
    8481379%endif ; BS3_INSTANTIATING_CMN
    8491380
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