Changeset 106677 in vbox

Timestamp:

Oct 25, 2024 6:22:09 AM (5 months ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

165545

Message:

ValidationKit/bootsectors: SIMD FP testcases for 'cvt' family instructions: improve error reporting; bugref:10658; jiraref:VBP-1206

• issue error reports from inner worker, so full details can be included
• put mask details next to each other
• add a few missing, and remove a few duplicate 'addps' testcases

File:

• trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32 (modified) (12 diffs)

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32

@@ -2593 +2593 @@
     uint8_t                              bXcptExpect;  /**< The expected exception while/after executing the instruction. */
     uint16_t                             idTestStep;   /**< The test iteration step. */
+    const char BS3_FAR                  *pszTestIdStr; /**< The test ID string for error printouts. */
 } BS3CPUINSTR4_TEST1_CTX_T;
 /** Pointer to a test 1 context. */
@@ -2634 +2635 @@
  * Worker for bs3CpuInstr4_WorkerTestType1.
  */
-static uint16_t bs3CpuInstr4_WorkerTestType1_Inner(uint8_t bMode, PBS3CPUINSTR4_TEST1_CTX_T pTestCtx,
+static void bs3CpuInstr4_WorkerTestType1_Inner(uint8_t bMode, PBS3CPUINSTR4_TEST1_CTX_T pTestCtx,
                                                    PCBS3CPUINSTRX_CONFIG_SAVED_T pSavedCfg)
 {
@@ -2656 +2657 @@
     X86YMMREG        MemOpExpect;
     uint16_t         cErrors;
-    uint16_t         cErrorsInit         = Bs3TestSubErrorCount();
     uint32_t         uExpectedMxCsr;
     bool             fFpXcptExpected;
+    uint8_t          cbBytesExecuted;
 
     uint32_t uSpecifiedMask, uExpectedMask, uImpliedMask, uCombinedMask, uMaskedMask, uUnmaskedMask, uThisMask;
@@ -2666 +2667 @@
     uint32_t uForceOnMask, uForceOffMask;
     static const char * const s_apszMaskType[] = { "Specified", "Expected", "Implied", "Combined", "Masked", "Unmasked", "Random" };
+    static const char * const s_apszMaskTyp[] =  { "spec",      "expc",     "impl",    "comb",     "mask",   "umsk",     "rand"   };
     unsigned iMaskType;
 
@@ -2868 +2870 @@
          * Prepare globals and execute.
          */
-        g_uBs3TrapEipHint = pCtx->rip.u32;
-        if (fNonFpOK && !fFpXcptExpected)
-            g_uBs3TrapEipHint += cbInstr + 1;
+        cbBytesExecuted = (fNonFpOK && !fFpXcptExpected) ? cbInstr + 1 : 0;
+        g_uBs3TrapEipHint = pCtx->rip.u32 + cbBytesExecuted;
         Bs3TrapSetJmpAndRestoreWithExtCtxAndRm(pCtx, pExtCtx, pTrapFrame, pExtCtxOut);
 
@@ -2921 +2922 @@
                 bs3CpuInstr4GetXcptMasks(&szGotMasks[0],   sizeof(szGotMasks),  uGotMxCsr);
                 bs3CpuInstr4GetXcptOthers(&szGotOthers[0], sizeof(szGotOthers), uGotMxCsr);
+                Bs3TestFailedF("mask-mode %s, mask=%#RX32, in-except=%#RX32, expect-raise=%#RX32, in-MXCSR=%#RX32", s_apszMaskType[iMaskType], uThisMask, uInitialExceptions, uExpectedExceptions, uMxCsr);
                 Bs3TestFailedF("Expected MXCSR %#RX32 (%s%s%s ) got MXCSR %#RX32 (%s%s%s )", uExpectedMxCsr,
                                szExpectFlags, szExpectMasks, szExpectOthers, uGotMxCsr, szGotFlags, szGotMasks, szGotOthers);
@@ -2952 +2954 @@
         if (bXcptExpect == X86_XCPT_PF)
             pCtx->cr2.u = (uintptr_t)puMemOp;
-        Bs3TestCheckRegCtxEx(&pTrapFrame->Ctx, pCtx, fNonFpOK && !fFpXcptExpected ? cbInstr + 1 : 0, 0 /*cbSpAdjust*/,
+        Bs3TestCheckRegCtxEx(&pTrapFrame->Ctx, pCtx, cbBytesExecuted, 0 /*cbSpAdjust*/,
                              (fNonFpOK && !fFpXcptExpected) || BS3_MODE_IS_16BIT_SYS(bMode) ? 0 : X86_EFL_RF,
                              pTestCtx->pszMode, pTestCtx->idTestStep);
@@ -2961 +2963 @@
 
         if (cErrors != Bs3TestSubErrorCount())
-            Bs3TestFailedF("Mask mode %s, mask=%#RX32, in-exceptions=%#RX32, in-MxCsr=%#RX32, expect-MxCsr=%#RX32", s_apszMaskType[iMaskType], uThisMask, uInitialExceptions, uMxCsr, uExpectedMxCsr);
+        {
+#define PUMEMOP_MAXSIZE sizeof("puMemOp=0x0123456789abcdef, EFLAGS=0x01234567, ")
+            char szPuMemOpStr[PUMEMOP_MAXSIZE] = "";
+
+            if (!pTestCtx->pConfig->fAligned)
+                Bs3StrPrintf(szPuMemOpStr, PUMEMOP_MAXSIZE, "puMemOp=%p, EFLAGS=%#RX32, ", puMemOp, pTestCtx->pTrapFrame->Ctx.rflags.u32);
+            Bs3TestFailedF("%s/%s failed (bXcptExpect=%u %s, %s%s-%u)",
+                           pTestCtx->pszTestIdStr, s_apszMaskTyp[iMaskType], bXcptExpect, bs3CpuInstr4XcptName(bXcptExpect),
+                           szPuMemOpStr, fSseInstr ? "SSE" : "AVX", pTestCtx->cbOperand * 8);
+            Bs3TestPrintf("\n");
+        }
     }
-
-    return cErrorsInit;
 }
 
@@ -3072 +3082 @@
                         for (iVal = 0; iVal < cValues; iVal++, idTestStep++, cRecompRuns++)
                         {
-                            uint16_t                 cErrors;
+#define TESTID_MAXSIZE sizeof("32-bit pae, v8086 pae: ring-3/(Normal)/tst#123/val#123")
+                            char szTestIdStr[TESTID_MAXSIZE];
                             BS3CPUINSTR4_TEST1_CTX_T TestCtx;
 
@@ -3101 +3112 @@
                             TestCtx.bXcptExpect  = bXcptExpect;
                             TestCtx.idTestStep   = idTestStep;
-                            cErrors = bs3CpuInstr4_WorkerTestType1_Inner(bMode, &TestCtx, &SavedCfg);
-                            if (cErrors != Bs3TestSubErrorCount())
-                            {
-#define PUMEMOP_MAXLEN          sizeof("puMemOp=0x0123456789abcdef, EFLAGS=0x01234567, ")
-                                char szPuMemOpStr[PUMEMOP_MAXLEN] = "";
-
-                                if (!paConfigs[iCfg].fAligned)
-                                    Bs3StrPrintf(szPuMemOpStr, PUMEMOP_MAXLEN, "puMemOp=%p, EFLAGS=%#RX32, ", puMemOp, TrapFrame.Ctx.rflags.u32);
-                                Bs3TestFailedF("%s: ring-%d/%u:%s/tst#%u/val#%u failed (bXcptExpect=%u %s, %s%s-%u)",
-                                               Bs3GetModeName(bMode), bRing, iCfg, paConfigs[iCfg].pszCfgName, iTest, iVal, bXcptExpect,
-                                               bs3CpuInstr4XcptName(bXcptExpect), szPuMemOpStr, fSseInstr ? "SSE" : "AVX", cbOperand * 8);
-                                Bs3TestPrintf("\n");
-                            }
+                            Bs3StrPrintf(szTestIdStr, TESTID_MAXSIZE, "%s: ring-%d/%u:%s/tst#%u/val#%u",
+                                         pszMode, bRing, iCfg, paConfigs[iCfg].pszCfgName, iTest, iVal);
+                            TestCtx.pszTestIdStr = szTestIdStr;
+
+                            bs3CpuInstr4_WorkerTestType1_Inner(bMode, &TestCtx, &SavedCfg);
                         }
                     }
@@ -3503 +3506 @@
         { bs3CpuInstr4_vaddps_YMM1_YMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, YMM1, YMM2, FSxBX, PASS_s_aValues   },
 
-        { bs3CpuInstr4_addps_XMM1_XMM1_icebp_c64,        255, RM_REG, T_SSE,     XMM1, XMM1, XMM1,  PASS_s_aValuesSR },
-        { bs3CpuInstr4_vaddps_YMM1_YMM1_YMM1_icebp_c64,  255, RM_REG, T_AVX_256, YMM1, YMM1, YMM1,  PASS_s_aValuesSR },
-        { bs3CpuInstr4_vaddps_YMM1_YMM1_YMM2_icebp_c64,  255, RM_REG, T_AVX_256, YMM1, YMM1, YMM2,  PASS_s_aValuesSR },
-        { bs3CpuInstr4_vaddps_YMM1_YMM1_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, YMM1, YMM1, FSxBX, PASS_s_aValuesSR },
+        { bs3CpuInstr4_addps_XMM8_XMM9_icebp_c64,        255, RM_REG, T_SSE,     XMM8, XMM8, XMM9,  PASS_s_aValues   },
+        { bs3CpuInstr4_addps_XMM8_FSxBX_icebp_c64,       255, RM_MEM, T_SSE,     XMM8, XMM8, FSxBX, PASS_s_aValues   },
+
+        { bs3CpuInstr4_vaddps_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, XMM8, XMM9, XMM10, PASS_s_aValues   },
+        { bs3CpuInstr4_vaddps_XMM8_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, XMM8, XMM9, FSxBX, PASS_s_aValues   },
+        { bs3CpuInstr4_vaddps_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX_256, YMM8, YMM9, YMM10, PASS_s_aValues   },
+        { bs3CpuInstr4_vaddps_YMM8_YMM9_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, YMM8, YMM9, FSxBX, PASS_s_aValues   },
 
         { bs3CpuInstr4_addps_XMM1_XMM1_icebp_c64,        255, RM_REG, T_SSE,     XMM1, XMM1, XMM1,  PASS_s_aValuesSR },
@@ -4500 +4506 @@
         { bs3CpuInstr4_addsd_XMM8_FSxBX_icebp_c64,       X86_XCPT_AC, RM_MEM, T_SSE,     XMM8, XMM8, FSxBX, PASS_s_aValues   },
 
-        { bs3CpuInstr4_vaddsd_XMM8_XMM9_XMM10_icebp_c64, 255,         RM_REG, T_AVX_128, XMM8, XMM9, XMM10,  PASS_s_aValues   },
+        { bs3CpuInstr4_vaddsd_XMM8_XMM9_XMM10_icebp_c64, 255,         RM_REG, T_AVX_128, XMM8, XMM9, XMM10, PASS_s_aValues   },
         { bs3CpuInstr4_vaddsd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, XMM8, XMM9, FSxBX, PASS_s_aValues   },