Changeset 106679 in vbox

Timestamp:

Oct 25, 2024 8:55:05 AM (6 months ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

165549

Message:

Disasembler: Decode unprivileged load/store instructions, bugref:10394

Location:

trunk/src/VBox/Disassembler

Files:

• DisasmTables-armv8-a64.cpp (modified) (3 diffs)
• testcase/tstDisasmArmv8-1-asm.S (modified) (2 diffs)

trunk/src/VBox/Disassembler/DisasmTables-armv8-a64.cpp

@@ -1042 +1042 @@
     DIS_ARMV8_OP(0x78000400, "strh",            OP_ARMV8_A64_STRH,      DISOPTYPE_HARMLESS),
     DIS_ARMV8_OP(0x78400400, "ldrh",            OP_ARMV8_A64_LDRH,      DISOPTYPE_HARMLESS),
- DIS_ARMV8_OP_EX(0x78800400, "ldrsh",           OP_ARMV8_A64_LDURSH,    DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
- DIS_ARMV8_OP_EX(0x78c00400, "ldrsh",           OP_ARMV8_A64_LDURSH,    DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
+ DIS_ARMV8_OP_EX(0x78800400, "ldrsh",           OP_ARMV8_A64_LDRSH,     DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
+ DIS_ARMV8_OP_EX(0x78c00400, "ldrsh",           OP_ARMV8_A64_LDRSH,     DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
     DIS_ARMV8_OP(0xb8000400, "str",             OP_ARMV8_A64_STR,       DISOPTYPE_HARMLESS),
     DIS_ARMV8_OP(0xb8400400, "ldr",             OP_ARMV8_A64_LDR,       DISOPTYPE_HARMLESS),
- DIS_ARMV8_OP_EX(0xb8800400, "ldrsw",           OP_ARMV8_A64_LDURSW,    DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
+ DIS_ARMV8_OP_EX(0xb8800400, "ldrsw",           OP_ARMV8_A64_LDRSW,     DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
     INVALID_OPCODE,
     DIS_ARMV8_OP(0xf8000400, "str",             OP_ARMV8_A64_STR,       DISOPTYPE_HARMLESS),
@@ -1074 +1074 @@
 
 /*
+ * STTRB/LDTRB/LDTRSB/STTRH/LDTRH/LDTRSH/LDTRSH/STTR/LDTR/LDTRSW/STTR/LDTR
+ *
+ * Note: The size,opc bitfields are concatenated to form an index.
+ */
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegUnpriv)
+    DIS_ARMV8_INSN_DECODE(kDisParmParseSize,               30,  2, DIS_ARMV8_INSN_PARAM_UNSET),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr,               0,  5, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp,           5,  5, 1 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOffUnscaled, 12,  9, 1 /*idxParam*/),
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegUnpriv)
+    DIS_ARMV8_OP(0x38000800, "sttrb",           OP_ARMV8_A64_STTRB,     DISOPTYPE_HARMLESS),
+    DIS_ARMV8_OP(0x38400800, "ldtrb",           OP_ARMV8_A64_LDTRB,     DISOPTYPE_HARMLESS),
+ DIS_ARMV8_OP_EX(0x38800800, "ldtrsb",          OP_ARMV8_A64_LDTRSB,    DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
+ DIS_ARMV8_OP_EX(0x38c00800, "ldtrsb",          OP_ARMV8_A64_LDTRSB,    DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
+    DIS_ARMV8_OP(0x78000800, "sttrh",           OP_ARMV8_A64_STTRH,     DISOPTYPE_HARMLESS),
+    DIS_ARMV8_OP(0x78400800, "ldtrh",           OP_ARMV8_A64_LDTRH,     DISOPTYPE_HARMLESS),
+ DIS_ARMV8_OP_EX(0x78800800, "ldtrsh",          OP_ARMV8_A64_LDTRSH,    DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
+ DIS_ARMV8_OP_EX(0x78c00800, "ldtrsh",          OP_ARMV8_A64_LDTRSH,    DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
+    DIS_ARMV8_OP(0xb8000800, "sttr",            OP_ARMV8_A64_STTR,      DISOPTYPE_HARMLESS),
+    DIS_ARMV8_OP(0xb8400800, "ldtr",            OP_ARMV8_A64_LDTR,      DISOPTYPE_HARMLESS),
+ DIS_ARMV8_OP_EX(0xb8800800, "ldtrsw",          OP_ARMV8_A64_LDTRSW,    DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
+    INVALID_OPCODE,
+    DIS_ARMV8_OP(0xf8000800, "sttr",            OP_ARMV8_A64_STTR,      DISOPTYPE_HARMLESS),
+    DIS_ARMV8_OP(0xf8400800, "ldtr",            OP_ARMV8_A64_LDTR,      DISOPTYPE_HARMLESS),
+    INVALID_OPCODE,
+    INVALID_OPCODE,
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegUnpriv, 0xffe00c00 /*fFixedInsn*/,
+                                       kDisArmV8OpcDecodeCollate,
+                                       RT_BIT_32(22) | RT_BIT_32(23) | RT_BIT_32(30) | RT_BIT_32(31), 22);
+
+
+/*
  * C4.1.94 - Loads and Stores - Load/Store register variants
  *
@@ -1088 +1120 @@
     DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegUnscaledImm),
     DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegImmPostIndex),
-    DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,         /** @todo */
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegUnpriv),       /* No vector variants. */
     DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegImmPreIndex),
 DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegOp2_11_0, RT_BIT_32(10) | RT_BIT_32(11), 10);

trunk/src/VBox/Disassembler/testcase/tstDisasmArmv8-1-asm.S

@@ -787 +787 @@
         ldursw x0, [sp, #255]
 
+
+        ldtrb w0, [x28]
+        ldtrb w0, [x28, #-256]
+        ldtrb w0, [x28, #255]
+
+        ldtrb w0, [sp]
+        ldtrb w0, [sp, #-256]
+        ldtrb w0, [sp, #255]
+
+        ldtrsb w0, [x28]
+        ldtrsb w0, [x28, #-256]
+        ldtrsb w0, [x28, #255]
+
+        ldtrsb w0, [sp]
+        ldtrsb w0, [sp, #-256]
+        ldtrsb w0, [sp, #255]
+
+        ldtrsb x0, [x28]
+        ldtrsb x0, [x28, #-256]
+        ldtrsb x0, [x28, #255]
+
+        ldtrsb x0, [sp]
+        ldtrsb x0, [sp, #-256]
+        ldtrsb x0, [sp, #255]
+
+        ldtrh w0, [x28]
+        ldtrh w0, [x28, #-256]
+        ldtrh w0, [x28, #255]
+
+        ldtrh w0, [sp]
+        ldtrh w0, [sp, #-256]
+        ldtrh w0, [sp, #255]
+
+        ldtrsh w0, [x28]
+        ldtrsh w0, [x28, #-256]
+        ldtrsh w0, [x28, #255]
+
+        ldtrsh w0, [sp]
+        ldtrsh w0, [sp, #-256]
+        ldtrsh w0, [sp, #255]
+
+        ldtrsh x0, [x28]
+        ldtrsh x0, [x28, #-256]
+        ldtrsh x0, [x28, #255]
+
+        ldtrsh x0, [sp]
+        ldtrsh x0, [sp, #-256]
+        ldtrsh x0, [sp, #255]
+
+        ldtr x0, [x28]
+        ldtr x0, [x28, #-256]
+        ldtr x0, [x28, #255]
+
+        ldtr x0, [sp]
+        ldtr x0, [sp, #-256]
+        ldtr x0, [sp, #255]
+
+        ldtr w0, [x28]
+        ldtr w0, [x28, #-256]
+        ldtr w0, [x28, #255]
+
+        ldtr w0, [sp]
+        ldtr w0, [sp, #-256]
+        ldtr w0, [sp, #255]
+
+        ldtrsw x0, [x28]
+        ldtrsw x0, [x28, #-256]
+        ldtrsw x0, [x28, #255]
+
+        ldtrsw x0, [sp]
+        ldtrsw x0, [sp, #-256]
+        ldtrsw x0, [sp, #255]
+
+
         ldp w0, w1, [x28]
         ldp w0, w1, [x28, #4]
@@ -1072 +1146 @@
         stur w0, [sp, #-256]
         stur w0, [sp, #255]
+
+
+        sttrb w0, [x28]
+        sttrb w0, [x28, #-256]
+        sttrb w0, [x28, #255]
+
+        sttrb w0, [sp]
+        sttrb w0, [sp, #-256]
+        sttrb w0, [sp, #255]
+
+        sttrh w0, [x28]
+        sttrh w0, [x28, #-256]
+        sttrh w0, [x28, #255]
+
+        sttrh w0, [sp]
+        sttrh w0, [sp, #-256]
+        sttrh w0, [sp, #255]
+
+        sttr x0, [x28]
+        sttr x0, [x28, #-256]
+        sttr x0, [x28, #255]
+
+        sttr x0, [sp]
+        sttr x0, [sp, #-256]
+        sttr x0, [sp, #255]
+
+        sttr w0, [x28]
+        sttr w0, [x28, #-256]
+        sttr w0, [x28, #255]
+
+        sttr w0, [sp]
+        sttr w0, [sp, #-256]
+        sttr w0, [sp, #255]
+
 
         stp w0, w1, [x28]