Changeset 106692 in vbox for trunk/src/VBox/ValidationKit

Timestamp:

Oct 25, 2024 12:27:42 PM (6 months ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

165562

Message:

ValidationKit/bootsectors: Implement SIMD FP testcases for cvtpi2ps, and fix it in IEM; bugref:10658; jiraref:VBP-1206

IEM:

• fix IEM cvtpi2ps [mem] trashing the target register
• fix IEM cvtpi2ps [mem] sometimes leaving x87/MMX FTW in the wrong state

Valkit:

• fix Bs3ExtCtxSetReg() ability to load MMX registers
• add BS3_REGISTER_IS_MMX macro
• fix test worker's interaction with x87/MMX FTW
• add 'RAND_x6' FP32 value bars for use in tests of these instructions
• add wacky set of macros for injecting integers into FP data arrays
• implement cvtpi2ps tests

Location:

trunk/src/VBox/ValidationKit/bootsectors

Files:

• bs3-cpu-instr-4.c32 (modified) (4 diffs)
• bs3-cpu-instr-x-regs.c32 (modified) (2 diffs)

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32

@@ -252 +252 @@
  * intended to be used for for unused arguments in scalar instructions.
  */
-#define FP32_0_x7(a_Sign)                   FP32_0(a_Sign), FP32_0(a_Sign), FP32_0(a_Sign),      \
-                                            FP32_0(a_Sign), FP32_0(a_Sign), FP32_0(a_Sign),      \
-                                            FP32_0(a_Sign)
-#define FP32_RAND_x7_V0                     FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(0),   \
-                                            FP32_RAND_V3(0), FP32_NORM_V1(1), FP32_RAND_V5(1),   \
-                                            FP32_RAND_V6(0)
-#define FP32_RAND_x7_V1                     FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1),   \
-                                            FP32_RAND_V4(1), FP32_QNAN(0),    FP32_RAND_V2(1),   \
-                                            FP32_NORM_V0(1)
-#define FP32_RAND_x7_V2                     FP32_RAND_V1(0), FP32_RAND_V7(1), FP32_RAND_V6(1),   \
-                                            FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0),   \
-                                            FP32_INF(0)
-#define FP32_RAND_x7_V3                     FP32_RAND_V6(1), FP32_QNAN(0),    FP32_RAND_V2(1),   \
-                                            FP32_1(1),       FP32_RAND_V1(0), FP32_INF(1),       \
-                                            FP32_RAND_V5(0)
-#define FP32_RAND_x7_V4                     FP32_RAND_V4(1), FP32_RAND_V6(0), FP32_RAND_V0(0),   \
-                                            FP32_RAND_V2(1), FP32_RAND_V1(0), FP32_1(1),         \
-                                            FP32_SNAN_MAX(1)
-#define FP32_RAND_x7_V5                     FP32_RAND_V5(1),  FP32_RAND_V4(1), FP32_QNAN_MAX(1), \
-                                            FP32_QNAN_MAX(1), FP32_RAND_V1(0), FP32_RAND_V2(0),  \
-                                            FP32_RAND_V6(0)
-#define FP32_RAND_x7_V6                     FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V6(1),   \
-                                            FP32_RAND_V2(0), FP32_QNAN(1),    FP32_QNAN_V(1, 0), \
-                                            FP32_SNAN(1)
-#define FP32_RAND_x7_V7                     FP32_RAND_V7(0), FP32_RAND_V1(1),   FP32_RAND_V2(0), \
-                                            FP32_RAND_V6(1), FP32_QNAN_V(0, 1), FP32_RAND_V2(1), \
-                                            FP32_NORM_SAFE_INT_MAX(1)
+#define FP32_0_x6(a_Sign)                   FP32_0(a_Sign), FP32_0(a_Sign), FP32_0(a_Sign),      \
+                                            FP32_0(a_Sign), FP32_0(a_Sign), FP32_0(a_Sign)
+#define FP32_0_x7(a_Sign)                   FP32_0_x6(a_Sign), FP32_0(a_Sign)
+#define FP32_RAND_x6_V0                     FP32_RAND_V0(0), FP32_RAND_V1(1), FP32_RAND_V2(0),   \
+                                            FP32_RAND_V3(0), FP32_NORM_V1(1), FP32_RAND_V5(1)
+#define FP32_RAND_x7_V0                     FP32_RAND_x6_V0, FP32_RAND_V6(0)
+#define FP32_RAND_x6_V1                     FP32_RAND_V7(0), FP32_RAND_V6(0), FP32_RAND_V5(1),   \
+                                            FP32_RAND_V4(1), FP32_QNAN(0),    FP32_RAND_V2(1)
+#define FP32_RAND_x7_V1                     FP32_RAND_x6_V1, FP32_NORM_V0(1)
+#define FP32_RAND_x6_V2                     FP32_RAND_V1(0), FP32_RAND_V7(1), FP32_RAND_V6(1),   \
+                                            FP32_RAND_V2(1), FP32_RAND_V3(1), FP32_RAND_V4(0)
+#define FP32_RAND_x7_V2                     FP32_RAND_x6_V2, FP32_INF(0)
+#define FP32_RAND_x6_V3                     FP32_RAND_V6(1), FP32_QNAN(0),    FP32_RAND_V2(1),   \
+                                            FP32_1(1),       FP32_RAND_V1(0), FP32_INF(1)
+#define FP32_RAND_x7_V3                     FP32_RAND_x6_V3, FP32_RAND_V5(0)
+#define FP32_RAND_x6_V4                     FP32_RAND_V4(1), FP32_RAND_V6(0), FP32_RAND_V0(0),   \
+                                            FP32_RAND_V2(1), FP32_RAND_V1(0), FP32_1(1)
+#define FP32_RAND_x7_V4                     FP32_RAND_x6_V4, FP32_SNAN_MAX(1)
+#define FP32_RAND_x6_V5                     FP32_RAND_V5(1),  FP32_RAND_V4(1), FP32_QNAN_MAX(1), \
+                                            FP32_QNAN_MAX(1), FP32_RAND_V1(0), FP32_RAND_V2(0)
+#define FP32_RAND_x7_V5                     FP32_RAND_x6_V5, FP32_RAND_V6(0)
+#define FP32_RAND_x6_V6                     FP32_RAND_V1(1), FP32_RAND_V4(0), FP32_RAND_V6(1),   \
+                                            FP32_RAND_V2(0), FP32_QNAN(1),    FP32_QNAN_V(1, 0)
+#define FP32_RAND_x7_V6                     FP32_RAND_x6_V6, FP32_SNAN(1)
+#define FP32_RAND_x6_V7                     FP32_RAND_V7(0), FP32_RAND_V1(1),   FP32_RAND_V2(0), \
+                                            FP32_RAND_V6(1), FP32_QNAN_V(0, 1), FP32_RAND_V2(1)
+#define FP32_RAND_x7_V7                     FP32_RAND_x6_V7, FP32_NORM_SAFE_INT_MAX(1)
 #define FP32_ROW_UNUSED                     FP32_1(0),       FP32_RAND_x7_V0
 
@@ -2893 +2893 @@
         if (fNonFpOK)
         {
+            /* MMX instructions set FTW to 0xff 'all valid' (even if they MXCSR-fault) */
+            if (BS3_REGISTER_IS_MMX(pTest->iRegSrc1) || BS3_REGISTER_IS_MMX(pTest->iRegSrc2) || BS3_REGISTER_IS_MMX(pTest->iRegDst))
+                Bs3ExtCtxSetAbridgedFtw(pExtCtx, 0xff);
+
             if (fFuzzyPE)
             {
@@ -16308 +16312 @@
 
 
+#define FP32_INT_SIGN_PART(a_uInt32) ((((uint32_t)a_uInt32) >> 31) & 1)
+#define FP32_INT_EXPN_PART(a_uInt32) ((((uint32_t)a_uInt32) >> 23) & 0xFF)
+#define FP32_INT_FRAC_PART(a_uInt32) (((uint32_t)a_uInt32) & 0x7FFFFF)
+#define FP32_INT(a_uInt32) RTFLOAT32U_INIT(FP32_INT_SIGN_PART(a_uInt32), FP32_INT_FRAC_PART(a_uInt32), FP32_INT_EXPN_PART(a_uInt32))
+
+#define FP64_INT_SIGN_PART(a_uInt64) ((((uint64_t)a_uInt64) >> 63) & 1)
+#define FP64_INT_EXPN_PART(a_uInt64) ((((uint64_t)a_uInt64) >> 52) & 0x7FF)
+#define FP64_INT_FRAC_PART(a_uInt64) (((uint64_t)a_uInt64) & 0xFFFFFFFFFFFFF)
+#define FP64_INT(a_uInt64) RTFLOAT64U_INIT(FP64_INT_SIGN_PART(a_uInt64), FP64_INT_FRAC_PART(a_uInt64), FP64_INT_EXPN_PART(a_uInt64))
+
+/*
+ * CVTPI2PS.
+ */
+BS3_DECL_FAR(uint8_t) bs3CpuInstr4_cvtpi2ps(uint8_t bMode)
+{
+    static BS3CPUINSTR4_TEST1_VALUES_SS_T const s_aValues[] =
+    {
+    /*
+     * Zero.
+     */
+    /* 0*/{ { /*init dst */ { FP32_RAND_V1(0), FP32_RAND_V3(1), FP32_RAND_x6_V0 } },
+            { /*  mm src */ { FP32_INT(0),     FP32_INT(0),     FP32_RAND_x6_V2 } },
+            { /* =>      */ { FP32_0(0),       FP32_0(0),       FP32_RAND_x6_V0 } },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ -1 },
+
+    /*
+     * Normals & Precision.
+     */
+    /* 1*/{ { /*init dst */ { FP32_NORM_V0(0),         FP32_NORM_V4(0),         FP32_RAND_x6_V3 } },
+            { /*  mm src */ { FP32_INT(123456789),     FP32_INT(-123456789),    FP32_RAND_x6_V4 } },
+            { /* =>      */ { FP32_V(0,0x6b79a3,0x99), FP32_V(1,0x6b79a3,0x99), FP32_RAND_x6_V3 } },
+                              /*123456792.0*/          /*-123456792.0*/
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_PE,
+              /*256:out  */ -1 },
+          { { /*init dst */ { FP32_NORM_V1(0),         FP32_NORM_V7(0),         FP32_RAND_x6_V5 } },
+            { /*  mm src */ { FP32_INT(-47),           FP32_INT(42),            FP32_RAND_x6_V1 } },
+            { /* =>      */ { FP32_V(1,0x3c0000,0x84), FP32_V(0,0x280000,0x84), FP32_RAND_x6_V5 } },
+                              /*-47.0*/                /*42.0*/
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ -1 },
+          { { /*init dst */ { FP32_NORM_V0(0),     FP32_NORM_V4(0),      FP32_RAND_x6_V0 } },
+            { /*  mm src */ { FP32_INT(INT32_MAX), FP32_INT(-INT32_MAX), FP32_RAND_x6_V5 } },
+            { /* =>      */ { FP32_V(0,0,0x9e),    FP32_V(1,0,0x9e),     FP32_RAND_x6_V0 } },
+                              /*2147483648.0*/     /*-2147483648.0*/
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_PE,
+              /*256:out  */ -1 },
+          { { /*init dst */ { FP32_NORM_V0(0),         FP32_NORM_V4(0),         FP32_RAND_x6_V7 } },
+            { /*  mm src */ { FP32_INT(123456789),     FP32_INT(-123456789),    FP32_RAND_x6_V7 } },
+            { /* =>      */ { FP32_V(0,0x6b79a3,0x99), FP32_V(1,0x6b79a3,0x99), FP32_RAND_x6_V7 } },
+                              /*123456792.0*/          /*-123456792.0*/
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_DAZ,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_DAZ | X86_MXCSR_PE,
+              /*256:out  */ -1 },
+          { { /*init dst */ { FP32_NORM_V0(0),         FP32_NORM_V4(0),         FP32_RAND_x6_V6 } },
+            { /*  mm src */ { FP32_INT(123456789),     FP32_INT(-123456789),    FP32_RAND_x6_V4 } },
+            { /* =>      */ { FP32_V(0,0x6b79a2,0x99), FP32_V(1,0x6b79a3,0x99), FP32_RAND_x6_V6 } },
+                              /*123456784.0*/          /*-123456792.0*/
+              /*mxcsr:in */ X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_RC_DOWN | X86_MXCSR_PE,
+              /*256:out  */ -1 },
+          { { /*init dst */ { FP32_NORM_V0(0),         FP32_NORM_V4(0),         FP32_RAND_x6_V2 } },
+            { /*  mm src */ { FP32_INT(123456789),     FP32_INT(-123456789),    FP32_RAND_x6_V1 } },
+            { /* =>      */ { FP32_V(0,0x6b79a3,0x99), FP32_V(1,0x6b79a2,0x99), FP32_RAND_x6_V2 } },
+                              /*123456792.0*/          /*-123456784.0*/
+              /*mxcsr:in */ X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_RC_UP | X86_MXCSR_PE,
+              /*256:out  */ -1 },
+          { { /*init dst */ { FP32_NORM_V0(0),         FP32_NORM_V4(0),         FP32_RAND_x6_V0 } },
+            { /*  mm src */ { FP32_INT(123456789),     FP32_INT(-123456789),    FP32_RAND_x6_V5 } },
+            { /* =>      */ { FP32_V(0,0x6b79a2,0x99), FP32_V(1,0x6b79a2,0x99), FP32_RAND_x6_V0 } },
+                              /*123456784.0*/          /*-123456784.0*/
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
+              /*256:out  */ -1 },
+    };
+    /*
+     * Infinity, Overflow, Underflow, Invalids not possible.
+     */
+
+    static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
+    {
+        { bs3CpuInstr4_cvtpi2ps_XMM1_MM1_icebp_c16,   255, RM_REG, T_SSE, XMM1, MM1,   XMM1, PASS_s_aValues },
+        { bs3CpuInstr4_cvtpi2ps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, XMM1, FSxBX, XMM1, PASS_s_aValues },
+    };
+    static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
+    {
+        { bs3CpuInstr4_cvtpi2ps_XMM1_MM1_icebp_c32,   255, RM_REG, T_SSE, XMM1, MM1,   XMM1, PASS_s_aValues },
+        { bs3CpuInstr4_cvtpi2ps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, XMM1, FSxBX, XMM1, PASS_s_aValues },
+    };
+    static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
+    {
+        { bs3CpuInstr4_cvtpi2ps_XMM1_MM1_icebp_c64,   255, RM_REG, T_SSE, XMM1, MM1,   XMM1, PASS_s_aValues },
+        { bs3CpuInstr4_cvtpi2ps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, XMM1, FSxBX, XMM1, PASS_s_aValues },
+        { bs3CpuInstr4_cvtpi2ps_XMM8_MM1_icebp_c64,   255, RM_REG, T_SSE, XMM8, MM1,   XMM8, PASS_s_aValues },
+        { bs3CpuInstr4_cvtpi2ps_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, XMM8, FSxBX, XMM8, PASS_s_aValues },
+    };
+
+    static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
+    unsigned const                         iTest       = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
+    return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+                                        g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5));
+}
+
+
 /**
  * The 32-bit protected mode main function.
@@ -16365 +16478 @@
         { "[v]rsqrtps",     bs3CpuInstr4_v_rsqrtps,  0 },
         { "[v]rsqrtss",     bs3CpuInstr4_v_rsqrtss,  0 },
+        { "cvtpi2ps",       bs3CpuInstr4_cvtpi2ps,   0 },
 #endif
     };

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-x-regs.c32

@@ -334 +334 @@
 #define MM6     (BS3_REGISTER_FAMILY_MMX        | 6)
 #define MM7     (BS3_REGISTER_FAMILY_MMX        | 7)
+#define          BS3_REGISTER_IS_MMX(uReg)      ((uReg) >= MM0 && (uReg) <= MM7)
 
 #define          BS3_REGISTER_FAMILY_OPMASK     (0xE8 | BS3_REGISTER_FAMILY_AVX512_TODO)
@@ -490 +491 @@
                 return true;
             case BS3_REGISTER_FAMILY_OTHER:
-                if (uReg >= MM0 && uReg <= MM7)
-                    return Bs3ExtCtxSetMm(pExtCtx, uRegNum, (uint64_t)pValue, BS3EXTCTXTOPMM_SET);
+                if (BS3_REGISTER_IS_MMX(uReg))
+                    return Bs3ExtCtxSetMm(pExtCtx, uRegNum, *((uint64_t *)pValue), BS3EXTCTXTOPMM_AS_IS);
+                break;
             case BS3_REGISTER_FAMILY_8BIT_L:
             case BS3_REGISTER_FAMILY_ZMM: