Changeset 106694 in vbox

Timestamp:

Oct 25, 2024 12:55:26 PM (4 months ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

165565

Message:

Disassembler: Decode ldnp/stnp non temporal hint load/store instructions, bugref:10394

Location:

trunk/src/VBox/Disassembler

Files:

• DisasmTables-armv8-a64-ld-st.cpp.h (modified) (2 diffs)
• testcase/tstDisasmArmv8-1-asm.S (modified) (2 diffs)

trunk/src/VBox/Disassembler/DisasmTables-armv8-a64-ld-st.cpp.h

@@ -449 +449 @@
 
 /*
+ * stnp/LDNP - no-allocate variant.
+ *
+ * Note: The opc,L bitfields are concatenated to form an index.
+ */
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegPairNoAllocGpr)
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr,           0,  5, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr,          10,  5, 1 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp,       5,  5, 2 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOff,     15,  7, 2 /*idxParam*/),
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegPairNoAllocGpr)
+ DIS_ARMV8_OP_EX(0x28000000, "stnp",            OP_ARMV8_A64_STNP,      DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
+ DIS_ARMV8_OP_EX(0x28400000, "ldnp",            OP_ARMV8_A64_LDNP,      DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
+    INVALID_OPCODE,
+    INVALID_OPCODE,
+ DIS_ARMV8_OP_EX(0xa8000000, "stnp",            OP_ARMV8_A64_STNP,      DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
+ DIS_ARMV8_OP_EX(0xa8400000, "ldnp",            OP_ARMV8_A64_LDNP,      DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
+    INVALID_OPCODE,
+    INVALID_OPCODE,
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegPairNoAllocGpr, 0xffc00000 /*fFixedInsn*/,
+                                       kDisArmV8OpcDecodeCollate,
+                                       RT_BIT_32(22) | RT_BIT_32(30) | RT_BIT_32(31), 22);
+
+
+/*
+ * C4.1.94.21 - Loads and Stores - Load/Store register (immediate post-indexed) variants
+ *
+ * Differentiate further based on the VR field.
+ *
+ *     Bit  26
+ *     +-------------------------------------------
+ *           0 GPR variants.
+ *           1 SIMD/FP variants
+ */
+DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegPairNoAlloc)
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegPairNoAllocGpr),
+    DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,             /** @todo */
+DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegPairNoAlloc, RT_BIT_32(26), 26);
+
+
+/*
  * C4.1.94 - Loads and Stores - Load/Store register pair variants
  *
@@ -461 +501 @@
  */
 DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegPair)
-    DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,             /** @todo */
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegPairNoAlloc),
     DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegPairPostIndex),
     DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegPairOff),

trunk/src/VBox/Disassembler/testcase/tstDisasmArmv8-1-asm.S

@@ -919 +919 @@
         ldp x0, x1, [sp], #504
 
+        ldnp w0, w1, [x28]
+        ldnp w0, w1, [x28, #4]
+        ldnp w0, w1, [x28, #-256]
+        ldnp w0, w1, [x28, #252]
+
+        ldnp w0, w1, [sp]
+        ldnp w0, w1, [sp, #4]
+        ldnp w0, w1, [sp, #-256]
+        ldnp w0, w1, [sp, #252]
+
+        ldnp x0, x1, [x28]
+        ldnp x0, x1, [x28, #8]
+        ldnp x0, x1, [x28, #-512]
+        ldnp x0, x1, [x28, #504]
+
+        ldnp x0, x1, [sp]
+        ldnp x0, x1, [sp, #8]
+        ldnp x0, x1, [sp, #-512]
+        ldnp x0, x1, [sp, #504]
+
         ldr  x0, [x1, x2]
         ldr  w0, [x1, x2]
@@ -1238 +1258 @@
         stp x0, x1, [sp], #-512
         stp x0, x1, [sp], #504
+
+
+        stnp w0, w1, [x28]
+        stnp w0, w1, [x28, #4]
+        stnp w0, w1, [x28, #-256]
+        stnp w0, w1, [x28, #252]
+
+        stnp w0, w1, [sp]
+        stnp w0, w1, [sp, #4]
+        stnp w0, w1, [sp, #-256]
+        stnp w0, w1, [sp, #252]
+
+        stnp x0, x1, [x28]
+        stnp x0, x1, [x28, #8]
+        stnp x0, x1, [x28, #-512]
+        stnp x0, x1, [x28, #504]
+
+        stnp x0, x1, [sp]
+        stnp x0, x1, [sp, #8]
+        stnp x0, x1, [sp, #-512]
+        stnp x0, x1, [sp, #504]
+
 
         str  x0, [x1, x2]