Changeset 106721 in vbox
- Timestamp:
- Oct 26, 2024 3:47:35 AM (5 months ago)
- svn:sync-xref-src-repo-rev:
- 165604
- Location:
- trunk/src/VBox/ValidationKit/bootsectors
- Files:
-
- 3 edited
-
bs3-cpu-instr-4-template.mac (modified) (3 diffs)
-
bs3-cpu-instr-4.c32 (modified) (12 diffs)
-
bs3-cpu-instr-x-regs.c32 (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4-template.mac
r106676 r106721 879 879 EMIT_INSTR_PLUS_ICEBP_C64 cvtpi2ps, XMM8, MM1 880 880 EMIT_INSTR_PLUS_ICEBP_C64 cvtpi2ps, XMM8, FSxBX 881 ; note: transition from x87 FPU to MMX; takes FPU exceptions (SDM does not mention MM forms only?) 881 882 882 ; 883 883 ;; cvtps2pi … … 887 887 EMIT_INSTR_PLUS_ICEBP cvtps2pi, MM1, FSxBX 888 888 EMIT_INSTR_PLUS_ICEBP_C64 cvtps2pi, MM1, XMM8 889 ; note: transition from x87 FPU to MMX; takes FPU exceptions890 889 891 890 ; … … 896 895 EMIT_INSTR_PLUS_ICEBP cvttps2pi, MM1, FSxBX 897 896 EMIT_INSTR_PLUS_ICEBP_C64 cvttps2pi, MM1, XMM8 898 ; note: transition from x87 FPU to MMX; takes FPU exceptions 897 899 898 ; 900 899 ;; cvtsi2ss -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32
r106692 r106721 280 280 #define FP32_RAND_x7_V7 FP32_RAND_x6_V7, FP32_NORM_SAFE_INT_MAX(1) 281 281 #define FP32_ROW_UNUSED FP32_1(0), FP32_RAND_x7_V0 282 #define FP32_x6_UNUSED FP32_RAND_x6_V7 282 283 283 284 /* … … 16327 16328 BS3_DECL_FAR(uint8_t) bs3CpuInstr4_cvtpi2ps(uint8_t bMode) 16328 16329 { 16329 static BS3CPUINSTR4_TEST1_VALUES_ SS_T const s_aValues[] =16330 static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValues[] = 16330 16331 { 16331 16332 /* … … 16333 16334 */ 16334 16335 /* 0*/{ { /*init dst */ { FP32_RAND_V1(0), FP32_RAND_V3(1), FP32_RAND_x6_V0 } }, 16335 { /* mm src */ { FP32_INT(0), FP32_INT(0), FP32_RAND_x6_V2 } }, 16336 { /* => */ { FP32_0(0), FP32_0(0), FP32_RAND_x6_V0 } }, 16337 /*mxcsr:in */ 0, 16338 /*128:out */ 0, 16339 /*256:out */ -1 }, 16340 16336 { /* src mm */ { FP32_INT(0), FP32_INT(0), FP32_RAND_x6_V2 } }, 16337 { /* => xmm */ { FP32_0(0), FP32_0(0), FP32_RAND_x6_V0 } }, 16338 /*mxcsr:in */ 0, 16339 /*128:out */ 0, 16340 /*256:out */ -1 }, 16341 16341 /* 16342 16342 * Normals & Precision. 16343 16343 */ 16344 16344 /* 1*/{ { /*init dst */ { FP32_NORM_V0(0), FP32_NORM_V4(0), FP32_RAND_x6_V3 } }, 16345 { /* mm src*/ { FP32_INT(123456789), FP32_INT(-123456789), FP32_RAND_x6_V4 } },16346 { /* => 16345 { /* src mm */ { FP32_INT(123456789), FP32_INT(-123456789), FP32_RAND_x6_V4 } }, 16346 { /* => xmm */ { FP32_V(0,0x6b79a3,0x99), FP32_V(1,0x6b79a3,0x99), FP32_RAND_x6_V3 } }, 16347 16347 /*123456792.0*/ /*-123456792.0*/ 16348 16348 /*mxcsr:in */ 0, … … 16350 16350 /*256:out */ -1 }, 16351 16351 { { /*init dst */ { FP32_NORM_V1(0), FP32_NORM_V7(0), FP32_RAND_x6_V5 } }, 16352 { /* mm src*/ { FP32_INT(-47), FP32_INT(42), FP32_RAND_x6_V1 } },16353 { /* => 16352 { /* src mm */ { FP32_INT(-47), FP32_INT(42), FP32_RAND_x6_V1 } }, 16353 { /* => xmm */ { FP32_V(1,0x3c0000,0x84), FP32_V(0,0x280000,0x84), FP32_RAND_x6_V5 } }, 16354 16354 /*-47.0*/ /*42.0*/ 16355 16355 /*mxcsr:in */ 0, … … 16357 16357 /*256:out */ -1 }, 16358 16358 { { /*init dst */ { FP32_NORM_V0(0), FP32_NORM_V4(0), FP32_RAND_x6_V0 } }, 16359 { /* mm src*/ { FP32_INT(INT32_MAX), FP32_INT(-INT32_MAX), FP32_RAND_x6_V5 } },16360 { /* => 16359 { /* src mm */ { FP32_INT(INT32_MAX), FP32_INT(-INT32_MAX), FP32_RAND_x6_V5 } }, 16360 { /* => xmm */ { FP32_V(0,0,0x9e), FP32_V(1,0,0x9e), FP32_RAND_x6_V0 } }, 16361 16361 /*2147483648.0*/ /*-2147483648.0*/ 16362 16362 /*mxcsr:in */ 0, … … 16364 16364 /*256:out */ -1 }, 16365 16365 { { /*init dst */ { FP32_NORM_V0(0), FP32_NORM_V4(0), FP32_RAND_x6_V7 } }, 16366 { /* mm src*/ { FP32_INT(123456789), FP32_INT(-123456789), FP32_RAND_x6_V7 } },16367 { /* => 16366 { /* src mm */ { FP32_INT(123456789), FP32_INT(-123456789), FP32_RAND_x6_V7 } }, 16367 { /* => xmm */ { FP32_V(0,0x6b79a3,0x99), FP32_V(1,0x6b79a3,0x99), FP32_RAND_x6_V7 } }, 16368 16368 /*123456792.0*/ /*-123456792.0*/ 16369 16369 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_DAZ, … … 16371 16371 /*256:out */ -1 }, 16372 16372 { { /*init dst */ { FP32_NORM_V0(0), FP32_NORM_V4(0), FP32_RAND_x6_V6 } }, 16373 { /* mm src*/ { FP32_INT(123456789), FP32_INT(-123456789), FP32_RAND_x6_V4 } },16374 { /* => 16373 { /* src mm */ { FP32_INT(123456789), FP32_INT(-123456789), FP32_RAND_x6_V4 } }, 16374 { /* => xmm */ { FP32_V(0,0x6b79a2,0x99), FP32_V(1,0x6b79a3,0x99), FP32_RAND_x6_V6 } }, 16375 16375 /*123456784.0*/ /*-123456792.0*/ 16376 16376 /*mxcsr:in */ X86_MXCSR_RC_DOWN, … … 16378 16378 /*256:out */ -1 }, 16379 16379 { { /*init dst */ { FP32_NORM_V0(0), FP32_NORM_V4(0), FP32_RAND_x6_V2 } }, 16380 { /* mm src*/ { FP32_INT(123456789), FP32_INT(-123456789), FP32_RAND_x6_V1 } },16381 { /* => 16380 { /* src mm */ { FP32_INT(123456789), FP32_INT(-123456789), FP32_RAND_x6_V1 } }, 16381 { /* => xmm */ { FP32_V(0,0x6b79a3,0x99), FP32_V(1,0x6b79a2,0x99), FP32_RAND_x6_V2 } }, 16382 16382 /*123456792.0*/ /*-123456784.0*/ 16383 16383 /*mxcsr:in */ X86_MXCSR_RC_UP, … … 16385 16385 /*256:out */ -1 }, 16386 16386 { { /*init dst */ { FP32_NORM_V0(0), FP32_NORM_V4(0), FP32_RAND_x6_V0 } }, 16387 { /* mm src*/ { FP32_INT(123456789), FP32_INT(-123456789), FP32_RAND_x6_V5 } },16388 { /* => 16387 { /* src mm */ { FP32_INT(123456789), FP32_INT(-123456789), FP32_RAND_x6_V5 } }, 16388 { /* => xmm */ { FP32_V(0,0x6b79a2,0x99), FP32_V(1,0x6b79a2,0x99), FP32_RAND_x6_V0 } }, 16389 16389 /*123456784.0*/ /*-123456784.0*/ 16390 16390 /*mxcsr:in */ X86_MXCSR_RC_ZERO, … … 16393 16393 }; 16394 16394 /* 16395 * Infinity, Overflow, Underflow, Invalidsnot possible.16395 * Infinity, Overflow, Underflow, Denormal, Invalid not possible. 16396 16396 */ 16397 16397 … … 16412 16412 { bs3CpuInstr4_cvtpi2ps_XMM8_MM1_icebp_c64, 255, RM_REG, T_SSE, XMM8, MM1, XMM8, PASS_s_aValues }, 16413 16413 { bs3CpuInstr4_cvtpi2ps_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, XMM8, FSxBX, XMM8, PASS_s_aValues }, 16414 }; 16415 16416 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 16417 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode); 16418 return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 16419 g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5)); 16420 } 16421 16422 16423 /* 16424 * CVTPS2PI. 16425 */ 16426 BS3_DECL_FAR(uint8_t) bs3CpuInstr4_cvtps2pi(uint8_t bMode) 16427 { 16428 static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValues[] = 16429 { 16430 /* 16431 * Zero. 16432 */ 16433 /* 0*/{ { /* unused */ { FP32_ROW_UNUSED } }, 16434 { /* src xmm */ { FP32_0(0), FP32_0(1), FP32_RAND_x6_V1 } }, 16435 { /* => mm */ { FP32_INT(0), FP32_INT(0), FP32_x6_UNUSED } }, 16436 /*mxcsr:in */ 0, 16437 /*128:out */ 0, 16438 /*256:out */ -1 }, 16439 /* 16440 * Infinity. 16441 */ 16442 /* 1*/{ { /* unused */ { FP32_ROW_UNUSED } }, 16443 { /* src xmm */ { FP32_INF(1), FP32_INF(0), FP32_RAND_x6_V1 } }, 16444 { /* => mm */ { FP32_INT(INT32_MIN), FP32_INT(INT32_MIN), FP32_x6_UNUSED } }, 16445 /*mxcsr:in */ 0, 16446 /*128:out */ X86_MXCSR_IE, 16447 /*256:out */ -1 }, 16448 /* 16449 * Normals & Precision. 16450 */ 16451 /* 2*/{ { /* unused */ { FP32_ROW_UNUSED } }, 16452 { /* src xmm */ { FP32_V(0,0x712000,0x8f), FP32_V(1,0x712000,0x8f), FP32_RAND_x6_V0 } }, 16453 { /* => mm */ { FP32_INT(123456), FP32_INT(-123456), FP32_x6_UNUSED } }, 16454 /*mxcsr:in */ 0, 16455 /*128:out */ 0, 16456 /*256:out */ -1 }, 16457 { { /* unused */ { FP32_ROW_UNUSED } }, 16458 { /* src xmm */ { FP32_V(0,0x71200d,0x8f), FP32_V(1,0x71200d,0x8f), FP32_RAND_x6_V2 } }, 16459 /*123456.1*/ /*-123456.1*/ 16460 { /* => mm */ { FP32_INT(123456), FP32_INT(-123456), FP32_x6_UNUSED } }, 16461 /*mxcsr:in */ 0, 16462 /*128:out */ X86_MXCSR_PE, 16463 /*256:out */ -1 }, 16464 { { /* unused */ { FP32_ROW_UNUSED } }, 16465 { /* src xmm */ { FP32_V(0,0x71200d,0x8f), FP32_V(1,0x71200d,0x8f), FP32_RAND_x6_V2 } }, 16466 /*123456.1*/ /*-123456.1*/ 16467 { /* => mm */ { FP32_INT(123456), FP32_INT(-123457), FP32_x6_UNUSED } }, 16468 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 16469 /*128:out */ X86_MXCSR_PE | X86_MXCSR_RC_DOWN, 16470 /*256:out */ -1 }, 16471 { { /* unused */ { FP32_ROW_UNUSED } }, 16472 { /* src xmm */ { FP32_V(0,0x71200d,0x8f), FP32_V(1,0x71200d,0x8f), FP32_RAND_x6_V2 } }, 16473 /*123456.1*/ /*-123456.1*/ 16474 { /* => mm */ { FP32_INT(123457), FP32_INT(-123456), FP32_x6_UNUSED } }, 16475 /*mxcsr:in */ X86_MXCSR_RC_UP, 16476 /*128:out */ X86_MXCSR_PE | X86_MXCSR_RC_UP, 16477 /*256:out */ -1 }, 16478 { { /* unused */ { FP32_ROW_UNUSED } }, 16479 { /* src xmm */ { FP32_V(0,0x71200d,0x8f), FP32_V(1,0x71200d,0x8f), FP32_RAND_x6_V2 } }, 16480 /*123456.1*/ /*-123456.1*/ 16481 { /* => mm */ { FP32_INT(123456), FP32_INT(-123456), FP32_x6_UNUSED } }, 16482 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 16483 /*128:out */ X86_MXCSR_PE | X86_MXCSR_RC_ZERO, 16484 /*256:out */ -1 }, 16485 { { /* unused */ { FP32_ROW_UNUSED } }, 16486 { /* src xmm */ { FP32_V(1,0x666666,0x7e), FP32_V(0,0x666666,0x7e), FP32_RAND_x6_V2 } }, 16487 /*-0.9*/ /*0.9*/ 16488 { /* => mm */ { FP32_INT(-1), FP32_INT(1), FP32_x6_UNUSED } }, 16489 /*mxcsr:in */ X86_MXCSR_FZ, 16490 /*128:out */ X86_MXCSR_PE | X86_MXCSR_FZ, 16491 /*256:out */ -1 }, 16492 { { /* unused */ { FP32_ROW_UNUSED } }, 16493 { /* src xmm */ { FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x6_V2 } }, 16494 { /* => mm */ { FP32_INT(-16777215), FP32_INT(16777215), FP32_x6_UNUSED } }, 16495 /*mxcsr:in */ 0, 16496 /*128:out */ 0, 16497 /*256:out */ -1 }, 16498 /* 16499 * Denormals. 16500 */ 16501 /* 9*/{ { /* unused */ { FP32_ROW_UNUSED } }, 16502 { /* src xmm */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_RAND_x6_V2 } }, 16503 { /* => mm */ { FP32_INT(0), FP32_INT(0), FP32_x6_UNUSED } }, 16504 /*mxcsr:in */ 0, 16505 /*128:out */ X86_MXCSR_PE, 16506 /*256:out */ -1 }, 16507 { { /* unused */ { FP32_ROW_UNUSED } }, 16508 { /* src xmm */ { FP32_DENORM_MIN(0), FP32_DENORM_MAX(1), FP32_RAND_x6_V2 } }, 16509 { /* => mm */ { FP32_INT(0), FP32_INT(0), FP32_x6_UNUSED } }, 16510 /*mxcsr:in */ X86_MXCSR_DAZ, 16511 /*128:out */ X86_MXCSR_DAZ, 16512 /*256:out */ -1 }, 16513 /* 16514 * Overflow (Underflow not possible). 16515 */ 16516 /*11*/{ { /* unused */ { FP32_ROW_UNUSED } }, 16517 { /* src xmm */ { FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_RAND_x6_V2 } }, 16518 { /* => mm */ { FP32_INT(INT32_MIN), FP32_INT(INT32_MIN), FP32_x6_UNUSED } }, 16519 /*mxcsr:in */ 0, 16520 /*128:out */ X86_MXCSR_IE, 16521 /*256:out */ -1 }, 16522 /* 16523 * Invalids. 16524 */ 16525 /*12*/{ { /* unused */ { FP32_ROW_UNUSED } }, 16526 { /* src xmm */ { FP32_QNAN(0), FP32_QNAN(1), FP32_RAND_x6_V2 } }, 16527 { /* => mm */ { FP32_INT(INT32_MIN), FP32_INT(INT32_MIN), FP32_x6_UNUSED } }, 16528 /*mxcsr:in */ 0, 16529 /*128:out */ X86_MXCSR_IE, 16530 /*256:out */ -1 }, 16531 { { /* unused */ { FP32_ROW_UNUSED } }, 16532 { /* src xmm */ { FP32_SNAN(1), FP32_SNAN(0), FP32_RAND_x6_V2 } }, 16533 { /* => mm */ { FP32_INT(INT32_MIN), FP32_INT(INT32_MIN), FP32_x6_UNUSED } }, 16534 /*mxcsr:in */ 0, 16535 /*128:out */ X86_MXCSR_IE, 16536 /*256:out */ -1 }, 16537 }; 16538 16539 static BS3CPUINSTR4_TEST1_T const s_aTests16[] = 16540 { 16541 { bs3CpuInstr4_cvtps2pi_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, MM1, FSxBX, NOREG, PASS_s_aValues }, 16542 { bs3CpuInstr4_cvtps2pi_MM1_XMM1_icebp_c16, 255, RM_REG, T_SSE, MM1, XMM1, NOREG, PASS_s_aValues }, 16543 }; 16544 16545 static BS3CPUINSTR4_TEST1_T const s_aTests32[] = 16546 { 16547 { bs3CpuInstr4_cvtps2pi_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, MM1, FSxBX, NOREG, PASS_s_aValues }, 16548 { bs3CpuInstr4_cvtps2pi_MM1_XMM1_icebp_c32, 255, RM_REG, T_SSE, MM1, XMM1, NOREG, PASS_s_aValues }, 16549 }; 16550 static BS3CPUINSTR4_TEST1_T const s_aTests64[] = 16551 { 16552 { bs3CpuInstr4_cvtps2pi_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, MM1, FSxBX, NOREG, PASS_s_aValues }, 16553 { bs3CpuInstr4_cvtps2pi_MM1_XMM1_icebp_c64, 255, RM_REG, T_SSE, MM1, XMM1, NOREG, PASS_s_aValues }, 16554 { bs3CpuInstr4_cvtps2pi_MM1_XMM8_icebp_c64, 255, RM_REG, T_SSE, MM1, XMM8, NOREG, PASS_s_aValues }, 16555 }; 16556 16557 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 16558 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode); 16559 return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 16560 g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5)); 16561 } 16562 16563 16564 /* 16565 * CVTTPS2PI. 16566 */ 16567 BS3_DECL_FAR(uint8_t) bs3CpuInstr4_cvttps2pi(uint8_t bMode) 16568 { 16569 static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValues[] = 16570 { 16571 /* 16572 * Zero. 16573 */ 16574 /* 0*/{ { /* unused */ { FP32_ROW_UNUSED } }, 16575 { /* src xmm */ { FP32_0(0), FP32_0(1), FP32_RAND_x6_V1 } }, 16576 { /* => mm */ { FP32_INT(0), FP32_INT(0), FP32_x6_UNUSED } }, 16577 /*mxcsr:in */ 0, 16578 /*128:out */ 0, 16579 /*256:out */ -1 }, 16580 /* 16581 * Infinity. 16582 */ 16583 /* 1*/{ { /* unused */ { FP32_ROW_UNUSED } }, 16584 { /* src xmm */ { FP32_INF(1), FP32_INF(0), FP32_RAND_x6_V1 } }, 16585 { /* => mm */ { FP32_INT(INT32_MIN), FP32_INT(INT32_MIN), FP32_x6_UNUSED } }, 16586 /*mxcsr:in */ 0, 16587 /*128:out */ X86_MXCSR_IE, 16588 /*256:out */ -1 }, 16589 /* 16590 * Normals & Precision. 16591 */ 16592 /* 2*/{ { /* unused */ { FP32_ROW_UNUSED } }, 16593 { /* src xmm */ { FP32_V(0,0x712000,0x8f), FP32_V(1,0x712000,0x8f), FP32_RAND_x6_V0 } }, 16594 { /* => mm */ { FP32_INT(123456), FP32_INT(-123456), FP32_x6_UNUSED } }, 16595 /*mxcsr:in */ 0, 16596 /*128:out */ 0, 16597 /*256:out */ -1 }, 16598 { { /* unused */ { FP32_ROW_UNUSED } }, 16599 { /* src xmm */ { FP32_V(0,0x71200d,0x8f), FP32_V(1,0x71200d,0x8f), FP32_RAND_x6_V2 } }, 16600 /*123456.1*/ /*-123456.1*/ 16601 { /* => mm */ { FP32_INT(123456), FP32_INT(-123456), FP32_x6_UNUSED } }, 16602 /*mxcsr:in */ 0, 16603 /*128:out */ X86_MXCSR_PE, 16604 /*256:out */ -1 }, 16605 { { /* unused */ { FP32_ROW_UNUSED } }, 16606 { /* src xmm */ { FP32_V(0,0x71200d,0x8f), FP32_V(1,0x71200d,0x8f), FP32_RAND_x6_V2 } }, 16607 /*123456.1*/ /*-123456.1*/ 16608 { /* => mm */ { FP32_INT(123456), FP32_INT(-123456), FP32_x6_UNUSED } }, 16609 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 16610 /*128:out */ X86_MXCSR_PE | X86_MXCSR_RC_DOWN, 16611 /*256:out */ -1 }, 16612 { { /* unused */ { FP32_ROW_UNUSED } }, 16613 { /* src xmm */ { FP32_V(0,0x71200d,0x8f), FP32_V(1,0x71200d,0x8f), FP32_RAND_x6_V2 } }, 16614 /*123456.1*/ /*-123456.1*/ 16615 { /* => mm */ { FP32_INT(123456), FP32_INT(-123456), FP32_x6_UNUSED } }, 16616 /*mxcsr:in */ X86_MXCSR_RC_UP, 16617 /*128:out */ X86_MXCSR_PE | X86_MXCSR_RC_UP, 16618 /*256:out */ -1 }, 16619 { { /* unused */ { FP32_ROW_UNUSED } }, 16620 { /* src xmm */ { FP32_V(0,0x71200d,0x8f), FP32_V(1,0x71200d,0x8f), FP32_RAND_x6_V2 } }, 16621 /*123456.1*/ /*-123456.1*/ 16622 { /* => mm */ { FP32_INT(123456), FP32_INT(-123456), FP32_x6_UNUSED } }, 16623 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 16624 /*128:out */ X86_MXCSR_PE | X86_MXCSR_RC_ZERO, 16625 /*256:out */ -1 }, 16626 { { /* unused */ { FP32_ROW_UNUSED } }, 16627 { /* src xmm */ { FP32_V(1,0x666666,0x7e), FP32_V(0,0x666666,0x7e), FP32_RAND_x6_V2 } }, 16628 /*-0.9*/ /*0.9*/ 16629 { /* => mm */ { FP32_INT(0), FP32_INT(0), FP32_x6_UNUSED } }, 16630 /*mxcsr:in */ X86_MXCSR_FZ, 16631 /*128:out */ X86_MXCSR_PE | X86_MXCSR_FZ, 16632 /*256:out */ -1 }, 16633 { { /* unused */ { FP32_ROW_UNUSED } }, 16634 { /* src xmm */ { FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x6_V2 } }, 16635 { /* => mm */ { FP32_INT(-16777215), FP32_INT(16777215), FP32_x6_UNUSED } }, 16636 /*mxcsr:in */ 0, 16637 /*128:out */ 0, 16638 /*256:out */ -1 }, 16639 /* 16640 * Denormals. 16641 */ 16642 /* 9*/{ { /* unused */ { FP32_ROW_UNUSED } }, 16643 { /* src xmm */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(1), FP32_RAND_x6_V2 } }, 16644 { /* => mm */ { FP32_INT(0), FP32_INT(0), FP32_x6_UNUSED } }, 16645 /*mxcsr:in */ 0, 16646 /*128:out */ X86_MXCSR_PE, 16647 /*256:out */ -1 }, 16648 { { /* unused */ { FP32_ROW_UNUSED } }, 16649 { /* src xmm */ { FP32_DENORM_MIN(0), FP32_DENORM_MAX(1), FP32_RAND_x6_V2 } }, 16650 { /* => mm */ { FP32_INT(0), FP32_INT(0), FP32_x6_UNUSED } }, 16651 /*mxcsr:in */ X86_MXCSR_DAZ, 16652 /*128:out */ X86_MXCSR_DAZ, 16653 /*256:out */ -1 }, 16654 /* 16655 * Overflow (Underflow not possible). 16656 */ 16657 /*11*/{ { /* unused */ { FP32_ROW_UNUSED } }, 16658 { /* src xmm */ { FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_RAND_x6_V2 } }, 16659 { /* => mm */ { FP32_INT(INT32_MIN), FP32_INT(INT32_MIN), FP32_x6_UNUSED } }, 16660 /*mxcsr:in */ 0, 16661 /*128:out */ X86_MXCSR_IE, 16662 /*256:out */ -1 }, 16663 /* 16664 * Invalids. 16665 */ 16666 /*12*/{ { /* unused */ { FP32_ROW_UNUSED } }, 16667 { /* src xmm */ { FP32_QNAN(0), FP32_QNAN(1), FP32_RAND_x6_V2 } }, 16668 { /* => mm */ { FP32_INT(INT32_MIN), FP32_INT(INT32_MIN), FP32_x6_UNUSED } }, 16669 /*mxcsr:in */ 0, 16670 /*128:out */ X86_MXCSR_IE, 16671 /*256:out */ -1 }, 16672 { { /* unused */ { FP32_ROW_UNUSED } }, 16673 { /* src xmm */ { FP32_SNAN(1), FP32_SNAN(0), FP32_RAND_x6_V2 } }, 16674 { /* => mm */ { FP32_INT(INT32_MIN), FP32_INT(INT32_MIN), FP32_x6_UNUSED } }, 16675 /*mxcsr:in */ 0, 16676 /*128:out */ X86_MXCSR_IE, 16677 /*256:out */ -1 }, 16678 }; 16679 16680 static BS3CPUINSTR4_TEST1_T const s_aTests16[] = 16681 { 16682 { bs3CpuInstr4_cvttps2pi_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, MM1, FSxBX, NOREG, PASS_s_aValues }, 16683 { bs3CpuInstr4_cvttps2pi_MM1_XMM1_icebp_c16, 255, RM_REG, T_SSE, MM1, XMM1, NOREG, PASS_s_aValues }, 16684 }; 16685 16686 static BS3CPUINSTR4_TEST1_T const s_aTests32[] = 16687 { 16688 { bs3CpuInstr4_cvttps2pi_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, MM1, FSxBX, NOREG, PASS_s_aValues }, 16689 { bs3CpuInstr4_cvttps2pi_MM1_XMM1_icebp_c32, 255, RM_REG, T_SSE, MM1, XMM1, NOREG, PASS_s_aValues }, 16690 }; 16691 static BS3CPUINSTR4_TEST1_T const s_aTests64[] = 16692 { 16693 { bs3CpuInstr4_cvttps2pi_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, MM1, FSxBX, NOREG, PASS_s_aValues }, 16694 { bs3CpuInstr4_cvttps2pi_MM1_XMM1_icebp_c64, 255, RM_REG, T_SSE, MM1, XMM1, NOREG, PASS_s_aValues }, 16695 { bs3CpuInstr4_cvttps2pi_MM1_XMM8_icebp_c64, 255, RM_REG, T_SSE, MM1, XMM8, NOREG, PASS_s_aValues }, 16414 16696 }; 16415 16697 … … 16479 16761 { "[v]rsqrtss", bs3CpuInstr4_v_rsqrtss, 0 }, 16480 16762 { "cvtpi2ps", bs3CpuInstr4_cvtpi2ps, 0 }, 16763 { "cvtps2pi", bs3CpuInstr4_cvtps2pi, 0 }, 16764 { "cvttps2pi", bs3CpuInstr4_cvttps2pi, 0 }, 16481 16765 #endif 16482 16766 }; -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-x-regs.c32
r106692 r106721 492 492 case BS3_REGISTER_FAMILY_OTHER: 493 493 if (BS3_REGISTER_IS_MMX(uReg)) 494 return Bs3ExtCtxSetMm(pExtCtx, uRegNum, *((uint64_t *)pValue), BS3EXTCTXTOPMM_ AS_IS);494 return Bs3ExtCtxSetMm(pExtCtx, uRegNum, *((uint64_t *)pValue), BS3EXTCTXTOPMM_SET); 495 495 break; 496 496 case BS3_REGISTER_FAMILY_8BIT_L:
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