Changeset 106736 in vbox for trunk/src/VBox/ValidationKit/bootsectors
- Timestamp:
- Oct 28, 2024 8:11:30 AM (6 months ago)
- svn:sync-xref-src-repo-rev:
- 165619
- Location:
- trunk/src/VBox/ValidationKit/bootsectors
- Files:
-
- 3 edited
-
bs3-cpu-instr-3.c32 (modified) (8 diffs)
-
bs3-cpu-instr-4.c32 (modified) (64 diffs)
-
bs3-cpu-instr-x-regs.c32 (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32
r106733 r106736 14239 14239 uint8_t enmType; 14240 14240 uint8_t cbGpr; 14241 uint8_t cBitsGprValMask; 14241 uint8_t iMediaRegDst; 14242 uint8_t iMediaRegSrc; 14242 14243 uint8_t iGprReg; 14243 uint8_t iMediaRegSrc;14244 uint8_t iMediaRegDst;14245 14244 uint8_t cValues; 14246 14245 BS3CPUINSTR3_TEST6_VALUES_T const BS3_FAR *paValues; … … 14272 14271 PBS3EXTCTX pExtCtxOut; 14273 14272 PBS3EXTCTX pExtCtx = bs3CpuInstr3AllocExtCtxs(&pExtCtxOut); 14273 BS3SETREGCTX pSetRegCtx; 14274 14274 if (!pExtCtx) 14275 14275 return 0; … … 14285 14285 Bs3RegCtxSaveForMode(&Ctx, bMode, 1024); 14286 14286 bs3CpuInstr3SetupSseAndAvx(&Ctx, pExtCtx); 14287 14288 pSetRegCtx.pExtCtx = pExtCtx; 14289 pSetRegCtx.pCtx = &Ctx; 14290 pSetRegCtx.bMode = bMode; 14287 14291 14288 14292 /* … … 14324 14328 : fSseInstr ? paConfigs[iCfg].bXcptSse 14325 14329 : BS3_MODE_IS_RM_OR_V86(bMode) ? X86_XCPT_UD : paConfigs[iCfg].bXcptAvx; 14326 uint64_t const fGprValMask = paTests[iTest].cBitsGprValMask == 64 ? UINT64_MAX14327 : RT_BIT_64(paTests[iTest].cBitsGprValMask) - 1;14328 14330 uint16_t idTestStep = bRing * 10000 + iCfg * 100 + iTest * 10; 14329 14331 unsigned cRecompRuns = 0; … … 14335 14337 if ((paTests[iTest].enmRm == RM_REG || paTests[iTest].enmRm == RM_MEM8) && (!paConfigs[iCfg].fAligned || paConfigs[iCfg].fAlignCheck || fPf)) 14336 14338 continue; 14339 14340 pSetRegCtx.fZeroYMMHi = fSseInstr; 14337 14341 14338 14342 /* #AC is only raised in ring-3.: */ … … 14366 14370 */ 14367 14371 /* source - media */ 14368 BS3_ASSERT(paTests[iTest].iMediaRegSrc != UINT8_MAX); 14369 if (fMmxInstr) 14370 Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iMediaRegSrc, paValues[iVal].uMediaSrc.QWords.qw0, BS3EXTCTXTOPMM_ZERO); 14371 else if (fSseInstr) 14372 Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iMediaRegSrc, &paValues[iVal].uMediaSrc.DQWords.dqw0); 14373 else 14374 Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iMediaRegSrc, &paValues[iVal].uMediaSrc, 32); 14372 Bs3ExtCtxSetReg(&pSetRegCtx, paTests[iTest].iMediaRegSrc, &paValues[iVal].uMediaSrc); 14375 14373 14376 14374 /* source - gpr/mem */ 14377 if ( paTests[iTest].iGprReg == UINT8_MAX)14375 if (BS3_REGISTER_IS_MEMREF(paTests[iTest].iGprReg)) 14378 14376 { 14379 14377 BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM); 14380 14378 Bs3MemSet(&uMemOpExpect, 0xcc, sizeof(uMemOpExpect)); 14381 14379 if (bXcptExpect == X86_XCPT_DB) 14382 switch (paTests[iTest].cbGpr) 14383 { 14384 case 1: uMemOpExpect.au8[0] = (uint8_t) (paValues[iVal].uGpr & fGprValMask); break; 14385 case 2: uMemOpExpect.au16[0] = (uint16_t)(paValues[iVal].uGpr & fGprValMask); break; 14386 case 4: uMemOpExpect.au32[0] = (uint32_t)(paValues[iVal].uGpr & fGprValMask); break; 14387 case 8: uMemOpExpect.au64[0] = (paValues[iVal].uGpr & fGprValMask); break; 14388 default: BS3_ASSERT(0); 14389 } 14380 Bs3MemCpy(&uMemOpExpect, &paValues[iVal].uGpr, paTests[iTest].cbGpr); 14390 14381 Bs3MemCpy(puMemOpAlias, &uMemOpExpect, cbMemOp); 14391 14382 } 14392 14383 else 14393 Bs3 RegCtxSetGpr(&Ctx, paTests[iTest].iGprReg, paValues[iVal].uGpr & fGprValMask, paTests[iTest].cbGpr);14384 Bs3ExtCtxSetReg(&pSetRegCtx, paTests[iTest].iGprReg, (PCRTUINT256U)&paValues[iVal].uGpr); 14394 14385 14395 14386 /* Memory pointer. */ 14396 14387 if (paTests[iTest].enmRm >= RM_MEM) 14397 { 14398 BS3_ASSERT(paTests[iTest].iGprReg == UINT8_MAX || paTests[iTest].iMediaRegSrc == UINT8_MAX); 14399 Bs3RegCtxSetGrpSegFromCurPtr(&Ctx, &Ctx.rbx, &Ctx.fs, puMemOp); 14400 } 14388 Bs3ExtCtxSetReg(&pSetRegCtx, paTests[iTest].iGprReg, (void *)puMemOp); 14401 14389 14402 14390 /* … … 14418 14406 14419 14407 if (bXcptExpect == X86_XCPT_DB) 14420 { 14421 if (fMmxInstr) 14422 Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iMediaRegDst, paValues[iVal].uMediaDst.QWords.qw0, BS3EXTCTXTOPMM_SET); 14423 else if (fSseInstr) 14424 Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iMediaRegDst, &paValues[iVal].uMediaDst.DQWords.dqw0); 14425 else 14426 Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iMediaRegDst, &paValues[iVal].uMediaDst, 32); 14427 } 14408 Bs3ExtCtxSetReg(&pSetRegCtx, paTests[iTest].iMediaRegDst, &paValues[iVal].uMediaDst); 14428 14409 14429 14410 Bs3TestCheckExtCtx(pExtCtxOut, pExtCtx, 0 /*fFlags*/, pszMode, idTestStep); … … 14550 14531 static BS3CPUINSTR3_TEST6_T const s_aTests16[] = 14551 14532 { 14552 { bs3CpuInstr3_pinsrb_XMM1_EDX_0FFh_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 8, 2, 1, 1,RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b },14553 { bs3CpuInstr3_pinsrb_XMM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM8, T_SSE4_1, 1, 8, 255, 1, 1, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b },14554 { bs3CpuInstr3_pinsrb_XMM1_EDX_000h_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 8, 2, 1, 1,RT_ELEMENTS(s_aValues00_b), s_aValues00_b },14555 { bs3CpuInstr3_pinsrb_XMM1_FSxBX_000h_icebp_c16, 255, RM_MEM8, T_SSE4_1, 1, 8, 255, 1, 1, RT_ELEMENTS(s_aValues00_b), s_aValues00_b },14556 14557 { bs3CpuInstr3_vpinsrb_XMM1_XMM2_EDX_0FFh_icebp_c16, 255, RM_REG, T_AVX_128, 1, 8, 2, 2, 1,RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b },14558 { bs3CpuInstr3_vpinsrb_XMM1_XMM2_FSxBX_0FFh_icebp_c16, X86_XCPT_AC, RM_MEM8, T_AVX_128, 1, 8, 255, 2, 1, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b },14559 { bs3CpuInstr3_vpinsrb_XMM1_XMM2_EDX_000h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 8, 2, 2, 1,RT_ELEMENTS(s_aValues00_b), s_aValues00_b },14560 { bs3CpuInstr3_vpinsrb_XMM1_XMM2_FSxBX_000h_icebp_c16, X86_XCPT_AC, RM_MEM8, T_AVX_128, 1, 8, 255, 2, 1, RT_ELEMENTS(s_aValues00_b), s_aValues00_b },14561 14562 { bs3CpuInstr3_pinsrw_MM1_EDX_000h_icebp_c16, 255, RM_REG, T_MMX_SSE, 2, 16, 2, 1, 1,RT_ELEMENTS(s_aValues00_w), s_aValues00_w },14563 { bs3CpuInstr3_pinsrw_MM1_FSxBX_000h_icebp_c16, X86_XCPT_AC, RM_MEM32, T_MMX_SSE, 2, 16, 255, 1, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w },14564 { bs3CpuInstr3_pinsrw_MM1_EDX_0FFh_icebp_c16, 255, RM_REG, T_MMX_SSE, 2, 16, 2, 1, 1,RT_ELEMENTS(s_aValuesFF_w_64), s_aValuesFF_w_64 },14565 { bs3CpuInstr3_pinsrw_MM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM32, T_MMX_SSE, 2, 16, 255, 1, 1, RT_ELEMENTS(s_aValuesFF_w_64), s_aValuesFF_w_64 },14566 14567 { bs3CpuInstr3_pinsrw_XMM1_EDX_000h_icebp_c16, 255, RM_REG, T_SSE, 2, 16, 2, 1, 1,RT_ELEMENTS(s_aValues00_w), s_aValues00_w },14568 { bs3CpuInstr3_pinsrw_XMM1_FSxBX_000h_icebp_c16, 255, RM_MEM32, T_SSE, 2, 16, 255, 1, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w },14569 { bs3CpuInstr3_pinsrw_XMM1_EDX_0FFh_icebp_c16, 255, RM_REG, T_SSE, 2, 16, 2, 1, 1,RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w },14570 { bs3CpuInstr3_pinsrw_XMM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM32, T_SSE, 2, 16, 255, 1, 1, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w },14571 14572 { bs3CpuInstr3_vpinsrw_XMM1_XMM2_EDX_000h_icebp_c16, 255, RM_REG, T_AVX_128, 2, 16, 2, 2, 1,RT_ELEMENTS(s_aValues00_w), s_aValues00_w },14573 { bs3CpuInstr3_vpinsrw_XMM1_XMM2_FSxBX_000h_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 2, 16, 255, 2, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w },14574 { bs3CpuInstr3_vpinsrw_XMM1_XMM2_EDX_0FFh_icebp_c16, 255, RM_REG, T_AVX_128, 2, 16, 2, 2, 1,RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w },14575 { bs3CpuInstr3_vpinsrw_XMM1_XMM2_FSxBX_0FFh_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 2, 16, 255, 2, 1, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w },14576 14577 { bs3CpuInstr3_pinsrd_XMM1_EDX_0FFh_icebp_c16, 255, RM_REG, T_SSE4_1, 4, 32, 2, 1, 1,RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d },14578 { bs3CpuInstr3_pinsrd_XMM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM32, T_SSE4_1, 4, 32, 255, 1, 1, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d },14579 { bs3CpuInstr3_pinsrd_XMM1_EDX_000h_icebp_c16, 255, RM_REG, T_SSE4_1, 4, 32, 2, 1, 1,RT_ELEMENTS(s_aValues00_d), s_aValues00_d },14580 { bs3CpuInstr3_pinsrd_XMM1_FSxBX_000h_icebp_c16, 255, RM_MEM32, T_SSE4_1, 4, 32, 255, 1, 1, RT_ELEMENTS(s_aValues00_d), s_aValues00_d },14581 { bs3CpuInstr3_vpinsrd_XMM1_XMM2_EDX_0FFh_icebp_c16, 255, RM_REG, T_AVX_128, 4, 32, 2, 2, 1,RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d },14582 { bs3CpuInstr3_vpinsrd_XMM1_XMM2_FSxBX_0FFh_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, 255, 2, 1, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d },14583 { bs3CpuInstr3_vpinsrd_XMM1_XMM2_EDX_000h_icebp_c16, 255, RM_REG, T_AVX_128, 4, 32, 2, 2, 1,RT_ELEMENTS(s_aValues00_d), s_aValues00_d },14584 { bs3CpuInstr3_vpinsrd_XMM1_XMM2_FSxBX_000h_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, 255, 2, 1, RT_ELEMENTS(s_aValues00_d), s_aValues00_d },14533 { bs3CpuInstr3_pinsrb_XMM1_EDX_0FFh_icebp_c16, 255, RM_REG, T_SSE4_1, 1, XMM1, XMM1, EDX, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, 14534 { bs3CpuInstr3_pinsrb_XMM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM8, T_SSE4_1, 1, XMM1, XMM1, FSxBX, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, 14535 { bs3CpuInstr3_pinsrb_XMM1_EDX_000h_icebp_c16, 255, RM_REG, T_SSE4_1, 1, XMM1, XMM1, EDX, RT_ELEMENTS(s_aValues00_b), s_aValues00_b }, 14536 { bs3CpuInstr3_pinsrb_XMM1_FSxBX_000h_icebp_c16, 255, RM_MEM8, T_SSE4_1, 1, XMM1, XMM1, FSxBX, RT_ELEMENTS(s_aValues00_b), s_aValues00_b }, 14537 14538 { bs3CpuInstr3_vpinsrb_XMM1_XMM2_EDX_0FFh_icebp_c16, 255, RM_REG, T_AVX_128, 1, XMM1, XMM2, EDX, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, 14539 { bs3CpuInstr3_vpinsrb_XMM1_XMM2_FSxBX_0FFh_icebp_c16, X86_XCPT_AC, RM_MEM8, T_AVX_128, 1, XMM1, XMM2, FSxBX, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, 14540 { bs3CpuInstr3_vpinsrb_XMM1_XMM2_EDX_000h_icebp_c16, 255, RM_REG, T_AVX_128, 1, XMM1, XMM2, EDX, RT_ELEMENTS(s_aValues00_b), s_aValues00_b }, 14541 { bs3CpuInstr3_vpinsrb_XMM1_XMM2_FSxBX_000h_icebp_c16, X86_XCPT_AC, RM_MEM8, T_AVX_128, 1, XMM1, XMM2, FSxBX, RT_ELEMENTS(s_aValues00_b), s_aValues00_b }, 14542 14543 { bs3CpuInstr3_pinsrw_MM1_EDX_000h_icebp_c16, 255, RM_REG, T_MMX_SSE, 2, MM1, MM1, EDX, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, 14544 { bs3CpuInstr3_pinsrw_MM1_FSxBX_000h_icebp_c16, X86_XCPT_AC, RM_MEM32, T_MMX_SSE, 2, MM1, MM1, FSxBX, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, 14545 { bs3CpuInstr3_pinsrw_MM1_EDX_0FFh_icebp_c16, 255, RM_REG, T_MMX_SSE, 2, MM1, MM1, EDX, RT_ELEMENTS(s_aValuesFF_w_64), s_aValuesFF_w_64 }, 14546 { bs3CpuInstr3_pinsrw_MM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM32, T_MMX_SSE, 2, MM1, MM1, FSxBX, RT_ELEMENTS(s_aValuesFF_w_64), s_aValuesFF_w_64 }, 14547 14548 { bs3CpuInstr3_pinsrw_XMM1_EDX_000h_icebp_c16, 255, RM_REG, T_SSE, 2, XMM1, XMM1, EDX, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, 14549 { bs3CpuInstr3_pinsrw_XMM1_FSxBX_000h_icebp_c16, 255, RM_MEM32, T_SSE, 2, XMM1, XMM1, FSxBX, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, 14550 { bs3CpuInstr3_pinsrw_XMM1_EDX_0FFh_icebp_c16, 255, RM_REG, T_SSE, 2, XMM1, XMM1, EDX, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, 14551 { bs3CpuInstr3_pinsrw_XMM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM32, T_SSE, 2, XMM1, XMM1, FSxBX, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, 14552 14553 { bs3CpuInstr3_vpinsrw_XMM1_XMM2_EDX_000h_icebp_c16, 255, RM_REG, T_AVX_128, 2, XMM1, XMM2, EDX, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, 14554 { bs3CpuInstr3_vpinsrw_XMM1_XMM2_FSxBX_000h_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 2, XMM1, XMM2, FSxBX, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, 14555 { bs3CpuInstr3_vpinsrw_XMM1_XMM2_EDX_0FFh_icebp_c16, 255, RM_REG, T_AVX_128, 2, XMM1, XMM2, EDX, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, 14556 { bs3CpuInstr3_vpinsrw_XMM1_XMM2_FSxBX_0FFh_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 2, XMM1, XMM2, FSxBX, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, 14557 14558 { bs3CpuInstr3_pinsrd_XMM1_EDX_0FFh_icebp_c16, 255, RM_REG, T_SSE4_1, 4, XMM1, XMM1, EDX, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d }, 14559 { bs3CpuInstr3_pinsrd_XMM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM32, T_SSE4_1, 4, XMM1, XMM1, FSxBX, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d }, 14560 { bs3CpuInstr3_pinsrd_XMM1_EDX_000h_icebp_c16, 255, RM_REG, T_SSE4_1, 4, XMM1, XMM1, EDX, RT_ELEMENTS(s_aValues00_d), s_aValues00_d }, 14561 { bs3CpuInstr3_pinsrd_XMM1_FSxBX_000h_icebp_c16, 255, RM_MEM32, T_SSE4_1, 4, XMM1, XMM1, FSxBX, RT_ELEMENTS(s_aValues00_d), s_aValues00_d }, 14562 { bs3CpuInstr3_vpinsrd_XMM1_XMM2_EDX_0FFh_icebp_c16, 255, RM_REG, T_AVX_128, 4, XMM1, XMM2, EDX, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d }, 14563 { bs3CpuInstr3_vpinsrd_XMM1_XMM2_FSxBX_0FFh_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, XMM1, XMM2, FSxBX, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d }, 14564 { bs3CpuInstr3_vpinsrd_XMM1_XMM2_EDX_000h_icebp_c16, 255, RM_REG, T_AVX_128, 4, XMM1, XMM2, EDX, RT_ELEMENTS(s_aValues00_d), s_aValues00_d }, 14565 { bs3CpuInstr3_vpinsrd_XMM1_XMM2_FSxBX_000h_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, XMM1, XMM2, FSxBX, RT_ELEMENTS(s_aValues00_d), s_aValues00_d }, 14585 14566 }; 14586 14567 static BS3CPUINSTR3_TEST6_T const s_aTests32[] = 14587 14568 { 14588 { bs3CpuInstr3_pinsrb_XMM1_EDX_0FFh_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 8, 2, 1, 1,RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b },14589 { bs3CpuInstr3_pinsrb_XMM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM8, T_SSE4_1, 1, 8, 255, 1, 1, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b },14590 { bs3CpuInstr3_pinsrb_XMM1_EDX_000h_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 8, 2, 1, 1,RT_ELEMENTS(s_aValues00_b), s_aValues00_b },14591 { bs3CpuInstr3_pinsrb_XMM1_FSxBX_000h_icebp_c32, 255, RM_MEM8, T_SSE4_1, 1, 8, 255, 1, 1, RT_ELEMENTS(s_aValues00_b), s_aValues00_b },14592 14593 { bs3CpuInstr3_vpinsrb_XMM1_XMM2_EDX_0FFh_icebp_c32, 255, RM_REG, T_AVX_128, 1, 8, 2, 2, 1,RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b },14594 { bs3CpuInstr3_vpinsrb_XMM1_XMM2_FSxBX_0FFh_icebp_c32, X86_XCPT_AC, RM_MEM8, T_AVX_128, 1, 8, 255, 2, 1, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b },14595 { bs3CpuInstr3_vpinsrb_XMM1_XMM2_EDX_000h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 8, 2, 2, 1,RT_ELEMENTS(s_aValues00_b), s_aValues00_b },14596 { bs3CpuInstr3_vpinsrb_XMM1_XMM2_FSxBX_000h_icebp_c32, X86_XCPT_AC, RM_MEM8, T_AVX_128, 1, 8, 255, 2, 1, RT_ELEMENTS(s_aValues00_b), s_aValues00_b },14597 14598 { bs3CpuInstr3_pinsrw_MM1_EDX_000h_icebp_c32, 255, RM_REG, T_MMX_SSE, 2, 16, 2, 1, 1,RT_ELEMENTS(s_aValues00_w), s_aValues00_w },14599 { bs3CpuInstr3_pinsrw_MM1_FSxBX_000h_icebp_c32, 255, RM_MEM32, T_MMX_SSE, 2, 16, 255, 1, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w },14600 { bs3CpuInstr3_pinsrw_MM1_EDX_0FFh_icebp_c32, 255, RM_REG, T_MMX_SSE, 2, 16, 2, 1, 1,RT_ELEMENTS(s_aValuesFF_w_64), s_aValuesFF_w_64 },14601 { bs3CpuInstr3_pinsrw_MM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM32, T_MMX_SSE, 2, 16, 255, 1, 1, RT_ELEMENTS(s_aValuesFF_w_64), s_aValuesFF_w_64 },14602 14603 { bs3CpuInstr3_pinsrw_XMM1_EDX_000h_icebp_c32, 255, RM_REG, T_SSE, 2, 16, 2, 1, 1,RT_ELEMENTS(s_aValues00_w), s_aValues00_w },14604 { bs3CpuInstr3_pinsrw_XMM1_FSxBX_000h_icebp_c32, 255, RM_MEM32, T_SSE, 2, 16, 255, 1, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w },14605 { bs3CpuInstr3_pinsrw_XMM1_EDX_0FFh_icebp_c32, 255, RM_REG, T_SSE, 2, 16, 2, 1, 1,RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w },14606 { bs3CpuInstr3_pinsrw_XMM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM32, T_SSE, 2, 16, 255, 1, 1, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w },14607 14608 { bs3CpuInstr3_vpinsrw_XMM1_XMM2_EDX_000h_icebp_c32, 255, RM_REG, T_AVX_128, 2, 16, 2, 2, 1,RT_ELEMENTS(s_aValues00_w), s_aValues00_w },14609 { bs3CpuInstr3_vpinsrw_XMM1_XMM2_FSxBX_000h_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 2, 16, 255, 2, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w },14610 { bs3CpuInstr3_vpinsrw_XMM1_XMM2_EDX_0FFh_icebp_c32, 255, RM_REG, T_AVX_128, 2, 16, 2, 2, 1,RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w },14611 { bs3CpuInstr3_vpinsrw_XMM1_XMM2_FSxBX_0FFh_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 2, 16, 255, 2, 1, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w },14612 14613 { bs3CpuInstr3_pinsrd_XMM1_EDX_0FFh_icebp_c32, 255, RM_REG, T_SSE4_1, 4, 32, 2, 1, 1,RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d },14614 { bs3CpuInstr3_pinsrd_XMM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM32, T_SSE4_1, 4, 32, 255, 1, 1, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d },14615 { bs3CpuInstr3_pinsrd_XMM1_EDX_000h_icebp_c32, 255, RM_REG, T_SSE4_1, 4, 32, 2, 1, 1,RT_ELEMENTS(s_aValues00_d), s_aValues00_d },14616 { bs3CpuInstr3_pinsrd_XMM1_FSxBX_000h_icebp_c32, 255, RM_MEM32, T_SSE4_1, 4, 32, 255, 1, 1, RT_ELEMENTS(s_aValues00_d), s_aValues00_d },14617 { bs3CpuInstr3_vpinsrd_XMM1_XMM2_EDX_0FFh_icebp_c32, 255, RM_REG, T_AVX_128, 4, 32, 2, 2, 1,RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d },14618 { bs3CpuInstr3_vpinsrd_XMM1_XMM2_FSxBX_0FFh_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, 255, 2, 1, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d },14619 { bs3CpuInstr3_vpinsrd_XMM1_XMM2_EDX_000h_icebp_c32, 255, RM_REG, T_AVX_128, 4, 32, 2, 2, 1,RT_ELEMENTS(s_aValues00_d), s_aValues00_d },14620 { bs3CpuInstr3_vpinsrd_XMM1_XMM2_FSxBX_000h_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, 255, 2, 1, RT_ELEMENTS(s_aValues00_d), s_aValues00_d },14569 { bs3CpuInstr3_pinsrb_XMM1_EDX_0FFh_icebp_c32, 255, RM_REG, T_SSE4_1, 1, XMM1, XMM1, EDX, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, 14570 { bs3CpuInstr3_pinsrb_XMM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM8, T_SSE4_1, 1, XMM1, XMM1, FSxBX, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, 14571 { bs3CpuInstr3_pinsrb_XMM1_EDX_000h_icebp_c32, 255, RM_REG, T_SSE4_1, 1, XMM1, XMM1, EDX, RT_ELEMENTS(s_aValues00_b), s_aValues00_b }, 14572 { bs3CpuInstr3_pinsrb_XMM1_FSxBX_000h_icebp_c32, 255, RM_MEM8, T_SSE4_1, 1, XMM1, XMM1, FSxBX, RT_ELEMENTS(s_aValues00_b), s_aValues00_b }, 14573 14574 { bs3CpuInstr3_vpinsrb_XMM1_XMM2_EDX_0FFh_icebp_c32, 255, RM_REG, T_AVX_128, 1, XMM1, XMM2, EDX, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, 14575 { bs3CpuInstr3_vpinsrb_XMM1_XMM2_FSxBX_0FFh_icebp_c32, X86_XCPT_AC, RM_MEM8, T_AVX_128, 1, XMM1, XMM2, FSxBX, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, 14576 { bs3CpuInstr3_vpinsrb_XMM1_XMM2_EDX_000h_icebp_c32, 255, RM_REG, T_AVX_128, 1, XMM1, XMM2, EDX, RT_ELEMENTS(s_aValues00_b), s_aValues00_b }, 14577 { bs3CpuInstr3_vpinsrb_XMM1_XMM2_FSxBX_000h_icebp_c32, X86_XCPT_AC, RM_MEM8, T_AVX_128, 1, XMM1, XMM2, FSxBX, RT_ELEMENTS(s_aValues00_b), s_aValues00_b }, 14578 14579 { bs3CpuInstr3_pinsrw_MM1_EDX_000h_icebp_c32, 255, RM_REG, T_MMX_SSE, 2, MM1, MM1, EDX, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, 14580 { bs3CpuInstr3_pinsrw_MM1_FSxBX_000h_icebp_c32, 255, RM_MEM32, T_MMX_SSE, 2, MM1, MM1, FSxBX, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, 14581 { bs3CpuInstr3_pinsrw_MM1_EDX_0FFh_icebp_c32, 255, RM_REG, T_MMX_SSE, 2, MM1, MM1, EDX, RT_ELEMENTS(s_aValuesFF_w_64), s_aValuesFF_w_64 }, 14582 { bs3CpuInstr3_pinsrw_MM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM32, T_MMX_SSE, 2, MM1, MM1, FSxBX, RT_ELEMENTS(s_aValuesFF_w_64), s_aValuesFF_w_64 }, 14583 14584 { bs3CpuInstr3_pinsrw_XMM1_EDX_000h_icebp_c32, 255, RM_REG, T_SSE, 2, XMM1, XMM1, EDX, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, 14585 { bs3CpuInstr3_pinsrw_XMM1_FSxBX_000h_icebp_c32, 255, RM_MEM32, T_SSE, 2, XMM1, XMM1, FSxBX, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, 14586 { bs3CpuInstr3_pinsrw_XMM1_EDX_0FFh_icebp_c32, 255, RM_REG, T_SSE, 2, XMM1, XMM1, EDX, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, 14587 { bs3CpuInstr3_pinsrw_XMM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM32, T_SSE, 2, XMM1, XMM1, FSxBX, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, 14588 14589 { bs3CpuInstr3_vpinsrw_XMM1_XMM2_EDX_000h_icebp_c32, 255, RM_REG, T_AVX_128, 2, XMM1, XMM2, EDX, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, 14590 { bs3CpuInstr3_vpinsrw_XMM1_XMM2_FSxBX_000h_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 2, XMM1, XMM2, FSxBX, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, 14591 { bs3CpuInstr3_vpinsrw_XMM1_XMM2_EDX_0FFh_icebp_c32, 255, RM_REG, T_AVX_128, 2, XMM1, XMM2, EDX, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, 14592 { bs3CpuInstr3_vpinsrw_XMM1_XMM2_FSxBX_0FFh_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 2, XMM1, XMM2, FSxBX, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, 14593 14594 { bs3CpuInstr3_pinsrd_XMM1_EDX_0FFh_icebp_c32, 255, RM_REG, T_SSE4_1, 4, XMM1, XMM1, EDX, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d }, 14595 { bs3CpuInstr3_pinsrd_XMM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM32, T_SSE4_1, 4, XMM1, XMM1, FSxBX, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d }, 14596 { bs3CpuInstr3_pinsrd_XMM1_EDX_000h_icebp_c32, 255, RM_REG, T_SSE4_1, 4, XMM1, XMM1, EDX, RT_ELEMENTS(s_aValues00_d), s_aValues00_d }, 14597 { bs3CpuInstr3_pinsrd_XMM1_FSxBX_000h_icebp_c32, 255, RM_MEM32, T_SSE4_1, 4, XMM1, XMM1, FSxBX, RT_ELEMENTS(s_aValues00_d), s_aValues00_d }, 14598 { bs3CpuInstr3_vpinsrd_XMM1_XMM2_EDX_0FFh_icebp_c32, 255, RM_REG, T_AVX_128, 4, XMM1, XMM2, EDX, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d }, 14599 { bs3CpuInstr3_vpinsrd_XMM1_XMM2_FSxBX_0FFh_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, XMM1, XMM2, FSxBX, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d }, 14600 { bs3CpuInstr3_vpinsrd_XMM1_XMM2_EDX_000h_icebp_c32, 255, RM_REG, T_AVX_128, 4, XMM1, XMM2, EDX, RT_ELEMENTS(s_aValues00_d), s_aValues00_d }, 14601 { bs3CpuInstr3_vpinsrd_XMM1_XMM2_FSxBX_000h_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, XMM1, XMM2, FSxBX, RT_ELEMENTS(s_aValues00_d), s_aValues00_d }, 14621 14602 }; 14622 14603 static BS3CPUINSTR3_TEST6_T const s_aTests64[] = 14623 14604 { 14624 { bs3CpuInstr3_pinsrb_XMM1_EDX_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 8, 2, 1, 1,RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b },14625 { bs3CpuInstr3_pinsrb_XMM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM8, T_SSE4_1, 1, 8, 255, 1, 1, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b },14626 { bs3CpuInstr3_pinsrb_XMM1_EDX_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 8, 2, 1, 1,RT_ELEMENTS(s_aValues00_b), s_aValues00_b },14627 { bs3CpuInstr3_pinsrb_XMM1_FSxBX_000h_icebp_c64, 255, RM_MEM8, T_SSE4_1, 1, 8, 255, 1, 1, RT_ELEMENTS(s_aValues00_b), s_aValues00_b },14628 14629 { bs3CpuInstr3_pinsrb_XMM8_R9D_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 8, 9, 8, 8,RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b },14630 { bs3CpuInstr3_pinsrb_XMM8_FSxBX_0FFh_icebp_c64, 255, RM_MEM8, T_SSE4_1, 1, 8, 255, 8, 8, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b },14631 { bs3CpuInstr3_pinsrb_XMM8_R9D_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 8, 9, 8, 8,RT_ELEMENTS(s_aValues00_b), s_aValues00_b },14632 { bs3CpuInstr3_pinsrb_XMM8_FSxBX_000h_icebp_c64, 255, RM_MEM8, T_SSE4_1, 1, 8, 255, 8, 8, RT_ELEMENTS(s_aValues00_b), s_aValues00_b },14633 14634 { bs3CpuInstr3_vpinsrb_XMM1_XMM2_EDX_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 1, 8, 2, 2, 1,RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b },14635 { bs3CpuInstr3_vpinsrb_XMM1_XMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_AC, RM_MEM8, T_AVX_128, 1, 8, 255, 2, 1, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b },14636 { bs3CpuInstr3_vpinsrb_XMM1_XMM2_EDX_000h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 8, 2, 2, 1,RT_ELEMENTS(s_aValues00_b), s_aValues00_b },14637 { bs3CpuInstr3_vpinsrb_XMM1_XMM2_FSxBX_000h_icebp_c64, X86_XCPT_AC, RM_MEM8, T_AVX_128, 1, 8, 255, 2, 1, RT_ELEMENTS(s_aValues00_b), s_aValues00_b },14638 14639 { bs3CpuInstr3_vpinsrb_XMM8_XMM9_R9D_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 1, 8, 9, 9, 8,RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b },14640 { bs3CpuInstr3_vpinsrb_XMM8_XMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_AC, RM_MEM8, T_AVX_128, 1, 8, 255, 9, 8, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b },14641 { bs3CpuInstr3_vpinsrb_XMM8_XMM9_R9D_000h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 8, 9, 9, 8,RT_ELEMENTS(s_aValues00_b), s_aValues00_b },14642 { bs3CpuInstr3_vpinsrb_XMM8_XMM9_FSxBX_000h_icebp_c64, X86_XCPT_AC, RM_MEM8, T_AVX_128, 1, 8, 255, 9, 8, RT_ELEMENTS(s_aValues00_b), s_aValues00_b },14643 14644 { bs3CpuInstr3_pinsrw_MM1_EDX_000h_icebp_c64, 255, RM_REG, T_MMX_SSE, 2, 16, 2, 1, 1,RT_ELEMENTS(s_aValues00_w), s_aValues00_w },14645 { bs3CpuInstr3_pinsrw_MM1_R9D_000h_icebp_c64, 255, RM_REG, T_MMX_SSE, 2, 16, 9, 1, 1,RT_ELEMENTS(s_aValues00_w), s_aValues00_w },14646 { bs3CpuInstr3_pinsrw_MM1_FSxBX_000h_icebp_c64, 255, RM_MEM32, T_MMX_SSE, 2, 16, 255, 1, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w },14647 { bs3CpuInstr3_pinsrw_MM1_EDX_0FFh_icebp_c64, 255, RM_REG, T_MMX_SSE, 2, 16, 2, 1, 1,RT_ELEMENTS(s_aValuesFF_w_64), s_aValuesFF_w_64 },14648 { bs3CpuInstr3_pinsrw_MM1_R9D_0FFh_icebp_c64, 255, RM_REG, T_MMX_SSE, 2, 16, 9, 1, 1,RT_ELEMENTS(s_aValuesFF_w_64), s_aValuesFF_w_64 },14649 { bs3CpuInstr3_pinsrw_MM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM32, T_MMX_SSE, 2, 16, 255, 1, 1, RT_ELEMENTS(s_aValuesFF_w_64), s_aValuesFF_w_64 },14650 14651 { bs3CpuInstr3_pinsrw_XMM1_EDX_000h_icebp_c64, 255, RM_REG, T_SSE, 2, 16, 2, 1, 1,RT_ELEMENTS(s_aValues00_w), s_aValues00_w },14652 { bs3CpuInstr3_pinsrw_XMM1_FSxBX_000h_icebp_c64, 255, RM_MEM32, T_SSE, 2, 16, 255, 1, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w },14653 { bs3CpuInstr3_pinsrw_XMM1_EDX_0FFh_icebp_c64, 255, RM_REG, T_SSE, 2, 16, 2, 1, 1,RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w },14654 { bs3CpuInstr3_pinsrw_XMM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM32, T_SSE, 2, 16, 255, 1, 1, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w },14655 14656 { bs3CpuInstr3_pinsrw_XMM8_R9D_000h_icebp_c64, 255, RM_REG, T_SSE, 2, 16, 9, 8, 8,RT_ELEMENTS(s_aValues00_w), s_aValues00_w },14657 { bs3CpuInstr3_pinsrw_XMM8_FSxBX_000h_icebp_c64, 255, RM_MEM32, T_SSE, 2, 16, 255, 8, 8, RT_ELEMENTS(s_aValues00_w), s_aValues00_w },14658 { bs3CpuInstr3_pinsrw_XMM8_R9D_0FFh_icebp_c64, 255, RM_REG, T_SSE, 2, 16, 9, 8, 8,RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w },14659 { bs3CpuInstr3_pinsrw_XMM8_FSxBX_0FFh_icebp_c64, 255, RM_MEM32, T_SSE, 2, 16, 255, 8, 8, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w },14660 14661 { bs3CpuInstr3_pinsrw_XMM1_RDX_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 2, 16, 2, 1, 1,RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w },14662 { bs3CpuInstr3_pinsrw_XMM8_R9_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 2, 16, 9, 8, 8,RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w },14663 { bs3CpuInstr3_pinsrw_XMM1_RDX_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 2, 16, 2, 1, 1,RT_ELEMENTS(s_aValues00_w), s_aValues00_w },14664 { bs3CpuInstr3_pinsrw_XMM8_R9_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 2, 16, 9, 8, 8,RT_ELEMENTS(s_aValues00_w), s_aValues00_w },14665 14666 { bs3CpuInstr3_vpinsrw_XMM1_XMM2_EDX_000h_icebp_c64, 255, RM_REG, T_AVX_128, 2, 16, 2, 2, 1,RT_ELEMENTS(s_aValues00_w), s_aValues00_w },14667 { bs3CpuInstr3_vpinsrw_XMM1_XMM2_FSxBX_000h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 2, 16, 255, 2, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w },14668 { bs3CpuInstr3_vpinsrw_XMM1_XMM2_EDX_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 2, 16, 2, 2, 1,RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w },14669 { bs3CpuInstr3_vpinsrw_XMM1_XMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 2, 16, 255, 2, 1, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w },14670 14671 { bs3CpuInstr3_vpinsrw_XMM8_XMM9_R9D_000h_icebp_c64, 255, RM_REG, T_AVX_128, 2, 16, 9, 9, 8,RT_ELEMENTS(s_aValues00_w), s_aValues00_w },14672 { bs3CpuInstr3_vpinsrw_XMM8_XMM9_FSxBX_000h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 2, 16, 255, 9, 8, RT_ELEMENTS(s_aValues00_w), s_aValues00_w },14673 { bs3CpuInstr3_vpinsrw_XMM8_XMM9_R9D_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 2, 16, 9, 9, 8,RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w },14674 { bs3CpuInstr3_vpinsrw_XMM8_XMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 2, 16, 255, 9, 8, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w },14675 14676 { bs3CpuInstr3_pinsrd_XMM1_EDX_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 4, 32, 2, 1, 1,RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d },14677 { bs3CpuInstr3_pinsrd_XMM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM32, T_SSE4_1, 4, 32, 255, 1, 1, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d },14678 { bs3CpuInstr3_pinsrd_XMM1_EDX_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 4, 32, 2, 1, 1,RT_ELEMENTS(s_aValues00_d), s_aValues00_d },14679 { bs3CpuInstr3_pinsrd_XMM1_FSxBX_000h_icebp_c64, 255, RM_MEM32, T_SSE4_1, 4, 32, 255, 1, 1, RT_ELEMENTS(s_aValues00_d), s_aValues00_d },14680 14681 { bs3CpuInstr3_pinsrd_XMM8_R9D_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 4, 32, 9, 8, 8,RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d },14682 { bs3CpuInstr3_pinsrd_XMM8_FSxBX_0FFh_icebp_c64, 255, RM_MEM32, T_SSE4_1, 4, 32, 255, 8, 8, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d },14683 { bs3CpuInstr3_pinsrd_XMM8_R9D_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 4, 32, 9, 8, 8,RT_ELEMENTS(s_aValues00_d), s_aValues00_d },14684 { bs3CpuInstr3_pinsrd_XMM8_FSxBX_000h_icebp_c64, 255, RM_MEM32, T_SSE4_1, 4, 32, 255, 8, 8, RT_ELEMENTS(s_aValues00_d), s_aValues00_d },14685 14686 { bs3CpuInstr3_vpinsrd_XMM1_XMM2_EDX_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, 2, 2, 1,RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d },14687 { bs3CpuInstr3_vpinsrd_XMM1_XMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, 255, 2, 1, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d },14688 { bs3CpuInstr3_vpinsrd_XMM1_XMM2_EDX_000h_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, 2, 2, 1,RT_ELEMENTS(s_aValues00_d), s_aValues00_d },14689 { bs3CpuInstr3_vpinsrd_XMM1_XMM2_FSxBX_000h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, 255, 2, 1, RT_ELEMENTS(s_aValues00_d), s_aValues00_d },14690 14691 { bs3CpuInstr3_vpinsrd_XMM8_XMM9_R9D_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, 9, 9, 8,RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d },14692 { bs3CpuInstr3_vpinsrd_XMM8_XMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, 255, 9, 8, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d },14693 { bs3CpuInstr3_vpinsrd_XMM8_XMM9_R9D_000h_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, 9, 9, 8,RT_ELEMENTS(s_aValues00_d), s_aValues00_d },14694 { bs3CpuInstr3_vpinsrd_XMM8_XMM9_FSxBX_000h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, 255, 9, 8, RT_ELEMENTS(s_aValues00_d), s_aValues00_d },14695 14696 { bs3CpuInstr3_pinsrq_XMM1_RDX_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 64, 2, 1, 1,RT_ELEMENTS(s_aValuesFF_q), s_aValuesFF_q },14697 { bs3CpuInstr3_pinsrq_XMM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM64, T_SSE4_1, 8, 64, 255, 1, 1, RT_ELEMENTS(s_aValuesFF_q), s_aValuesFF_q },14698 { bs3CpuInstr3_pinsrq_XMM1_RDX_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 64, 2, 1, 1,RT_ELEMENTS(s_aValues00_q), s_aValues00_q },14699 { bs3CpuInstr3_pinsrq_XMM1_FSxBX_000h_icebp_c64, 255, RM_MEM64, T_SSE4_1, 8, 64, 255, 1, 1, RT_ELEMENTS(s_aValues00_q), s_aValues00_q },14700 14701 { bs3CpuInstr3_pinsrq_XMM8_R9_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 64, 9, 8, 8,RT_ELEMENTS(s_aValuesFF_q), s_aValuesFF_q },14702 { bs3CpuInstr3_pinsrq_XMM8_FSxBX_0FFh_icebp_c64, 255, RM_MEM64, T_SSE4_1, 8, 64, 255, 8, 8, RT_ELEMENTS(s_aValuesFF_q), s_aValuesFF_q },14703 { bs3CpuInstr3_pinsrq_XMM8_R9_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 64, 9, 8, 8,RT_ELEMENTS(s_aValues00_q), s_aValues00_q },14704 { bs3CpuInstr3_pinsrq_XMM8_FSxBX_000h_icebp_c64, 255, RM_MEM64, T_SSE4_1, 8, 64, 255, 8, 8, RT_ELEMENTS(s_aValues00_q), s_aValues00_q },14705 14706 { bs3CpuInstr3_vpinsrq_XMM1_XMM2_RDX_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 8, 64, 2, 2, 1,RT_ELEMENTS(s_aValuesFF_q), s_aValuesFF_q },14707 { bs3CpuInstr3_vpinsrq_XMM1_XMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, 255, 2, 1, RT_ELEMENTS(s_aValuesFF_q), s_aValuesFF_q },14708 { bs3CpuInstr3_vpinsrq_XMM1_XMM2_RDX_000h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 64, 2, 2, 1,RT_ELEMENTS(s_aValues00_q), s_aValues00_q },14709 { bs3CpuInstr3_vpinsrq_XMM1_XMM2_FSxBX_000h_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, 255, 2, 1, RT_ELEMENTS(s_aValues00_q), s_aValues00_q },14710 14711 { bs3CpuInstr3_vpinsrq_XMM8_XMM9_R9_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 8, 64, 9, 9, 8,RT_ELEMENTS(s_aValuesFF_q), s_aValuesFF_q },14712 { bs3CpuInstr3_vpinsrq_XMM8_XMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, 255, 9, 8, RT_ELEMENTS(s_aValuesFF_q), s_aValuesFF_q },14713 { bs3CpuInstr3_vpinsrq_XMM8_XMM9_R9_000h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 64, 9, 9, 8,RT_ELEMENTS(s_aValues00_q), s_aValues00_q },14714 { bs3CpuInstr3_vpinsrq_XMM8_XMM9_FSxBX_000h_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, 255, 9, 8, RT_ELEMENTS(s_aValues00_q), s_aValues00_q },14605 { bs3CpuInstr3_pinsrb_XMM1_EDX_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 1, XMM1, XMM1, EDX, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, 14606 { bs3CpuInstr3_pinsrb_XMM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM8, T_SSE4_1, 1, XMM1, XMM1, FSxBX, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, 14607 { bs3CpuInstr3_pinsrb_XMM1_EDX_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 1, XMM1, XMM1, EDX, RT_ELEMENTS(s_aValues00_b), s_aValues00_b }, 14608 { bs3CpuInstr3_pinsrb_XMM1_FSxBX_000h_icebp_c64, 255, RM_MEM8, T_SSE4_1, 1, XMM1, XMM1, FSxBX, RT_ELEMENTS(s_aValues00_b), s_aValues00_b }, 14609 14610 { bs3CpuInstr3_pinsrb_XMM8_R9D_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 1, XMM8, XMM8, R9D, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, 14611 { bs3CpuInstr3_pinsrb_XMM8_FSxBX_0FFh_icebp_c64, 255, RM_MEM8, T_SSE4_1, 1, XMM8, XMM8, FSxBX, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, 14612 { bs3CpuInstr3_pinsrb_XMM8_R9D_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 1, XMM8, XMM8, R9D, RT_ELEMENTS(s_aValues00_b), s_aValues00_b }, 14613 { bs3CpuInstr3_pinsrb_XMM8_FSxBX_000h_icebp_c64, 255, RM_MEM8, T_SSE4_1, 1, XMM8, XMM8, FSxBX, RT_ELEMENTS(s_aValues00_b), s_aValues00_b }, 14614 14615 { bs3CpuInstr3_vpinsrb_XMM1_XMM2_EDX_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 1, XMM1, XMM2, EDX, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, 14616 { bs3CpuInstr3_vpinsrb_XMM1_XMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_AC, RM_MEM8, T_AVX_128, 1, XMM1, XMM2, FSxBX, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, 14617 { bs3CpuInstr3_vpinsrb_XMM1_XMM2_EDX_000h_icebp_c64, 255, RM_REG, T_AVX_128, 1, XMM1, XMM2, EDX, RT_ELEMENTS(s_aValues00_b), s_aValues00_b }, 14618 { bs3CpuInstr3_vpinsrb_XMM1_XMM2_FSxBX_000h_icebp_c64, X86_XCPT_AC, RM_MEM8, T_AVX_128, 1, XMM1, XMM2, FSxBX, RT_ELEMENTS(s_aValues00_b), s_aValues00_b }, 14619 14620 { bs3CpuInstr3_vpinsrb_XMM8_XMM9_R9D_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 1, XMM8, XMM9, R9D, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, 14621 { bs3CpuInstr3_vpinsrb_XMM8_XMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_AC, RM_MEM8, T_AVX_128, 1, XMM8, XMM9, FSxBX, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, 14622 { bs3CpuInstr3_vpinsrb_XMM8_XMM9_R9D_000h_icebp_c64, 255, RM_REG, T_AVX_128, 1, XMM8, XMM9, R9D, RT_ELEMENTS(s_aValues00_b), s_aValues00_b }, 14623 { bs3CpuInstr3_vpinsrb_XMM8_XMM9_FSxBX_000h_icebp_c64, X86_XCPT_AC, RM_MEM8, T_AVX_128, 1, XMM8, XMM9, FSxBX, RT_ELEMENTS(s_aValues00_b), s_aValues00_b }, 14624 14625 { bs3CpuInstr3_pinsrw_MM1_EDX_000h_icebp_c64, 255, RM_REG, T_MMX_SSE, 2, MM1, MM1, EDX, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, 14626 { bs3CpuInstr3_pinsrw_MM1_R9D_000h_icebp_c64, 255, RM_REG, T_MMX_SSE, 2, MM1, MM1, R9D, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, 14627 { bs3CpuInstr3_pinsrw_MM1_FSxBX_000h_icebp_c64, 255, RM_MEM32, T_MMX_SSE, 2, MM1, MM1, FSxBX, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, 14628 { bs3CpuInstr3_pinsrw_MM1_EDX_0FFh_icebp_c64, 255, RM_REG, T_MMX_SSE, 2, MM1, MM1, EDX, RT_ELEMENTS(s_aValuesFF_w_64), s_aValuesFF_w_64 }, 14629 { bs3CpuInstr3_pinsrw_MM1_R9D_0FFh_icebp_c64, 255, RM_REG, T_MMX_SSE, 2, MM1, MM1, R9D, RT_ELEMENTS(s_aValuesFF_w_64), s_aValuesFF_w_64 }, 14630 { bs3CpuInstr3_pinsrw_MM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM32, T_MMX_SSE, 2, MM1, MM1, FSxBX, RT_ELEMENTS(s_aValuesFF_w_64), s_aValuesFF_w_64 }, 14631 14632 { bs3CpuInstr3_pinsrw_XMM1_EDX_000h_icebp_c64, 255, RM_REG, T_SSE, 2, XMM1, XMM1, EDX, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, 14633 { bs3CpuInstr3_pinsrw_XMM1_FSxBX_000h_icebp_c64, 255, RM_MEM32, T_SSE, 2, XMM1, XMM1, FSxBX, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, 14634 { bs3CpuInstr3_pinsrw_XMM1_EDX_0FFh_icebp_c64, 255, RM_REG, T_SSE, 2, XMM1, XMM1, EDX, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, 14635 { bs3CpuInstr3_pinsrw_XMM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM32, T_SSE, 2, XMM1, XMM1, FSxBX, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, 14636 14637 { bs3CpuInstr3_pinsrw_XMM8_R9D_000h_icebp_c64, 255, RM_REG, T_SSE, 2, XMM8, XMM8, R9D, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, 14638 { bs3CpuInstr3_pinsrw_XMM8_FSxBX_000h_icebp_c64, 255, RM_MEM32, T_SSE, 2, XMM8, XMM8, FSxBX, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, 14639 { bs3CpuInstr3_pinsrw_XMM8_R9D_0FFh_icebp_c64, 255, RM_REG, T_SSE, 2, XMM8, XMM8, R9D, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, 14640 { bs3CpuInstr3_pinsrw_XMM8_FSxBX_0FFh_icebp_c64, 255, RM_MEM32, T_SSE, 2, XMM8, XMM8, FSxBX, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, 14641 14642 { bs3CpuInstr3_pinsrw_XMM1_RDX_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 2, XMM1, XMM1, RDX, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, 14643 { bs3CpuInstr3_pinsrw_XMM8_R9_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 2, XMM8, XMM8, R9, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, 14644 { bs3CpuInstr3_pinsrw_XMM1_RDX_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 2, XMM1, XMM1, RDX, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, 14645 { bs3CpuInstr3_pinsrw_XMM8_R9_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 2, XMM8, XMM8, R9, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, 14646 14647 { bs3CpuInstr3_vpinsrw_XMM1_XMM2_EDX_000h_icebp_c64, 255, RM_REG, T_AVX_128, 2, XMM1, XMM2, EDX, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, 14648 { bs3CpuInstr3_vpinsrw_XMM1_XMM2_FSxBX_000h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 2, XMM1, XMM2, FSxBX, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, 14649 { bs3CpuInstr3_vpinsrw_XMM1_XMM2_EDX_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 2, XMM1, XMM2, EDX, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, 14650 { bs3CpuInstr3_vpinsrw_XMM1_XMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 2, XMM1, XMM2, FSxBX, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, 14651 14652 { bs3CpuInstr3_vpinsrw_XMM8_XMM9_R9D_000h_icebp_c64, 255, RM_REG, T_AVX_128, 2, XMM8, XMM9, R9D, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, 14653 { bs3CpuInstr3_vpinsrw_XMM8_XMM9_FSxBX_000h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 2, XMM8, XMM9, FSxBX, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, 14654 { bs3CpuInstr3_vpinsrw_XMM8_XMM9_R9D_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 2, XMM8, XMM9, R9D, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, 14655 { bs3CpuInstr3_vpinsrw_XMM8_XMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 2, XMM8, XMM9, FSxBX, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, 14656 14657 { bs3CpuInstr3_pinsrd_XMM1_EDX_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 4, XMM1, XMM1, EDX, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d }, 14658 { bs3CpuInstr3_pinsrd_XMM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM32, T_SSE4_1, 4, XMM1, XMM1, FSxBX, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d }, 14659 { bs3CpuInstr3_pinsrd_XMM1_EDX_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 4, XMM1, XMM1, EDX, RT_ELEMENTS(s_aValues00_d), s_aValues00_d }, 14660 { bs3CpuInstr3_pinsrd_XMM1_FSxBX_000h_icebp_c64, 255, RM_MEM32, T_SSE4_1, 4, XMM1, XMM1, FSxBX, RT_ELEMENTS(s_aValues00_d), s_aValues00_d }, 14661 14662 { bs3CpuInstr3_pinsrd_XMM8_R9D_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 4, XMM8, XMM8, R9D, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d }, 14663 { bs3CpuInstr3_pinsrd_XMM8_FSxBX_0FFh_icebp_c64, 255, RM_MEM32, T_SSE4_1, 4, XMM8, XMM8, FSxBX, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d }, 14664 { bs3CpuInstr3_pinsrd_XMM8_R9D_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 4, XMM8, XMM8, R9D, RT_ELEMENTS(s_aValues00_d), s_aValues00_d }, 14665 { bs3CpuInstr3_pinsrd_XMM8_FSxBX_000h_icebp_c64, 255, RM_MEM32, T_SSE4_1, 4, XMM8, XMM8, FSxBX, RT_ELEMENTS(s_aValues00_d), s_aValues00_d }, 14666 14667 { bs3CpuInstr3_vpinsrd_XMM1_XMM2_EDX_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 4, XMM1, XMM2, EDX, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d }, 14668 { bs3CpuInstr3_vpinsrd_XMM1_XMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, XMM1, XMM2, FSxBX, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d }, 14669 { bs3CpuInstr3_vpinsrd_XMM1_XMM2_EDX_000h_icebp_c64, 255, RM_REG, T_AVX_128, 4, XMM1, XMM2, EDX, RT_ELEMENTS(s_aValues00_d), s_aValues00_d }, 14670 { bs3CpuInstr3_vpinsrd_XMM1_XMM2_FSxBX_000h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, XMM1, XMM2, FSxBX, RT_ELEMENTS(s_aValues00_d), s_aValues00_d }, 14671 14672 { bs3CpuInstr3_vpinsrd_XMM8_XMM9_R9D_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 4, XMM8, XMM9, R9D, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d }, 14673 { bs3CpuInstr3_vpinsrd_XMM8_XMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, XMM8, XMM9, FSxBX, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d }, 14674 { bs3CpuInstr3_vpinsrd_XMM8_XMM9_R9D_000h_icebp_c64, 255, RM_REG, T_AVX_128, 4, XMM8, XMM9, R9D, RT_ELEMENTS(s_aValues00_d), s_aValues00_d }, 14675 { bs3CpuInstr3_vpinsrd_XMM8_XMM9_FSxBX_000h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, XMM8, XMM9, FSxBX, RT_ELEMENTS(s_aValues00_d), s_aValues00_d }, 14676 14677 { bs3CpuInstr3_pinsrq_XMM1_RDX_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 8, XMM1, XMM1, RDX, RT_ELEMENTS(s_aValuesFF_q), s_aValuesFF_q }, 14678 { bs3CpuInstr3_pinsrq_XMM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM64, T_SSE4_1, 8, XMM1, XMM1, FSxBX, RT_ELEMENTS(s_aValuesFF_q), s_aValuesFF_q }, 14679 { bs3CpuInstr3_pinsrq_XMM1_RDX_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 8, XMM1, XMM1, RDX, RT_ELEMENTS(s_aValues00_q), s_aValues00_q }, 14680 { bs3CpuInstr3_pinsrq_XMM1_FSxBX_000h_icebp_c64, 255, RM_MEM64, T_SSE4_1, 8, XMM1, XMM1, FSxBX, RT_ELEMENTS(s_aValues00_q), s_aValues00_q }, 14681 14682 { bs3CpuInstr3_pinsrq_XMM8_R9_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 8, XMM8, XMM8, R9, RT_ELEMENTS(s_aValuesFF_q), s_aValuesFF_q }, 14683 { bs3CpuInstr3_pinsrq_XMM8_FSxBX_0FFh_icebp_c64, 255, RM_MEM64, T_SSE4_1, 8, XMM8, XMM8, FSxBX, RT_ELEMENTS(s_aValuesFF_q), s_aValuesFF_q }, 14684 { bs3CpuInstr3_pinsrq_XMM8_R9_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 8, XMM8, XMM8, R9, RT_ELEMENTS(s_aValues00_q), s_aValues00_q }, 14685 { bs3CpuInstr3_pinsrq_XMM8_FSxBX_000h_icebp_c64, 255, RM_MEM64, T_SSE4_1, 8, XMM8, XMM8, FSxBX, RT_ELEMENTS(s_aValues00_q), s_aValues00_q }, 14686 14687 { bs3CpuInstr3_vpinsrq_XMM1_XMM2_RDX_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 8, XMM1, XMM2, RDX, RT_ELEMENTS(s_aValuesFF_q), s_aValuesFF_q }, 14688 { bs3CpuInstr3_vpinsrq_XMM1_XMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, XMM1, XMM2, FSxBX, RT_ELEMENTS(s_aValuesFF_q), s_aValuesFF_q }, 14689 { bs3CpuInstr3_vpinsrq_XMM1_XMM2_RDX_000h_icebp_c64, 255, RM_REG, T_AVX_128, 8, XMM1, XMM2, RDX, RT_ELEMENTS(s_aValues00_q), s_aValues00_q }, 14690 { bs3CpuInstr3_vpinsrq_XMM1_XMM2_FSxBX_000h_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, XMM1, XMM2, FSxBX, RT_ELEMENTS(s_aValues00_q), s_aValues00_q }, 14691 14692 { bs3CpuInstr3_vpinsrq_XMM8_XMM9_R9_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 8, XMM8, XMM9, R9, RT_ELEMENTS(s_aValuesFF_q), s_aValuesFF_q }, 14693 { bs3CpuInstr3_vpinsrq_XMM8_XMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, XMM8, XMM9, FSxBX, RT_ELEMENTS(s_aValuesFF_q), s_aValuesFF_q }, 14694 { bs3CpuInstr3_vpinsrq_XMM8_XMM9_R9_000h_icebp_c64, 255, RM_REG, T_AVX_128, 8, XMM8, XMM9, R9, RT_ELEMENTS(s_aValues00_q), s_aValues00_q }, 14695 { bs3CpuInstr3_vpinsrq_XMM8_XMM9_FSxBX_000h_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, XMM8, XMM9, FSxBX, RT_ELEMENTS(s_aValues00_q), s_aValues00_q }, 14715 14696 }; 14716 14697 -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32
r106733 r106736 178 178 /* The maximum integer value (all 23 + 1 implied bit of the fraction part set) without losing precision. */ 179 179 #define FP32_NORM_SAFE_INT_MAX(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_NORM_MAX, FP32_EXP_SAFE_INT_MAX) 180 /* The minimum integer value without losing precision. */181 #define FP32_NORM_SAFE_INT_MIN(a_Sign) RTFLOAT32U_INIT_C(a_Sign, FP32_FRAC_NORM_MIN, FP32_EXP_SAFE_INT_MIN)182 180 183 181 /* … … 402 400 /* The maximum integer value (all 52 + 1 implied bit of the fraction part set) without losing precision. */ 403 401 #define FP64_NORM_SAFE_INT_MAX(a_Sign) RTFLOAT64U_INIT_C(a_Sign, FP64_FRAC_NORM_MAX, FP64_EXP_SAFE_INT_MAX) 404 /* The minimum integer value without losing precision. */405 #define FP64_NORM_SAFE_INT_MIN(a_Sign) RTFLOAT64U_INIT_C(a_Sign, FP64_FRAC_NORM_MIN, FP64_EXP_SAFE_INT_MIN)406 402 407 403 /* … … 3343 3339 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_OM_FIXED, 3344 3340 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_OM_FIXED }, 3345 { { /*src2 */ { FP32_NORM_ SAFE_INT_MIN(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1) } },3341 { { /*src2 */ { FP32_NORM_MIN(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MIN(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1) } }, 3346 3342 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1) } }, 3347 3343 { /* => */ { FP32_V(0, FP32_FRAC_NORM_MAX, FP32_EXP_SAFE_INT_MAX), FP32_0(0), FP32_0(0), FP32_V(0, FP32_FRAC_NORM_MAX, FP32_EXP_SAFE_INT_MAX + 1), FP32_V(0, FP32_FRAC_NORM_MAX, FP32_EXP_SAFE_INT_MAX), FP32_0(0), FP32_0(0), FP32_V(1, FP32_FRAC_NORM_MAX, FP32_EXP_SAFE_INT_MAX + 1) } }, … … 3388 3384 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 3389 3385 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO }, 3390 { { /*src2 */ { FP32_NORM_ SAFE_INT_MIN(0), FP32_0(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0), FP32_0(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0)} },3391 { /*src1 */ { FP32_NORM_ SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0), FP32_NORM_SAFE_INT_MIN(0)} },3392 { /* => */ { FP32_0(1), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0, FP32_EXP_SAFE_INT_MIN + 1), FP32_0(1), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_V(0, 0, FP32_EXP_SAFE_INT_MIN + 1) } },3386 { { /*src2 */ { FP32_NORM_MIN(0), FP32_0(0), FP32_NORM_MIN(0), FP32_NORM_MIN(0), FP32_NORM_MIN(0), FP32_0(0), FP32_NORM_MIN(0), FP32_NORM_MIN(0) } }, 3387 { /*src1 */ { FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_0(0), FP32_NORM_MIN(0), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_0(0), FP32_NORM_MIN(0) } }, 3388 { /* => */ { FP32_0(1), FP32_NORM_MIN(1), FP32_NORM_MIN(0), FP32_V(0, 0, FP32_EXP_SAFE_INT_MIN + 1), FP32_0(1), FP32_NORM_MIN(1), FP32_NORM_MIN(0), FP32_V(0, 0, FP32_EXP_SAFE_INT_MIN + 1) } }, 3393 3389 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 3394 3390 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 3395 3391 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN }, 3396 { { /*src2 */ { FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_V(0, 0x3ce348, 0x90)/*193421.125*/, FP32_V(0, 0x6423f2, 0x92)/*934463.125*/, FP32_NORM_ SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0),FP32_V(0, 0x16b43a, 0x93)/*1234567.25*/, FP32_V(0, 0x792318, 0x91)/*510232.75*/, FP32_V(0, 0x600000, 0x7e)/* 0.875*/ } },3397 { /*src1 */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_V(0, 0x430ebc, 0x91)/*399477.875*/, FP32_V(1, 0x0a19f0, 0x8f)/*-70707.875*/, FP32_NORM_ SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0),FP32_V(0, 0x00c6d3, 0x94)/*2109876.75*/, FP32_V(1, 0x316740, 0x8e)/*-45415.25*/, FP32_V(0, 0x769b50, 0x92)/*1010101.000*/ } },3392 { { /*src2 */ { FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_V(0, 0x3ce348, 0x90)/*193421.125*/, FP32_V(0, 0x6423f2, 0x92)/*934463.125*/, FP32_NORM_MIN(1), FP32_NORM_MIN(0), FP32_V(0, 0x16b43a, 0x93)/*1234567.25*/, FP32_V(0, 0x792318, 0x91)/*510232.75*/, FP32_V(0, 0x600000, 0x7e)/* 0.875*/ } }, 3393 { /*src1 */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_V(0, 0x430ebc, 0x91)/*399477.875*/, FP32_V(1, 0x0a19f0, 0x8f)/*-70707.875*/, FP32_NORM_MIN(1), FP32_NORM_MIN(0), FP32_V(0, 0x00c6d3, 0x94)/*2109876.75*/, FP32_V(1, 0x316740, 0x8e)/*-45415.25*/, FP32_V(0, 0x769b50, 0x92)/*1010101.000*/ } }, 3398 3394 { /* => */ { FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/, FP32_V(0, 0x10c030, 0x92)/*592899.000*/, FP32_V(0, 0x52e0b4, 0x92)/*863755.250*/, FP32_V(1, 0, FP32_EXP_SAFE_INT_MIN + 1), FP32_V(0, 0, FP32_EXP_SAFE_INT_MIN + 1), FP32_V(0, 0x4c20f0, 0x94)/*3344444.00*/, FP32_V(0, 0x62f630, 0x91)/*464817.50*/, FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/ } }, 3399 3395 /*mxcsr:in */ X86_MXCSR_RC_DOWN, … … 3680 3676 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* i7-10700, IEM */, 3681 3677 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* i7-10700, IEM */ }, 3682 { { /*src2 */ { FP64_NORM_ SAFE_INT_MIN(0),FP64_NORM_MAX(0), FP64_0(0), FP64_NORM_SAFE_INT_MAX(1) } },3678 { { /*src2 */ { FP64_NORM_MIN(0), FP64_NORM_MAX(0), FP64_0(0), FP64_NORM_SAFE_INT_MAX(1) } }, 3683 3679 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_MAX(1), FP64_0(0), FP64_NORM_SAFE_INT_MAX(1) } }, 3684 3680 { /* => */ { FP64_V(0, FP64_FRAC_NORM_MAX, FP64_EXP_SAFE_INT_MAX), FP64_0(0), FP64_0(0), FP64_V(1, FP64_FRAC_NORM_MAX, FP64_EXP_SAFE_INT_MAX + 1) } }, … … 3719 3715 /*128:out */ X86_MXCSR_FZ, 3720 3716 /*256:out */ X86_MXCSR_FZ }, 3721 { { /*src2 */ { FP64_NORM_ SAFE_INT_MIN(0), FP64_0(0), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(0)} },3722 { /*src1 */ { FP64_NORM_ SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(1), FP64_0(0), FP64_NORM_SAFE_INT_MIN(0)} },3723 { /* => */ { FP64_0(1), FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(0), FP64_V(0, 0, FP32_EXP_SAFE_INT_MIN + 1) } },3717 { { /*src2 */ { FP64_NORM_MIN(0), FP64_0(0), FP64_NORM_MIN(0), FP64_NORM_MIN(0) } }, 3718 { /*src1 */ { FP64_NORM_MIN(1), FP64_NORM_MIN(1), FP64_0(0), FP64_NORM_MIN(0) } }, 3719 { /* => */ { FP64_0(1), FP64_NORM_MIN(1), FP64_NORM_MIN(0), FP64_V(0, 0, FP32_EXP_SAFE_INT_MIN + 1) } }, 3724 3720 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 3725 3721 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 3726 3722 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN }, 3727 { { /*src2 */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_0(0), FP64_0(0), FP64_NORM_ SAFE_INT_MIN(1)} },3728 { /*src1 */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_0(0), FP64_0(0), FP64_NORM_ SAFE_INT_MIN(1)} },3723 { { /*src2 */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_0(0), FP64_0(0), FP64_NORM_MIN(1) } }, 3724 { /*src1 */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_0(0), FP64_0(0), FP64_NORM_MIN(1) } }, 3729 3725 { /* => */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_0(0), FP64_0(0), FP64_V(1, 0, FP32_EXP_SAFE_INT_MIN + 1) } }, 3730 3726 /*mxcsr:in */ X86_MXCSR_RC_UP, … … 4007 4003 /*128:out */ X86_MXCSR_OM | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_OM_FIXED, 4008 4004 /*256:out */ -1 }, 4009 { { /*src2 */ { FP32_NORM_ SAFE_INT_MIN(0),FP32_RAND_x7_V3 } },4005 { { /*src2 */ { FP32_NORM_MIN(0), FP32_RAND_x7_V3 } }, 4010 4006 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V0 } }, 4011 4007 { /* => */ { FP32_V(0, FP32_FRAC_NORM_MAX, FP32_EXP_SAFE_INT_MAX), FP32_RAND_x7_V0 } }, … … 4013 4009 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, 4014 4010 /*256:out */ -1 }, 4015 { { /*src2 */ { FP32_NORM_ SAFE_INT_MIN(1),FP32_RAND_x7_V6 } },4011 { { /*src2 */ { FP32_NORM_MIN(1), FP32_RAND_x7_V6 } }, 4016 4012 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(1), FP32_RAND_x7_V4 } }, 4017 4013 { /* => */ { FP32_V(1, FP32_FRAC_NORM_MAX, FP32_EXP_SAFE_INT_MAX), FP32_RAND_x7_V4 } }, … … 4070 4066 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 4071 4067 /*256:out */ -1 }, 4072 { { /*src2 */ { FP32_NORM_ SAFE_INT_MIN(0), FP32_RAND_x7_V2 } },4073 { /*src1 */ { FP32_NORM_ SAFE_INT_MIN(1), FP32_RAND_x7_V3 } },4074 { /* => */ { FP32_0(0), 4068 { { /*src2 */ { FP32_NORM_MIN(0), FP32_RAND_x7_V2 } }, 4069 { /*src1 */ { FP32_NORM_MIN(1), FP32_RAND_x7_V3 } }, 4070 { /* => */ { FP32_0(0), FP32_RAND_x7_V3 } }, 4075 4071 /*mxcsr:in */ X86_MXCSR_FZ, 4076 4072 /*128:out */ X86_MXCSR_FZ, … … 4346 4342 /*128:out */ X86_MXCSR_OM | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_OM_FIXED, 4347 4343 /*256:out */ -1 }, 4348 { { /*src2 */ { FP64_NORM_ SAFE_INT_MIN(0),FP64_RAND_V1(1), FP64_RAND_V3(0), FP64_RAND_V0(1) } },4344 { { /*src2 */ { FP64_NORM_MIN(0), FP64_RAND_V1(1), FP64_RAND_V3(0), FP64_RAND_V0(1) } }, 4349 4345 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, 4350 4346 { /* => */ { FP64_V(0, FP64_FRAC_NORM_MAX, FP64_EXP_SAFE_INT_MAX), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } }, … … 4352 4348 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, 4353 4349 /*256:out */ -1 }, 4354 { { /*src2 */ { FP64_NORM_ SAFE_INT_MIN(1),FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(1) } },4350 { { /*src2 */ { FP64_NORM_MIN(1), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(1) } }, 4355 4351 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(1), FP64_RAND_V2(1), FP64_RAND_V0(1), FP64_RAND_V1(0) } }, 4356 4352 { /* => */ { FP64_V(1, FP64_FRAC_NORM_MAX, FP64_EXP_SAFE_INT_MAX), FP64_RAND_V2(1), FP64_RAND_V0(1), FP64_RAND_V1(0) } }, … … 4415 4411 /*128:out */ X86_MXCSR_FZ, 4416 4412 /*256:out */ -1 }, 4417 { { /*src2 */ { FP64_NORM_ SAFE_INT_MIN(0), FP64_RAND_V2(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } },4418 { /*src1 */ { FP64_NORM_ SAFE_INT_MIN(1), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V1(1) } },4419 { /* => */ { FP64_0(1), 4413 { { /*src2 */ { FP64_NORM_MIN(0), FP64_RAND_V2(1), FP64_RAND_V2(0), FP64_RAND_V3(0) } }, 4414 { /*src1 */ { FP64_NORM_MIN(1), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V1(1) } }, 4415 { /* => */ { FP64_0(1), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V1(1) } }, 4420 4416 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 4421 4417 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, … … 4717 4713 /*128:out */ X86_MXCSR_OM | X86_MXCSR_RC_ZERO, 4718 4714 /*256:out */ X86_MXCSR_OM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_OM_FIXED }, 4719 { { /*src2 */ { FP32_NORM_ SAFE_INT_MIN(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MIN(0),FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1) } },4720 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_ SAFE_INT_MIN(0),FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1) } },4715 { { /*src2 */ { FP32_NORM_MIN(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_MIN(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1) } }, 4716 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MIN(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1) } }, 4721 4717 { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_V(1, FP32_FRAC_NORM_MAX, FP32_EXP_SAFE_INT_MAX + 1), FP32_NORM_MAX(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_MAX(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_MAX(0), FP32_NORM_SAFE_INT_MAX(1) } }, 4722 4718 /*mxcsr:in */ X86_MXCSR_RC_ZERO, … … 4768 4764 /*128:out */ X86_MXCSR_FZ, 4769 4765 /*256:out */ X86_MXCSR_FZ }, 4770 { { /*src2 */ { FP32_V(0, 0x6423f2, 0x92)/* 934463.125*/, FP32_V(1, 0x0a19f0, 0x8f)/*-70707.875*/, FP32_NORM_ SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0),FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_V(0, 0x769b50, 0x92)/*1010101.000*/ } },4766 { { /*src2 */ { FP32_V(0, 0x6423f2, 0x92)/* 934463.125*/, FP32_V(1, 0x0a19f0, 0x8f)/*-70707.875*/, FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MIN(0), FP32_NORM_MIN(0), FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_V(0, 0x769b50, 0x92)/*1010101.000*/ } }, 4771 4767 { /*src1 */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_V(0, 0x430ebc, 0x91)/*399477.875*/, FP32_V(0, 0x3ce348, 0x90)/*193421.125*/, FP32_V(0, 0x16b43a, 0x93)/*1234567.25*/, FP32_V(0, 0x00c6d3, 0x94)/*2109876.75*/, FP32_V(0, 0x792318, 0x91)/*510232.750*/, FP32_V(1, 0x316740, 0x8e)/* -45415.250*/ } }, 4772 4768 { /* => */ { FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/, FP32_V(0, 0x10c030, 0x92)/*592899.000*/, FP32_V(0, 0x52e0b4, 0x92)/*863755.250*/, FP32_V(1, 0, FP32_EXP_SAFE_INT_MIN + 1), FP32_V(0, 0x4c20f0, 0x94)/*3344444.00*/, FP32_V(0, 0x62f630, 0x91)/*464817.50*/, FP32_V(0, 0, FP32_EXP_SAFE_INT_MIN + 1), FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/ } }, … … 5058 5054 /*128:out */ X86_MXCSR_RC_ZERO, 5059 5055 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY }, 5060 { { /*src2 */ { FP64_NORM_ SAFE_INT_MIN(0),FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(1) } },5061 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_ SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MIN(0)} },5056 { { /*src2 */ { FP64_NORM_MIN(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(1) } }, 5057 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_MIN(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_MIN(0) } }, 5062 5058 { /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0), FP64_0(0) } }, 5063 5059 /*mxcsr:in */ X86_MXCSR_RC_ZERO, … … 5091 5087 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 5092 5088 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO }, 5093 { { /*src2 */ { FP64_NORM_ SAFE_INT_MIN(0), FP64_0(0), FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(1)} },5094 { /*src1 */ { FP64_NORM_ SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(0)} },5095 { /* => */ { FP64_0(1), FP64_NORM_SAFE_INT_MIN(0), FP64_V(0, 0, FP32_EXP_SAFE_INT_MIN + 1), FP64_V(1, 0, FP32_EXP_SAFE_INT_MIN + 1) } },5089 { { /*src2 */ { FP64_NORM_MIN(0), FP64_0(0), FP64_NORM_MIN(1), FP64_NORM_MIN(1) } }, 5090 { /*src1 */ { FP64_NORM_MIN(1), FP64_NORM_MIN(0), FP64_NORM_MIN(0), FP64_NORM_MIN(0) } }, 5091 { /* => */ { FP64_0(1), FP64_NORM_MIN(0), FP64_V(0, 0, FP32_EXP_SAFE_INT_MIN + 1), FP64_V(1, 0, FP32_EXP_SAFE_INT_MIN + 1) } }, 5096 5092 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 5097 5093 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 5098 5094 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN }, 5099 { { /*src2 */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_V(1, 0xc122186c3cfd0, 0x42d)/*-123456789876543.25*/, FP64_NORM_ SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(1)} },5100 { /*src1 */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_V(0, 0xb88e0395d49b0, 0x42d)/* 121098765432102.75*/, FP64_NORM_V0(0), 5101 { /* => */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_0(0), FP64_0(0), 5095 { { /*src2 */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_V(1, 0xc122186c3cfd0, 0x42d)/*-123456789876543.25*/, FP64_NORM_MIN(1), FP64_NORM_MIN(1) } }, 5096 { /*src1 */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_V(0, 0xb88e0395d49b0, 0x42d)/* 121098765432102.75*/, FP64_NORM_V0(0), FP64_NORM_V0(1) } }, 5097 { /* => */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_0(0), FP64_0(0), FP64_V(1, 0, FP32_EXP_SAFE_INT_MIN + 1) } }, 5102 5098 /*mxcsr:in */ X86_MXCSR_RC_UP, 5103 5099 /*128:out */ X86_MXCSR_RC_UP, … … 5426 5422 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE }, 5427 5423 #ifdef TODO_X86_MXCSR_PE_IEM_SSE /** @todo THIS FAILS ON IEM: X86_MXCSR_PE not set in 128:out(SSE-128) (but occasionally is set???); properly set in 128:out(AVX-128) */ 5428 /*--|23*/{ { /*src2 */ { FP32_NORM_ SAFE_INT_MIN(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MIN(0),FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1) } },5424 /*--|23*/{ { /*src2 */ { FP32_NORM_MIN(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_MIN(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1) } }, 5429 5425 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1) } }, 5430 5426 { /* => */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_INF(1), FP32_0(1), FP32_0(1), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_INF(1), FP32_0(1), FP32_0(1) } }, … … 5433 5429 /*256:out */ X86_MXCSR_RC_DOWN | X86_MXCSR_OE | X86_MXCSR_PE }, 5434 5430 #endif /* TODO_X86_MXCSR_PE_IEM_SSE */ 5435 /*22|24*/{ { /*src2 */ { FP32_NORM_ SAFE_INT_MIN(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MIN(0),FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1) } },5431 /*22|24*/{ { /*src2 */ { FP32_NORM_MIN(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_MIN(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1) } }, 5436 5432 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1) } }, 5437 5433 { /* => */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_INF(1), FP32_0(1), FP32_0(1), FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_INF(1), FP32_0(1), FP32_0(1) } }, … … 5478 5474 /*128:out */ X86_MXCSR_RC_UP, 5479 5475 /*256:out */ X86_MXCSR_RC_UP }, 5480 { { /*src2 */ { FP32_NORM_ SAFE_INT_MIN(0), FP32_0(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0), FP32_0(1), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1) } },5481 { /*src1 */ { FP32_NORM_ SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0), FP32_V(0, 0, FP32_EXP_SAFE_INT_MIN + 1), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0), FP32_NORM_SAFE_INT_MIN(1) } },5482 { /* => */ { FP32_0(0), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_0(0), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_0(0)} },5476 { { /*src2 */ { FP32_NORM_MIN(0), FP32_0(0), FP32_NORM_MIN(0), FP32_NORM_MIN(0), FP32_NORM_MIN(0), FP32_0(1), FP32_NORM_MIN(1), FP32_NORM_MIN(1) } }, 5477 { /*src1 */ { FP32_NORM_MIN(0), FP32_NORM_MIN(1), FP32_0(0), FP32_V(0, 0, FP32_EXP_SAFE_INT_MIN + 1), FP32_NORM_MIN(0), FP32_NORM_MIN(1), FP32_0(0), FP32_NORM_MIN(1) } }, 5478 { /* => */ { FP32_0(0), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MIN(0), FP32_0(0), FP32_NORM_MIN(1), FP32_NORM_MIN(0), FP32_0(0) } }, 5483 5479 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 5484 5480 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 5485 5481 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO }, 5486 { { /*src2 */ { FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_V(0, 0x3ce348, 0x90)/*193421.125*/, FP32_V(1, 0x0a19f0, 0x8f)/*-70707.875*/, FP32_NORM_ SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0),FP32_V(0, 0x00c6d3, 0x94)/*2109876.75*/, FP32_V(0, 0x316740, 0x8e)/* 45415.25*/, FP32_V(0, 0x600000, 0x7e)/* 0.875*/ } },5487 { /*src1 */ { FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/, FP32_V(0, 0x10c030, 0x92)/*592899.000*/, FP32_V(0, 0x52e0b4, 0x92)/*863755.250*/, FP32_NORM_ SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1),FP32_V(0, 0x4c20f0, 0x94)/*3344444.00*/, FP32_V(0, 0x792318, 0x91)/*510232.75*/, FP32_V(1, 0x769b50, 0x92)/*-1010101.000*/ } },5482 { { /*src2 */ { FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_V(0, 0x3ce348, 0x90)/*193421.125*/, FP32_V(1, 0x0a19f0, 0x8f)/*-70707.875*/, FP32_NORM_MIN(1), FP32_NORM_MIN(0), FP32_V(0, 0x00c6d3, 0x94)/*2109876.75*/, FP32_V(0, 0x316740, 0x8e)/* 45415.25*/, FP32_V(0, 0x600000, 0x7e)/* 0.875*/ } }, 5483 { /*src1 */ { FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/, FP32_V(0, 0x10c030, 0x92)/*592899.000*/, FP32_V(0, 0x52e0b4, 0x92)/*863755.250*/, FP32_NORM_MIN(0), FP32_NORM_MIN(1), FP32_V(0, 0x4c20f0, 0x94)/*3344444.00*/, FP32_V(0, 0x792318, 0x91)/*510232.75*/, FP32_V(1, 0x769b50, 0x92)/*-1010101.000*/ } }, 5488 5484 { /* => */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_V(0, 0x430ebc, 0x91)/*399477.875*/, FP32_V(0, 0x6423f2, 0x92)/*934463.125*/, FP32_V(0, 0, FP32_EXP_SAFE_INT_MIN + 1), FP32_V(1, 0, FP32_EXP_SAFE_INT_MIN + 1), FP32_V(0, 0x16b43a, 0x93)/*1234567.25*/, FP32_V(0, 0x62f630, 0x91)/*464817.50*/, FP32_V(1, 0x769b5e, 0x92)/*-1010101.875*/ } }, 5489 5485 /*mxcsr:in */ 0, … … 5786 5782 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, 5787 5783 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE }, 5788 { { /*src2 */ { FP64_NORM_ SAFE_INT_MIN(0),FP64_NORM_MAX(0), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MAX(1) } },5784 { { /*src2 */ { FP64_NORM_MIN(0), FP64_NORM_MAX(0), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MAX(1) } }, 5789 5785 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_MAX(1), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MAX(1) } }, 5790 5786 { /* => */ { FP64_V(0,0xffffffffffffe,0x433), FP64_NORM_MAX(1), FP64_0(0), FP64_0(0) } }, … … 5825 5821 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 5826 5822 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO }, 5827 { { /*src2 */ { FP64_NORM_SAFE_INT_MAX(1), FP64_0(0), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(1)} },5828 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_ SAFE_INT_MIN(1), FP64_0(0), FP64_NORM_SAFE_INT_MIN(0)} },5829 { /* => */ { FP64_0(0), FP64_NORM_ SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(1), FP64_V(0, 0, FP32_EXP_SAFE_INT_MIN + 1) } },5823 { { /*src2 */ { FP64_NORM_SAFE_INT_MAX(1), FP64_0(0), FP64_NORM_MIN(0), FP64_NORM_MIN(1) } }, 5824 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_MIN(1), FP64_0(0), FP64_NORM_MIN(0) } }, 5825 { /* => */ { FP64_0(0), FP64_NORM_MIN(1), FP64_NORM_MIN(1), FP64_V(0, 0, FP32_EXP_SAFE_INT_MIN + 1) } }, 5830 5826 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 5831 5827 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 5832 5828 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP }, 5833 { { /*src2 */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_0(0), FP64_0(1), FP64_NORM_ SAFE_INT_MIN(0)} },5834 { /*src1 */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_0(0), FP64_0(1), FP64_NORM_ SAFE_INT_MIN(1)} },5829 { { /*src2 */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_0(0), FP64_0(1), FP64_NORM_MIN(0) } }, 5830 { /*src1 */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_0(0), FP64_0(1), FP64_NORM_MIN(1) } }, 5835 5831 { /* => */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_0(1), FP64_0(1), FP64_V(1, 0, FP32_EXP_SAFE_INT_MIN + 1) } }, 5836 5832 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, … … 6083 6079 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, 6084 6080 /*256:out */ -1 }, 6085 { { /*src2 */ { FP32_NORM_ SAFE_INT_MIN(0),FP32_0_x7(0) } },6081 { { /*src2 */ { FP32_NORM_MIN(0), FP32_0_x7(0) } }, 6086 6082 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_0_x7(0) } }, 6087 6083 { /* => */ { FP32_V(0, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_0_x7(0) } }, … … 6089 6085 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, 6090 6086 /*256:out */ -1 }, 6091 { { /*src2 */ { FP32_NORM_ SAFE_INT_MIN(1),FP32_0_x7(0) } },6087 { { /*src2 */ { FP32_NORM_MIN(1), FP32_0_x7(0) } }, 6092 6088 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(1), FP32_0_x7(0) } }, 6093 6089 { /* => */ { FP32_V(1, FP32_FRAC_NORM_MAX - 1, FP32_EXP_SAFE_INT_MAX), FP32_0_x7(0) } }, … … 6140 6136 /*128:out */ 0, 6141 6137 /*256:out */ -1 }, 6142 { { /*src2 */ { FP32_NORM_ SAFE_INT_MIN(0), FP32_RAND_x7_V1 } },6143 { /*src1 */ { FP32_NORM_ SAFE_INT_MIN(0), FP32_RAND_x7_V3 } },6144 { /* => */ { FP32_0(0), 6138 { { /*src2 */ { FP32_NORM_MIN(0), FP32_RAND_x7_V1 } }, 6139 { /*src1 */ { FP32_NORM_MIN(0), FP32_RAND_x7_V3 } }, 6140 { /* => */ { FP32_0(0), FP32_RAND_x7_V3 } }, 6145 6141 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 6146 6142 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ, … … 6400 6396 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, 6401 6397 /*256:out */ -1 }, 6402 { { /*src2 */ { FP64_NORM_ SAFE_INT_MIN(0),FP64_NORM_MAX(0), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MAX(1) } },6398 { { /*src2 */ { FP64_NORM_MIN(0), FP64_NORM_MAX(0), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MAX(1) } }, 6403 6399 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_MAX(1), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MAX(1) } }, 6404 6400 { /* => */ { FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_NORM_MAX(1), FP64_0(0), FP64_0(0) } }, … … 6737 6733 /*128:out */ 0, 6738 6734 /*256:out */ 0 }, 6739 { { /*src2 */ { FP32_V(0, 0x6423f2, 0x92)/* 934463.125*/, FP32_V(0, 0x0a19f0, 0x8f)/* 70707.875*/, FP32_NORM_ SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1),FP32_1(1), FP32_1(0), FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/, FP32_V(0, 0x600000, 0x7e)/* 0.875*/ } },6735 { { /*src2 */ { FP32_V(0, 0x6423f2, 0x92)/* 934463.125*/, FP32_V(0, 0x0a19f0, 0x8f)/* 70707.875*/, FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_1(1), FP32_1(0), FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/, FP32_V(0, 0x600000, 0x7e)/* 0.875*/ } }, 6740 6736 { /*src1 */ { FP32_V(0, 0x769b5e, 0x92)/*1010101.875*/, FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_V(0, 0x10c030, 0x92)/*592899.000*/, FP32_V(0, 0x3ce348, 0x90)/*193421.125*/, FP32_V(1, 0x16b43a, 0x93)/*-1234567.25*/, FP32_V(0, 0x00c6d3, 0x94)/*2109876.75*/, FP32_V(0, 0x792318, 0x91)/*510232.750*/, FP32_V(0, 0x316740, 0x8e)/* 45415.250*/ } }, 6741 6737 { /* => */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_V(0, 0x430ebc, 0x91)/*399477.875*/, FP32_V(0, 0x52e0b4, 0x92)/*863755.250*/, FP32_0(0), FP32_V(1, 0x4c20f0, 0x94)/*-3344444.00*/, FP32_V(0, 0x62f630, 0x91)/* 464817.50*/, FP32_2(1), FP32_V(0, 0x769b50, 0x92)/*1010101.000*/ } }, … … 7023 7019 /*128:out */ 0, 7024 7020 /*256:out */ X86_MXCSR_PE }, 7025 { { /*src2 */ { FP64_NORM_ SAFE_INT_MIN(1),FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0) } },7026 { /*src1 */ { FP64_NORM_ SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MIN(0)} },7021 { { /*src2 */ { FP64_NORM_MIN(1), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0) } }, 7022 { /*src1 */ { FP64_NORM_MIN(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_MIN(0) } }, 7027 7023 { /* => */ { FP64_V(1, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_NORM_SAFE_INT_MAX(1), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_0(0) } }, 7028 7024 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 7029 7025 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, 7030 7026 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE }, 7031 { { /*src2 */ { FP64_NORM_ SAFE_INT_MIN(1),FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0) } },7032 { /*src1 */ { FP64_NORM_ SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MIN(0)} },7027 { { /*src2 */ { FP64_NORM_MIN(1), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0) } }, 7028 { /*src1 */ { FP64_NORM_MIN(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_MIN(0) } }, 7033 7029 { /* => */ { FP64_V(1, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MAX(0), FP64_0(0) } }, 7034 7030 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_DAZ | X86_MXCSR_RC_UP, … … 7386 7382 /*128:out */ 0, 7387 7383 /*256:out */ 0 }, 7388 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_NORM_SAFE_INT_MAX(1), FP32_1(1), FP32_NORM_SAFE_INT_MIN(1), FP32_1(1), FP32_NORM_SAFE_INT_MIN(0), FP32_0(1) } },7389 { /*src1 */ { FP32_1(0), FP32_NORM_ SAFE_INT_MIN(0), FP32_1(0), FP32_NORM_SAFE_INT_MAX(1), FP32_1(0), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0),FP32_NORM_SAFE_INT_MAX(0) } },7390 { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_ SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_0(0),FP32_0(1) } },7384 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_NORM_SAFE_INT_MAX(1), FP32_1(1), FP32_NORM_MIN(1), FP32_1(1), FP32_NORM_MIN(0), FP32_0(1) } }, 7385 { /*src1 */ { FP32_1(0), FP32_NORM_MIN(0), FP32_1(0), FP32_NORM_SAFE_INT_MAX(1), FP32_1(0), FP32_NORM_MIN(1), FP32_0(0), FP32_NORM_SAFE_INT_MAX(0) } }, 7386 { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MIN(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MIN(1), FP32_NORM_MIN(0), FP32_0(0), FP32_0(1) } }, 7391 7387 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 7392 7388 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, … … 7671 7667 /*128:out */ X86_MXCSR_RC_DOWN, 7672 7668 /*256:out */ X86_MXCSR_RC_DOWN }, 7673 { { /*src2 */ { FP64_1(0), FP64_1(0), FP64_NORM_ SAFE_INT_MIN(0), FP64_1(0)} },7674 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_1(0), FP64_NORM_SAFE_INT_MIN(1) } },7675 { /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_NORM_ SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(1) } },7669 { { /*src2 */ { FP64_1(0), FP64_1(0), FP64_NORM_MIN(0), FP64_1(0) } }, 7670 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_1(0), FP64_NORM_MIN(1) } }, 7671 { /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_NORM_MIN(0), FP64_NORM_MIN(1) } }, 7676 7672 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 7677 7673 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, … … 7768 7764 /*128:out */ X86_MXCSR_RC_ZERO, 7769 7765 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */ }, 7770 { { /*src2 */ { FP64_NORM_ SAFE_INT_MIN(0), FP64_NORM_MAX(0), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MIN(0)} },7766 { { /*src2 */ { FP64_NORM_MIN(0), FP64_NORM_MAX(0), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_MIN(0) } }, 7771 7767 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_MAX(1), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MAX(0) } }, 7772 7768 { /* => */ { FP64_V(0, FP64_FRAC_NORM_MAX, FP64_FRAC_BITS + 1), FP64_NORM_MAX(1), FP64_V(0, FP64_FRAC_NORM_MAX - 1, 0x468), FP64_V(0, FP64_FRAC_NORM_MAX, 0x035) } }, … … 7774 7770 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */, 7775 7771 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* IEM */ }, 7776 { { /*src2 */ { FP64_NORM_ SAFE_INT_MIN(0), FP64_NORM_MAX(0), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MIN(0)} },7772 { { /*src2 */ { FP64_NORM_MIN(0), FP64_NORM_MAX(0), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_MIN(0) } }, 7777 7773 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_MAX(1), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MAX(0) } }, 7778 7774 { /* => */ { FP64_V(0, FP64_FRAC_NORM_MAX, FP64_FRAC_BITS + 1), FP64_INF(1), FP64_V(0, FP64_FRAC_NORM_MAX - 1, 0x468), FP64_V(0, FP64_FRAC_NORM_MAX, 0x035) } }, … … 8212 8208 /*128:out */ X86_MXCSR_RC_DOWN, 8213 8209 /*256:out */ -1 }, 8214 { { /*src2 */ { FP64_1(0), FP64_0(0), FP64_NORM_ SAFE_INT_MIN(0), FP64_NORM_MAX(1)} },8215 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_INF(1), FP64_NORM_SAFE_INT_MIN(1) } },8216 { /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_INF(1), FP64_NORM_SAFE_INT_MIN(1) } },8210 { { /*src2 */ { FP64_1(0), FP64_0(0), FP64_NORM_MIN(0), FP64_NORM_MAX(1) } }, 8211 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_INF(1), FP64_NORM_MIN(1) } }, 8212 { /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_INF(1), FP64_NORM_MIN(1) } }, 8217 8213 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 8218 8214 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, … … 8547 8543 /*128:out */ 0, 8548 8544 /*256:out */ 0 }, 8549 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_NORM_SAFE_INT_MAX(1), FP32_1(1), FP32_NORM_SAFE_INT_MIN(1), FP32_1(1), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MAX(0) } },8550 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_ SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_0(0),FP32_0(1) } },8551 { /* => */ { FP32_1(0), FP32_NORM_ SAFE_INT_MIN(0), FP32_1(0), FP32_NORM_SAFE_INT_MAX(1), FP32_1(0), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0),FP32_0(1) } },8545 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_1(0), FP32_NORM_SAFE_INT_MAX(1), FP32_1(1), FP32_NORM_MIN(1), FP32_1(1), FP32_NORM_MIN(0), FP32_NORM_SAFE_INT_MAX(0) } }, 8546 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MIN(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MIN(1), FP32_NORM_MIN(0), FP32_0(0), FP32_0(1) } }, 8547 { /* => */ { FP32_1(0), FP32_NORM_MIN(0), FP32_1(0), FP32_NORM_SAFE_INT_MAX(1), FP32_1(0), FP32_NORM_MIN(1), FP32_0(0), FP32_0(1) } }, 8552 8548 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 8553 8549 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, … … 8826 8822 /*128:out */ X86_MXCSR_RC_DOWN, 8827 8823 /*256:out */ X86_MXCSR_RC_DOWN }, 8828 { { /*src2 */ { FP64_1(0), FP64_1(0), FP64_NORM_ SAFE_INT_MIN(0), FP64_1(0)} },8829 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_NORM_ SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(1) } },8830 { /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_1(0), FP64_NORM_SAFE_INT_MIN(1) } },8824 { { /*src2 */ { FP64_1(0), FP64_1(0), FP64_NORM_MIN(0), FP64_1(0) } }, 8825 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_NORM_MIN(0), FP64_NORM_MIN(1) } }, 8826 { /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_1(0), FP64_NORM_MIN(1) } }, 8831 8827 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 8832 8828 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, … … 8981 8977 /*128:out */ X86_MXCSR_RC_ZERO, 8982 8978 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY /* i7-10700, IEM */ }, 8983 { { /*src2 */ { FP64_NORM_ SAFE_INT_MIN(0), FP64_NORM_MAX(0), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MIN(0)} },8979 { { /*src2 */ { FP64_NORM_MIN(0), FP64_NORM_MAX(0), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_MIN(0) } }, 8984 8980 { /*src1 */ { FP64_V(0, FP64_FRAC_NORM_MAX, FP64_FRAC_BITS + 1), FP64_NORM_MAX(1), FP64_V(0, FP64_FRAC_NORM_MAX - 1, 0x468), FP64_V(0, FP64_FRAC_NORM_MAX, 0x035) } }, 8985 8981 { /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_1(1), FP64_V(1, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_NORM_SAFE_INT_MAX(0) } }, … … 8987 8983 /*128:out */ X86_MXCSR_RC_ZERO, 8988 8984 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE }, 8989 { { /*src2 */ { FP64_NORM_ SAFE_INT_MIN(0),FP64_NORM_MAX(0), FP64_V(0, 0x8000000000000, 0x400)/*3.0*/, FP64_1(1) } },8985 { { /*src2 */ { FP64_NORM_MIN(0), FP64_NORM_MAX(0), FP64_V(0, 0x8000000000000, 0x400)/*3.0*/, FP64_1(1) } }, 8990 8986 { /*src1 */ { FP64_V(0, FP64_FRAC_NORM_MAX, FP64_FRAC_BITS + 1), FP64_INF(1), FP64_1(1), FP64_1(0) } }, 8991 8987 { /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_INF(1), FP64_V(1, 0x5555555555556, 0x3fd)/*1/3*/, FP64_1(1) } }, … … 9425 9421 /*128:out */ X86_MXCSR_RC_DOWN, 9426 9422 /*256:out */ -1 }, 9427 { { /*src2 */ { FP64_1(0), FP64_0(0), FP64_NORM_ SAFE_INT_MIN(0), FP64_NORM_MAX(1)} },9428 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_INF(1), FP64_NORM_SAFE_INT_MIN(1) } },9429 { /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_INF(1), FP64_NORM_SAFE_INT_MIN(1) } },9423 { { /*src2 */ { FP64_1(0), FP64_0(0), FP64_NORM_MIN(0), FP64_NORM_MAX(1) } }, 9424 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_INF(1), FP64_NORM_MIN(1) } }, 9425 { /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_INF(1), FP64_NORM_MIN(1) } }, 9430 9426 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 9431 9427 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, … … 9829 9825 /*128:out */ X86_MXCSR_OM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_OM_FIXED, 9830 9826 /*256:out */ X86_MXCSR_OM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_OM_FIXED }, 9831 { { /*src2 */ { FP32_NORM_ SAFE_INT_MIN(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MIN(0),FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1) } },9827 { { /*src2 */ { FP32_NORM_MIN(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_MIN(0), FP32_NORM_MAX(0), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1) } }, 9832 9828 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1) } }, 9833 9829 { /* => */ { FP32_V(0, FP32_FRAC_NORM_MAX, FP32_EXP_SAFE_INT_MAX), FP32_0(0), FP32_0(0), FP32_V(1, FP32_FRAC_NORM_MAX, FP32_EXP_SAFE_INT_MAX + 1), FP32_V(0, FP32_FRAC_NORM_MAX, FP32_EXP_SAFE_INT_MAX), FP32_0(0), FP32_0(0), FP32_V(1, FP32_FRAC_NORM_MAX, FP32_EXP_SAFE_INT_MAX + 1) } }, … … 9862 9858 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, 9863 9859 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP }, 9864 { { /*src2 */ { FP32_NORM_ SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0), FP32_0(0), FP32_0(0), FP32_NORM_SAFE_INT_MIN(0), FP32_1(0), FP32_NORM_SAFE_INT_MIN(0)} },9865 { /*src1 */ { FP32_NORM_ SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_V(0, 0, FP32_EXP_SAFE_INT_MIN + 1), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MIN(0)} },9866 { /* => */ { FP32_0(1), FP32_0(1), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_V(1, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_V(0, 0, FP32_EXP_SAFE_INT_MIN + 1) } },9860 { { /*src2 */ { FP32_NORM_MIN(0), FP32_NORM_MIN(0), FP32_NORM_MIN(0), FP32_0(0), FP32_0(0), FP32_NORM_MIN(0), FP32_1(0), FP32_NORM_MIN(0) } }, 9861 { /*src1 */ { FP32_NORM_MIN(0), FP32_NORM_MIN(1), FP32_V(0, 0, FP32_EXP_SAFE_INT_MIN + 1), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_0(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_MIN(0) } }, 9862 { /* => */ { FP32_0(1), FP32_0(1), FP32_NORM_MIN(0), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_MIN(0), FP32_V(1, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_V(0, 0, FP32_EXP_SAFE_INT_MIN + 1) } }, 9867 9863 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 9868 9864 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, … … 10213 10209 /*128:out */ X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY, 10214 10210 /*256:out */ X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_PE_FUZZY }, 10215 { { /*src2 */ { FP64_NORM_ SAFE_INT_MIN(0),FP64_NORM_MAX(0), FP64_0(0), FP64_NORM_SAFE_INT_MAX(1) } },10211 { { /*src2 */ { FP64_NORM_MIN(0), FP64_NORM_MAX(0), FP64_0(0), FP64_NORM_SAFE_INT_MAX(1) } }, 10216 10212 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_MAX(1), FP64_0(0), FP64_NORM_SAFE_INT_MAX(1) } }, 10217 10213 { /* => */ { FP64_V(0, FP64_FRAC_NORM_MAX, FP64_EXP_SAFE_INT_MAX), FP64_0(0), FP64_0(0), FP64_V(1, FP64_FRAC_NORM_MAX, FP64_EXP_SAFE_INT_MAX + 1) } }, … … 10252 10248 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 10253 10249 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO }, 10254 { { /*src2 */ { FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_ SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(0) } },10255 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_ SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(0), FP64_0(0)} },10256 { /* => */ { FP64_0(0), FP64_V(0, 0, FP64_EXP_SAFE_INT_MIN + 1), FP64_V(0, 0, FP64_EXP_SAFE_INT_MIN + 1), FP64_NORM_ SAFE_INT_MIN(0) } },10250 { { /*src2 */ { FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_MIN(0), FP64_NORM_MIN(1), FP64_NORM_MIN(0) } }, 10251 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_MIN(0), FP64_NORM_MIN(0), FP64_0(0) } }, 10252 { /* => */ { FP64_0(0), FP64_V(0, 0, FP64_EXP_SAFE_INT_MIN + 1), FP64_V(0, 0, FP64_EXP_SAFE_INT_MIN + 1), FP64_NORM_MIN(0) } }, 10257 10253 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 10258 10254 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, 10259 10255 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP }, 10260 { { /*src2 */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_NORM_ SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(0),FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/ } },10261 { /*src1 */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_NORM_ SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(1),FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/ } },10256 { { /*src2 */ { FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/, FP64_NORM_MIN(1), FP64_NORM_MIN(0), FP64_V(0, 0xc122186c3cfd0, 0x42d)/*123456789876543.25*/ } }, 10257 { /*src1 */ { FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/, FP64_NORM_MIN(1), FP64_NORM_MIN(1), FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/ } }, 10262 10258 { /* => */ { FP64_V(0, 0xb88e0395d49b0, 0x42d)/*121098765432102.75*/, FP64_V(1, 0, FP64_EXP_SAFE_INT_MIN + 1), FP64_V(1, 0, FP64_EXP_SAFE_INT_MIN + 1), FP64_V(0, 0xbcd80e0108cc0, 0x42e)/*244555555308646.00*/ } }, 10263 10259 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, … … 10619 10615 /*128:out */ 0, 10620 10616 /*256:out */ 0 }, 10621 { { /*src2 */ { FP32_NORM_ SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1),FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(1) } },10622 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_ SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1)} },10623 { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_ SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1)} },10617 { { /*src2 */ { FP32_NORM_MIN(0), FP32_NORM_MIN(0), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(1) } }, 10618 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_MIN(0), FP32_NORM_MIN(1), FP32_NORM_MIN(0), FP32_NORM_MIN(1) } }, 10619 { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MIN(0), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MIN(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MIN(0), FP32_NORM_MIN(1) } }, 10624 10620 /*mxcsr:in */ 0, 10625 10621 /*128:out */ 0, … … 10643 10639 /*128:out */ X86_MXCSR_RC_ZERO, 10644 10640 /*256:out */ X86_MXCSR_RC_ZERO }, 10645 { { /*src2 */ { FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_V(0, 0x3ce348, 0x90)/*193421.125*/, FP32_V(0, 0x6423f2, 0x92)/*934463.125*/, FP32_NORM_ SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0),FP32_V(0, 0x16b43a, 0x93)/*1234567.25*/, FP32_V(0, 0x792318, 0x91)/*510232.75*/, FP32_V(0, 0x600000, 0x7e)/* 0.875*/ } },10646 { /*src1 */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_V(0, 0x430ebc, 0x91)/*399477.875*/, FP32_V(0, 0x52e0b4, 0x92)/*863755.250*/, FP32_NORM_ SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MAX(1), FP32_V(0, 0x00c6d3, 0x94)/*2109876.75*/, FP32_V(1, 0x316740, 0x8e)/*-45415.25*/, FP32_V(1, 0, 0x7d)/*-0.250*/ } },10647 { /* => */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_V(0, 0x430ebc, 0x91)/*399477.875*/, FP32_V(0, 0x6423f2, 0x92)/*934463.125*/, FP32_NORM_ SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0),FP32_V(0, 0x00c6d3, 0x94)/*2109876.75*/, FP32_V(0, 0x792318, 0x91)/*510232.75*/, FP32_V(0, 0x600000, 0x7e)/* 0.875*/ } },10641 { { /*src2 */ { FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_V(0, 0x3ce348, 0x90)/*193421.125*/, FP32_V(0, 0x6423f2, 0x92)/*934463.125*/, FP32_NORM_MIN(1), FP32_NORM_MIN(0), FP32_V(0, 0x16b43a, 0x93)/*1234567.25*/, FP32_V(0, 0x792318, 0x91)/*510232.75*/, FP32_V(0, 0x600000, 0x7e)/* 0.875*/ } }, 10642 { /*src1 */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_V(0, 0x430ebc, 0x91)/*399477.875*/, FP32_V(0, 0x52e0b4, 0x92)/*863755.250*/, FP32_NORM_MIN(1), FP32_NORM_SAFE_INT_MAX(1), FP32_V(0, 0x00c6d3, 0x94)/*2109876.75*/, FP32_V(1, 0x316740, 0x8e)/*-45415.25*/, FP32_V(1, 0, 0x7d)/*-0.250*/ } }, 10643 { /* => */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_V(0, 0x430ebc, 0x91)/*399477.875*/, FP32_V(0, 0x6423f2, 0x92)/*934463.125*/, FP32_NORM_MIN(1), FP32_NORM_MIN(0), FP32_V(0, 0x00c6d3, 0x94)/*2109876.75*/, FP32_V(0, 0x792318, 0x91)/*510232.75*/, FP32_V(0, 0x600000, 0x7e)/* 0.875*/ } }, 10648 10644 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 10649 10645 /*128:out */ X86_MXCSR_RC_DOWN, … … 10914 10910 /*128:out */ X86_MXCSR_RC_ZERO, 10915 10911 /*256:out */ X86_MXCSR_RC_ZERO }, 10916 { { /*src2 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_ SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MIN(0) } },10917 { /*src1 */ { FP64_1(0), FP64_NORM_ SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(0), FP64_0(0)} },10918 { /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_ SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MIN(0) } },10912 { { /*src2 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_MIN(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_MIN(0) } }, 10913 { /*src1 */ { FP64_1(0), FP64_NORM_MIN(1), FP64_NORM_MIN(0), FP64_0(0) } }, 10914 { /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_MIN(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_MIN(0) } }, 10919 10915 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 10920 10916 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 10921 10917 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO }, 10922 { { /*src2 */ { FP64_NORM_ SAFE_INT_MIN(0), FP64_0(0), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(1) } },10923 { /*src1 */ { FP64_NORM_ SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(1), FP64_0(0), FP64_NORM_SAFE_INT_MIN(0) } },10924 { /* => */ { FP64_NORM_ SAFE_INT_MIN(0), FP64_0(0), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(0) } },10918 { { /*src2 */ { FP64_NORM_MIN(0), FP64_0(0), FP64_NORM_MIN(0), FP64_NORM_MIN(1) } }, 10919 { /*src1 */ { FP64_NORM_MIN(1), FP64_NORM_MIN(1), FP64_0(0), FP64_NORM_MIN(0) } }, 10920 { /* => */ { FP64_NORM_MIN(0), FP64_0(0), FP64_NORM_MIN(0), FP64_NORM_MIN(0) } }, 10925 10921 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 10926 10922 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, … … 11235 11231 /*128:out */ 0, 11236 11232 /*256:out */ -1 }, 11237 { { /*src2 */ { FP32_NORM_ SAFE_INT_MIN(0),FP32_RAND_x7_V2 } },11233 { { /*src2 */ { FP32_NORM_MIN(0), FP32_RAND_x7_V2 } }, 11238 11234 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V1 } }, 11239 11235 { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V1 } }, … … 11248 11244 /*256:out */ -1 }, 11249 11245 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V0 } }, 11250 { /*src1 */ { FP32_NORM_ SAFE_INT_MIN(0),FP32_RAND_x7_V1 } },11246 { /*src1 */ { FP32_NORM_MIN(0), FP32_RAND_x7_V1 } }, 11251 11247 { /* => */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V1 } }, 11252 11248 /*mxcsr:in */ 0, … … 11634 11630 /*128:out */ 0, 11635 11631 /*256:out */ -1 }, 11636 { { /*src2 */ { FP64_NORM_ SAFE_INT_MIN(0),FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V3(0) } },11632 { { /*src2 */ { FP64_NORM_MIN(0), FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V3(0) } }, 11637 11633 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_RAND_V1(0), FP64_RAND_V1(0), FP64_RAND_V3(1) } }, 11638 11634 { /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_RAND_V1(0), FP64_RAND_V1(0), FP64_RAND_V3(1) } }, … … 11647 11643 /*256:out */ -1 }, 11648 11644 { { /*src2 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_INF(0), FP64_QNAN(1), FP64_QNAN(0) } }, 11649 { /*src1 */ { FP64_NORM_ SAFE_INT_MIN(0),FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } },11645 { /*src1 */ { FP64_NORM_MIN(0), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } }, 11650 11646 { /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } }, 11651 11647 /*mxcsr:in */ 0, … … 11987 11983 /*128:out */ 0, 11988 11984 /*256:out */ 0 }, 11989 { { /*src2 */ { FP32_NORM_ SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(1),FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(1) } },11990 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_ SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1)} },11991 { /* => */ { FP32_NORM_ SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MIN(0), FP32_NORM_SAFE_INT_MIN(1),FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(1) } },11985 { { /*src2 */ { FP32_NORM_MIN(0), FP32_NORM_MIN(0), FP32_NORM_MIN(1), FP32_NORM_MIN(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(1) } }, 11986 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_MIN(0), FP32_NORM_MIN(1), FP32_NORM_MIN(0), FP32_NORM_MIN(1) } }, 11987 { /* => */ { FP32_NORM_MIN(0), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_MIN(1), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_MIN(0), FP32_NORM_MIN(1), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(1) } }, 11992 11988 /*mxcsr:in */ 0, 11993 11989 /*128:out */ 0, … … 12011 12007 /*128:out */ X86_MXCSR_RC_ZERO, 12012 12008 /*256:out */ X86_MXCSR_RC_ZERO }, 12013 { { /*src2 */ { FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_V(0, 0x3ce348, 0x90)/*193421.125*/, FP32_V(0, 0x6423f2, 0x92)/*934463.125*/, FP32_NORM_ SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MIN(0),FP32_V(0, 0x16b43a, 0x93)/*1234567.25*/, FP32_V(0, 0x792318, 0x91)/*510232.75*/, FP32_V(0, 0x600000, 0x7e)/* 0.875*/ } },12014 { /*src1 */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_V(0, 0x430ebc, 0x91)/*399477.875*/, FP32_V(0, 0x52e0b4, 0x92)/*863755.250*/, FP32_NORM_ SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MAX(1), FP32_V(0, 0x00c6d3, 0x94)/*2109876.75*/, FP32_V(1, 0x316740, 0x8e)/*-45415.25*/, FP32_V(1, 0, 0x7d)/*-0.250*/ } },12015 { /* => */ { FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_V(0, 0x3ce348, 0x90)/*193421.125*/, FP32_V(0, 0x52e0b4, 0x92)/*863755.250*/, FP32_NORM_ SAFE_INT_MIN(1), FP32_NORM_SAFE_INT_MAX(1), FP32_V(0, 0x16b43a, 0x93)/*1234567.25*/, FP32_V(1, 0x316740, 0x8e)/*-45415.25*/, FP32_V(1, 0, 0x7d)/*-0.250*/ } },12009 { { /*src2 */ { FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_V(0, 0x3ce348, 0x90)/*193421.125*/, FP32_V(0, 0x6423f2, 0x92)/*934463.125*/, FP32_NORM_MIN(1), FP32_NORM_MIN(0), FP32_V(0, 0x16b43a, 0x93)/*1234567.25*/, FP32_V(0, 0x792318, 0x91)/*510232.75*/, FP32_V(0, 0x600000, 0x7e)/* 0.875*/ } }, 12010 { /*src1 */ { FP32_V(0, 0x769b50, 0x92)/*1010101.000*/, FP32_V(0, 0x430ebc, 0x91)/*399477.875*/, FP32_V(0, 0x52e0b4, 0x92)/*863755.250*/, FP32_NORM_MIN(1), FP32_NORM_SAFE_INT_MAX(1), FP32_V(0, 0x00c6d3, 0x94)/*2109876.75*/, FP32_V(1, 0x316740, 0x8e)/*-45415.25*/, FP32_V(1, 0, 0x7d)/*-0.250*/ } }, 12011 { /* => */ { FP32_V(0, 0x600000, 0x7e)/* 0.875*/, FP32_V(0, 0x3ce348, 0x90)/*193421.125*/, FP32_V(0, 0x52e0b4, 0x92)/*863755.250*/, FP32_NORM_MIN(1), FP32_NORM_SAFE_INT_MAX(1), FP32_V(0, 0x16b43a, 0x93)/*1234567.25*/, FP32_V(1, 0x316740, 0x8e)/*-45415.25*/, FP32_V(1, 0, 0x7d)/*-0.250*/ } }, 12016 12012 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 12017 12013 /*128:out */ X86_MXCSR_RC_DOWN, … … 12282 12278 /*128:out */ X86_MXCSR_RC_ZERO, 12283 12279 /*256:out */ X86_MXCSR_RC_ZERO }, 12284 { { /*src2 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_ SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MIN(0) } },12285 { /*src1 */ { FP64_1(0), FP64_NORM_ SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(0), FP64_0(0)} },12286 { /* => */ { FP64_1(0), FP64_NORM_ SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(0), FP64_0(0)} },12280 { { /*src2 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_MIN(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_MIN(0) } }, 12281 { /*src1 */ { FP64_1(0), FP64_NORM_MIN(1), FP64_NORM_MIN(0), FP64_0(0) } }, 12282 { /* => */ { FP64_1(0), FP64_NORM_MIN(1), FP64_NORM_MIN(0), FP64_0(0) } }, 12287 12283 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 12288 12284 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, 12289 12285 /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO }, 12290 { { /*src2 */ { FP64_NORM_ SAFE_INT_MIN(0), FP64_0(0), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MIN(1) } },12291 { /*src1 */ { FP64_NORM_ SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(1), FP64_0(0), FP64_NORM_SAFE_INT_MIN(0) } },12292 { /* => */ { FP64_NORM_ SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MIN(1), FP64_0(0), FP64_NORM_SAFE_INT_MIN(1) } },12286 { { /*src2 */ { FP64_NORM_MIN(0), FP64_0(0), FP64_NORM_MIN(0), FP64_NORM_MIN(1) } }, 12287 { /*src1 */ { FP64_NORM_MIN(1), FP64_NORM_MIN(1), FP64_0(0), FP64_NORM_MIN(0) } }, 12288 { /* => */ { FP64_NORM_MIN(1), FP64_NORM_MIN(1), FP64_0(0), FP64_NORM_MIN(1) } }, 12293 12289 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, 12294 12290 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, … … 12603 12599 /*128:out */ 0, 12604 12600 /*256:out */ -1 }, 12605 { { /*src2 */ { FP32_NORM_ SAFE_INT_MIN(0),FP32_RAND_x7_V2 } },12601 { { /*src2 */ { FP32_NORM_MIN(0), FP32_RAND_x7_V2 } }, 12606 12602 { /*src1 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V5 } }, 12607 { /* => */ { FP32_NORM_ SAFE_INT_MIN(0),FP32_RAND_x7_V5 } },12603 { /* => */ { FP32_NORM_MIN(0), FP32_RAND_x7_V5 } }, 12608 12604 /*mxcsr:in */ 0, 12609 12605 /*128:out */ 0, … … 12616 12612 /*256:out */ -1 }, 12617 12613 { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_RAND_x7_V6 } }, 12618 { /*src1 */ { FP32_NORM_ SAFE_INT_MIN(0),FP32_RAND_x7_V3 } },12619 { /* => */ { FP32_NORM_ SAFE_INT_MIN(0),FP32_RAND_x7_V3 } },12614 { /*src1 */ { FP32_NORM_MIN(0), FP32_RAND_x7_V3 } }, 12615 { /* => */ { FP32_NORM_MIN(0), FP32_RAND_x7_V3 } }, 12620 12616 /*mxcsr:in */ 0, 12621 12617 /*128:out */ 0, … … 13003 12999 /*128:out */ 0, 13004 13000 /*256:out */ -1 }, 13005 { { /*src2 */ { FP64_NORM_ SAFE_INT_MIN(0),FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V3(0) } },13001 { { /*src2 */ { FP64_NORM_MIN(0), FP64_RAND_V2(1), FP64_RAND_V2(1), FP64_RAND_V3(0) } }, 13006 13002 { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_RAND_V1(0), FP64_RAND_V1(0), FP64_RAND_V3(1) } }, 13007 { /* => */ { FP64_NORM_ SAFE_INT_MIN(0),FP64_RAND_V1(0), FP64_RAND_V1(0), FP64_RAND_V3(1) } },13003 { /* => */ { FP64_NORM_MIN(0), FP64_RAND_V1(0), FP64_RAND_V1(0), FP64_RAND_V3(1) } }, 13008 13004 /*mxcsr:in */ 0, 13009 13005 /*128:out */ 0, … … 13016 13012 /*256:out */ -1 }, 13017 13013 { { /*src2 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_INF(0), FP64_QNAN(1), FP64_QNAN(0) } }, 13018 { /*src1 */ { FP64_NORM_ SAFE_INT_MIN(0),FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } },13019 { /* => */ { FP64_NORM_ SAFE_INT_MIN(0),FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } },13014 { /*src1 */ { FP64_NORM_MIN(0), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } }, 13015 { /* => */ { FP64_NORM_MIN(0), FP64_RAND_V1(0), FP64_RAND_V2(1), FP64_RAND_V0(1) } }, 13020 13016 /*mxcsr:in */ 0, 13021 13017 /*128:out */ 0, … … 14582 14578 FP32_NORM_MIN(0), 14583 14579 FP32_NORM_SAFE_INT_MAX(0), 14584 FP32_NORM_ SAFE_INT_MIN(0),14580 FP32_NORM_MIN(0), 14585 14581 FP32_NORM_MAX(1), 14586 14582 FP32_NORM_MIN(1), 14587 14583 FP32_NORM_SAFE_INT_MAX(1), 14588 FP32_NORM_ SAFE_INT_MIN(1) } },14584 FP32_NORM_MIN(1) } }, 14589 14585 { /*unused */ { FP32_ROW_UNUSED } }, 14590 14586 { /* => */ { FP32_V(0,0x7fffff,0xbe)/*sqrt(FP32_NORM_MAX)*/, 14591 14587 FP32_V(0,0x0,0x40)/*sqrt(FP32_NORM_MIN)*/, 14592 14588 FP32_V(0,0x7fffff,0x8a)/*sqrt(FP32_NORM_SAFE_INT_MAX)*/, 14593 FP32_V(0,0x0,0x40)/*sqrt(FP32_NORM_ SAFE_INT_MIN)*/,14589 FP32_V(0,0x0,0x40)/*sqrt(FP32_NORM_MIN)*/, 14594 14590 FP32_QNAN(1), 14595 14591 FP32_QNAN(1), … … 15096 15092 /*256:out */ -1 }, 15097 15093 { { /*src1 */ { FP32_NORM_V3(0), FP32_0_x7(0) } }, 15098 { /*src2 */ { FP32_NORM_ SAFE_INT_MIN(0),FP32_RAND_x7_V1 } },15094 { /*src2 */ { FP32_NORM_MIN(0), FP32_RAND_x7_V1 } }, 15099 15095 { /* => */ { FP32_V(0,0x27905f,0xbe)/*sqrt(FP32_NORM_V3)*/, FP32_RAND_x7_V1 } }, 15100 15096 /*mxcsr:in */ X86_MXCSR_DAZ, … … 15119 15115 /*128:out */ X86_MXCSR_PE, 15120 15116 /*256:out */ -1 }, 15121 { { /*src1 */ { FP32_NORM_ SAFE_INT_MIN(0), FP32_RAND_x7_V5 } },15122 { /*src2 */ { FP32_RAND_V0(0), 15123 { /* => */ { FP32_V(0,0x0,0x40)/*sqrt(FP32_NORM_ SAFE_INT_MIN)*/, FP32_RAND_x7_V7 } },15117 { { /*src1 */ { FP32_NORM_MIN(0), FP32_RAND_x7_V5 } }, 15118 { /*src2 */ { FP32_RAND_V0(0), FP32_RAND_x7_V7 } }, 15119 { /* => */ { FP32_V(0,0x0,0x40)/*sqrt(FP32_NORM_MIN)*/, FP32_RAND_x7_V7 } }, 15124 15120 /*mxcsr:in */ 0, 15125 15121 /*128:out */ 0, … … 15526 15522 /*256:out */ -1 }, 15527 15523 { { /*src1 */ { FP64_NORM_V3(0), FP64_0_x3(0) } }, 15528 { /*src2 */ { FP64_NORM_ SAFE_INT_MIN(0),FP64_RAND_x3_V1 } },15524 { /*src2 */ { FP64_NORM_MIN(0), FP64_RAND_x3_V1 } }, 15529 15525 { /* => */ { FP64_V(0,0x4ebe86dd38102,0x440)/*sqrt(FP64_NORM_V3)*/, FP64_RAND_x3_V1 } }, 15530 15526 /*mxcsr:in */ X86_MXCSR_DAZ, … … 15549 15545 /*128:out */ X86_MXCSR_PE, 15550 15546 /*256:out */ -1 }, 15551 { { /*src1 */ { FP64_NORM_ SAFE_INT_MIN(0), FP64_RAND_x3_V1 } },15552 { /*src2 */ { FP64_RAND_V0(0), 15553 { /* => */ { FP64_V(0,0x0,0x200)/*sqrt(FP64_NORM_ SAFE_INT_MIN)*/, FP64_RAND_x3_V3 } },15547 { { /*src1 */ { FP64_NORM_MIN(0), FP64_RAND_x3_V1 } }, 15548 { /*src2 */ { FP64_RAND_V0(0), FP64_RAND_x3_V3 } }, 15549 { /* => */ { FP64_V(0,0x0,0x200)/*sqrt(FP64_NORM_MIN)*/, FP64_RAND_x3_V3 } }, 15554 15550 /*mxcsr:in */ 0, 15555 15551 /*128:out */ 0, … … 15881 15877 #define FP32_RSQRT_NORM_MIN FP32_V(0, 0x7ff000, 0xbd) /* 1/sqrt(NORM_MIN) */ 15882 15878 #define FP32_RSQRT_NS_INT_MAX FP32_V(0, 0x000800, 0x73) /* 1/sqrt(NORM_SAFE_INT_MAX) */ 15883 #define FP32_RSQRT_NS_INT_MIN FP32_V(0, 0x7ff000, 0xbd) /* 1/sqrt(NORM_SAFE_INT_MIN) */15884 15879 /* 15885 15880 * Zero. … … 15984 15979 /*128:out */ X86_MXCSR_RC_ZERO, 15985 15980 /*256:out */ X86_MXCSR_RC_ZERO }, 15986 { { /*src1 */ { FP32_NORM_MAX(0), FP32_NORM_MIN(0), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_ SAFE_INT_MIN(0), FP32_NORM_MAX(1), FP32_NORM_MIN(1), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MIN(1) } },15981 { { /*src1 */ { FP32_NORM_MAX(0), FP32_NORM_MIN(0), FP32_NORM_SAFE_INT_MAX(0), FP32_NORM_MIN(0), FP32_NORM_MAX(1), FP32_NORM_MIN(1), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_MIN(1) } }, 15987 15982 { /*unused */ { FP32_ROW_UNUSED } }, 15988 { /* => */ { FP32_RSQRT_NORM_MAX, FP32_RSQRT_NORM_MIN, FP32_RSQRT_NS_INT_MAX, FP32_RSQRT_N S_INT_MIN, FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1)} },15983 { /* => */ { FP32_RSQRT_NORM_MAX, FP32_RSQRT_NORM_MIN, FP32_RSQRT_NS_INT_MAX, FP32_RSQRT_NORM_MIN, FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1), FP32_QNAN(1) } }, 15989 15984 /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ, 15990 15985 /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ, … … 16213 16208 /*128:out */ X86_MXCSR_FZ, 16214 16209 /*256:out */ -1 }, 16215 { { /*src1 */ { FP32_NORM_V3(0), 16216 { /*src2 */ { FP32_NORM_ SAFE_INT_MIN(0),FP32_RAND_x7_V1 } },16217 { /* => */ { FP32_RSQRT_NORM_V3, 16210 { { /*src1 */ { FP32_NORM_V3(0), FP32_0_x7(0) } }, 16211 { /*src2 */ { FP32_NORM_MIN(0), FP32_RAND_x7_V1 } }, 16212 { /* => */ { FP32_RSQRT_NORM_V3, FP32_RAND_x7_V1 } }, 16218 16213 /*mxcsr:in */ X86_MXCSR_DAZ, 16219 16214 /*128:out */ X86_MXCSR_DAZ, … … 16237 16232 /*128:out */ 0, 16238 16233 /*256:out */ -1 }, 16239 { { /*src1 */ { FP32_NORM_ SAFE_INT_MIN(0),FP32_RAND_x7_V5 } },16240 { /*src2 */ { FP32_RAND_V0(0), 16241 { /* => */ { FP32_RSQRT_N S_INT_MIN,FP32_RAND_x7_V7 } },16234 { { /*src1 */ { FP32_NORM_MIN(0), FP32_RAND_x7_V5 } }, 16235 { /*src2 */ { FP32_RAND_V0(0), FP32_RAND_x7_V7 } }, 16236 { /* => */ { FP32_RSQRT_NORM_MIN, FP32_RAND_x7_V7 } }, 16242 16237 /*mxcsr:in */ 0, 16243 16238 /*128:out */ 0, -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-x-regs.c32
r106733 r106736 381 381 #define BS3_REGISTER_FLAG_MEMREF 0x100 382 382 #define BS3_FSxREG(reg) (((reg) == FSxBX || (reg) == FSxDI) ? reg : ((reg) & BS3_REGISTER_REGISTER_MASK) | BS3_REGISTER_FLAG_MEMREF) 383 #define BS3_REGISTER_IS_MEMREF(reg) (((reg) & BS3_REGISTER_FLAG_MEMREF) || (((reg) & BS3_REGISTER_FAMILY_MEMREF) == BS3_REGISTER_FAMILY_MEMREF)) 384 #define BS3_REGISTER_MEMREF_TO(reg) (((reg) == FSxBX ? BX : (reg) == FSxDI ? DI : (reg)) & BS3_REGISTER_REGISTER_MASK) 383 385 384 386 #define BS3_REGISTER_NAME_MAXSIZE sizeof("FSx(avail)") … … 482 484 char pszRegName[BS3_REGISTER_NAME_MAXSIZE]; 483 485 484 if ( uReg & BS3_REGISTER_FLAG_MEMREF || uReg == FSxBX || uReg == FSxDI)486 if (BS3_REGISTER_IS_MEMREF(uReg)) 485 487 { 486 if (uRegSet <= BS3_REGISTER_FAMILY_64BIT) 487 uRegNum &= BS3_REGISTER_REGISTER_MASK; 488 else if (uReg == FSxBX) 489 uRegNum = BX; 490 else if (uReg == FSxDI) 491 uRegNum = DI; 488 if (uReg == FSxBX || uReg == FSxDI || uRegSet <= BS3_REGISTER_FAMILY_64BIT) 489 uRegNum = BS3_REGISTER_MEMREF_TO(uReg); 492 490 else 493 491 uRegNum = 255; /* Fall through to error handling below to complain about 'FSxZMM31' or whatever */
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