Changeset 106744 in vbox for trunk/src/VBox/Disassembler

Timestamp:

Oct 28, 2024 12:06:08 PM (6 months ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

165628

Message:

Disassembler: Calculate final displacement in the core already, some preparations for SIMD loads/stores, bugref:10394

Location:

trunk/src/VBox/Disassembler

Files:

• DisasmCore-armv8.cpp (modified) (1 diff)
• DisasmFormatArmV8.cpp (modified) (7 diffs)

trunk/src/VBox/Disassembler/DisasmCore-armv8.cpp

@@ -264 +264 @@
 
     pParam->armv8.enmType = kDisArmv8OpParmImmRel;
-    pParam->uValue = (int64_t)disArmV8ExtractBitVecFromInsnSignExtend(u32Insn, pInsnParm->idxBitStart, pInsnParm->cBits);
+    pParam->uValue = (int64_t)disArmV8ExtractBitVecFromInsnSignExtend(u32Insn, pInsnParm->idxBitStart, pInsnParm->cBits) * sizeof(uint32_t);
     if (pInsnParm->cBits <= 8)
     {

trunk/src/VBox/Disassembler/DisasmFormatArmV8.cpp

@@ -69 +69 @@
     "h0\0",  "h1\0",  "h2\0",  "h3\0",  "h4\0",  "h5\0",  "h6\0",  "h7\0",  "h8\0",  "h9\0",  "h10",  "h11",  "h12",  "h13",  "h14",  "h15",
     "h16",   "h17",   "h18",   "h19",   "h20",   "h21",   "h22",   "h23",   "h24",   "h25",   "h26",  "h27",  "h28",  "h29",  "h30",  "h31"
+};
+static const char g_aszArmV8RegSimdScalar8Bit[32][4] =
+{
+    "b0\0",  "b1\0",  "b2\0",  "b3\0",  "b4\0",  "b5\0",  "b6\0",  "b7\0",  "b8\0",  "b9\0",  "b10",  "b11",  "b12",  "b13",  "b14",  "b15",
+    "b16",   "b17",   "b18",   "b19",   "b20",   "b21",   "b22",   "b23",   "b24",   "b25",   "b26",  "b27",  "b28",  "b29",  "b30",  "b31"
 };
 static const char g_aszArmV8RegSimdScalar128Bit[32][4] =
@@ -362 +367 @@
             return psz;
         }
+        case kDisOpParamArmV8RegType_Simd_Scalar_32Bit:
         case kDisOpParamArmV8RegType_FpReg_Single:
         {
@@ -378 +384 @@
             return psz;
         }
+        case kDisOpParamArmV8RegType_Simd_Scalar_16Bit:
         case kDisOpParamArmV8RegType_FpReg_Half:
         {
@@ -383 +390 @@
             Assert(pReg->idReg < RT_ELEMENTS(g_aszArmV8RegFpHalf));
             const char *psz = g_aszArmV8RegFpHalf[pReg->idReg];
+            *pcchReg = 2 + !!psz[2];
+            return psz;
+        }
+        case kDisOpParamArmV8RegType_Simd_Scalar_8Bit:
+        {
+            Assert(pReg->idReg < RT_ELEMENTS(g_aszArmV8RegSimdScalar8Bit));
+            const char *psz = g_aszArmV8RegSimdScalar8Bit[pReg->idReg];
             *pcchReg = 2 + !!psz[2];
             return psz;
@@ -734 +748 @@
                         offDisplacement = (int8_t)pParam->uValue;
                         if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
-                            PUT_NUM_S8(offDisplacement * sizeof(uint32_t));
+                            PUT_NUM_S8(offDisplacement);
                     }
                     else if (pParam->fUse & DISUSE_IMMEDIATE16_REL)
@@ -740 +754 @@
                         offDisplacement = (int16_t)pParam->uValue;
                         if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
-                            PUT_NUM_S16(offDisplacement * sizeof(uint32_t));
+                            PUT_NUM_S16(offDisplacement);
                     }
                     else
@@ -746 +760 @@
                         offDisplacement = (int32_t)pParam->uValue;
                         if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
-                            PUT_NUM_S32(offDisplacement * sizeof(uint32_t));
+                            PUT_NUM_S32(offDisplacement);
                     }
                     if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
                         PUT_SZ(" ; (");
 
-                    RTUINTPTR uTrgAddr = pDis->uInstrAddr + (offDisplacement * sizeof(uint32_t));
+                    RTUINTPTR uTrgAddr = pDis->uInstrAddr + offDisplacement;
                     if (   pDis->uCpuMode == DISCPUMODE_ARMV8_A32
                         || pDis->uCpuMode == DISCPUMODE_ARMV8_T32)